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Cypress CY7C1510KV18 User's Manual

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1. 1 2 3 4 5 6 7 8 9 10 11 A ca A A WPS NWS K NC 144M RPS A A CO B NC NC NC A NC 288M K NWS A NC NC Q3 NC NC NC Vss A A A Vss NC NC D3 D NC D4 NC Vss Vss Vss Vss Vss NC NC NC E NC NC Q4 VDDQ Vss Vss Vss Vppa NC D2 Q2 F NC NC NC Visi Von Vss Vig Mop NC NC NC G NC D5 Q5 Vppa Vpp Vss Vpp Vppa NC NC NC H DOFF Vrer Vppo Vppo Von Vss Vop Vppa Vppa VREF ZQ J NC NC NC VDDQ Vpp Vss Mop Vppa NC Q1 D1 K NC NC NC VDDQ Von Vss Me VDDQ NC NC NC L NC Q6 D6 Vppa Vss Vss Vss Vppa NC NC Qo M NC NC NC Vss Vss Vss Vss Vss NC NC DO N NC D7 NC Vss A A A Vss NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1525KV18 8M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ A A WPS NC K NC 44M RPS A A CO B NC NC NC A NC 288M K BWSg A NC NC Q4 C NC NC NC Vss A A A Vss NC NC D4 D NC D5 NC Vss Vss Vss Vss Vss NC NC NC E NC NC Q5 Vppa Vss Vss Vss Vppa NC D3 Q3 F NC NC NC Vppa Vni Vss Ke Vppa NC NC NC G NC D6 Q6 VDDQ Vpp Vss Vpp Vppa NC NC NC H DOFF VREF VDDQ VDDQ VDD Vss VDD VDDQ VDDQ VREF ZQ J NC NC NC Vppa Vpp Vss Von Vppa NC Q2 D2 K NC NC NC Vppa Mag Vss Van Vppa NC NC NC L NC Q7 D7 VDDQ Vss Vss Vss Vppa NC NC Q1 M NC NC NC Ves Vss Vss Vss Vss NC NC D1 N NC D8 NC Vss A A A Vss NC NC NC P NC NC Q8 A A C A A NC DO QO R TDO TCK A A A C A A A TMS TDI Note 1 NC 144M and NC 288
2. NOTES 1 L eoooo ooood rT e 000000000 ooooooooooo ooooo6ooooo oooooo ooooo ooooooooooo oooooo9oooooo g a o 5 o e e o 8 oooooo ooooo E ooooo ooooo ooooooooooo R oooooo ooooo ooooo6ooooo ooooooooooo 600000000996 A Sad Er 10 00 B 4 13 00 0 10 I 0 15 4X SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0 475g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE CODE BBOAC 51 85180 A Page 29 of 30 Feedback s CYPRESS PERFORM CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 LM Y Document History Page Document Title CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72 Mbit QDR II SRAM 2 Word Burst Architecture Document Number 001 00436 Rev ECN No a a en Description of Change Ws 374703 SYT See ECN New Data Sheet A 1103823 VKN See ECN Updated Ipp Spec Updated ordering information table B 1699083 VKN AESA See ECN Converted from Advance Information to Preliminary C 2148307 VKN AESA See ECN Changed PLL lock time from 1024 cycles to 20 us Added footnote 19 related to Ipp Corrected typo in the footnote 23 D 2606839 VKN PYRS 11 13 08 Changed JTAG ID 31 29 from 001 to 000 Updated power up sequence waveform and its description Changed Ambient Temperature with Power Applied from
3. us tke Reset tkc Reset K Static to PLL Reset 30 30 30 30 30 ns Notes 23 These parameters are extrapolated from the input timing parameters tcyc 2 250 ps where 250 ps is the internal jitter These parameters are only guaranteed by design and are not tested in production 24 tcuz tci z are specified with a load capacitance of 5 pF as in part b of AC Test Loads and Waveforms Transition is measured 100 mV from steady state voltage 25 At any voltage and temperature toyz is less than tc 7 and toyz less than tco Document Number 001 00436 Rev E Page 24 of 30 Feedback g gt CY7C1510KV18 CY7C1525KV18 EE CYPRESS CY7C1512KV18 CY7C1514KV18 PERFORM Switching Waveforms Figure 5 Read Write Deselect Sequence 26 27 28 READ WRITE READ WRITE READ WRITE NOP WRITE NOP Ee oso Y osi Z o l SER lt gt 4 gt tsp tup tsp tup tcOHCOH DON T CARE RY UNDEFINED Notes 26 Q00 refers to output from address AO Q01 refers to output from the next internal burst address following AO that is AO 1 27 Outputs are disabled High Z one clock cycle after a NOP 28 In this example if address AO A1 then data O00 D10 and Q01 D11 Write data is forwarded immediately as read results This note applies to the whole diagram Document Number 001 00436 Rev E Page 25 of 30 Feedback PERFORM Orderin
4. 10 C to 85 C to 55 C to 125 C in the Maximum Ratings on page 20 Included Thermal Resistance values Changed the package size from 15 x 17 x 1 4 mm to 13 x 15 x 1 4 mm E 2681899 VKN PYRS 04 01 2009 Converted from preliminary to final Added note on top of the Ordering Information table Moved to external web Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2005 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or
5. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns However it is not necessary to reset the PLL to lock to the desired frequency The PLL automatically locks 20 us after a stable clock is presented The PLL may be disabled by applying ground to the DOFF pin When the PLL is turned off the device behaves in QDR I mode with one cycle latency and a longer access time Figure 1 Application Example R 2500hms SRAM 2 Zo R 2500hms CQ CQ Q C CH K K DATA IN DATA OUT Address RPS BUS WPS MASTER BWS CPU CLKIN CLKIN Mi Source K ASIC Source Kit Delayed K A Delayed Kit WW R R 500hms Vt Vddq 2 Document Number 001 00436 Rev E Page 9 of 30 Feedback CY7C1510KV18 CY7C1525KV18 F CYPRESS CY7C1512KV18 CY7C1514KV18 PERFORM Truth Table The truth table for CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 and CY7C1514KV18 follow 2 3 4 5 6 7 Operation K RPS WPS DQ DQ Write Cycle _ L H X L D A O atK t T D A 1 at Kt Load address on the rising edge of K input write data on K and K rising edges Read Cycle L H L X IQ A 0 at C t 1 1 Q A 1 at C t 2 Load address on the rising edge of K _ wait one and a half cycle read data on C and C rising edges NOP No Operation L H H H D X D X O High Z O High Z Standby Cl
6. 30 Feedback Eee CY7C1510KV18 CY7C1525KV18 lt f CYPRESS CY7C1512KV18 CY7C1514KV18 PERFORM Write Cycle Descriptions The write cycle description table for CY7C1525KV18 follow gt 8 BWS K K L L H During the data portion of a write sequence the single byte Dys ol is written into the device L L H During the data portion of a write sequence the single byte Dra oj is written into the device H L H No data is written into the device during this portion of a write operation H L H No data is written into the device during this portion of a write operation Write Cycle Descriptions The write cycle description table for CY7C1514KV18 follow gt 81 BWS BWS BWS BWS3 K K Comments L L L L L H During the data portion of a write sequence all four bytes D 35 9 are written into the device L L L L L H During the data portion of a write sequence all four bytes Urs ol are written into the device L H H H L H During the data portion of a write sequence only the lower byte Ur ol is written into the device Droe o remains unaltered L H H H L H During the data portion of a write sequence only the lower byte Ur od is written into the device Dj35 9 remains unaltered H L H H L H During the data portion of a write sequence only the byte Dr17 9j is written into the device Drg oj and Dee remains unaltered H L
7. 333 MHz x8 290 mA Current Both Ports Deselected Vin 2 Vin OF Vin lt Vi Ges f fmax 1 tcyc x18 290 Inputs Static x36 290 300 MHz x8 280 mA x9 280 x18 280 x36 280 250 MHz x8 270 mA x9 270 x18 270 x36 270 200 MHz x8 250 mA x9 250 x18 250 x36 250 167 MHz x8 250 mA x9 250 x18 250 x36 250 AC Electrical Characteristics Over the Operating Range n Parameter Description Test Conditions Min Typ Max Unit Vin Input HIGH Voltage Vner 0 2 V Vu Input LOW Voltage Vngr 0 2 V Document Number 001 00436 Rev E Page 21 of 30 Feedback CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 PERFORM Capacitance Tested initially and after any design or process change that may affect these parameters Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHZ Vpp 1 8V Vppo 1 5V 2 pF Co Output Capacitance 3 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters HENA an 165 FBGA Parameter Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard test methods and 13 7 C W Junction to Ambient procedures for measuring thermal impedance in accordance with EIA JESD51 Ou Thermal Resistance 3 73 C W Junction to Case Figure 4 AC Test Loads and
8. H H L H During the data portion of a write sequence only the byte D 47 gj is written into the device Drg oj and Dj35 18 remains unaltered H H L H L H During the data portion of a write sequence only the byte Dj2g 18 is written into the device D17 0 and Dr35 27 remains unaltered H H L H L H During the data portion of a write sequence only the byte D 26 1gj is written into the device Dr47 0 and De za remains unaltered H H H L L H During the data portion of a write sequence only the byte re cd is written into the device De o remains unaltered H H H L L H During the data portion of a write sequence only the byte Dj35 27 is written into the device De o remains unaltered L H No data is written into the device during this portion of a write operation L H No data is written into the device during this portion of a write operation Document Number 001 00436 Rev E Page 11 of 30 Feedback YPRESS PERFORM Ml WW C3 IEEE 1149 1 Serial Boundary Scan JTAG These SRAMs incorporate a serial boundary scan Test Access Port TAP in the FBGA package This part is fully compliant with IEEE Standard 1149 1 2001 The TAP operates using JEDEC standard 1 8V IO logic levels Disabling the JTAG Feature lt is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vgg t
9. state The ID register has a vendor code and other information described in Identification Register Definitions on page 17 TAP Instruction Set Eight different instructions are possible with the three bit instruction register All combinations are listed in Instruction Codes on page 17 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in this section in detail Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO pins To execute the instruction after it is shifted in the TAP controller must be moved into the Update IR state Page 12 of 30 Feedback PERFORM The IDCODE instruction loads a vendor specific 32 bit code into the instruction register It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test Logic Reset state SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is suppli
10. 14KV18 PERFORM Power Up Sequence in QDR II SRAM PLL Constraints m PLL uses K clock as its synchronizing input The input must QDR II SRAMs must be powered up and initialized in a h h itt hich i ified ast predefined manner to prevent undefined operations ave OW Phase Jer MENS Speen aS KC Ver m The PLL functions at frequencies down to 120 MHz m If the input clock is unstable and the PLL is enabled then the Power Up Sequence PLL may lock onto an incorrect frequency causing unstable m Apply power and drive DOFF either HIGH or LOW All other inputs can be HIGH or LOW SRAM behavior To avoid this provide 20 us of stable clock to a Apply Vpp before Vppo relock to the desired clock frequency I Apply Vppo before Vngr or at the same time as VREF 9 Drive DOFF HIGH m Provide stable DOFF HIGH power and clock K K for 20 us to lock the PLL Figure 3 Power Up Waveforms PITTI i oV oU uU Ww uuu Dest Clock Clock Start Clock Starts after Vpp Vppq Stable Vop Vppa Vpp Vppo Stable lt 0 1V DC per 50ns Fix HIGH or tie to YppQ DOFF Page 19 of 30 Document Number 001 00436 Rev E Feedback CY7C1510KV18 CY7C1525KV18 F CYPRESS CY7C1512KV18 CY7C1514KV18 PERFORM Maximum Ratings Exceedin
11. 5KV18 CY7C1512KV18 CY7C1514KV18 i 333MHz 300MHz 250MHz 200 MHz 167 MHz in Gn Description Unit arameten aramerer Min Max Min Max Min Max Min Max Min Max Output Times tco tcHav CIC Clock Rise or K K in single 045 045 045 045 0 50 ns clock mode to Data Valid tDOH tcHax Data Output Hold after Output C C 0 45 0 45 045 0 45 0 50 ns Clock Rise Active to Active tccoo tcHcov C C Clock Rise to Echo Clock Valid 0 45 0 45 0 45 0 45 0 50 ns tcooH tcHcox Echo Clock Hold after C C Clock 0 45 0 45 045 0 45 0 50 ns Rise Loop tcoHov Echo Clock High to Data Valid 0 25 0 27 030 035 0 40 ns tcoDoH tcoHox Echo Clock High to Data Invalid 0 25 027 030 0 335 0 40 ns toon teaucar Output Clock CQ CQ HIGH HI 1 25 140 175 225 275 ns tcoucaH tcoHCOH CQ Clock Rise to CO Clock Rise 1 25 140 175 225 275 ns rising edge to rising edge tcHz tcHaz Clock C C Rise to a Z 045 045 1045 045 10 50 ns Active to High gl tciz tcHOX1 Clock C C Rise to Low Z 25 291 _0 45 0 45 045 0 45 0 50 ns PLL Timing tke Var tkc Var Clock Phase Jitter 1020 020 020 020 0 20 ns lC lock Her lock PLL Lock Time K C 20 20 20 20 20
12. BILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 00436 Rev E Revised March 30 2009 Page 30 of 30 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress IDT NEC Renesas and Samsung All product and company names mentioned in this document are the trademarks of their respective holders Feedback
13. EST is entered as the current instruction When HIGH it enables the output buffers to drive the output bus When LOW this bit places the output bus into a High Z condition This bit is set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell latches into the preload register When the EXTEST instruction is entered this bit directly controls the output Q bus pins Note that this bit is pre set LOW to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Page 13 of 30 Feedback PERFORM TAP Controller State Diagram The state diagram for the TAP controller follows 9 is CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 TEST LOGIC a RESET d 1 TEST LOGIC 1 SELECT SELECT gt gt IDLE DR SCAN IR SCAN d d 1 CAPTURE DR CAPTURE IR 0 0 P SHIFT DR SHIFT IR 0 Y Y 1 gt EXIT1 DR gt EXIT1 IR d E PAUSE DR PAUSE IR 0 y Y 0 EXIT2 DR EXIT2 IR Y Y UPDATE DR UPDATE IR 1 0 Note Y 9 The 0 1 next to
14. K K Clock Rise to C C Clock Rise 0 130 0 1 45 O 1 8 O 22 0 2 7 ns rising edge to rising edge Setup Times tsa tAVKH Address Setup to K Clock Rise 04 04 1051 06 07 ns tsc tivkH Control Setup to K Clock Rise 04 104 05 06 07 ns RPS WPS tscppR tivKH DDR Control Setup to Clock K K 0 3 03 035 04 05 ns Rise BWSp BWS4 BWS BWS3 tsp tDVKH Drx o Setup to Clock K K Rise 0 3 0 3 0 35 0 4 0 5 ns Hold Times tha tkHax Address Hold after K Clock Rise 03 03 035 04 05 ns tuc tkHIX Control Hold after K Clock Rise 03 103 035 04 05 ns RPS WPS tucppR tkHIx DDR Control Hold after Clock K K 0 3 0 3 035 04 05 ns Rise BWSp BWS BWS BWS3 tub tkHDX Drx o Hold after Clock KIK Rise 0 3 0 3 0 35 0 4 0 5 ns Notes 21 When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range 22 This part has a voltage regulator internally tpoygg is the time that the power must be supplied above Vpp minimum initially before initiating a read or write operation Document Number 001 00436 Rev E Page 23 of 30 Feedback PERFORM Switching Characteristics continued Over the Operating Range 20 21 CY7C1510KV18 CY7C152
15. M are not connected to the die and can be tied to any voltage level Document Number 001 00436 Rev E Page 4 of 30 Feedback Lc CY7C1510KV18 CY7C1525KV18 CYPRESS CY7C1512KV18 CY7C1514KV18 PERFORM Pin Configuration continued The pin configurations for CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 and CY7C1514KV18 follow M 165 Ball FBGA 13 x 15 x 1 4 mm Pinout CY7C1512KV18 4M x 18 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 144M A WPS BWS K NC 288M RPS A A CQ B NC Q9 D9 A NC K BWSg A NC NC Q8 e NC NC D10 Vss A A A Vss NC Q7 D8 D NC D11 Q10 Vss Vss Vss Vss Vss NC NC D7 E NC NC Q11 Vid Vss Vss Vss Vo NC D6 Q6 F NC Q12 D12 Vapa Vpp Vss Vag Vena NC NC Q5 G NC D13 Q13 Vase Ve Vss Vb Vane NC NC D5 H DOFF Vaer Vppo Vopa Von Vss Vop Vppa Vppa VREF ZQ J NC NC D14 Vasa Vpp Vss Msg VDDQ NC Q4 D4 K NC NC Q14 Vane Vo Vss Vag Vine NC D3 Q3 L NC Q15 D15 Vna Vss Vss Vss VpDO NC NC Q2 M NC NC D16 Vss Vss Vss Vss Vss NC Q1 D2 N NC D17 Q16 Vss A A A Vss NC NC D1 P NC NC Q17 A A C A A NC DO QO R TDO TCK A A A C A A A TMS TDI CY7C1514KV18 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A CO NC 288M A WPS BWS K BWS RPS A NC 144M CO B Q27 Q18 D18 A BWS K BWSg A D17 O17 Q8 C D27 Q28 D19 Vss A A A Vss D16 Q7 D8 D D28 D20 Q19 Vss Vss Vss Vss Vss Q16 D15 D7 E Q29 D29 Q20
16. ORM Mi Low Functional Overview The CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 and CY7C1514KV18 are synchronous pipelined Burst SRAMs with a read port and a write port The read port is dedicated to read operations and the write port is dedicated to write operations Data flows into the SRAM through the write port and flows out through the read port These devices multiplex the address inputs to minimize the number of address pins required By having separate read and write ports the ODR II completely eliminates the need to turn around the data bus and avoids any possible data contention thereby simplifying system design Each access consists of two 8 bit data transfers in the case of CY7C1510KV18 two 9 bit data transfers in the case of CY7C1525KV18 two 18 bit data transfers in the case of CY7C1512KV18 and two 36 bit data transfers in the case of CY7C1514KV18 in one clock cycle This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH When DOFF pin is set LOW or connected to Vas then the device behaves in ODR I mode with a read latency of one clock cycle Accesses for both ports are initiated on the rising edge of the positive input clock K All synchronous input timing is refer enced from the rising edge of the input clocks K and K and all output timing is referenced to the output clocks C and C or K and K when in single clock mode All synchronous data inputs Dr ml pass through input r
17. PERFORM Features m Separate Independent Read and Write Data Ports mn Supports concurrent transactions m 333 MHz Clock for High Bandwidth m 2 word Burst on all Accesses m Double Data Rate DDR Interfaces on both Read and Write Ports data transferred at 666 MHz at 333 MHz m Two Input Clocks K and K for precise DDR timing a SRAM uses rising edges only m Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time mismatches m Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems m Single Multiplexed Address Input bus latches Address Inputs for both Read and Write Ports m Separate Port Selects for Depth Expansion m Synchronous internally Self timed Writes m QDR II operates with 1 5 Cycle Read Latency when DOFF is asserted HIGH m Operates similar to ODR I Device with 1 Cycle Read Latency when DOFF is asserted LOW m Available in x8 x9 x18 and x36 Configurations m Full Data Coherency providing Most Current Data m Core Von 1 8V 0 1V IO VDDQ 1 4V to Von a Supports both 1 5V and 1 8V IO supply m Available in 165 ball FBGA Package 13 x 15 x 1 4 mm m Offered in both Pb free and non Pb free Packages m Variable Drive HSTL Output Buffers m JTAG 1149 1 Compatible Test Access Port m Phase Locked Loop PLL for Accurate Data Placement Table 1 Selection Guide CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72 Mbit ODR M II SRAM 2 Word Burst Architectur
18. Vina Vss Vss Vss VDDQ Q15 D6 Q6 F Q30 Q21 D21 Vane Von Vss Vpp Vosa D14 Q14 Q5 G D30 D22 Q22 Vena Vpp Vss Vpp Vena Q13 D13 D5 H DOFF VREF VDDQ VDDQ VDD Vss VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 Vane Vpp Vss Vip Vapa D12 Q4 D4 K Q32 D32 Q23 VDDQ Vo Veg Vag Vane Q12 D3 Q3 L Q33 Q24 D24 Vane Vss Vss Vss Vos D11 Q11 Q2 M D33 Q34 D25 Vss Vss Vss Vss Vss D10 Q1 D2 N D34 D26 Q25 Vss A A A Vss Q10 D9 D1 P Q35 D35 Q26 A A C A A Q9 DO QO R TDO TCK A A A C A A A TMS TDI Document Number 001 00436 Rev E Page 5 of 30 Feedback CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 PERFORM Pin Definitions Pin Name I O Pin Description U x 0 Input Synchronous Data Input Signals Sampled on the rising edge of K and K clocks during valid write operations CY7C1510KV18 Drz o CY7C1525KV18 Djg o CY7C1512KV18 Di47 0 CY7C1514KV18 D g5 0 Input Synchronous Write Port Select Active LOW Sampled on the rising edge of the K clock When asserted active a write operation is initiated Deasserting deselects the write port Deselecting the write port ignores Dyx 9 Input Synchronous Input Synchronous Nibble Write Select 0 1 Active LOW CY7C1510KV18 Only Sampled on the rising edge of the K and K clocks during write operations Used to select which nibble is written into the device during the current portion of the write operations Nibbles not written remain unaltered NWS con
19. Waveforms VREF 0 75V Verto 075V OUTPUT VReF t e 0 75V R 500 20 ALL INPUT PULSES DEVICE OUTPUT 1 25V TEST UNDER 5pF 0 25V 26 Vner 0 75V TEST ZQ JE SLEW RATE 2 V ns RQ um 2500 INCLUDING JIG AND b SCOPE Note 20 Unless otherwise noted test conditions are based on signal transition time of 2V ns timing reference levels of 0 75V Vref 0 75V RQ 2500 Vppq 1 5V input pulse levels of 0 25V to 1 25V and output loading of the specified lo Tou and load capacitance shown in a of AC Test Loads and Waveforms Page 22 of 30 Document Number 001 00436 Rev E Feedback PERFO RM Switching Characteristics Over the Operating Range 20 21 CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 i 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz KOR oan Description Unit arameten e anameser Min Max Min Max Min Max Min Max Min Max tPOWER Vpp Typical to the First Access 22 4 1 1 1 1 ms tcvc tKHKH K Clock and C Clock Cycle Time 3 0 8 4 3 3 84 4 0 8 4 5 0 8 4 6 0 84 ns tkH tKHKL Input Clock K K C C HIGH 120 132 16 20 24 ns tk tKLKH Input Clock K K C C LOW 120 132 16 20 24 ns tKHKH tKHKH K Clock Rise to K Clock Rise andC 1 35 149 18 22 27 ns to C Rise rising edge to rising edge tKHCH tkHCH
20. an register Page 16 of 30 Feedback PER FORM Identification Register Definitions CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 Value Instruction Field Description CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 Revision Number 000 000 000 000 Version number 31 29 Cypress Device ID 11010011010000100 11010011010001100 11010011010010100 11010011010100100 Defines the type of 28 12 SRAM Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique 11 1 identification of SRAM vendor ID Register 1 1 1 1 Indicates the Presence 0 presence of an ID register Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 109 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the input and output contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED 101 Do Not Use Thi
21. byte write operation Single Clock Mode The CY7C1510KV18 is used with a single clock that controls both the input and output registers In this mode the device recognizes only a single pair of input clocks K and K that control both the input and output registers This operation is identical to the operation if the device had zero skew between the K K and C C clocks All timing parameters remain the same in this mode To use this mode of operation the user must tie C and C HIGH at power on This function is a strap option and not alterable during device operation Concurrent Transactions The read and write ports on the CY7C1512KV18 operate completely independently of one another As each port latches the address inputs on different clock edges the user can read or write to any location regardless of the transaction on the other port The user can start reads and writes in the same clock cycle If the ports access the same location at the same time the SRAM delivers the most recent information associated with the specified address location This includes forwarding data from a write cycle that was initiated on the previous K clock rise Depth Expansion The CY7C1512KV18 has a port select input for each port This enables for easy depth expansion Both port selects are sampled on the rising edge of the positive input clock only K Each port select input can deselect the specified port Deselecting a port does not affect the other p
22. cument Number 001 00436 Rev E Page 15 of 30 Feedback PERFORM TAP AC Switching Characteristics Over the Operating Range 3 141 CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 Parameter Description Min Max Unit trcvc TCK Clock Cycle Time 50 ns trr TCK Clock Freguency 20 MHz tru TCK Clock HIGH 20 ns tn TCK Clock LOW 20 ns Setup Times ttuss TMS Setup to TCK Clock Rise 5 ns trpis TDI Setup to TCK Clock Rise 5 ns tcs Capture Setup to TCK Rise ns Hold Times trMsH TMS Hold after TCK Clock Rise 5 ns trpiH TDI Hold after Clock Rise 5 ns tcH Capture Hold after Clock Rise 5 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns ttpox TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions 14 Figure 2 TAP Timing and Test Conditions 0 9V ALL INPUT PULSES 1 8V 0 9V TDO OV 2 9 L c 20 pF a GND tru tr gt e Test Clock N N TCK trcvc trusH gt truss Lal a a Test Mode Select TMS WK MD trpis i TDIH at m DV MI MZ TDI Test Data Out TDO 4 A trpov XS trpox Notes 13 tcs and tcp refer to the setup and hold time requirements of latching data from the bou 14 Test conditions are specified using the load in TAP AC Test Conditions tp te 1 ns Document Number 001 00436 Rev E ndary sc
23. e Configurations CY7C1510KV18 8M x 8 CY7C1525KV18 8M x 9 CY7C1512KV18 4M x 18 CY7C1514KV18 2M x 36 Functional Description The CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 and CY7C1514KV18 are 1 8V Synchronous Pipelined SRAMs equipped with QDR II architecture ODR II architecture consists of two separate ports the read port and the write port to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations ODR II architecture has separate data inputs and data outputs to completely eliminate the need to turnaround the data bus that exists with common I O devices Access to each port is through a common address bus Addresses for read and write addresses are latched on alternate rising edges of the input K clock Accesses to the QDR II read and write ports are completely independent of one another To maximize data throughput both read and write ports are equipped with DDR interfaces Each address location is associated with two 8 bit words CY7C1510KV18 9 bit words CY7C1525KV18 18 bit words CY7C1512KV18 or 36 bit words CY7C1514KV18 that burst sequentially into or out of the device Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds Depth expans
24. each state represents the value at TMS at the rising edge of TCK Document Number 001 00436 Rev E Page 14 of 30 Feedback CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 PERFORM TAP Controller Block Diagram z 0 Bypass Register B2170 mn Selection TDO Selection TDI Instruction Register Circuitry EN THUS ee Circuitry 31130 291 2 1 0 gt Identification Register 2 1 0 gt l p gt 108 Boundary Scan Register LIT tt t ft d TAP Controller TCK TMS p TAP Electrical Characteristics Over the Operating Range HO 11 12 Parameter Description Test Conditions Min Max Unit Mou Output HIGH Voltage lou 2 0 mA 1 4 V Vou2 Output HIGH Voltage lou 100 pA 1 6 V VoL1 Output LOW Voltage lon 2 0 mA 0 4 V Voi2 Output LOW Voltage lo 100 pA 0 2 V Vin Input HIGH Voltage 0 65Vpp Vpp 0 3 V Vu Input LOW Voltage 0 3 0 35Vpp V Ix Input and Output Load Current GND lt Vi Vpp 5 5 uA Notes 10 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are specified in the Electrical Characteristics table 11 Overshoot V H AC lt Vppa 0 85V Pulse width less than tcyc 2 Undershoot Vi AC gt 1 5V Pulse width less than tcyc 2 12 All voltage referenced to Ground Do
25. ed during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the input and output pins is captured in the boundary scan register The TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output undergoes a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and tcp The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the bounda
26. eference Voltage 81 Typical Value 0 75V 0 68 0 75 0 95 V Ipp 9 Vpp Operating Supply Vpp Max 333 MHz x8 790 mA lour 0 mA f fmax ltoyc pen x18 810 x36 990 300 MHz x8 730 mA x9 730 x18 750 x36 910 250 MHz x8 640 mA x9 640 x18 650 x36 790 Notes 15 Power up Assumes a linear ramp from OV to Vpp min within 200 ms During this time Vu lt Vpp and Vppo lt Vpp 16 Output are impedance controlled lou Vppo 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 17 Output are impedance controlled lo Vppo 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 18 Veer min 0 68V or 0 46Vppq whichever is larger Vref max 0 95V or 0 54Vppq whichever is smaller 19 The operation current is calculated with 50 read cycle and 50 write cycle Document Number 001 00436 Rev E Page 20 of 30 Feedback am 4 CY7C1510KV18 CY7C1525KV18 CYPRESS CY7C1512KV18 CY7C1514KV18 PERFORM Electrical Characteristics continued DC Electrical Characteristics Over the Operating Range 12 Parameter Description Test Conditions Min Typ Max Unit Ibp D I Vpp Operating Supply Vpp Max 200 MHz x8 540 mA tae dics pm 940 x18 550 x36 660 167 MHz x8 480 mA x9 480 x18 490 x36 580 lsg1 Automatic Power Down Max Vpp
27. egisters controlled by the input clocks tic and K All synchronous data outputs Qix 0 pass through output registers controlled by the rising See of the output clocks C and C or K and K when in single clock mode All synchronous control RPS WPS BWS pco inputs pass through input registers controlled by the rising edge of the input clocks K and K CY7C1512KV18 is described in the following sections The same basic descriptions apply to CY7C1510KV18 CY7C1525KV18 and CY7C1514KV18 Read Operations The CY7C1512KV18 is organized internally as two arrays of 2M x 18 Accesses are completed in a burst of two sequential 18 bit data words Read operations are initiated by asserting RPS active at the rising edge of the positive input clock K The address is latched on the rising edge of the K clock The address presented to the address inputs is stored in the read address register Following the next K clock rise the corresponding lowest order 18 bit word of data is driven onto the Qr 7 9 using C asthe output timing reference On the subsequent rising edge of C the next 18 bit data word is driven onto the Qy17 9 The requested data is valid 0 45 ns from the rising edge of the output clock C and C or K and K when in single clock mode Synchronous internal circuitry automatically tristates the outputs following the next rising edge of the output clocks C C This enables for a seamless transition between devices without the inserti
28. g Information CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 The following table lists all possible speed package and temperature range options supported for these devices Note that some options listed may not be available for order entry To verify the availability of a specific option visit the Cypress website at www cypress com and refer to the product summary page at http www cypress com products or contact your local sales representative for the status of availability of parts Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at http app cypress com portal server pt space CommunityPage amp control SetCommunity amp CommunityID 201 amp PageID 230 Table 2 Ordering Information Speed MHz Ordering Code Package Diagram Package Type Operating Range 333 CY7C1510KV18 333BZC CY7C1525KV18 333BZC CY7C1512KV18 333BZC CY7C1514KV18 333BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1510KV18 333BZXC CY7C1525KV18 333BZXC CY7C1512KV18 333BZXC CY7C1514KV18 333BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Commercial CY7C1510KV18 333BZI CY7C1525KV18 333BZI CY7C1512KV18 333BZI CY7C1514KV18 333BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industria
29. g maximum ratings may impair the useful life of the Current into Outputs OW 20 mA device These user guidelines are not tested Static Discharge Voltage MIL STD 883 M 3015 gt 2001V Storage Temperature ses 65 C to 150 C Latch up Cumrent gt 200 mA Ambient Temperature with Power Applied 55 C to 125 C o ti R Supply Voltage on Vpp Relative to GND 0 5V to 2 9V perating Range Supply Voltage on Vppo Relative to GND 0 5V to V Ambient PEN Vg ppa Re po Range Temperature Ta Vpop Vppq DC Applied to Outputs in High Z 0 5V to Vppa 0 5V gt gt 11 Commercial 0 C to 70 C 1 8 0 1V 1 4V to DC Input Voltage TTT 0 5V to Vpp 0 5V V Industrial 40 C to 85 C DD Electrical Characteristics DC Electrical Characteristics Over the Operating Range 12 Parameter Description Test Conditions Min Typ Max Unit Von Power Supply Voltage 1 7 1 8 1 9 V VDDQ IO Supply Voltage 1 4 1 5 Vpp V Vou Output HIGH Voltage Note 16 Vppo 2 0 12 Vppo 2 0 12 V VoL Output LOW Voltage Note 17 Vppo 2 0 12 Vppo 2 0 12 V VoH Low Output HIGH Voltage lop 0 1 mA Nominal Impedance Vppo 0 2 VDDQ V VoL LOW Output LOW Voltage lo 0 1 mA Nominal Impedance Vss 0 2 V VIH Input HIGH Voltage VREF 0 1 VDDQ 0 3 V Vu Input LOW Voltage 0 3 Vner 0 1 V Ix Input Leakage Current GND lt Vi lt Vppo 5 5 uA loz Output Leakage Current GND lt V lt Vppo Output Disabled 5 5 HA VREF Input R
30. ion Codes on page 17 The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This Reset does not affect the operation of the SRAM and is performed when the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a high Z state TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry Only one register can be selected at a time through the instruction registers Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Document Number 001 00436 Rev E CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 Instruction Register Three bit instructions are serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 15 Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to enable fault isolation of the board level serial test pa
31. ion is accomplished with port selects which enables each port to operate independently All synchronous inputs pass through input registers controlled by the K or K input clocks All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks Writes are conducted with on chip synchronous self timed write circuitry Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit Maximum Operating Frequency 333 300 250 200 167 MHz Maximum Operating Current x8 790 730 640 540 480 mA x9 790 730 640 540 480 x18 810 750 650 550 490 x36 990 910 790 660 580 Cypress Semiconductor Corporation Document Number 001 00436 Rev E 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 30 2009 Feedback PERFORM Logic Block Diagram CY7C1510KV18 8 Dro Ce Address Register Control Write Write D Reg b keny 9 X Ny H Write Add Decode Read Add Decode AU 9 X INE I Read Data Reg CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 Address Register ZN A 21 0 Control Logic Logic Block Diagram CY7C1525KV18 Do 22 Address A21 0 7 P Register VREF WPS Control Logic Document Number 001 00436 Rev E Write Write Reg Reg Wri
32. l CY7C1510KV18 333BZXI CY7C1525KV18 333BZXI CY7C1512KV18 333BZXI CY7C1514KV18 333BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 300 CY7C1510KV18 300BZC CY7C1525KV18 300BZC CY7C1512KV18 300BZC CY7C1514KV18 300BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1510KV18 300BZXC CY7C1525KV18 300BZXC CY7C1512KV18 300BZXC CY7C1514KV18 300BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1510KV18 300BZI CY7C1525KV18 300BZI CY7C1512KV18 300BZI CY7C1514KV18 300BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1510KV18 300BZXI CY7C1525KV18 300BZXI CY7C1512KV18 300BZXI CY7C1514KV18 300BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Document Number 001 00436 Rev E Page 26 of 30 Feedback PERFORM Table 2 Ordering Information continued CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 CY7C1510KV18 250BZI CY7C1525KV18 250BZI CY7C1512KV18 250BZI CY7C1514KV18 250BZI CY7C1510KV18 250BZXI CY7C1525KV18 250BZXI CY7C1512KV18 250BZXI CY7C1514KV18 250BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Speed Package Operating MHz Ordering C
33. mpedance CQ CQ and Q x 0 Output impedance are set to 0 2 x RQ where RQ is a resistor connected between ZQ and ground Allerhatively connect this pin directly to Vppo which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected DOFF Input PLL Turn Off Active LOW Connecting this pin to ground turns off the PLL inside the device The timing in the operation with the PLL turned off differs from those listed in this data sheet For normal operation connect this pin to a pull up through a 10 KO or less pull up resistor The device behaves in QDR I mode when the PLL is turned off In this mode the device can be operated at a freguency of up to 167 MHz with QDR I timing TDO Output TDO for JTAG TCK Input TCK Pin for JTAG TDI Input TDI Pin for JTAG TMS Input TMS Pin for JTAG NC N A Not Connected to the Die Can be tied to any voltage level NC 144M Input Not Connected to the Die Can be tied to any voltage level NC 288M Input Not Connected to the Die Can be tied to any voltage level VREF Input Reference Voltage Input Static input used to set the reference level for HSTL inputs outputs and AC Reference measurement points Von Power Supply Power Supply Inputs to the Core of the Device Vss Ground Ground for the device Vppa Power Supply Power Supply Inputs for the Outputs of the Device Document Number 001 00436 Rev E Page 7 of 30 Feedback YPRESS PERF
34. n the board back to the controller See Application Example on page 9 for further details Input Clock Positive Input Clock Input The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Or o when in single clock mode All accesses are initiated on the rising edge of K Al Document Number 001 00436 Rev E Input Clock Negative Input Clock Input Kis used to capture synchronous inputs being presented to the device and to drive out data through Or o when in single clock mode Page 6 of 30 Feedback CY7C1510KV18 CY7C1525KV18 CYPRESS CY7C1512KV18 CY7C1514KV18 PERFOR M Pin Definitions continued Pin Name y o Pin Description CO Echo Clock CO Referenced with Respect to C This is a free running clock and is synchronized to the input clock for output data C of the QDR II In single clock mode CQ is generated with respect to K The timing for the echo clocks is shown in Switching Characteristics on page 23 ca Echo Clock ca Referenced with Respect to C This is a free running clock and is synchronized to the input clock for output data C of the QDR II In single clock mode CO is generated with respect to K The timing for the echo clocks is shown in the Switching Characteristics on page 23 ZO Input Output Impedance Matching Input This input is used to tune the device outputs to the system data bus i
35. o prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternatively be connected to Vpp through a pull up resistor TDO must be left unconnected Upon power up the device comes up in a reset state which does not interfere with the operation of the device Test Access Port Test Clock The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK This pin may be left unconnected if the TAP is not used The pin is pulled up inter nally resulting in a logic HIGH level Test Data In TDI The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information about loading the instruction register see the TAP Controller State Diagram on page 14 TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see Instruct
36. ock Stopped Stopped X X Previous State Previous State Write Cycle Descriptions The write cycle description table for CY7C1510KV18 and CY7C1512KV18 follow gt 8l BWSy BWS NWS NWS L L L H During the data portion of a write sequence CY7C1510KV18 both nibbles Dro are written into the device CY7C1512KV18 both bytes Di are written into the device L L L H During the data portion of a write sequence CY7C1510KV18 both nibbles Dr ol are written into the device CY7C1512KV18 both bytes Dno are written into the device L H L H During the data portion of a write sequence CY7C1510KV18 only the lower nibble D g oj is written into the device Dr7 4j remains unaltered CY7C1512KV18 only the lower byte Djg oj is written into the device Du e remains unaltered K K Comments L H L H During the data portion of a write sequence CY7C1510KV18 only the lower nibble D g oj is written into the device Dr7 4j remains unaltered CY7C1512KV18 only the lower byte Dys ol Is written into the device Dr47 9j remains unaltered H L L H During the data portion of a write sequence CY7C1510KV18 only the upper nibble Dr al is written into the device Dr o remains unaltered CY7C1512KV18 only the upper byte Bra is written into the device Djg o remains unaltered H L L H During the data portion of a write sequence CY7C1510KV18 only the up
37. ode Diagram Package Type Range 250 CY7C1510KV18 250BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1525KV18 250BZC CY7C1512KV18 250BZC CY7C1514KV18 250BZC CY7C1510KV18 250BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1525KV18 250BZXC CY7C1512KV18 250BZXC CY7C1514KV18 250BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial 200 CY7C1510KV18 200BZC CY7C1525KV18 200BZC CY7C1512KV18 200BZC CY7C1514KV18 200BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1510KV18 200BZXC CY7C1525KV18 200BZXC CY7C1512KV18 200BZXC CY7C1514KV18 200BZXC CY7C1510KV18 200BZI CY7C1525KV18 200BZI CY7C1512KV18 200BZI CY7C1514KV18 200BZI 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial Industrial CY7C1510KV18 200BZXI CY7C1525KV18 200BZXI CY7C1512KV18 200BZXI CY7C1514KV18 200BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Document Number 001 00436 Rev E Page 27 of 30 Feedback PERFORM Table 2 Ordering Information continued CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 CY7C1525KV18 167BZC CY7C1512KV18 167BZC CY7C1514KV18 167BZC Speed Package O
38. on of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock K On the same K clock rise the data presented to Dj17 9 is latched and stored into the Document Number 001 00436 Rev E CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 lower 18 bit write data register provided DW o are both asserted active On the subsequent rising edge o the negative input clock K the address is latched and the information presented to Dr7 9j is also stored into the write data register provided BW o are both asserted active The 36 bits of data are then written into the memory array at the specified location When deselected the write port ignores all inputs after the pending write operations are completed Byte Write Operations Byte write operations are supported by the CY7C1512KV18 A write operation is initiated as described in the Write Operations section The bytes that are written are determined by BWSg and BWS which are sampled with each set of 18 bit data words Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device Deasserting the Byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered This feature is used to simplify read modify or write operations to a
39. ort All pending transactions read and write are completed before the device is deselected Programmable Impedance An external resistor RQ must be connected between the ZQ pin on the SRAM and Vss to enable the SRAM to adjust its output driver impedance The value of RO must be 5X the value of the intended line impedance driven by the SRAM The allowable range of RO to guarantee impedance matching with a tolerance of 15 is between 1750 and 3500 with Vppo 1 5V The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature Page 8 of 30 Feedback PERFORM Echo Clocks Echo clocks are provided on the QDR II to simplify data capture on high speed systems Two echo clocks are generated by the ODR II CQ is referenced with respect to C and CQ is referenced with respect to C These are free running clocks and are synchro nized to the output clock of the QDR II In the single clock mode CQ is generated with respect to K and CQ is generated with respect to K The timing for the echo clocks is shown in Switching Characteristics on page 23 Application Example Figure 1 shows two QDR II used in an application CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency During power up when the DOFF is tied HIGH the PLL is locked after 20 us of stable clock
40. per nibble Dj7 4 is written into the device Dro remains unaltered CY7C1512KV18 only the upper byte Dara is written into the device Djg o remains unaltered L H No data is written into the devices during this portion of a write operation L H No data is written into the devices during this portion of a write operation Notes 2 X Don t Care H Logic HIGH L Logic LOW T represents rising edge 3 Device powers up deselected with the outputs in a tristate condition 4 A represents address location latched by the devices when transaction was initiated A 0 A 1 represents the internal address sequence in the burst 5 t represents the cycle at which a read write operation is started t 1 and t 2 are the first and second clock cycles respectively succeeding the t clock cycle 6 Data inputs are registered at K and K rising edges Data outputs are delivered on C and C rising edges except when in single clock mode 7 Ensure that when the clock is stopped K K and C C HIGH This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically 8 Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table NWSg NWS4 BWSp BWS4 BWS and BWS can be altered on different portions of a write cycle as long as the setup and hold requirements are achieved Document Number 001 00436 Rev E Page 10 of
41. perating MHz Ordering Code Diagram Package Type Range 167 CY7C1510KV18 167BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1510KV18 167BZXC CY7C1525KV18 167BZXC CY7C1512KV18 167BZXC CY7C1514KV18 167BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1510KV18 167BZI CY7C1525KV18 167BZI CY7C1512KV18 167BZI CY7C1514KV18 167BZI CY7C1510KV18 167BZXI CY7C1525KV18 167BZXI CY7C1512KV18 167BZXI CY7C1514KV18 167BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Industrial Document Number 001 00436 Rev E Page 28 of 30 Feedback PERFORM Package Diagram CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 Figure 6 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 TOP VIEW x PIN 1 CORNER D 4 15 00 0 10 Ss Er x Bt 13 00 0 10 0 53 0 05 140 MAX m 025C BOTTOM VIEW PIN 1 CORNER p 2005 MC V go25MC B 90 50 85x 0 14 3 o D EI 6 5 4 3 D 0 15C al SEATING PLANE 0 36 Document Number 001 00436 Rev E 0 35 0 06
42. ress inputs for CY7C1512KV 18 and 20 address inputs for CY7C1514KV18 These inputs are ignored when the appro priate port is deselected Qpx o Output Synchronous Data Output Signals These pins drive out the requested data during a read operation Valid data is driven out on the rising edge of the C and C clocks during read operations or K and K when in single clock mode When the read port is deselected Qr are automatically tristated CY7C1510KV 18 Qr CY7C1525KV 18 Um CY7C1512KV 18 Quz CY7C1514KV 18 Qr35 0 RPS Input Synchronous Read Port Select Active LOW Sampled on the rising edge of positive input clock K When active a read operation is initiated Deasserting deselects the read port When deselected the pending access is allowed to complete and the output drivers are automatically tristated following the next rising edge of the C clock Each read access consists of a burst of two sequential transfers Input Clock Positive Input Clock for Output Data C is used in conjunction with C to clock out the read data from the device Use C and C together to deskew the flight times of various devices on the board back to the controller See Application Example on page 9 for further details Ol Input Clock Negative Input Clock for Output Data C is used in conjunction with C to clock out the read data from the device Use C and C together to deskew the flight times of various devices o
43. ry scan register between the TDI and TDO pins PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while the data captured is shifted out the preloaded data can be shifted in Document Number 001 00436 Rev E CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST The EXTEST instruction drives the preloaded data out through the system output pins This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift DR controller state EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tristate mode The boundary scan register has a special bit located at bit 108 When this scan cell called the extest output bus tristate is latched into the preload register during the Update DR state in the TAP controller it directly controls the state of the output Q bus pins when the EXT
44. s instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Document Number 001 00436 Rev E Page 17 of 30 Feedback Boundary Scan Order PERFORM CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 Bit Bump ID Bit Bump ID Bit Bump ID Bit ff Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B TT 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number 001 00436 Rev E Page 18 of 30 Feedback pd CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C15
45. safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTA
46. te Add Decode Aeuy 6 X Wr Aeuy 6 X Wr l gt Read Data Reg Address Register ZN A 21 0 Control Logic Read Add Decode CQ Us o Page 2 of 30 Feedback PERFORM Logic Block Diagram CY7C1512KV18 18 D 17 0 Ds A 21 Address 20 0 Register DOFF gt VREF gt WPS Control BWS Write Write gt Reg Reg Write Add Decode Kev 9L X WZ Kei 9L X WZ Read Data Reg CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 Read Add Decode A 20 0 Logic Block Diagram CY7C1514KV18 36 D 35 0 Write Write gt Reg Reg 20 Address A99 r Register CN Key OC X AL Key 9 X WL Write Add Decode gt Read Data Reg Read Add Decode VREF WPS BWS g 0 Control Logic Document Number 001 00436 Rev E A 19 0 lt RPS C C gt ca CO 38 Qr55 9 Page 3 of 30 Feedback Lc CY7C1510KV18 CY7C1525KV18 CYPRESS CY7C1512KV18 CY7C1514KV18 PERFORM Pin Configuration The pin configurations for CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 and CY7C1514KV18 follow I 165 Ball FBGA 13 x 15 x 1 4 mm Pinout CY7C1510KV18 8M x 8
47. th Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between TDI and TDO pins This enables shifting of data through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM Several No Connect NC pins are also included in the scan register to reserve pins for higher density devices The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions are used to capture the contents of the input and output ring The Boundary Scan Order on page 18 shows the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR
48. trols Dr o and NWS controls Dr a All the Nibble Write Selects are sampled on the same edge as the data Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device Byte Write Select 0 1 2 and 3 Active LOW Sampled on the rising edge of the K and K clocks during write operations Used to select which byte is written into the device during the current portion of the write operations Bytes not written remain unaltered CY7C1525KV18 BWSp controls Dr o CY7C1512KV18 BWS controls Dr a and BWS controls Dyz CY7C1514KV18 BWS controls D on BWS controls Dr ot BWS controls Djag 18 and BWS3 controls Dr35 271 Al the byte Write Selects are sampled on the same edge as the data Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device Input Synchronous Address Inputs Sampled on the rising edge of the K read address and K write address clocks during active read and write operations These address inputs are multiplexed for both read and write operations Internally the device is organized as 8M x 8 2 arrays each of 4M x 8 for CY7C1510KV18 8M x 9 2 arrays each of 4M x 9 for CY7C1525KV 18 4M x 18 2 arrays each of 2M x 18 for CY7C1512KV18 and 2M x 36 2 arrays each of 1M x 36 for CY7C1514KV 18 Therefore only 22 address inputs are needed to access the entire memory array of CY7C1510KV18 and CY7C1525KV 18 21 add

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