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Cypress CY7C1480V25 User's Manual

1. Document 38 05282 Rev H Page 16 of 32 Feedback CY7C1480V25 E CY7C1482V25 CYPRESS CY7C1486V25 PERFORM Boundary Scan Exit Order 4M x 18 Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID 1 D2 19 R8 37 C11 2 E2 20 P3 38 A11 3 F2 21 P4 39 A10 4 G2 22 P8 40 B10 5 J1 23 P9 41 A9 6 K1 24 P10 42 B9 7 L1 25 R9 43 A8 8 M1 26 R10 44 B8 9 N1 27 R11 45 A7 10 R1 28 M10 46 B7 11 R2 29 L10 47 B6 12 R3 30 K10 48 A6 13 P2 31 J10 49 B5 14 R4 32 H11 50 A4 15 P6 33 G11 51 B3 16 R6 34 F11 52 A3 17 N6 35 E11 53 A2 18 P11 36 D11 54 B2 Document 38 05282 Rev H Page 17 of 32 Feedback CY7C1480V25 CY7C1482V25 CYPRESS CY7C1486V25 PERFORM Boundary Scan Exit Order 1M x 72 Bit 209 Ball ID Bit 209 Ball ID Bit 209 Ball ID Bit 209 Ball ID 1 A1 29 T1 57 V10 85 C11 2 A2 30 T2 58 U11 86 C10 3 B1 31 U1 59 U10 87 B11 4 B2 32 U2 60 T11 88 B10 5 C1 33 V1 61 T10 89 A11 6 C2 34 2 62 R11 90 A10 7 D1 35 W1 63 R10 91 A9 8 D2 36 W2 64 P11 92 U8 9 E1 37 T6 65 P10 93 A7 10 E2 38 V3 66 N11 94 A5 11 F1 39 V4 67 N10 95 A6 12 F2 40 U4 68 M11 96 06 13 1 41 W5 69 M10 97 B6 14 G2 42 V6 70 L11 98 D7 15 H1 43 W6 71 L10 99 K3 16 H2 44 U3 72 P6 100 A8 17 J1 45 U9 73 J11 101 B4 18 J2 46 V5 74
2. 30 oT 2 Es W lt lt lt lt aL 9 8 lt lt lt lt lt lt lt 4 lt lt lt lt lt 42 lt lt 8 lt lt lt lt lt lt lt lt lt gt gt gt gt 2 5 Document 38 05282 Rev 4 of 32 Feedback CY7C1480V25 CY7C1482V25 CYPRESS CY7C1486V25 PERFORM Pin Configurations continued 165 Ball FBGA 15 x 17 x 1 4 mm Pinout CY7C1480V25 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A NC 288M A CE BWc BWg BWE ADSC ADV A NC NC 4M CE2 BWp BWA CLK GW ADSP NC 576M C DQPc NC Vppo Vss Vss Vss Vss Vss Vppo NC 1G D DQc DQc Vppo Vpp Vss Vss Vss Vpp Vppo DQg DQg E DQc DQc Vppa Vpp Vss Vss Vss Vpp VppQ DQg F DQc DQc Vppo Vpp Vss Vss Vss Vpp Vppo DQg G DQc DQc Vppo Vpp Vss Vss Vss Vpp Vppo Vpp Vss Vss Vss Vpp NC NC ZZ J DQp DQp Vppo Vpp Vss Vss Vss Vpp Vppo DQA DQA K DQp DQp Vppo Vpp Vss Vss Vss Vpp VDDQ DQA DQA L DQp DQp VDDQ VDD Vss Vss Vss VDD VDDQ DQA DQA M DQp DQp Vppa Vpp Vss Vss Vss Vpp Vppa DQa DQA N NC Voa Vss NC A NC Vss Vopo NC DQP P NC A A A TDI A1 TDO A A A A R MODE A A A TMS A0 TCK A A A A CY7C1482V25 4M x 18 1 2 3 4 5 6 7 8 9 10 11 A NC 288M A CE BWg NC BWE ADSC ADV A A NC
3. H DQc DQc Vss Vss Vss NC Vss Vss Vss J DQc DQc Vopo NC DQk K NC NC CLK NC Vss Vss Vss NC NC NC NC L DQH Vona Voo NC Vppa DQA M Vss Vss Vss NC Vss Vss Vss DQA DQA N DQy Vppo Voo NC Voo DQ P Vss Vss Vss 22 Vss Vss Vss DQA DQA R DQPp DQPH Voo Vpp Voo Vopo DQPe T DQp DQp Vss NC NC MODE NC NC Vss DQe U DQp DQp A A A A A A n DQe V DQp DQp A A A A1 A A A DQ w DQp DQp TMS TDI A A0 A TDO TCK Document 38 05282 Rev 6 of 32 Feedback Pin Definitions CY7C1480V25 CY7C1482V25 CY7C1486V25 Pin Name y o Description Ao A4 Input Address Inputs used to select one of the address locations Sampled at the rising Synchronous edge of the CLK if ADSP or ADSC is active LOW and CE4 and CE are sampled active A1 AO are fed to the two bit counter BWA BWg BWc Input Byte Write Select Inputs active LOW Qualified with BWE to conduct byte writes to the BWp BWg BWs Synchronous SRAM Sampled on the rising edge of CLK BWg BWy GW Input Global Write Enable Input active LOW When asserted LOW on the
4. _ P as lt s s gt W U SSE 00 207 ee T CY7C1480V25 CY7C1482V25 CY7C1486V25 YPRESS PERFORM Features Supports bus operation up to 250 MHz Available speed grades are 250 200 and 167 MHz Registered inputs and outputs for pipelined operation 2 5V core power supply 2 5V 1 8V IO operation Fast clock to output time 3 0 ns for 250 MHz device Provide high performance 3 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed writes Asynchronous output enable Single cycle chip deselect e CY7C1480V25 CY7C1482V25 available in JEDEC standard Pb free 100 pin TQFP Pb free and non Pb free 165 ball FBGA package CY7C1486V25 available in Pb free and non Pb free 209 ball FBGA package IEEE 1149 1 JTAG Compatible Boundary Scan ZZ Sleep Mode option Selection Guide 72 Mbit 2M x 36 4M x 18 1M x 72 Pipelined Sync SRAM Functional Description The CY7C1480V25 CY7C1482V25 CY7C1486V25 SRAM integrates 2M x 36 4 x 18 1M x 72 SRAM cells with advanced synchronous peripheral circuitry and a two bit counter for internal burst operation All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK The synchronous inputs include all
5. Note 22 Full width write can be initiated by either GW LOW or by GW HIGH BWE LOW and BWx LOW Document 38 05282 Rev H Page 23 of 32 Feedback CY7C1480V25 ass lt CY7C1482V25 7 CYPRESS CY7C1486V25 PERFORM i Switching Waveforms continued Read Write Cycle 21 23 24 m V d Eom Q mmmn JC p U I wi JI WX yu pum mm Ji s wi VU i 277 77777 ktoBak WRITES E FRR wc Not es 23 The data bus ES remains in high Z following a write cycle unless a new read access is initiated by ADSP or ADSC 24 GW is HIGH Page 24 of 32 Document 38 05282 Rev H Feedback CY7C1480V25 CY7C1482V25 CY7C1486V25 PERFORM Switching Waveforms continued ZZ Mode Timing gt 26 ye i te LP eg Ge uz ZZREC 77 Y tzz Supply 1 0077 ta AEE INPUTS DESELECT or READ Only except ZZ A DON T 25 Device must be deselected when entering ZZ mode See Truth Table 10 for all possible signal conditions to deselect the device Notes 26 DQs are in high Z when exiting ZZ sleep mode Document 38 05282 Rev H Page 25 of 32 Feedback CY7C1480V25 e CY7C1482V25 2 CYPRESS CY7C1486V25 l PERFORM Ordering Information
6. u CONTROL Logic Block Diagram CY7C1482V25 4M x 18 ADDRESS y AQ Al A REGISTER A 2 Alto MODE E CLK COUNTER AND LOGIC clr 00 LI ADSC SE Ul P DO amp DOPs w 000 m H WRITE DRIVER E N L dod SENSE OUTPUT AUTRUI Dos MEMORY AMPS BUFFERS lt DQPA ARRAY REGISTERS b DOA DOPA DQPs zur DOADOP A WRITE DRIVER 4 BWA WRITE REGISTER gt WE D am Em INPU GW ENABLE REGISTERS CE1 REGISTER PIPELINED ENABLE OF e zz SLEEP CONTROL Document 38 05282 Rev H Page 2 of 32 Feedback CY7C1480V25 CY7C1482V25 PRESS CY7C1486V25 PERFORM Logic Block Diagram CY7C1486V25 1M x 72 ADDRESS AG ALA REGISTER gt A 1 0 MODE ADV Q1 CLK BINARY COUNTER CLR Qo oS d ADSP D pap dm gt D tj WRITE DRIVER D e DRI
7. 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document 38 05282 Rev H Revised April 23 2007 CY7C1480V25 CY7C1482V25 CYPRESS 7 1486 25 PERFORM Logic Block Diagram CY7C1480V25 2M x 36 AO AA gt ADDRESS REGISTER MODE ADV q COUNTER AND LOGIC Ke SD ADSP 4 5 00000 000 000 BYTE 8 E ab ID WRITE REGISTER tD WRITE DRIVER DQPc Bwe TH a t WRI i IVER OUTPUT IB WRITE REGISTER E NEMORE OUTPUT D HY ARRAY sense L recsters m BUFFERS Bou __ DOs DOP Ks s i A E 00 ul WATE SEN L4 D 7 WRITE DRIVER l nds E REGISTE DQPp gt DOn DOPA DOn ROA ae WATE Rea L4 tl WE ANE t N INPU GW L p PIPELINED REGISTERS CE REGISTER ENABLE amp je li
8. o6 96 0 O OOG O H 8 1 E L N R A H 5 00 10 00 B 15 00 0 10 A 0 15 4X 51 85165 A Page 29 of 32 Feedback CY7C1480V25 CY7C1482V25 CY7C1486V25 PERFORM Package Diagrams continued Figure 3 209 Ball FBGA 14 x 22 x 1 76 mm 51 85167 22 A 51 85167 i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation All products and company names mentioned in this document may be the trademarks of their respective holders Document 38 05282 Rev H Page 30 of 32 Cypress Semiconductor Corporation 2002 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The in
9. Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Mh Ordering Code Diac Part and Package Type 167 CY7C1480V25 167AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 1 4 mm Pb Free Commercial CY7C1482V25 167AXC CY7C1480V25 167BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1482V25 167BZC CY7C1480V25 167BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1482V25 167BZXC CY7C1486V25 167BGC 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 CY7C1486V25 167BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free CY7C1480V25 167AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1482V25 167AXI CY7C1480V25 167BZl 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1482V25 167BZl CY7C1480V25 167BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1482V25 167BZXI CY7C1486V25 167BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1486V25 167BGXI 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free 200 CY7C1480V25 200AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1482V25
10. addresses all data inputs address pipelining Chip Enable CE4 depth expansion Chip Enables CE and CE3 Burst Control inputs ADSC ADSP and ADV Write Enables BWy and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC is active Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV Address data inputs and write controls are registered on chip to initiate a self timed Write cycle This part supports Byte Write operations see Pin Definitions on page 7 and Truth Table on page 10 for further details Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs When it is active LOW GW causes all bytes to be written The CY7C1480V25 CY7C1482V25 CY7C1486V25 operates from a 2 5V core power supply while all outputs may operate with either a 2 5 or 1 8V supply All inputs and outputs are JEDEC standard JESD8 5 compatible 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 3 0 3 0 3 4 ns Maximum Operating Current 450 450 400 mA Maximum CMOS Standby Current 120 120 120 mA Note 1 For best practices recommendations refer to the Cypress application note System Design Guidelines at www cypress com Cypress Semiconductor Corporation
11. ADV Setup Before CLK Rise 1 4 1 4 1 5 ns twes GW BWE BW Setup Before CLK Rise 1 4 1 4 1 5 ns tps Data Input Setup Before CLK Rise 1 4 1 4 1 5 ns tcEs Chip Enable Setup Before CLK Rise 1 4 1 4 1 5 ns Hold Times tay Address Hold After CLK Rise 0 4 0 4 0 5 ns tipi ADSP ADSC Hold After CLK Rise 0 4 0 4 0 5 ns tADVH ADV Hold After CLK Rise 0 4 0 4 0 5 ns twEH GW BWE BW Hold After CLK Rise 0 4 0 4 0 5 ns tpH Data Input Hold After CLK Rise 0 4 0 4 0 5 ns Chip Enable Hold After CLK Rise 0 4 0 4 0 5 ns Notes 15 Timing reference level is 1 25V when Vppq 2 5V and is 0 9V when Vppq 1 8V 16 Test conditions shown in a of AC Test Loads and Waveforms on page 20 unless otherwise noted 17 This part has a voltage regulator internally tpower is the time that the power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated 18 toyz tci z toELz and toguz are specified with AC test conditions shown in part b of AC Test Loads and Waveforms Transition is measured 200 mV from steady state voltage 19 At any possible voltage and temperature togpz is less than tog 7 and is less than to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z before Low Z under the same system conditions 2
12. En WA 51 js HHHHHHHHHHHHHHHHHHHH V 31 50 0 20 MAX 1 60 R 0 08 MIN 0 20 MAX m 0 MIN SEATING PLANE 0 1 0 05 MIN NOTE 0 15 GAUGE PLANE 1 JEDEC STD REF MS 026 i 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH aie MIN MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 MAX BODY LENGTH DIMENSIONS MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 020 MIN 1 00 REF 51 85050 B DETAIL A Document 38 05282 Rev H Page 28 of 32 Feedback PERFORM Package Diagrams continued TOP VIEW PIN 1 CORNER Figure 2 165 Ball FBGA 15 x 17 x 1 4 mm 51 85165 8 9 10 n Z 025C in E ge a 9 lol a 2 a 5 5 S PLANE Tod T 8 E S Document 38 05282 Rev H CY7C1480V25 CY7C1482V25 CY7C1486V25 BOTTOM VIEW PIN 1 CORNER amp g005MC Y gos MEAIB 0 45 0 05 165X 10 s E 7 6 S 4 3 2 1 A 1 1 eoooo ooood y oooogpooooo 2 8 D 3 O
13. L L Write Bytes L X X X X X Truth Table for Read Write The read write truth table for the CY7C1482V25 follows I Function GW BWE BWg BWA Read H H x x Read H L H H Write Byte A DQ and H L H L Write Byte B DQg and H L L H Write Bytes B A H L L L Write All Bytes H L L L Write All Bytes L X X X Truth Table for Read Write The read write truth table for the CY7C1486V25 follows 8 Function GW BWE BW Read H H X Read H L All BW H Write Byte x DQx and DQPx H L L Write All Bytes H L All BW L Write All Bytes L X X Note _ 8 BWx represents any byte write signal BW O 7 To enable any byte write BWx a Logic LOW signal must be applied at clock rise Any number of byte writes can be enabled at the same time for any given write Document 38 05282 Rev H Page 11 of 32 Feedback IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1480V25 CY7C1482V25 CY7C1486V25 incorpo rates a serial boundary scan test access port TAP This port operates in accordance with IEEE Standard 1149 1 1990 but does not have the set of functions required for full 1149 1 compliance These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149 1 fully compliant TAPs The TAP operates using JEDEC standar
14. Page 14 of 32 Feedback 2 CYPRESS j PERFORM 2 5V TAP AC Test Conditions CY7C1480V25 CY7C1482V25 CY7C1486V25 1 8V TAP AC Test Conditions Input pulse levels ree Vss to 2 5V Input pulse 0 2V to Vppo 0 2 Input rise and fall time ins Input rise and fall time ins Input timing reference levels 1 25V Input timing reference levels 0 9 Output reference levels 1 25V Output reference levels 0 9V Test load termination supply voltage 1 25V Test load termination supply voltage 0 9V 2 5V TAP AC Output Load Equivalent 1 8V TAP AC Output Load Equivalent 1 25V 0 9V 500 500 TDO TDO Zg 500 20pF Zo 500 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt Ta lt 70 Vpp 2 5V 0 125V unless otherwise noted Parameter Description Test Conditions Min Max Unit Vou Output HIGH Voltage lop 1 0 mA Vppo 7 2 5V 1 7 V Output HIGH Voltage lop 100 pA Vppo 2 5V 2 1 V Vppo 1 8V 1 6 V Output LOW Vo
15. cycle 250 MHz 200 mA Power Down Vin lt 0 3V or Vin gt Vppo 0 3V 5 Current CMOS Inputs f 1 iis cycle 200 MHz 200 6 0 cycle 167 MHz 200 Ispa Automatic CE Vpp Max Device Deselected All speeds 135 mA Power Down Vin gt or Vin lt f 0 Current TTL Inputs Notes 12 Overshoot lt Vpp 1 5V Pulse width less than 2 undershoot AC gt 2V Pulse width less than tcyc 2 13 Power up Assumes a linear ramp from OV to Vpp min within 200 ms During this time lt Vpp and lt Vpp Document 38 05282 Rev H Page 19 of 32 Feedback CY7C1480V25 CY7C1482V25 Say CYPRESS CY7C1486V25 PERFORM Capacitance 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Package Package Package Unit CADDRESS Address Input Capacitance TA 25 C f 1 MHz 6 6 6 pF Vpp 2 5 CDATA Data Input Capacitance 2 5V 5 5 5 CcTRL Control Input Capacitance 8 8 8 pF Clock Input Capacitance 6 6 6 pF Cio Input Output Capacitance 5 5 5 pF Thermal Resistance m 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Max Max Max Unit Thermal Resistance Test conditions follow 24 63 16 3 15 2 C W Junction to Ambient standard test methods and procedures for measu
16. data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The x36 configuration has a 73 bit long register and the x18 configuration has a 54 bit long register The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller moves to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in Identification Register Defini tions on page 15 TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are li
17. ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures the IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the IO ring contents Places the boundary scan register between TDI and TDO Does not affect SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operations Boundary Scan Exit Order 2M x 36 Bit 165 Ball ID Bit 165 Ball ID Bit 165 BallID Bit 165 Ball ID 1 C1 21 R3 41 L10 61 B8 2 D1 22 P2 42 K11 62 A7 3 E1 R 43 JM 63 B7 4 D2 24 P6 44 K10 64 B6 5 E2 25 R6 45 J10 65 A6 6 F1 26 46 H11 66 B5 7 G1 27 P11 47 G11 67 A5 8 F2 28 R8 48 F11 68 A4 G 239 P 48 EM 69 B4 10 J1 30 P4 50 D10 70 B3 11 K1 31 P8 51 D11 71 A3 102 11 32 P9 52 C11 72 A2 13 J2 33 P10 53 G10 73 B2 14 M1 34 R9 54 F10 15 N1 35 R10 55 E10 16 K2 36 R11 56 A10 17 L2 37 N11 57 B10 18 M 38 M11 58 A49 19 R1 39 L11 59 B9 20 R2 40 M10 60 A8
18. rising edge of CLK Synchronous a global write is conducted ALL bytes are written regardless of the values on BWy and BWE BWE Input Byte Write Enable Input active LOW Sampled on the rising edge of CLK This signal Synchronous must be asserted LOW to conduct a byte write CLK Input Clock Input Captures all synchronous inputs to the device Also increments the burst Clock counter when ADV is asserted LOW during a burst operation CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in _ Synchronous conjunction with CE and to select deselect the device ADSP is ignored if CE is HIGH CE is sampled only when a new external address is loaded Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in Synchronous conjunction with CE and CE3 to select deselect the device CE is sampled only when a new external address is loaded CE Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in Synchronous conjunction with CE and CE to select deselect the device CE3 is sampled only when a new external address is loaded OE Input Output Enable asynchronous input active LOW Controls the direction of the IO pins Asynchronous When LOW the IO pins behave as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state ADV Input Advance Input
19. signal sampled on the rising edge of CLK active LOW When Synchronous asserted it automatically increments the address in a burst cycle ADSP Input Address Strobe from Processor sampled on the rising edge of CLK active LOW Synchronous When asserted LOW addresses presented to the device are captured in the address registers A1 AO are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deasserted HIGH ADSC Input Address Strobe from Controller sampled on the rising edge of CLK active LOW Synchronous X When asserted LOW addresses presented to the device are captured in the address registers A1 AO are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ZZ Input ZZ sleep Input active HIGH When asserted HIGH places the device in a Asynchronous non time critical sleep condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down DQs DQPs I O Bidirectional Data IO lines As inputs they feed into an on chip data register that is Synchronous triggered by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When
20. 0 This parameter is sampled and not 100 tested Document 38 05282 Rev H Page 21 of 32 Feedback CY7C1480V25 CY7C1482V25 CYPRESS CY7C1486V25 PERFORM Switching Waveforms Read Cycle Timing lt HH ruf w v RE V V 07 7 ir v 0 v Y RE tas tADVS tADVH s gt um m vw n Im mI mm toyz 1 Q A2 2 NK owe 3 XX Q A2 Ww 1 L L Burst wra to its initi ps around BURST READ Note 21 On this diagram when CE is LOW CE is LOW CE is HIGH and CE is LOW When CE is HIGH CE is HIGH or is LOW or CE is HIGH Document 38 05282 Rev H Page 22 of 32 Feedback CY7C1480V25 CY7C1482V25 VEZ CYPRESS 7 1486 25 Switching Waveforms continued tces Write Cycle Timing 22 Eh nm za Cr CU ZW ow wo wow LZ Vw V Z y es arm mamam OXIDE lt 7 vz Lm m ur OO KARA Wo mum Za ZZ UI mum zz Data In D High Z D A1 D A2 NOK ow Wom DE DE D A3 1 Xs D A3 2 OEHZ lt n KC C L BURST READ Single WI BURST WRITE dis ded wi j eo BH DONT CARE UNDEFINED
21. 200AXC CY7C1480V25 200BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1482V25 200BZC CY7C1480V25 200BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1482V25 200BZXC CY7C1486V25 200BGC 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 CY7C1486V25 200BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free CY7C1480V25 200AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1482V25 200AXI CY7C1480V25 200BZl 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1482V25 200BZl CY7C1480V25 200BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1482V25 200BZXI CY7C1486V25 200BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1486V25 200BGXI 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free Document 38 05282 Rev H Page 26 of 32 Feedback CY7C1480V25 CY7C1482V25 EESZCYPRES CY7C148V25 Ordering Information continued Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Mo Ordering Code biegen Part and Package Type 250 CY7C1480V25 250AXC 51 85050 100 Pin Thin Quad Flat Pack 14 20 1 4 mm Lead Free Commercial CY7C1482V25 2
22. 25 TOW 95 ma we 955 l8 Bliss 2 8 al lt lt lt lt E 0 o 8 lt nnnm 88588298558885888885 8095 DOPcI 1 80 L3 DQPB NC C r 2 79 pos NC C 2 79 Fo NC DQc 78 F3 NC C 3 78 Fo NC Vppa 4 77 Vppa 4 E3 Vssa CH 5 76 1 Vsso 5 76 E31 Vaso DQc r 6 75 DQB 6 75 NC 7 74 F3 NC 7 74 E papa DQc g 73 Fo C4 g 73 Daa 9 72 F3 9 72 DOA Vssa 4 10 71 F4 Vsso Vssq 4 10 71 F Vesa 11 70 F3 L 44 70 E Dac gt 42 69 45 E pas Dac 43 68 L 43 67 Vss NC gt 14 67 2 Veg w CL 5 CY7C1480V25 CY7C1482V25 es E DD L3 Vss 17 2M x 36 ea Ez v E qe 4M x 18 L 4 18 63 L3 DOB 4g 63 Dan L 49 62 Das 4g 62 3 Daa 20 61 Vppa 4 20 61 Vona Vsso 21 60 F Vssa Vssa 4 21 60 Vssa Da 22 59 DQB 22 59 pas 23 58 DQa L 23 58 Es DOA Dan 24 57 E DQA DQPB 54 57 NC CH 55 56 L3 Daa NC E 55 a era a 55 H Vssa 26 55 27 54 F 27 54 E 28 53 L3 58 53 Dan M 29 52 F3 NC 29 52 E NC
23. 50AXC CY7C1480V25 250BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1482V25 250BZC CY7C1480V25 250BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Lead Free CY7C1482V25 250BZXC CY7C1486V25 250BGC 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 CY7C1486V25 250BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Lead Free CY7C1480V25 250AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1482V25 250AXI CY7C1480V25 250BZl 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1482V25 250BZl CY7C1480V25 250BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 17 x 1 4 mm Lead Free CY7C1482V25 250BZXI CY7C1486V25 250BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1486V25 250BGXI 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Lead Free Document 38 05282 Rev H Page 27 of 32 Feedback CY7C1480V25 CY7C1482V25 amp CYPRESS _ CY7Ci486V25 PERFORM Package Diagrams Figure 1 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 lt 14004010 Pl 1 40 0 05 100 81 BHHHHHRHRHHRHRHRHHRHHRH 1afo n 80 E 0 30 0 08 21 g g ES A 8 E E d i En 0 65 12 1 E SEE DETAIL A TYP 8X
24. A44MM BWA CLK GW ADSP A NC 576M C NC NC Vppo Vss Vss Vss Vss Vss Vppo NC 1G DQPA D NC DQg Vpp Vss Vss Vss Vpp Vppo NC DQA E NC VDDQ VDD Vss Vss Vss VDD VDDQ NC DQA F NC Vpp Vss Vss Vss Vpp Vppo NC DQA G NC DQg Vppo Vpp Vss Vss Vss Vpp Vppo NC DQA H NC NC NC Vpp Vss Vss Vss Vpp NC NC 22 J DQg NC Vppo Vpp Vss Vss Vss Vpp Vppo DQA NC K DQg NC Vppo Vpp Vss Vss Vss Vpp Vppo DQA NC L DQg NC VDDQ VDD Vss Vss Vss VDD DQA NC M DQg NC Vppo Vpp Vss Vss Vss Vpp Vppo DQA NC N DQPp NC Vppo Vss NC A NC Vss Vppo NC NC P NC A A A TDI A1 TDO A A A A R MODE A A A TMS TCK A A A A Document 38 05282 Rev H Page 5 of 32 Feedback CY7C1480V25 CY7C1482V25 CYPRESS CY7C1486V25 PERFORM Pin Configurations continued 209 Ball FBGA 14 x 22 x 1 76 mm Pinout CY7C1486V25 1M x 72 1 2 3 4 5 6 7 8 9 10 11 DQG DQ A CE ADSP ADSC ADV CE DQg B DQg 006 BWS NC 288M BWE A BWSg BWSe DQg C DQG DQg BWS BWSp NC 144M CE NC 576M BWS_ BWS DQg D DQg DQ Vss NC 1 OE GW NC Vss DQg DQg F DQPcG DQPc Vpp Voo DQc DQc Vss Vss Vss NC Vss Vss Vss G DQc DQc Vppa Voo NC Vova
25. HIGH DQs and DQPy are placed in a tri state condition Vpp Power Supply Power supply inputs to the core of the device Vss Ground Ground for the core of the device Ground Ground for the I O circuitry Vppo I O Power Supply Power supply for the I O circuitry Note 2 Applicable for TQFP package For BGA package Vss serves as ground for the core and the IO circuitry Document 38 05282 Rev H Page 7 of 32 Feedback Pin Definitions continued CY7C1480V25 CY7C1482V25 CY7C1486V25 Pin Name Description MODE Input Static Selects Burst Order When tied to GND selects linear burst sequence When tied to Vpp or left floating selects interleaved burst sequence This is a strap pin and must remain static during device operation Mode pin has an internal pull up TDO JTAG Serial Serial data out to the JTAG circuit Delivers data on the negative edge of TCK If the Output JTAG feature is not used this pin must be disconnected This pin is not available on TQFP Synchronous packages TDI JTAG Serial Input Serial data In to the JTAG circuit Sampled on the rising edge of TCK If the JTAG feature Synchronous is not used this pin can be disconnected or connected to Vpp This pin is not available on TQFP packages TMS JTAG Serial Input Serial data In to the JTAG circuit Sampled on the rising edge of TCK If the JTAG feature Synchronous is not used this pin can be disconnected or co
26. J10 102 B3 19 L1 47 U5 75 H11 103 C3 20 L2 48 U6 76 H10 104 C4 21 M1 49 W7 77 G11 105 C8 22 M2 50 V7 78 G10 106 C9 23 N1 51 U7 79 F11 107 B9 24 N2 52 V8 80 F10 108 B8 25 P1 53 v9 81 E10 109 A4 26 P2 54 w11 82 E11 110 C6 27 R2 55 W10 83 D11 111 B7 28 R1 56 V11 84 D10 112 A3 Document 38 05282 Rev H Page 18 of 32 Feedback CY7C1480V25 CY7C1482V25 CYPRESS CY7C1486V25 PERFORM Maximum Ratings DC Input Voltage 0 5V to Vpp 0 5V C t into Outputs LOW eee 20 mA Exceeding the maximum ratings may impair the useful life of ad n s Mut am the device These user guidelines are not tested Static Discharge Voltage AA DTE EE gt 2001V Storage Temperature 65 C to 150 C jua Method sets Ambient Temperature with atch Up Current u uuu rires gt 200 m Power 55 C to 125 Operating Range Supply Voltage on Vpp Relative to GND 0 3V to 3 6V Ambi Range mbient M M Supply Voltage on Vppo Relative to GND 0 3V to Vpp Temperature DD DDQ DC Voltage Applied to Outputs Commercial 0 C to 70 C 2 5V 5 5 1 7V to 0 5V to Vppo 0 5V Industrial 40 C to 85 Vpp Electrical Characteri
27. TDO balls The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Test Clock TCK 3 4 gt Test Mode Select XX TMS pis Test Data In yi Vi XX X XX TD ov p T Test Data Out KA WY Ya XN TDO DON T CARE KM UNDEFINED AC Switching Characteristics Over the Operating Rangel 10 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns tt TCK Clock Frequency 20 MHz Clock HIGH time 20 ns tr TCK Clock LOW time 20 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns Setup Times ttuss TMS Setup to TCK Clock Rise 5 ns trpis TDI Setup to TCK Clock Rise 5 ns tcs Capture Setup to TCK Rise 5 ns Hold Times trMSH TMS Hold after TCK Clock Rise 5 ns trpiH TDI Hold after Clock Rise 5 ns tcH Capture Hold after Clock Rise 5 ns Notes 9 tcs and refer to the setup and hold time requirements of latching data from the boundary scan register 10 Test conditions are specified using the load in AC Test Conditions tg te 1 ns Document 38 05282 Rev H
28. VER DOPF DQc qu X D WRITE DRIVER J t1 e WRITE DRIVER 87 DQr DOPr L N por L MEE D 4 WRITE DRIVER p WRITE DRIVER r e DQe DOPE L N pos pop BWe WRITE DRIVER t5 m py WRITE DRIVER v MEMORY D ARRAY DQp DQPp L N S WRITE DRIVER D m WRITE DRIVER HD DQc DQPc DQc DOPc 7 BWc a WRITE DRIVER WRITE DRIVER OUTPUT OUTPUT H iD REGISTERS GE 7 DQs DQPs uN DOS DOPE 2 1 i DQPs um LN WRITE DRIVER DRIVER DOPc D 41 DQPo DQa DOPE BWa LN DOA DOPA mA WRITE DRIVER DOP WRITE DRIVER DQPG BWE 1 DQPH 16 INPUT Gw EGISTERS as 4 PPIPELINED DN 7 j SLEEP 2 CONTROL Document 38 05282 Rev H Page 3 of 32 Feedback CY7C1480V25 CY7C1482V25 PRESS CY7C1486V25 PERFORM i Pin Configurations 100 Pin TQFP Pinout a sss Eu
29. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH before the start of the write cycle to enable the outputs to tri state OE is a don t care for the remainder of the write cycle _ 7 OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle all data bits are tri state when OE is inactive or when the device is deselected and all data bits behave as output when OE Is active LOW w Document 38 05282 Rev H Page 10 of 32 Feedback CY7C1480V25 CY7C1482V25 CYPRESS CY7C1486V25 PERFORM Truth Table for Read Write The read write truth table for the CY7C1480V25 follows P Function GW BWE BWp BWc BWg BWA Read H H X X X X Read H L H H H H Write Byte A DQ4 and DQPA H L H H H L Write Byte B DQg and H L H H L H Write Bytes B A H L H H L L Write Byte C DQc and DQPc H L H L H H Write Bytes C A H L H L H L Write Bytes C B H L H L L H Write Bytes C B A H L H L L L Write Byte D DQp and DQPp H L L H H H Write Bytes D A H L L H H L Write Bytes D B H L L H L H Write Bytes D B A H L L H L L Write Bytes D C H L L L H H Write Bytes D C A H L L L H L Write Bytes D C B H L L L L H Write Bytes H L L L
30. ampled on the rising edge of TCK You can leave this ball unconnected if the TAP is not used The ball is pulled up inter nally resulting in a logic HIGH level Test Data In TDI The TDI ball serially inputs information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see the TAP Controller State Diagram TDI is internally pulled up and can be uncon nected if the TAP is unused in an application TDI is connected to the most significant bit MSB of any register See TAP Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See TAP Controller State Diagram TAP Controller Block Diagram o Bypass Register spl Instruction Register Selection Circuitry Selection TDI Circuitry TDO 313029 1 1 121110 Identification Register Boundary Scan Register tt tt t ttt TAP CONTROLLER m x TCK TMS Performing a TAP Reset Perform a RESET by forcing TMS HIGH Vpp fo
31. ble 470723 VKN Added the Maximum Rating for Supply Voltage on Vppo Relative to GND Document 38 05282 Rev H Page 31 of 32 Feedback CY7C1480V25 CY7C1482V25 Sa CYPRESS CY7C1486V25 PERFORM Document Title CY7C1480V25 CY7C1482V25 CY7C1486V25 72 Mbit 2M x 36 4M x 18 1M x 72 Pipelined Sync SRAM Document Number 38 05282 REV NO Issue Date Orig of Description of Change Change p g G 486690 See ECN VKN Corrected the typo in the 209 Ball FBGA pinout Corrected the ball name H9 to Vss from Vaso H 1026720 See VKN KKVTMP Added footnote 2 related to Vaso Document 38 05282 Rev H Page 32 of 32 Feedback
32. clusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CY7C1480V25 CY7C1482V25 EEZCYPRES CY7C148V25 Document History Page Document Title CY7C1480V25 CY7C1482V25 CY7C1486V25 72 Mbit 2M x 36 4M x 18 1M x 72 Pipelined Sync SRAM Document Number 38 05282 REV NO Issue Date Coa Description of Change a 114670 08 06 02 PKS New Data Sheet 118281 01 21 03 HGK Changed tco from 2 4 to 2 6 ns for 250 MHz Updated features on page 1 for package offering Removed 300 MHz offering Updated Ordering Information Changed Advanced Information to Preliminary 233368 NJY Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified Functional Overview section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Included IDD and ISB values Removed 250 MHz speed grade offering and included 225 MHz speed bin Changed package outline for 165 package and 209 ball BGA package Removed 119 BGA package offering C 299452 See ECN SYT Removed 225 MHz offering and included 250 MHz speed bin Changed tcyc from 4 4 ns to 4 0 ns for 250 MHz Speed Bin Changed j from 16 8 to 24 63 C W and jc from 3 3 to 2 28 C W for 100 TQFP Package on Page 20 A
33. d 2 5V or 1 8V I O logic levels The CY7C1480V25 CY7C1482V25 CY7C1486V25 contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent device clocking TDI and TMS are internally pulled up and may be unconnected They may alternatively be connected to Vpp through a pull up resistor TDO must be left unconnected At power up the device comes up in a reset state which does not interfere with the operation of the device TAP Controller State Diagram 1 RUR TEST 1 TEST LOGIC RESET 0 SELECT 1 SELECT 1 DR SCAN IR SCAN 0 0 Y Y CAPTURE IR CAPTURE DR UPDATE IR To UPDATE DR 1 0 The 0 1 next to each state represents the value of TMS at the rising edge of TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Document 38 05282 Rev H CY7C1480V25 CY7C1482V25 CY7C1486V25 Test Mode Select TMS The TMS input gives commands to the TAP controller and is s
34. dded lead free information for 100 Pin TQFP 165 FBGA and 209 BGA Packages Added comment of Lead free BG packages availability below the Ordering Information D 323039 See ECN PCI Unshaded 200 and 167 MHz speed bin in the AC DC Table and Selection Guide Address expansion pins balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Added Truth Table and Note 7 for CY7C1486V25 on page 11 Modified Vo Test Conditions Added Industrial temperature range Removed comment of Lead free BG packages availability below the Ordering Information Updated Ordering Information Table E 416193 See ECN NXR Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed the description of lx from Input Load Current to Input Leakage Current on 19 Changed the lx current values of MODE on page 19 from 5 uA and 30 uA to 30 uA and 5 pA Changed the Ix current values of ZZ on page 19 from 30 uA and 5 uA to 5 uA and 30 pA Changed lt Vpp to lt Vpp on page 19 Replaced Package Name column with Package Diagram in the Ordering Information table Updated the Ordering Information Table Changed trr tr from 25 ns to 20 ns and trpov from 5 ns to 10 ns TAP AC Switching Characteristics table Updated the Ordering Information ta
35. e Write Select BWy inputs A Global Write Enable GW overrides all byte write inputs and writes data to all four bytes All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Selects CE4 CE3 and an asynchronous Output Enable OE provide easy bank selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise 1 ADSP or ADSC is asserted LOW 2 CE4 CE2 are all asserted active and 3 the write signals GW BWE are all deasserted HIGH ADSP is ignored if is HIGH The address presented to the address inputs A is stored into the address advancement logic and the Address Register while being presented to the memory array The Document 38 05282 Rev H corresponding data is allowed to propagate to the input of the Output Registers At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3 0 ns 250 MHz device if OE is active LOW The only exception occurs when the SRAM is emerging from a deselected state to a selected state its outputs are always tri stated during the first cycle of the access After the first cycle of the access the outputs are controlled by the OE signal Consecutive single read cycles are supported After the SRAM is deselected at clock rise by t
36. he MODE input u Og 1 Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence Both Read and Write burst operations are supported ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit 15077 Sleep Standby Current ZZ gt Vpp 0 2V 120 mA 1775 Device Operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzzREC ZZ Recovery Time ZZ lt 0 2V 2tcyc ns tzzi ZZ Active to Sleep Current This parameter is sampled 2tcyc ns 577 ZZ Inactive to Exit Sleep Current This parameter is sampled 0 ns Document 38 05282 Rev H Page 9 of 32 CY7C1480V25 e CY7C1482V25 h PERFORM Truth Table The truth table for CY7C1480V25 CY7C1482V25 and CY7C1486V25 follows I 5 6 7 2 CYPRESS CY7C1486V25 Operation Add Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle Power Down None H X X L X L X X X L H Tri State Deselect Cycle Power Down None L L X L L X X X X L H Tri State Deselect Cycle Power Down None L X H L L X X X X L H Tri State Deselect Cycle Power Down None L L X L H L X X X L H Tri State Deselect Cycle Power Down None L X H L H L X X X L H Tri State Sleep Mode Power Down None X X X H X X X X X X Tri State Read Cycle Begin Burst Externa
37. he chip select and either ADSP or ADSC signals its output will tri state immediately Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise 1 ADSP is asserted LOW and 2 CE4 CEs are all asserted active The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array The write signals GW BWE and BWy ADV inputs are ignored during this first cycle ADSP triggered write accesses require two clock cycles to complete If GW is asserted LOW on the second clock rise the data presented to the DQs inputs is written into the corre sponding address location in the memory array If GW is HIGH then the write operation is controlled by the BWE and BW signals The CY7C1480V25 CY7C1482V25 CY7C1486V25 provides Byte Write capability that is described in the Truth Table for Read Write on page 11 Asserting the Byte Write Enable input BWE with the selected Byte Write BW input will selec tively write to only the desired bytes Bytes not selected during a byte write operation remain unaltered A synchronous self timed write mechanism has been provided to simplify the write operations Because CY7C1480V25 CY7C1482V25 CY7C1486V25 is a common IO device the Output Enable OE must be deasserted HIGH before presenting data to the DQs inputs Doing so tri states the out
38. l L H L L L x x X L L H Q Read Cycle Begin Burst External L H L L L X X X H L H Tri State Write Cycle Begin Burst External L H L L H L X L X L H D Read Cycle Begin Burst External L H L L H L X H L L H Q Read Cycle Begin Burst External L H L L H L X H H L H Tri State Read Cycle Continue Burst Next X X X L H H L H L L H Q Read Cycle Continue Burst Next X X X L H H L H H L H Tri State Read Cycle Continue Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burst Current H X X L X H H H L L H Q Read Cycle Suspend Burst Current H X X L X H H H H L H Tri State Write Cycle Suspend Burst Current X X X L H H H L X L H D Write Cycle Suspend Burst Current H X X L X H H L X L H D Notes X Don t Care H Logic HIGH L Logic LOW WRITE L when any or more Byte Write Enable signals BWE L GW L WRITE when all Byte Write Enable signals BWE GW The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock The SRAM always initiates a read cycle when ADSP is asserted regardless of the state of GW BWE or BWx
39. ltage lo 1 0 mA Vppo 2 5V 0 4 V Voi2 Output LOW Voltage 1 100 Vppo 2 5V 0 2 V Vppo 1 8V 0 2 V Input HIGH Voltage Vppo 2 5V 1 7 Vpp 0 3 V Vppo 1 8V 1 26 Vpp 0 3 V Vi Input LOW Voltage Vppo 2 5V 0 3 0 7 V Vppo 1 8V 0 3 0 36 V Ix Input Load Current GND lt Vi lt Vppa 5 5 uA Identification Register Definitions Instruction Field x36 x 48 x72 Description Revision Number 31 29 000 000 000 Describes the version number Device Depth 28 24 01011 01011 01011 Reserved for internal use Architecture Memory 000000 000000 000000 Defines memory type and Type 23 18 architecture Bus Width Density 17 12 100100 010100 110100 Defines width and density Cypress JEDEC ID Code 00000110100 00000110100 00000110100 Enables unique identification 11 1 of SRAM vendor ID Register Presence 1 1 1 Indicates the presence of an Indicator 0 ID register Note 11 All voltages referenced to Vss GND Document 38 05282 Rev H Page 15 of 32 Feedback CYPRESS j PERFORM Scan Register Sizes CY7C1480V25 CY7C1482V25 CY7C1486V25 Register Name Bit Size x36 Bit Size x18 Bit Size x72 Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order 165FBGA 73 54 Boundary Scan Order 209BGA 112 Identification Codes Instruction Code Description EXTEST 000 Captures the IO
40. nnected to Vpp This pin is not available on TQFP packages TCK JTAG Clock Clock input to the JTAG circuitry If the JTAG feature is not used this pin must be connected to Vss This pin is not available on TQFP packages NC No Connects Not internally connected to the die 144M 288M 576M and 1G are address expansion pins and are not internally connected to the die Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise tco is 3 0 ns 250 MHz device The CY7C1480V25 CY7C1482V25 CY7C1486V25 supports secondary cache in systems using either a linear or inter leaved burst sequence The interleaved burst order supports Pentium and i486 processors The linear burst sequence is suited for processors that use a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses can be initiated with either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte write operations are qualified with the Byte Write Enable BWE and Byt
41. put returns LOW Interleaved Burst Address Table MODE Floating or Vpp address location in the memory core If a byte write is First Second Third Fourth conducted only the selected bytes are written Bytes not Address Address Address Address selected during a byte write operation remain unaltered A A1 A0 A1 A0 A1 A0 A1 A0 synchronous self timed write mechanism has been provided 00 01 10 11 to simplify the write operations 01 00 10 Because CY7C1480V25 CY7C1482V25 CY7C1486V25 is a 10 11 50 01 common IO device the Output Enable must deasserted HIGH before presenting data to the DQs inputs 11 10 01 00 Doing so tri states the output drivers As a safety precaution DQs are automatically tri stated whenever a write cycle is detected regardless of the state of OE Linear Burst Address Table Burst Sequences MODE B GND First Second Third Fourth The CY7C1480V25 CY7C1482V25 CY7C1486V25 provides Address Address Address Address a two bit wraparound counter fed by A1 A0 that implements A1 A0 A1 A1 either interleaved linear burst sequence The interleaved burst sequence is designed specificaly to support Intel 00 01 10 11 Pentium applications The linear burst sequence is designed 01 10 11 00 to support processors that follow a linear burst sequence The 10 11 00 01 burst sequence is user selectable through t
42. put drivers As a safety precaution Page 8 of 32 Feedback DQs are automatically tri stated whenever a write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following condi tions are satisfied 1 ADSC is asserted LOW 2 ADSP is deasserted HIGH 3 CE4 CE are all asserted active and 4 the appropriate combination of the write inputs GW BWE and BWy are asserted active to conduct a write to the desired byte s ADSC triggered write accesses need a single clock cycle to complete The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array The ADV input is ignored during this cycle If a global write is conducted the data presented to the DQs is written into the corresponding CY7C1480V25 CY7C1482V25 CY7C1486V25 Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE4 CE3 ADSP and ADSC must remain inactive for the duration of tzzggc after the ZZ in
43. r five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls and enable data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Page 12 of 32 Feedback Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 12 At power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to enable fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This enables
44. requencies itis possible that during the Capture DR state an input or output may undergo a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that may be captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold time tcs plus Page 13 of 32 Feedback The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the into the Shift DR state This places the boundary scan register between the TDI and TDO balls Note that because the PRELOAD part of the command is not implemented putting the TAP to the Update DR state while performing a SAMPLE PRELOAD instruction has the same effect as the Pause DR command TAP Timing CY7C1480V25 CY7C1482V25 CY7C1486V25 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and
45. ring uc thermal impedance 228 2 1 d EIA JESD51 AC Test Loads and Waveforms 2 5V I O Test Load R 16670 OUTPUT 2 5 ALL INPUT PULSES OUTPUT 500 5 pF R 15830 1 25V INCLUDING JIG AND c a 0 4 8V R 14KQ OUTPUT 500 5 pF R 14KQ 0 9V INCLUDING JIG AND c a 0 Note 14 Tested initially and after any design or process change that may affect these parameters Document 38 05282 Rev H Page 20 of 32 Switching Characteristics Over the Operating Rangel 16 CY7C1480V25 CY7C1482V25 CY7C1486V25 Parameter Description ee Unit Min Max Min Max Min tpowER Vpp Typical to the first access 7 1 1 1 ms Clock Clock Cycle Time 4 0 5 0 6 0 ns tcH Clock HIGH 2 0 2 0 2 4 ns tcL Clock LOW 2 0 2 0 2 4 ns Output Times tco Data Output Valid After CLK Rise 3 0 3 0 3 4 ns Data Output Hold After CLK Rise 1 3 1 3 1 5 ns telz Clock to Low z 8 19 20 1 3 1 3 1 5 ns tcHz Clock to High z 8 19 20 3 0 3 0 3 4 ns toEV OE LOW to Output Valid 3 0 3 0 3 4 ns toELZ OE LOW to Output Low zl 19 20 0 0 0 ns loEHz OE HIGH to Output 2118 19 20 3 0 3 0 34 ns Setup Times tas Address Setup Before CLK Rise 1 4 1 4 1 5 ns taps ADSC ADSP Setup Before CLK Rise 1 4 1 4 1 5 ns tapvs
46. s if a SAMPLE PRELOAD instruction has been loaded There is one difference between the two instructions Unlike the SAMPLE PRELOAD instruction EXTEST places the SRAM outputs in a High Z state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is in a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state It also places all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction The PRELOAD portion of this instruction is not implemented so the device TAP controller is not fully 1149 1 compliant When the SAMPLE PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register Be aware that the TAP controller clock can only operate at a frequency up to 10 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock f
47. sted in Identification Codes on page 16 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in detail below The TAP controller used in this SRAM is not fully compliant to the 1149 1 convention because some of the mandatory 1149 1 instructions are not fully implemented The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers The SRAM does not implement the 1149 1 commands EXTEST or INTEST or the PRELOAD portion of Document 38 05282 Rev H CY7C1480V25 CY7C1482V25 CY7C1486V25 SAMPLE PRELOAD rather it performs a capture of the IO ring when these instructions are executed Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction after it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST EXTEST is a mandatory 1149 1 instruction that is to be executed whenever the instruction register is loaded with all 05 EXTEST is not implemented in this SRAM TAP controller and therefore this device is not compliant to 1149 1 The TAP controller does recognize an all 0 instruction When an EXTEST instruction is loaded into the instruction register the SRAM responds a
48. stics Over the Operating Rangel 13 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 2 375 2 625 V Vppo IO Supply Voltage for 2 5V IO 2 375 Vpp V for 1 8V IO 1 7 1 9 V Vou Output HIGH Voltage for 2 5V IO 1 0 mA 2 0 V for 1 8V IO 100 1 6 V VoL Output LOW Voltage for 2 5V IO Io 1 0 mA 0 4 V for 1 8V IO lo 100 uA 0 2 V Vin Input HIGH Voltagel 2 for 2 5V IO 1 7 Vpp t 0 3V V for 1 8V IO 1 26 Vpp 0 3V V ViL Input LOW Voltage for 2 5V IO 0 3 0 7 V for 1 8V IO 0 3 0 36 V lx Input Leakage Current GND lt lt Vppo 5 5 except ZZ and Input Current of MODE Vss 30 uA Input Vpp 5 uA Input Current of ZZ Input Vss 5 uA Input Vpp 30 loz Output Leakage Current GND lt V lt Vppo Output Disabled 5 5 155 Vpp Operating Supply Vpp Max lour 0 mA 4 0 ns cycle 250 MHz 450 mA Current f fmax 1 5 0 ns cycle 200 MHz 450 mA 6 0 ns cycle 167 MHz 400 mA Isp1 Automatic CE Vpp Max Device Deselected 4 0 ns cycle 250 MHz 200 mA Power Down Vin gt or Vin lt Vi Current TTL Inputs f fmax 1 2 0 n 200 200 6 0 cycle 167 MHz 200 15 2 Automatic Vpp Max Device Deselected All speeds 120 mA Power Down Vin lt 0 3V or Vin gt Vpno 0 3V Current CMOS Inputs f 0 Isp3 Automatic CE Vpp Max Device Deselected or 4 0 ns

Cypress CY7C1480V25 User's Manual

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