Cypress CY7C1329H User's Manual
Contents
1. Maximum Ratings DC Input 0 5V to Vpp 0 5V Abavewiicihieasetullifednaycbe impaled Rorusenguid Current into Outputs LOW 20 mA lines not tested Static Discharge Voltage gt 2001V Storage Temperature 65 to 150 G a Monod Ambient Temperature with Latch up Current gt 200 mA Power 55 to 125 Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 4 6V Ambient Supply Voltage on Vppo Relative to GND 0 5V to Vpp Range Temperature Vpp Vppo DC Voltage Applied to Outputs Commercial 0 to 70 C 3 3V 2 5V 5 0 5V to Vppo 0 5 Industrial 40 to 85 5 10 to Vpp Electrical Characteristics Over the Operating Rangel Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ Supply Voltage for 3 3V I O 3 135 Vpp V for 2 5V I O 2 375 2 625 V Vou Output HIGH Voltage for 3 3V I O 4 0 mA 2 4 V V for 2 5V I O 1 0 mA 2 0 V V VoL Output LOW Voltage for 3 3V I O lo 8 0 mA 0 4 V for 2 5V I O log 1 0 mA 0 4 V ViH Input HIGH Voltage for 3 3V 22. ta taps ADH lt 4 5 7 D 9 s s e Byte write signals are irae wes EH ma UAM FA 9S ddl dl wes 7 UE MUN A Oo ow uu Ua Ics YUY hovs m lt ADV suspends burst l l l l l OE f LLL tos pH gt lt Data In D High Z t oan D A2 XX D A2 1 XX D A2 nom ay D A2 3 XX D A3 XX D A3 1 XX D A3 2 X OEHZ lt gt Es BURST READ Single WRITE BURST WRITE DON T CARE Q UNDEFINED Extended BURST WRITE Note 18 Full width Write can be initiated by either GW LOW or by GW HIGH BWE LOW and pj LOW Document 38 05673 Rev B Page 12 of 16 Feedback CYPRESS CY7C1329H PERFORM Switching Waveforms continued Read Write Cycle Timing 13 20 toc gt ejUdpguuduuuuuuwdui ta ta I hp taps ADH Ly x mm _ x a OTN gt C IU wo WU Hi a ig 7 OE tps lt gt 0 Dataln D Highz D A3 DIAS DIAG 07 ox lt gt
3. DataOut Highz OX QIA2 Back to Back READs Single WRITE lt Back to Back BURST READ WRITES M DON T CARE UNDEFINED Notes 19 The data bus Q remains in High Z following a Write cycle unless an ADSP ADSC or ADV cycle is performed 20 GW is HIGH Document 38 05673 Rev B Page 13 of 16 Feedback CYPRESS CY7C1329H PERFORM Switching Waveforms continued ZZ Mode Timing 22 VIN INSININEN tz tZZREC ALL INPUTS except ZZ Wn DON T CARE 21 Device must be deselected when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 22 DGs are in High Z when exiting ZZ sleep mode DESELECT or READ Only Document 38 05673 Rev B Page 14 of 16 Feedback CYPRESS CY7C1329H PERFORM Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Package Type Range 166 CY7C1329H 166AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1329H 166AXI 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial 133 CY7C1329H 133AXC 100 pin Thin Quad
4. Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1329H 133AXI 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial Package Diagram 100 pin TQFP 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14 00 0 10 1 40 0 05 100 81 9 E E 0 30 0 08 E af 8 S8 o 29 w SEE DETAIL A 30 Fm 51 lp EHHEJHEHHEHHEHHEHHEE V IR 31 50 0 20 MAX 1 60 R 0 08 MIN 0 20 m 0 MIN 2 SEATING PLANE N STAND OFF C d 0 05 MIN NOTE 0 25 fa H 0 15 MAX GAUGE PLANE U 1 JEDEC STD REF MS 026 r 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 MAX BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 0 20 MIN 51 85050 B 1 00 REF m DETAIL 1486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation PowerPC is a registered trademark of IBM Corporation All product and company names mentioned in this document may be trademarks of their respective holders Document 38 05673 Rev B Page 15 of 16 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without not
5. H L X X X Unselected None None L X H L H L X X X Begin Read External None X X X H X X X X X Begin Read External External L H L L L X X X L Continue Read Next External L H L L L X X X H Continue Read Next External L H L L H L X L X Continue Read Next External L H L L H L x H L Continue Read Next External L H L L H L x H H Suspend Read Current Next X X X L H H L H L Suspend Read Current Suspend Read Current Next X X X L H H L H H Suspend Read Current Next H X X L X H L H L Begin Write Current Next H X X L X H L H H Begin Write Current Next X X X L H H L L X Begin Write External Next H X X L X H L L X Continue Write Next Current X X X L H H H H L Continue Write Next Current X X X L H H H H H Suspend Write Current Current H X X L X H H H L Suspend Write Current Current H X X L X H H H H ZZ Sleep None Current X X X L H H H L X Truth Table for Read Write 2 31 Function GW BWE BWp BWc BWg BWA Read H H X X X X Read H L H H H H Write Byte A DQA H L H H H L Write Byte B DQp H L H H L H Write Bytes B H L H H L L Write Byte C DQc H L H L H H Write Bytes C A H L H L H L Write Bytes C B H L H L L H Write Bytes C B A H L H L L L Write Byte D DQp H L L H H H Notes 2 X Don t Care H Logic HIGH L Logic LOW 3 4 5 6 Document 38 05673 Rev B WRITE L when any one or more Byte Write Enable signals BW4A BWg BWc BWp and BWE L GW L WRITE H when
6. Rise 3 5 4 0 ns Data Output Hold after CLK Rise 1 5 1 5 ns tcLz Clock to 211 15 16 0 0 ns tcHz Clock to High Zll14 15 16 3 5 4 0 ns toev OE LOW to Output Valid 3 5 4 5 ns toELZ OE LOW to Output Low ZI 4 15 16 0 0 ns loEuz OE HIGH to Output High Z 4 15 16 3 5 4 0 ns Set up Times tas Address Set up before CLK Rise 1 5 1 5 ns taps ADSC ADSP Set up before CLK Rise 1 5 1 5 ns tADVS ADV Set up before CLK Rise 1 5 1 5 ns twes GW BWE BWja p Set up before CLK Rise 1 5 1 5 ns tps Data Input Set up before CLK Rise 1 5 1 5 ns tcEs Chip Enable Set Up before CLK Rise 1 5 1 5 ns Hold Times Address Hold after CLK Rise 0 5 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 5 0 5 ns ADV Hold after CLK Rise 0 5 0 5 ns twEH GW BWE Hold after CLK Rise 0 5 0 5 ns tpH Data Input Hold after CLK Rise 0 5 0 5 ns Enable Hold after CLK Rise 0 5 0 5 ns Notes 11 Timing reference level is 1 5V when Vppq 3 3V and is 1 25V when Vppq 2 5V 12 Test conditions shown in a of AC Test Loads unless otherwise noted 13 This part has a voltage regu can be initiated 14 tcrz togrz and are specified with AC test conditions shown in part b of AC Test Loads Transition is measured 200 mV from steady state voltage ator internally tpower is the time that the power needs to be supplied above Vpp minimum initially before a Read or Write operation 15 At any given voltage and
7. all Byte Write Enable signals BWA BWg BWc BWp BWE GW H NE un The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock CE CE and CE are available only in the TQFP package The SRAM always initiates a read cycle when ADSP is asserted regardless of the state of GW BWE or BW A Dj Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri State OE is a don t care for the remainder of the Write cycle OE is asynchronous and is not sampled with the clock rise It is masked internally during Write cycles During a Read cycle all data bits are Tri State when OE is inactive or when the device is deselected and all data bits behave as output when OE is active LOW Page 6 of 16 Feedback CIPHEDO CY7C1329H Truth Table for Read Write continued 3 Function GW BWE BWp BWc BWs BWA Write Bytes D A H L L H H L Write Bytes D B H L L H L H Write Bytes D B A H L L H L L Write Bytes D C H L L L H H Write Bytes D C A H L L L H L Write Bytes C B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Document 38 05673 Rev B Page 7 of 16 Feedback CYPRESS CY7C1329H PERFORM
8. 0 Vpp 0 3V V for 2 5V I O 1 7 Vpp 0 3V V Vi Input LOW Voltage Ifor 3 3V 1 0 0 3 0 8 for 2 5V I O 0 3 0 7 V Ix Input Leakage Current GND x Vj lt VDDQ 5 5 except ZZ and MODE Input Current of MODE Input Vss 30 uA Input Vpp 5 uA Input Current of ZZ Input Vss _5 Input Vpp 30 HA loz Output Leakage Current GND lt V lt Vppq Output Disabled 5 5 Ipp Vpp Operating Supply Vpp Max loyr 0 MA 6 cycle 166 MHz 240 mA Current f 1 7 5 ns cycle 133 MHz 225 mA 15 Automatic CS Vpp Max Device 6 ns cycle 166 MHz 100 mA ae 185 MHz m Ispo Automatic CS Vpp Max Device All speeds 40 mA Power down Deselected Viy lt 0 3V or Current CMOS Inputs Vin gt Vppo 0 3V f 0 Icp3 Automatic CS Vpp Max Device 6 ns cycle 166 MHz 85 mA Poor OS ipu S gt f fmax 1 Icp4 Automatic CS Vpp Max Device All speeds 45 mA Power down Deselected gt or Current TTL Inputs lt f 0 Notes 8 Overshoot lt Vpp 1 5V Pulse width less than tcyc 2 undershoot Vi AC gt 2V Pulse width less than tcyc 2 9 Assumes a linear ramp from Ov to Vpp min within 200 ms During this time lt Vpp and lt Vpp 10 Tested initially and after any design or process change that may affect these parameters Document 38 05673 Rev B Page 8 of 16 Feedbac
9. CY7C1329H PERFORM Features 2 Mbit 64K x 32 Pipelined Sync SRAM Functional Description Registered inputs and outputs for pipelined operation The CY7C1329H SRAM integrates 64K x 32 SRAM cells with 64K x 32 common I O architecture 3 3V core power supply 2 5V 3 3V I O operation Fast clock to output times 3 5 ns for 166 MHz device 4 0 ns for 133 MHz device Provide high performance 3 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed write Asynchronous output enable Offered in JEDEC standard lead free 100 pin TQFP package ZZ Sleep Mode Option advanced synchronous peripheral circuitry and a two bit counter for internal burst operation All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE4 depth expansion Chip Enables CE and CE3 Burst Control inputs ADSC ADSP and ADV Write Enables BWra p and BWE and Global Write GW Asynchronous inpille include the Output Enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP Address Strobe Controller ADSC are active Subsequent burst addresses can be internally generated as co
10. E WRITE REGISTER ED tu WRITE DRIVER Gw 1 INPUT CE L ENABLE REGISTERS Ee BUE PIPELINED ENABLE S ES gt a 42 SLEEP CONTROL Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 e 408 943 2600 Document 38 05673 Rev B Revised March 22 2006 Feedback C YPhESoO CY7C1329H PERFORM Selection Guide 166 MHz 133 MHz Unit Maximum Access Time 3 5 4 0 ns Maximum Operating Current 240 225 mA Maximum CMOS Standby Current 40 40 mA Pin Configuration 100 pin TQFP Pinout a lt 3 2 lt lt io O mimimimiO gt gt O oimioi i i lt lt S LO st CO CGN
11. T O0 1 st CO QN 7 zm O O O O O O O AD CO CO CO cO CO NC 5 1 80 NC 7 DQc 2 79 3 78 DQg 4 77 Vssq 5 76 Vsso DQc 6 75 DQg BYTEC L 3 7 74 DQc 8 73 DQ DQc 9 72 DQg Vsso 10 71 DDQ 11 70 Vppo DQc 12 69 LL 13 68 DQg 14 67 V Von 15 CY7C1329H 66 2 NC 16 65 Vss 17 64 ZZ DQp 18 63 DQA DQp 19 62 DQA Vppo 20 61 VDDQ Vssa 21 60 Vssa DQp 22 59 DQa DQp 23 58 DQA BYTE D DQp 24 57 DQA DQp 25 56 DQA Vssa 26 55 Vssa 27 54 DQp 28 53 DQp 29 52 DQA NC 30 51 NC N CO LO OO O O QN CO LO CO CO O O CO CO CO CO CO sb SF SF SF SF SF SB SF wo lt lt lt lt 22 885 5 lt lt lt lt lt 8 K 9 gt gt 5 gt 22 275 Document 38 05673 Rev 2 of 16 Feedback CYPRESS PERFORM Pin Definitions CY7C1329H Name Description A4 Input Address Inputs used to select one of the 64K address locations Sampled at the rising edge Synchronous ofthe CLK if ADSP or ADSC is active LOW and CE CEs and are sampled active A4 feed the 2 bit counter BWA BWs Input Byte Write Select Inputs active LOW Qualified with BWE to conduct Byte Writes to the SRAM BWc BWp Synchronous Sample
12. ZZ and MODE in the Electrical Characteristics Table Modified test condition from Vi lt Vpp to lt Vpp Replaced Package Name column with Package Diagram in the Ordering Information table Updated the Ordering Information Table Replaced Package Diagram of 51 85050 from A to B Included 3 3V I O option Updated the Ordering Information table Page 16 of 16 Feedback
13. anism has been provided to simplify the Write operations Because the CY7C1329H is a common I O device the Output Enable OE must be deasserted HIGH before presenting data to the DQ inputs Doing so will tri state the output drivers As a safety precaution DQs are automatically tri stated whenever a Write cycle is detected regardless of the state of OE Burst Sequences The CY7C1329H provides a two bit wraparound counter fed by A Ao that implements either an interleaved or linear burst sequence The interleaved burst sequence is designed specif ically to support Intel Pentium applications The linear burst sequence is designed to support processors that follow a linear burst sequence The burst sequence is user selectable through the MODE input Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence Both Read and Write burst operations are supported Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE4 CEs CE3 ADSP ADSC must remain inactive for the duration of tzzagc aft
14. d by A during the previous clock rise of the Read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQ are placed in a tri state condition Vpp Power Supply Power supply inputs to the core of the device Vss Ground Ground for the core of the device VDDQ I O Power Supply Power supply for the I O circuitry Vsso Ground Ground for the I O circuitry MODE Input Selects Burst Order When tied to GND selects linear burst sequence When tied to Vpp or left Static floating selects interleaved burst sequence This is a strap pin and should remain static during device operation Mode Pin has an internal pull up NC No Connects Not internally connected to the die 4M 9M 18M 72M 144M 288M 576M and 1G are address expansion pins and are not internally connected to the die Document 38 05673 Rev B Page 3 of 16 Feedback CYPRESS PERFORM Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock The CY7C1329H supports secondary cache in systems utilizing either a linear or interleaved burst sequence The interleaved burst order supports Pentium and i486 processors The linear burst sequence is suited for processors that utilize a linear burst sequence The burst order is user selectable and is det
15. d on the rising edge of CLK GW Input Global Write Enable Input active LOW When asserted LOW the rising edge of CLK a global Synchronous Write is conducted ALL bytes are written regardless of the values on BW A p BWE BWE Input Byte Write Enable Input active LOW Sampled on the rising edge of CLK This signal must be Synchronous LOW to conduct a Byte Write CLK Input Clock Input Used to capture all synchronous inputs to the device Also used to increment the Clock burst counter when ADV is asserted LOW during a burst operation CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE2 and CEs to select deselect the device ADSP is ignored if CE4 is HIGH CE is sampled only when a new external address is loaded Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction with Synchronous and CE to select deselect the device CE is sampled only when a new external address is loaded Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous and CE to select deselect the device Not connected for BGA Where referenced CE is assumed active throughout this document for BGA CE3 is sampled only when a new external address is loaded OE Input Output Enable asynchronous input active LOW Controls the direction of the I O pins When Asynch
16. er the ZZ input returns LOW Page 4 of 16 Feedback CYPRESS PERFORM Interleaved Burst Address Table MODE Floating or Vpp CY7C1329H Linear Burst Address Table MODE GND First Second Third Fourth First Second Third Fourth Address Address Address Address Address Address Address Address A1 A1 Ao A1 Ao A1 Ay A1 Ay 00 01 10 11 00 01 10 11 01 10 11 00 01 00 11 10 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ Vpp 0 2V 40 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzznEC ZZ recovery time ZZ 0 2V 2tcvc ns tzzi ZZ Active to sleep current This parameter is sampled 2tcyc ns trzzI ZZ Inactive to exit sleep current This parameter is sampled 0 ns Document 38 05673 Rev B Page 5 of 16 Feedback CY7C1329H PERFORM Truth Table 3 4 5 6 7 Next Cycle Add Used Add Used CE 22 ADSP ADSC ADV WRITE OE Unselected None None H X X L X L X X X Unselected None None L L X L L X X X X Unselected None None L X H L L X X X X Unselected None None L L X L
17. ermined by sampling the MODE input Accesses can be initiated with either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte Write operations are qualified with the Byte Write Enable BWE and Byte Write Select BWia p inputs A Global Write Enable GW overrides all Byte Write inputs and writes data to all four bytes All Writes are simplified with on chip synchronous self timed Write circuitry Three synchronous Chip Selects CE CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise 1 ADSP or ADSC is asserted LOW 2 CE CEs CEs are all asserted active and 3 the Write signals GW BWE are all deasserted HIGH ADSP is ignored if CE1 is HIGH The address presented to the address inputs A is stored into the address advancement logic and the address register while being presented to the memory array The corresponding data is allowed to propagate to the input of the output registers At the rising edge of the next clock the data is allowed to propagate through
18. ice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS PERFORM Document History Page CY7C1329H Document Title CY7C1329H 2 Mbit 64K x 32 Pipelined Sync SRAM Document Number 38 05673 REV ECN NO Issue Date Orig of Change Description of Change A B 347357 424820 433014 See ECN See ECN See ECN Document 38 05673 Rev B PCI RXU NXR New Data Sheet Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed Three State to Tri State Modified Input Load to Input Leakage Current except
19. k CYPRESS CY7C1329H PERFORM Capacitance 100 TQFP Parameter Description Test Conditions Max Unit Cin Input Capacitance 25 C f 1 MHz 5 pF Clock Input Capacitance H DD E 5 pF Cio Input Output Capacitance acd 5 pF Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard test 30 32 C W Junction to Ambient methods and procedures for ing thermal impedance per o Ojo Thermal Resistance measuring 6 85 C W Junction to Case EIA JESDS1 AC Test Loads and Waveforms 3 3V Test Load OUTPUT 3 3V Au OUTPUT 500 5pF T R 3510 INCLUDING Vr 15V JIG AND SCOPE b 2 5V I O Test Load R 16670 OUTPUT 2 5V OUTPUT 500 5pF L Vr 1 25V INCLUDING JIG AND SCOPE 5 Document 38 05673 Rev ALL INPUT PULSES Page 9 of 16 Feedback w 294 CYPRESS CY7C1329H PERFORM Switching Characteristics Over the Operating Range l1 12 166 MHz 133 MHz Parameter Description Min Max Min Max Unit POWER Vpp Typical to the First Access 8 1 1 ms Clock tcyc Clock Cycle Time 6 0 7 5 ns tcu Clock HIGH 2 5 3 0 ns teL Clock LOW 2 5 3 0 ns Output Times tco Data Output Valid after CLK
20. ntrolled by the Advance pin ADV Address data inputs and write controls are registered on chip to initiate a self timed Write cycle This part supports Byte Write operations see Pin Descriptions and Truth Table for further details Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs GW when active LOW causes all bytes to be written The CY7C1329H operates from a 3 3V core power supply while all outputs operate with either a 2 5V or 3 3V supply All inputs and outputs are JEDEC standard JESD8 5 compatible Logic Block Diagram 1 ADDRESS gt REGISTER 2 Ano a 15 a CLK BURST COUNTER o AND ao LOGIC ADSP DQo E Dos BWo BYTE BVT D TDH WRITE REGISTER LZ WRITE DRIVER DQc gt Z TDH WRITE REGISTER D WRITE DRIVER EMT OUTP E OUTPUT Ty ARRAY SENSE REGISTERS BUFFERS lt SDQ s DQs 2 DQs E BWs BYTE gt 2 BYTE i 4 D WRITE REGISTER 41 WRITE DRIVER DQA L r BW 7 E BYTE ies BW
21. ronous LOW the I O pins behave as outputs When deasserted HIGH I O pins are tri stated and act as input data pins OE is masked during the first clock of a Read cycle when emerging from a deselected state ADV Input Advance Input signal sampled on the rising edge of CLK active LOW When asserted it Synchronous automatically increments the address in a burst cycle ADSP Input Address Strobe from Processor sampled on the rising edge of CLK active LOW When Synchronous asserted LOW A is captured in the address registers A4 are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deasserted HIGH ADSC Input Address Strobe from Controller sampled on the rising edge of CLK active LOW When Synchronous asserted LOW A is captured in the address registers A4 Ag are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ZZ Input ZZ sleep Input active HIGH This input when HIGH places the device in a non time critical Asynchronous 5 condition with data integrity preserved For normal operation this pin has to be LOW left floating ZZ pin has an internal pull down DQA DQp Bidirectional Data I O lines As inputs they feed into an on chip data register that is triggered DQc DQp Synchronous by the rising edge of CLK As outputs they deliver the data contained in the memory location specifie
22. temperature togpz is less than tog and is less than to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 16 This parameter is sampled and not 100 tested Document 38 05673 Rev B Page 10 of 16 Feedback Switching Waveforms Read Cycle Timing ADSP ADSC ADDRESS GW BWE BW A D ADV Data Out Q CY7C1329H rr CAN AN AA AD AR W T S w G Gmm cx TC UI W w w w W w DI tapvs lt gt Db A High Z lt _ Single READ ADV suspends burst to lt 4 t CHZ Q A2 Q A2 1 XX Q A2 2 XX Q A2 3 X Q A2 x Q A2 1 Burst wrapsaround to itsinitial state BURST READ gt DON T CARE UNDEFINED Note 17 this diagram when CE is LOW CE is LOW is HIGH and CE is LOW When CE is HIGH CE is HIGH or is LOW or CE is HIGH Document 38 05673 Rev B Page 11 of 16 Feedback CYPRESS CY7C1329H PERFORM Switching Waveforms continued Write Cycle Timing 18 tec lt
23. the output register and onto the data bus within tco if OE is active LOW The only exception occurs when the SRAM is emerging from a deselected state to a selected state its outputs are always tri stated during the first cycle of the access After the first cycle of the access the outputs are controlled by the OE signal Consecutive single Read cycles are supported Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals its output will tri state immediately Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise 1 ADSP is asserted LOW and 2 CEs are all asserted active The address presented to A is loaded into the address register and the address advancement logic while being delivered to the RAM array The Write signals GW BWE and BWja pj and ADV inputs are ignored during this first cycle ADSP triggered Write accesses require two clock cycles to complete If GW is asserted LOW on the second clock rise the data presented to the DQ inputs is written into the corre sponding address location in the memory array If GW is HIGH Document 38 05673 Rev B CY7C1329H then the Write operation is controlled by BWE and BWra p signals The CY7C1329H provides Byte Write capability al is described in the Write Cycle Descriptions table Asserting the Byte Write Enable input BWE with the selected B
24. yte Write BW a p input will selectively write to only the desired bytes Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed Write mechanism has been provided to simplify the Write operations Because the CY7C1329H is a common I O device the Output Enable OE must be deasserted HIGH before presenting data to the DQ inputs Doing so will tri state the output drivers As a safety precaution DQs are automatically tri stated whenever a Write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following condi tions are satisfied 1 _ADSC is asserted LOW 2 ADSP is deasserted HIGH 3 CE CE3 are all asserted active and 4 the appropriate combination of the Write inputs GW BWE and BWy p are asserted active to conduct a Write to the desired byte s ADSC triggered Write accesses require a single clock cycle to complete The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array The ADV input is ignored during this cycle If a global Write is conducted the data presented to DQ is written into the corre sponding address location in the memory core If a Byte Write is conducted only the selected bytes are written Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed Write mech
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