Cypress CY7C1218H User's Manual
Contents
1. _ W YPRESS CY7C1218H PERFOR Mm Features Registered inputs and outputs for pipelined operation 32K x 36 common I O architecture 3 3V core power supply Vpp 2 5V 3 3V I O power supply Vppo Fast clock to output times 3 5 ns for 166 MHz device Provide high performance 3 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed write Asynchronous output enable Available in JEDEC standard lead free 100 Pin TQFP package ZZ Sleep Mode Option 1 Mbit 32K x36 Pipelined Sync SRAM Functional Description The CY7C1218H SRAM integrates 32K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two bit counter for internal burst operation All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK The synchronous inputs include addresses all data inputs address pipelining Chip Enable CE depth expansion Chip Enables CE gt and CE3 Burst Control inputs ADSC ADSP and ADV Write Enables BWra p and BWE and Global Write GW Asynchronous include the Output Enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP2. 343896 430678 New Data Sheet Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Added 2 5VI O option Changed Three State to Tri State Included Maximum Ratings for relative to GND Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Modified test condition from lt Vpp to Vin lt Vpp Replaced Package Name column with Package Diagram in the Ordering Information table 481916 See ECN VKN Converted from Preliminary to Final Updated the Ordering Information table Document 38 05667 Rev B Page 16 of 16 Feedback
3. Write Bytes D A Write Bytes D B Write Bytes D B A Write Bytes D C Write Bytes D C A Write Bytes D C B Write All Bytes Write All Bytes ea lt s 00 2 00 111 o z iz x 8 00 x r x irz m z 1110 2l 0 121 11115 51111 8 Document 38 05667 Rev B Page 6 of 16 Feedback CE CYPRESS P ERF ORM Maximum Ratings CY7C1218H DC Input Voltage abavaswiich ife For aserauides Current into Outputs LOW 20 mA lines not tested Static Discharge gt 2001V Storage Temperature 65 to 150 Method 30115 Ambient Temperature with Latch up Current 200 mA Power 55 to 125 Operating Range Supply Voltage on Vpp Relative to GND 0 5 to 4 6V Ambient Supply Voltage on Relative to GND 0 5V to Vpp Range Temperature Vpp VDDQ DC Voltage Applied to Outputs Commercial 0 C to 70 C 3 3 596 1096 2 5V 5
4. in Tri State sess 0 5V to Vppgq 0 5V Industrial 40 Cto 485 C to Vpp Electrical Characteristics Over the Operating Range 8 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ 1 Supply Voltage for 3 3V I O 3 135 for 2 5V I O 2 375 2 625 V Output HIGH Voltage for 3 3V I O lop 4 0 mA 2 4 V for 2 5V I O 1 0 mA 2 0 V VoL Output LOW Voltage for 3 3V I O 8 0 mA 0 4 V for 2 5V I O Io 1 0 mA 0 4 V Input HIGH Voltage for 3 3 2 0 Vpp 0 3V V for2 5VVO Vona V ViL Input LOW Voltage for 3 3V 0 3 0 8 V for 2 5V I O 0 3 0 7 V Ix Input Leakage Current lt V lt VDDQ 5 5 except ZZ and MODE Input Current of MODE Input Vss 30 Input 5 Input Current of ZZ Input Vas 5 Input Vpp 30 loz Output Leakage Current GND x V lt Vppq Output Disabled 5 5 Vpp Operating Supply Vpp Max lour 0 6 cycle 166 MHz 240 mA Current f fmax 1 7 5 ns cycle 133 MHz 225 mA 1 Automatic CS Vpp Max Device Deselected 6 ns cycle 166 MHz 100 mA Ispo Automatic CS Vpp Max Device Deselected All speeds 40 mA Power down Vin lt 0 3V or Vin gt 0 3V Current CMOS Inputs f 0 Automatic CS Vpp Max Device Deselected 6 ns cycle 166 MHz 85 mA Cument CMOS pus the Meyer S Ispa Automatic CS V
5. 11 Timing references level is 1 5V when Vppq 3 3V and is 1 25V when Vppq 2 5V 12 Test conditions shown in a of AC Test Loads unless otherwise noted 13 has a Voltage regulator internally tpower is the time that the power needs to be supplied above Vpp minimum initially before a Read or Write operation can be initiate 14 tcuz toLz toeLz and are specified with AC test conditions shown in part b of AC Test Loads Transition is measured 200 mV from steady state voltage 15 At any given voltage and temperature togpz is less than tog and is less than to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 16 This parameter is sampled and not 10096 tested Document 38 05667 Rev B Page 9 of 16 Feedback CYPRESS CYPRESS CY7C1218H PERFORM Switching Waveforms Read Cycle Timing 7 S1 E1717 owe toes cycle tapvs apvH D oO 0 0 re ADV suspends OE burst 080 w 2 A 0 2 2 3 4 08811686 Burst wraps around to its initia
6. B ALL INPUT PULSES Page 8 of 16 Feedback CYPRESS CY7C1218H PERFORM III Switching Characteristics Over the Operating Range 12 166 MHz 133 MHz Parameter Description Min Max Min Max Unit tPOWER Vpp Typical to the First Access 3l 1 1 ms Clock Clock Cycle Time 6 0 7 5 ns tcu Clock HIGH 2 5 3 0 ns teL Clock LOW 2 5 3 0 ns Output Times tco Data Output Valid after CLK Rise 3 5 4 0 ns Data Output Hold after CLK Rise 1 5 1 5 ns telz Clock to 2114 15 16 0 0 ns Clock to High z 15 16 3 5 4 0 ns OE LOW to Output Valid 3 5 4 5 ns toELz OE LOW to Output 2115 15 16 0 0 ns OE HIGH to Output 211 15 16 3 5 4 0 ns Set up Times tas Address Set up before CLK Rise 1 5 1 5 ns taps ADSC ADSP Set up before CLK Rise 1 5 1 5 ns tADVS ADV Set up before CLK Rise 1 5 1 5 ns twes GW BWE Set up before CLK Rise 1 5 1 5 ns tps Data Input Set up before CLK Rise 1 5 1 5 ns tcES Chip Enable Set Up before CLK Rise 1 5 1 5 ns Hold Times Address Hold after CLK Rise 0 5 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 5 0 5 ns ADV Hold after CLK Rise 0 5 0 5 ns twEH GW BWE BW A p Hold after CLK Rise 0 5 0 5 ns 1 Data Input Hold after CLK Rise 0 5 0 5 ns Chip Enable Hold after CLK Rise 0 5 0 5 ns Notes
7. If GW is HIGH then the Write operation is controlled by BWE and Document 38 05667 Rev B CY7C1218H signals The CY7C1218H provides Byte Write capability that is described in the Write Cycle Descriptions table Asserting the Byte Write Enable input BWE with the selected Byte Write BWrA pj input will selectively write to only the desired bytes Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed Write mechanism has been provided to simplify the Write operations Because the CY7C1218H is a common I O device the Output Enable OE must be deasserted HIGH before presenting data to the DQ inputs Doing so will tri state the output drivers As a safety precaution DQ are automatically tri stated whenever a Write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following condi tions are satisfied 1 ADSC is asserted LOW 2 ADSP is deasserted HIGH 8 CE4 CEs are all asserted active and 4 the appropriate combination of the Write inputs GW BWE and BW p are asserted active to conduct a Write to the desired byte s ADSC triggered Write accesses require single clock cycle to complete The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array The ADV input is ignored during this cycle If a g
8. Bidirectional Data 1 lines As inputs they feed into an on chip data register that is triggered by DQc DQp Synchronous the rising edge of CLK As outputs they deliver the data contained in the memory location specified by A during the previous clock rise of the Read cycle The direction of the pins is controlled by When OE is asserted LOW the pins behave as outputs When HIGH DQs and DQP a pj DQPg placed in a tri state condition Power Supply supply inputs to the core of the device Vss Ground Ground for the core of the device VDDQ Power Power supply for the I O circuitry Supply 0 Ground Ground for the I O circuitry MODE Input Selects Burst Order When tied to GND selects linear burst sequence When tied to Vpp or left Static floating selects interleaved burst sequence This is a strap pin and should remain static during device operation Mode Pin has an internal pull up NC No Connects Not internally connected to the die 2M 4M 9M 18M 72M 144M 288M 576M and 1G are address expansion pins and are not internally connected to the die Document 38 05667 Rev B Page 3 of 16 Feedback ZEE CYPRESS PERFORM Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock The CY7C1218H supports secondary
9. LOW and CE4 CEs and are sampled active A4 feed the 2 bit counter BWA BWg Input Byte Write Select Inputs active LOW Qualified with BWE to conduct Byte Writes to the SRAM BWp Synchronous Sampled on the rising edge of CLK GW Input Global Write Enable Input active LOW When asserted LOW on the rising edge of CLK a global Synchronous Write is conducted ALL bytes are written regardless of the values on BWE BWE Input Byte Write Enable Input active LOW Sampled on the rising edge of CLK This signal must be Synchronous LOW to conduct a Byte Write CLK Input Clock Input Used to capture all synchronous inputs to the device Also used to increment the burst Clock counter when ADV is asserted LOW during a burst operation CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device ADSP is ignored if CE is HIGH CE is sampled only when a new external address is loaded Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device is sampled only when a new external address is loaded CE Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and to select deselect the device Not connected for BGA Where referenc
10. 5 mA Maximum CMOS Standby Current 40 40 mA Pin Configuration 100 Pin TQFP Top View JB lt O Olmimimim O gt gt oloimoOl i i S o croi ODON 2 O 0 0 O O O 09 0 O O 00 c 0 o o DQPc 1 80 DQc 2 79 DQg DQc 78 DQg 4 77 Vssq 4 5 76 DQc 6 75 DQg BYTEC DQc 7 74 DQc 73 DQg DQc 9 72 Vssq 10 71 11 70 DQc 12 69 DQg L 13 68 NC 14 67 Vss 15 66 NC E 16 CY7C1218H 65 Vss 17 64 77 DQp 18 63 DQ DQp EH 19 62 DQ 20 61 Vssa 21 60 Vssa DQp 22 59 DQp 23 58 BYTE D DQp 24 57 DQ4 BYTE A DQp H 25 56 Vssa 26 55 27 54 DQp 28 53 DQp 29 52 DQPp 30 51 T N CO st LO CO 10 CO CO CO CO st TT SF SF SF SF SF oSF SOLO lt lt lt 20885 lt lt lt lt lt 2 zz z 2 2 2 Document 38 05667 Rev B Page 2 of 16 Feedback Pin Definitions CY7C1218H Name Description Ag A4 Input Address Inputs used to select one of the 32K address locations Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active
11. Address Strobe Controller ADSC are active Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV Address data inputs and write controls are registered on chip to initiate a self timed Write cycle This part supports Byte Write operations see Pin Descriptions and Truth Table for further details Write cycles can be one to four_bytes wide as controlled by the Byte Write control inputs GW when active LOW causes all bytes to be written The CY7C1218H operates from a 3 3V core power supply while all outputs may operate either with a 2 5V or 3 3V supply All inputs and outputs are JEDEC standard JESD8 5 compatible Logic Block Diagram 1 ADDRESS I REGISTER 2 Aro MODE ADV Q1 CLK BURST COUNTER AND ao ner 8 4 LOGIC ADSP 3 005005 BWo BYTE e WRITE REGISTER _ WRITE DRIVER DQc DQPc BWc DQc DQs MEMORY OUTPUT OUTPUT DQPa oy ARRAY PUES REGISTERS BUFFERS DQPs DQsDQPs BYTE ot TJ BWs _ WRITE REGISTER DQs DQPs WRITE DRIVER DQPc Mx IDH e 1 LA DQa BWa m gt
12. ION END FLASH SHALL EXCEED 0 0098 0 25 mm PER SIDE 0 7 0 20 BODY LENGTH DIMENSIONS MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 51 85050 B 1 00 REF DETAIL A Document 38 05667 Rev B Page 15 of 16 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback s CYPRESS PERFORM Document History Page CY7C1218H Document Title CY7C1218H 1 Mbit 32K x36 Pipelined Sync SRAM Document Number 38 05667 REV Issue Date Orig of Change Description of Change
13. WRITE DRIVER WRITE DRIVER gt i i D ID r D ID BYTE BWE WRTEREGITER INPUT REGISTERS GW ENABLE n PIPELINED REGISTER ENABLE cE D E D z SLEEP CONTROL Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com Cypress Semiconductor Corporation Document 38 05667 Rev B 198 Champion Court San Jose CA 95134 1709 e 408 943 2600 Revised July 6 2006 Feedback CYPRESS CY7C1218H PERFORM Selection Guide 166 MHz 133 MHz Unit Maximum Access Time 3 5 4 0 ns Maximum Operating Current 240 22
14. X L X X Tri State Unselected None L L X H L X X X Tri State Unselected None L L L L X X X Tri State Unselected None L L X H H L X X Tri State Unselected None L L L X H L X Tri State L L H L Tri State L L H L H L Tri State Read Continue Read Next L X X X H H L H Tri State Read Continue Read Next L H H L L DQ Read Continue Read Next L H X X L H Tri State Read Continue Read Next L H L L DQ Read Suspend Read Current L X X X H H H H Tri State Read Suspend Read Current L H H H L DQ Read Suspend Read Current L H H H H Tri State Read Suspend Read Current L H X X X H H L DQ Read Begin Write Current L X X X H H H X Tri State Write Begin Write Current L H X X X H H X Tri State Write Begin Write External L L H L H H X X Tri State Write Notes 2 X Don t Care H HIGH L LOW 3 WRITE L when any one or more Byte Write Enable signals BWa BWp BWc BWp and BWE L or GW L WRITE when all Byte Write Enable signals BWA BWg BWc BWp BWE GW 4 The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock 5 CE4 and CE are available only in the TQFP package 6 The SRAM always initiates a read cycle when ADSP is asserted regardless of the state of GW BWE BW A D Writes may occur only on subsequent clocks afte
15. a integrity 15 guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE4 ADSP ADSC must remain inactive for the duration of tzzagc after the ZZ input returns LOW Page 4 of 16 Feedback rd CYPRESS PERFORM Interleaved Burst Address Table CY7C1218H Linear Burst Address Table MODE GND MODE Floating or Vpp First Second Third Fourth First Second Third Fourth i bu wa i v vg AM M Address Address Address Address 1 8 Lii 10 po A Ag Ay Ag Ag A Ag 00 01 10 11 00 01 10 11 01 10 11 00 01 00 11 10 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ Vpp 0 2V 40 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcvc ns dZZrecovertim 22402 1 tvc ms tzzi ZZ Active to sleep current This parameter is sampled 2tcyc ns 8771 ZZ Inactive to exit sleep current This parameter is sampled 0 ns Truth Table 3 4 5 6 71 Next Cycle Add Used ZZ CE CE CE ADSP ADSC ADV OE DQ Write Unselected None L H X X
16. cache in systems utilizing either a linear or interleaved burst sequence The interleaved burst order supports Pentium i486 processors The linear burst sequence is suited for processors that utilize a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses can be initiated with either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte Write operations are qualified with the Byte Write Enable BWE and Byte Write Select BWia p inputs A Global Write Enable GW overrides all Byte Write inputs and writes data to all four bytes All Writes are simplified with on chip synchronous self timed Write circuitry Three synchronous Chip Selects CE CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise 1 ADSP or ADSC is asserted LOW 2 CE CE CEs are all asserted active and 3 the Write signals GW BWE are all deasserted HIGH ADSP is ignored if CE is HIGH The address presented to the address input
17. ed CE3 is assumed active throughout this document for BGA is sampled only when a new external address is loaded OE Input Output Enable asynchronous input active LOW Controls the direction of the I O pins When Asynchronous LOW the I O pins behave as outputs When deasserted HIGH I O pins are tri stated and act as input data pins OE is masked during the first clock of a Read cycle when emerging from a deselected state ADV Input Advance Input signal sampled on the rising edge of CLK active LOW When asserted it Synchronous automatically increments the address in a burst cycle ADSP Input Address Strobe from Processor sampled on the rising edge of CLK active LOW When Synchronous asserted LOW is captured in the address registers A4 Ag are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deasserted HIGH ADSC Input Address Strobe from Controller sampled on the rising edge of CLK active LOW When Synchronous asserted LOW is captured in the address registers A4 Ag are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized 22 Input ZZ Sleep Input active HIGH This input when High places the device in a non time critical Asynchronous sleep condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down I O
18. ilable Please contact your local sales representative visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Package Type Range 100 CY7C1218H 100AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial 7 1218 100 Industrial 133 CY7C1218H 133AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1218H 133AXI Industrial Document 8 38 05667 Rev B Page 14 of 16 Feedback E Cd 2 CYPRESS PERFORM CY7C1218H Package Diagram 100 Pin TQFP 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14004010 1 40 0 05 100 81 HRERRHRRERRRHRRRRRRRR Ho 6 n Ea 0 30 0 08 Ea zn E ES 8 g H co cz 8 E N EH IES i 065 A Eo TYP SEE DETAIL Ez 30 Fn 51 31 50 I 0 20 MAX 160 0 08 MIN 5 0 20 gt 0 MIN 5 STAND OFF q 1 RET 0 05 1 0 15 GAUGE PLANE 1 1 JEDEC STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH B OOS MIN MOLD PROTRUS
19. l state Data Out Q High Z BURST READ I Single READ gt 17 care UNDEFINED Note 17 On this diagram when CE is LOW CE is LOW CE is HIGH and is LOW When CE is HIGH CE is HIGH or is LOW or is HIGH Document 38 05667 Rev B Page 10 of 16 Feedback 4 a CYPRESS CY7C1218H PERFORM Switching Waveforms continued Write Cycle Timing 18 us 7 ADSC 7 when ADS initiates burst wes EH WD sT U a VM m Data In D High Z 11 D A1 D A2 D A2 1 D A2 X D A2 aXX D A2 3 XX D A3 XX D A3 1 XX D A3 2 X OEHZ lt gt BURST READ 8 Single WRITE 2 BURST WRITE ne Extended BURST WRITE DON T CARE n UNDEFINED Note 18 Full width Write can be initiated by either GW LOW or by GW HIGH BWE LOW and pj LOW Document 38 05667 Rev B Page 11 of 16 Feedback CYPRESS SS PERFORM Switching Waveforms continued 17 19 20 CY7C1218H Read Write Cycle Timing ARAL tH ta mI A Nm w
20. lobal Write is conducted the data presented to DQs is written into the corre sponding address location in the memory core If a Byte Write is conducted only the selected bytes are written Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed Write mechanism has been provided to simplify the Write operations Because the CY7C1218H is a common I O device the Output Enable OE must be deasserted HIGH before presenting data to the DQ inputs Doing so will tri state the output drivers As a safety precaution DQs are automatically tri stated whenever a Write cycle is detected regardless of the state of OE Burst Sequences The CY7C1218H provides a two bit wraparound counter fed by Aj Ag that implements either an interleaved or linear burst sequence The interleaved burst sequence is designed specif ically to support Intel Pentium applications The linear burst sequence is designed to support processors that follow a linear burst sequence The burst sequence is user selectable through the MODE input Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence Both Read and Write burst operations are supported Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode dat
21. n OM XC OR s VE _ id toes lt gt a _ A iim gt tos 77 me gt lt gt 7 Data In 0 High Z D A3 D A5 D A6 gt cz oez 4 9 0 4 XX Q A4 1 NX aise NN anes BURST READ Back to Back gt WRITES ir NN Data Out Q High z X Q A2 E Back to Back READs gt SingleWRITE gt 7 DON T CARE UNDEFINED Notes 19 The data bus Q remains in High Z following a Write cycle unless an ADSP ADSC or ADV cycle is performed 20 GW is HIGH Document 38 05667 Rev B Page 12 of 16 Feedback CY7C1218H EC CYPRESS PERFORM Switching Waveforms continued ZZ Mode Timing 22 tZZREC 924 SUPPLY i 0077 DESELECT READ Only ALL INPUTS except ZZ YU 17 DON T CARE Notes 21 Dev salen bodes ted whens ring ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the dev 22 DOs exiting 725 ale mode Page 13 of 16 Document 38 05667 Rev B Feedback 2 CYPRESS CY7C1218H Ordering Information Not all of the speed package and temperature ranges are ava
22. pp Max Device Deselected All speeds 45 mA Power down Vin 2 Vin or Vy lt Vit f 0 Current TTL Inputs Notes 8 Overshoot Vjq AC lt Vpp 1 5V Pulse width less than 2 undershoot AC gt 2V Pulse width less than 2 9 Tpower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time lt and x Vpp Document 38 05667 Rev B Page 7 of 16 CYPRESS CY7C1218H PERFORM Capacitance 100 TQFP Parameter Description Test Conditions Max Unit Cin Input Capacitance 25 C f 1 MHz 5 pF Clock Input Capacitance M DD 2 5 Cio Input Output Capacitance 5 Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard test methods 30 32 C W Junction to Ambient and procedures for measuring thermal Ojc Thermal Resistance impedance per EIAWJESD51 6 85 C W Junction to Case AC Test Loads and Waveforms 3 3V I O Test Load OUTPUT 3 3V OUTPUT 500 5pF L INCLUDING 1 1 5 JIG AND a SCOPE b 2 5V I O Test Load R 16670 OUTPUT 2 5V OUTPUT R 500 5pF R 15380 1 25V INCLUDING 1 JIG AND SCOPE Note 10 Tested initially and after any design or process change that may affect these parameters Document 38 05667 Rev
23. r the ADSP or with the assertion of ADSC As a result OE must be driven HIGH prior to the start of the don t care for the remainder of the Write cycle 7 OEis asynchronous and is not sampled with the clock rise It is masked internally during Write cycles During a Read cycle all data bits are tri state when is inactive or when the device is deselected and all data bits behave as output when OE is active LOW Document 38 05667 Rev B rite cycle to allow the outputs to Tri State OE is a Page 5 of 16 Feedback CYPRESS RM Truth Table 3 4 5 6 7 continued j CY7C1218H Next Cycle Add Used ZZ gt lt Write Continue Write Next Tri State Write Continue Write Next Tri State Write Suspend Write Current Tri State Write rir Suspend Write Current Tri State Write ZZ Sleep None H 18 18 5 Q Tri State Truth Table for Read Write 31 Function 00 9 gt Read Read Write Byte and Write Byte B DQg and Write Bytes B A Write Byte C and Write Bytes C A Write Bytes C B Write Bytes C B A Write Byte D DQp and DQPp
24. s A is stored into the address advancement logic and the address register while being presented to the memory array The corresponding data is allowed to propagate to the input of the output registers At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tco if OE is active LOW The only exception occurs when the SRAM is emerging from a deselected state to a selected state its outputs are always tri stated during the first cycle of the access After the first cycle of the access the outputs are controlled by the OE signal Consecutive single Read cycles are supported Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals its output will tri state immediately Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise 1 ADSP is asserted LOW and 2 are all asserted active The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array The Write signals GW BWE and and ADV inputs are ignored during this first cycle ADSP triggered Write accesses require two clock cycles to complete If GW is asserted LOW on the second clock rise the data presented to the DQ inputs is written into the corre sponding address location in the memory array
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