Cypress CY7C1006D User's Manual
Contents
1. tHZWE Truth Table CE OE WE Input Output Mode Power H X X High Z Power Down Standby lag L L H Data Out Read Active lec L L Data In Write Active lec L H H High Z Selected Outputs Disabled Active loc Ordering Information Speed Package Operating ns Ordering Code Diagram Package Type Range 10 CY7C106D 10VXI 51 85032 28 400 Mil Molded SOJ Pb free Industrial CY7C1006D 10VXI 51 85031 28 pin 300 Mil Molded SOJ Pb free Please contact your local Cypress sales representative for availability of these parts Page 8 of 11 Document 38 05459 Rev E Feedback CYPRESS PERFORM Wns Package Diagrams Figure 1 28 pin 300 Mil Molded SOJ 51 85031 NOTE 1 JEDEC STD REF MO088 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 006 in 0 152 mm PER SIDE 3 DIMENSIONS IN INCHES MIN MAX PIN 1 ID 14 if _ i NA 0 291 0 300 puuuuuuu 15 28 0 697 SEATING PLANE 0 713 AN d 04120 0440 Hs qM J 0 004 0 050 0 025 MIN Document 38 05459 Rev DETAIL CY7C106D CY7C1006D A EXTERNAL LEAD DESIGN E 0 013 0 019 OPTION 1 0 026 0 032 0 014 0 020 OPTION 2 51 85031 Pag2. gt _ r M M W Se SSE ecr T CY7C106D CY7C1006D YPRESS PERFOR Mm Features Pin and function compatible with CY7C106B CY7C1006B High speed taa 10 ns Low active power lcc 80 mA 10 ns Low CMOS standby power Ispo 3 0 mA 2 0V Data Retention Automatic power down when deselected CMOS for optimum speed power TTL compatible inputs and outputs CY7C106D available in Pb free 28 pin 400 Mil wide Molded SOJ package CY7C1006D available in Pb free 28 pin 300 Mil wide Molded SOJ package Logic Block Diagram 1 Mbit 256K x 4 Static RAM Functional Description The CY7C106D and CY7C1006D are high performance CMOS static RAMs organized as 262 144 words by 4 bits Easy memory expansion is provided by an active LOW Chip Enable CE an active LOW Output Enable OE and tri state drivers These devices have an automatic power down feature that reduces power consumption by more than 65 when the devices are deselected The four input and output pins through 105 are placed in a high impedance state when Deselected CE HIGH Outputs are disabled OE HIGH When the write operation is active CE and WE LOW Write to the device by taking Chip Enable CE and Write Enable WE inputs LOW Data on the four IO pins 10 through 103 is then written into the location specified on the address pin
3. Switching Waveforms Read Cycle No 1 Address Transition Controlled 15 16 ADDRESS DATA VALID DATA OUT PREVIOUS DATA VALID Read Cycle No 2 OE Controlled 16 171 ADDRESS HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT KK E Voc SUPPLY CURRENT Notes 13 Full device operation requires linear ramp from Vpg to 2 50 or stable at Vec miny gt 50 us 14 1 lt 3 ns for all speeds mE 15 Device is continuously selected OE and CE Vj 16 WE is HIGH for read cycle Document 38 05459 Rev E Page 6 of 11 Feedback CY7C106D CY7C1006D y CYPRESS PERFORM ip Switching Waveforms continued Write Cycle 1 CE Controlled 18 13 aue CE tHA DATA VALID Write Cycle 2 WE Controlled OE HIGH During Write 18 191 SSX tpwe DATA 10 fal E lt lt lt tHZOE m es 18 If CE goes HIGH simultaneously with WE going HIGH the output remains in a high impedance state 19 Data IO is high impedance if OE Vj Page 7 of 11 Document 38 05459 Rev E Feedback E CY7C106D CY7C1006D Cypress PERFORM Switching Waveforms continued Write Cycle 3 WE Controlled OE LOW 2 19 twc A tHa 5 tpwe A Ag tup emus 000 tLZWe
4. PERFORM Maximum Ratings DC Input Voltage 31 CY7C106D CY7C1006D 3 Current into Outputs LOW eee 20 mA Exceeding the maximum ratings may impair the useful life of Rs the device These user guidelines are not tested ee mde Ud d iE gt 2001V Storage Temperature 65 C to 150 i i 60108 9045 T E gt Ambient Temperature with atch up Current sanies niinen m P Applied critt 55 to 125 5 E Operating Range Supply Voltage on Vcc Relative to GND 3 0 5V to 6 0V Ambient DC Voltage Applied to Outputs Range Voc Speed in High Z State 9l 0 5V to Veg 0 5V Temperaire Industrial 40 C to 85 C 5V 0 5 10 ns Electrical Characteristics Over the Operating Range 7C106D 10 Parameter Description Test Conditions 7C1006D 10 Unit Min Max Output HIGH Voltage lou 4 0 mA 2 4 V VoL Output LOW Voltage lo 8 0 mA 0 4 V Vin Input HIGH Voltage 2 2 0 5 V Vi Input LOW Voltage 18 0 5 0 8 V lix Input Leakage Current GND lt V lt Voc 1 1 loz Output Leakage Current GND lt V x Output Disabled 1 1 loc Vcc Operating Supply Current Vcc Max 100 MHz 80 mA lout 0 mA f fmax Wine 83 MHz 72 mA 66 MHz 58 mA 40 MHz 37 mA legi Automatic CE Power Down CE gt 10 Current T
5. TL Inputs Vin gt Vin or Vin lt f fmax Ispo Automatic CE Power Down Max Vcc CE gt Voc 0 3 3 mA Current CMOS Inputs Vin gt 0 3V or Vin lt 0 3V 120 Note 3 min 2 0 and Vi max 1V for pulse durations of less than 5 ns Document 38 05459 Rev E Page 3 of 11 Feedback CY7C106D 6 Capacitance Parameter Description Test Conditions Max Unit Cin Addresses Input Capacitance 25 C f 1 MHZ 5 0V 7 pF Controls 10 pF Cour Output Capacitance 10 pF Thermal Resistance 1 a 300 Mil 400 Mil Parameter Description Test Conditions Wide SOJ Wide SOJ Unit OJA Thermal Resistance Still Air soldered on a 3 x 4 5 inch 59 16 58 76 C W Junction to Ambient four layer printed circuit board Thermal Resistance 40 84 40 54 C W Junction to Case AC Test Loads and Waveforms ALL INPUT PULSES 7 500 3 0V OUTPUT 90 10 500 30 pF GND CAPACITIVE LOAD CONSISTS 1 5V Rise Time lt 3 ns b Fall Time lt 3 ns TEST ENVIRONMENT a High Z characteristics R1 4800 5V OUTPUT 5 pF R2 INCLUDING 2550 JIG Notes 4 Tested initially and after any design or process changes that may affect these parameters 5 AC characteristics except High Z are tested using
6. e 9 of 11 Feedback CY7C106D CY7C1006D Saar CYPRESS PERFORM Package Diagrams Figure 2 28 pin 400 Mil Molded SOJ 51 85032 PIN 11D 14 1 i 5 DIMENSIONS IN INCHES MIN 435 AN 395 445 A05 1 15 28 720 730 SEATING PLANE f f 128 A 148 J 007 25 0004 026 360 n 51 85032 032 025 MIN 380 015 020 product and company names mentioned in this document may be the trademarks of their respective holders Document 38 05459 Rev E Page 10 of 11 Cypress Semiconductor Corporation 2006 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The
7. inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback Wag CYPRESS PERFORM Document History Page CY7C106D CY7C1006D Document Title CY7C106D CY7C1006D 1 Mbit 256K x 4 Static RAM Document Number 38 05459 REV NO Issue Date Orig of Description of Change Change p g M 201560 See ECN SWI Advance information data sheet for C9 IPP 233693 See 5 582 Specs are modified as per EROS Spec 01 2165 Pb free offering in the ordering information B 262950 See ECN RKF Added Tp ower Spec in Switching Characteristics table Shaded Ordering Information See See RKF Reduced Speed bins to 10 and 12 ns D 560995 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added values for the frequencies 83MHz 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information table Changed Overshoot spec from Vcc 2V to Vect1V in footnote 3 E 802877 See ECN VKN Changed Icc spec from 60 mA to 80 mA for 100MHz 55 mA to 72 mA for 83MHz 45 mA to 58 mA for 66MHz 30 mA to 37 mA for 40MHz Document 38 05459 Rev E Page 11 of 11 Feedback
8. minimum amount of time that the power supply should be at typical values until the first memory access can be performed 8 tuzoe tuzce and tyzwe are specified with a load capacitance of 5 pF as in part c of AC Test Loads and Waveforms 5l on page 4 Transition is measured when the outputs enter a high impedance state 9 At any given temperature and voltage condition tyzce is less than tj tuzog is less than tj zog and tyzwe is less than tj for any given device 10 This parameter is guaranteed by design and is not tested 11 The internal write time of the memory is defined by the overlap of CE and WE LOW CE and WE must be LOW to initiate a write and the transition of either of these signals can terminate the write The input data set up and hold timing should be referenced to the leading edge of the signal that terminates the write Document 38 05459 Rev E Page 5 of 11 Feedback SS CY7C106D CYPRESS CY7C1006D PERFORM Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Max Unit Vec for Data Retention Data Retention Current Vec Vpr 20V gt Vec 0 3V 3 mA Vin gt Vcc 0 3V or Vin lt 0 3V Chip Deselect to Data Retention Time 0 ns ns tr 3 14 Operation Recovery Time Data Retention Waveform DATA RETENTION MODE Vpr gt 2V MC gt tg
9. s Ag through A47 Read from the device by taking Chip Enable CE and Output Enable OE LOW while forcing Write Enable WE HIGH Under these conditions the contents of the memory location specified by the address pins appears on the four IO pins ROW DECODER Note SENSE AMPS 1 For guidelines on SRAM system design please refer to the System Design Guidelines Cypress application note available on the internet at www cypress com Cypress Semiconductor Corporation Document 38 05459 Rev E 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised February 22 2007 Feedback j CY7C106D gt CYPRESS CY7C1006D 6 PERFORM Pin Configuration f SOJ Top View 11 28 1 Vcc A4 2 27 A47 3 26 O Aig 4 25 5 24 A44 As 6 23 A43 O07 22 0 A42 A 8 2110 Aq As 19 200 NC Ag 110 19 103 111 18 O 105 CE 12 17 IO4 OE 113 16 O 100 GND 114 15 WE Selection Guide CY7C106D 10 CY7C1006D 10 Unit Maximum Access Time 10 ns Maximum Operating Current 80 mA Maximum Standby Current 3 mA Note 2 NC pins are not connected on the die Document 38 05459 Rev E Page 2 of 11 Feedback CYPRESS
10. the load conditions shown in Figure a High Z characteristics are tested for all speeds using the test load shown in Figure c Page 4 of 11 Document 38 05459 Rev E Feedback CY7C106D ZCYPRESS 076100600 PERFORM Switching Characteristics Over the Operating Range P 7C106D 10 Parameter Description 7C1006D 10 Unit Min Max Read Cycle toower Vec typical to the first access 100 us Read Cycle Time 10 ns taa Address to Data Valid 10 ns Data Hold from Address Change 3 ns tACE CE LOW to Data Valid 10 ns OE LOW to Data Valid 5 ns 170 LOW to Low 2 0 ns luzoE OE HIGH to High 2 8 91 5 ns lizcE CE LOW to Low Z P 3 ns tuzce CE HIGH to High 2 9 5 ns tpy 01 CE LOW to Power Up 0 ns tp 4 CE HIGH to Power Down 10 ns Write Cycle twe Write Cycle Time 10 ns LOW to Write End 7 ns taw Address Set Up to Write End 7 ns tua Address Hold from Write End 0 ns tsa Address Set Up to Write Start 0 ns tpwe WE Pulse Width 7 ns tsp Data Set Up to Write End 6 ns tup Data Hold from Write End 0 ns WE HIGH to Low Z 9 3 ns tuzwe WE LOW to High 2 I9 9 5 ns Notes 6 Test conditions assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V and output loading of the specified and 30 pF load capacitance 7 tpower gives the
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