Cypress CY62148E User's Manual
Contents
1. 1 mA 24 24 V Voltage VoL Output LOW Voltage 10 2 1 mA 0 4 0 4 V Vin Input HIGH Voltage Vcc 4 5V to 5 5V 2 2 Voc 05 2 2 05 V Vi Input LOW voltage Vcc 4 5V to 5 5V For TSOPII 0 5 0 8 V package For SOIC 0 5 0 6 package lix Input Leakage GND Vj lt Vee 1 1 1 1 uA Current loz Output Leakage GND lt Vo lt Vcc Output Disabled 1 1 1 1 uA Current loc Voc Operating f fmax 1 tac Vcc Vocc max 15 20 15 20 mA Supply Current lout 0 mA 1 MHz CMOS levels 2 5 2 5 Isg2 P Automatic CE Power CE gt Vec 0 2V 1 7 1 7 uA down Current Vin gt Vec 0 2V or Vin lt 0 2 CMOS Inputs f 0 Vcc Capacitance For All Packages 11 Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz 10 pF Cout Output Capacitance Voc Vecityp 10 pF Notes 5 ViL min 2 0V for pulse durations less than 20 ns for lt 30 mA 6 Vin max Vcc 0 75V for pulse durations less than 20 ns 7 Full device AC operation assumes a minimum of 100 us ramp time from 0 to Vcc min and 200 us wait time after Vcc stabilization 8 Under DC conditions the device meets a Vj of 0 8V However in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0 6V This is applicable to SOIC package only Refer to AN13470 for details 9 Only chip enable CE must be HIGH at CMOS level to meet the Igg2 spec Other inputs can be left floating 10 T2. P 0 r a sw s s gt W ra SSE ecr T ED CY62148E MoBL YPRESS PERFORM Features Very high speed 45 ns Voltage range 4 5V 5 5V Pin compatible with CY62148B Ultra low standby power Typical standby current 1 uA Maximum standby current 7 pA Industrial Ultra low active power Typical active current 2 0 mA f 1 MHz Easy memory expansion with CE and OE features Automatic power down when deselected CMOS for optimum speed and power Available in Pb free 32 pin TSOP II and 32 pin SOIC packages 4 Mbit 512K x 8 Static RAM Functional Description 1 The CY62148E is a high performance CMOS static RAM organized as 512K words by 8 bits This device features advanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling Placing the device into standby mode reduces power consumption by more than 99 when deselected CE HIGH The eight input and output pins IOg through 107 are placed in a high impedance state when Deselected CE HIGH Outputs are disabled OE HIGH Write operation is active CE LOW and WE LOW To write to the device take Chip Enable CE and Write Ena
3. tyzoe is less than tj zog and tyzwe_ is less than tj for any given device 14 tuzoe gt and tyzwe transitions are measured when the outputs enter a high impedance state 15 The internal write time of the memory is defined by the overlap of WE CE Vi All signals must be ACTIVE to initiate a write and any of these signals terminate a write by going INACTIVE The data input setup and hold timing should be referenced to the edge of the signal that terminates the write Document 38 05442 Rev F Page 5 of 10 Feedback Pe SSS CYPRESS CY62148E PERFORM Wq C Switching Waveforms Read Cycle No 1 Address Transition Controlled 16 17 tRC ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 2 OE Controlled 7 18 tpog Scc CH HIGH IMPEDANCE tLZ0E HIGH IMPEDANCE DATA OUT Vcc SUPPLY CURRENT Isp Write Cycle No 1 WE Controlled OE HIGH During Write 19 201 twc lt tscE taw tha gt tsa tpwe WE NI SN Xs E LLK lup DATA IO norz GXXX DATA VALID tHZOE Notes BEEN 16 Device is continuously selected OE CE Vi 17 WE is HIGH for read cycles 18 Address valid before or similar to CE transition LOW 19 Data IO is high impedance if OE 20 If CE goes HIGH simultaneously with WE HIGH the output remains in
4. x lt er er Pin Configuration 2 4 32 pin SOIC TSOP II Pinout Top View Note 4 NC pins are not connected on the die Document 38 05442 Rev F Page 2 of 10 Feedback CYPRESS PERFORM III QQ Maximum Ratings Exceeding maximum ratings may impair the useful life of the device These user guidelines are not tested 65 to 150 C Ambient Temperature with Storage Temperature CY62148E MoBL DC Input Voltage 0 5V to 6 0V Vccmax 0 5V Output Current into Outputs LOW 20 mA Static Discharge gt 2001V per MIL STD 883 Method 3015 Latch p Current 0 iret teer Etat 2200mA Power 55 C to 125 C Operating Range Supply Voltage to Ground Ambi mbient 0 5 to 6 0V Vocmax 0 5V Device Range temperature Vec DC Voltage Applied to Outputs n o o in High Z State 8l Ms esu ee S9 616165 Electrical Characteristics Over the Operating Range NE 45 ns 55 ns 12 Parameter Description Test Conditions I 3 3 Unit Min Typ I Max Min l Max Output HIGH
5. 03 See ECN NXR Included Automotive Range in product offering Updated the Ordering Information D 485639 See ECN VKN Corrected the operating range to 4 5V 5 5V on page 3 833080 See ECN VKN Added footnote 8 Added V spec for SOIC package F 890962 See ECN Document 38 05442 Rev F VKN Added Automotive A part and its related information Removed Automotive E part and its related information Added footnote 2 related to SOIC package Added footnote 9 related to Isp2 Added AC values for 55 ns Industrial SOIC range Updated Ordering Information table Page 10 of 10 Feedback
6. ble WE inputs LOW Data on the eight IO pins IOo through 107 is then written into the location specified on the address pins Ag through A48 To read from the device take Chip Enable CE and Output Enable OE LOW while forcing Write Enable WE HIGH Under these conditions the contents of the memory location specified by the address pins appear on the IO pins Product Portfolio Power Dissipation Product Range Vcc Range V ena Operating mA Standby 15 2 uA f 1MHz f fmax Min Typ 3 B Max B Max 3 Max CY62148ELL TSOP II Ind l 4 5 5 0 5 5 45 2 2 5 15 20 1 7 CY62148bLL SOIC Ind l Auto A 4 5 5 0 5 5 55 2 2 5 15 20 1 7 Notes 1 For best practice recommendations refer to the Cypress application note System Design Guidelines at http www cypress com 2 SOIC package is available only in 55 ns speed bin 3 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Vcc Vecityp TA 25 C 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 28 2007 Cypress Semiconductor Corporation Document 38 05442 Rev F Feedback CYPRESS CY62148E MoBL PERFORM Logic Block Diagram v gt 100 A2 E 8 me 102 Ag g 103 A7 a EE ER gt IO 4 6 CE gt IO 7
7. ct Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Feedback QG CYPRESS PERFORM Document History Page CY62148E MoBL Document Title CY62148E MoBL 4 Mbit 512K x 8 Static RAM Document Number 38 05442 REV ECN NO Issue Date Orig of Change Description of Change 201580 01 08 04 AJU New Data Sheet 249276 See ECN SYT Changed from Advance Information to Preliminary Moved Product Portfolio to Page 2 Added RTSOP Il and Removed FBGA Package Changed Vcc stabilization time in footnote 7 from 100 us to 200 us Changed from 2 0 pA to 2 5 uA Changed typo in Data Retention Characteristics tp from 100 us to tac ns Changed tora from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tyzoe tyzwe from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tscg from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed thzce from 12 to18 ns for 35 ns Speed Bin and 15 to 22 n
8. ested initially and after any design or process changes that may affect these parameters Document 38 05442 Rev F Page 3 of 10 Feedback CY62148E MoBL Thermal Resistance 9 e i SOIC TSOP II Parameter Description Test Conditions Package Package Unit OJA Thermal Resistance Still Air soldered on a 3 x 4 5 inch 75 77 C W Junction to Ambient two layer printed circuit board Oje Thermal Resistance 10 13 C W Junction to Case AC Test Loads and Waveforms R1 Vec ALL INPUT PULSES OUTPUT 3 0V 90 10 30 pF R2 GND 2 ii Rise Time 1 V ns gt Fall Time 1 V ns INCLUDING 7 JIG AND SCOPE Equivalent to THEVENIN EQUIVALENT OUTPUT o AT V Parameters 5 0V Unit R1 1800 O R2 990 Q Riu 639 Q VTH 1 77 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ B Max Unit Vor for Data Retention 2 V Data Retention Current Vcc Vor CE gt Vec 0 2V Ind l Auto A 1 7 LA Vin gt Vec 0 2V or lt 0 2 tepr 0 Chip Deselect to Data Retention Time 0 ns tr m Operation Recovery Time tac ns Data Retention Waveform Note Document 38 05442 Rev F DATA RETENTION MODE VpR gt 2 0V 11 Full device operation requires linear Vcc ramp from Vpg to Vcc min gt 100 us or stable at Vcc min gt 100 us Vcc
9. high impedance state 21 During this period the IOs are in output state and input signals must not be applied Document 38 05442 Rev F Page 6 of 10 Feedback CYPRESS CY62148E MoBL PERFORM Switching Waveforms continued Write Cycle No 2 CE Controlled 9 201 uc u H CE tHA tpwe t t SD HD DATA IO DATA VALID Write Cycle No 3 WE Controlled OE LOW 2 Osx A 15 900 un EC I rs 99 lizwE tHZWE Truth Table CE WE OE 10 s Mode Power H X X High Z Deselect Power down Standby lag L H L Data Out Read Active lcc L L X Data In Write Active lcc L H H High Z Selected Outputs Disabled Active lcc Page 7 of 10 Document 38 05442 Rev F Feedback CY62148E MoBL Ordering Information por Ordering Code Died Package Type de 45 CY62148ELL 45ZSXI 51 85095 32 pin Thin Small Outline Package II Pb free Industrial 55 CY62148ELL 55SXI 51 85081 32 pin Small Outline Integrated Circuit Pb free Industrial 55 CY62148ELL 55SXA 51 85081 32 pin Small Outline Integrated Circuit Pb free Automotive A Contact your local Cypress sales representative for availability of these parts Package Diagrams Figure 1 32 pin TSOP 51 85095 SEE DETAIL DIMENSIONS IN MILLIMETERS MIN MAX 15 5 TOP VIEW 127 BSC DETAIL A 51 85095 Page 8 of 10 Doc
10. min tR Page 4 of 10 Feedback CYPRESS PERFORM Switching Characteristics Over the Operating Range 112 CY62148E MoBL Parameter Description sans Unit Min Max Min Max Read Cycle tre Read Cycle Time 45 55 ns tAA Address to Data Valid 45 55 ns toHA Data Hold from Address Change 10 10 ns tace CE LOW to Data Valid 45 55 ns tpoE OE LOW to Data Valid 22 25 ns tLzoE OE LOW to Low Z 3 5 5 ns tHZOE OE HIGH to High 2 113 14 18 20 ns tLzcE CE LOW to Low Z 10 10 ns tuzcE CE HIGH to High Z 113 14 18 20 ns tpu CE LOW to Power up 0 0 5 tpp CE HIGH to Power down 45 55 ns Write Cycle 15 twe Write Cycle Time 45 55 ns tsce CE LOW to Write End 35 40 ns taw Address Setup to Write End 35 40 ns tua Address Hold from Write End 0 0 ns tsa Address Setup to Write Start 0 0 ns tPwE WE Pulse Width 35 40 ns tsp Data Setup to Write End 25 25 ns tup Data Hold from Write End 0 0 ns tuzwE WE LOW to High z 13 141 18 20 ns tLzwE WE HIGH to Low z 3l 10 10 ns Notes 12 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to and output loading of the specified lo as shown in the AC Test Loads and Waveforms on page 4 13 At any given temperature and voltage condition tyzcg is less than tj zcg
11. s for 45 ns Speed Bin Changed tsp from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed from 15 to 18 ns for 35 ns Speed Bin Corrected typo in Package Name Changed Ordering Information to include Pb Free Packages B 414820 See ECN ZSD Changed from Preliminary to Final Changed the address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Removed 35ns Speed Bin Removed L version of CY62148E Changed Icc Typ value from 1 5 mA to 2 mA at f 1 MHz Changed lcc Max value from 2 mA to 2 5 mA at f 1 MHz Changed Icc Typ value from 12 mA to 15 mA at f fmax Removed Isp spec from the Electrical characteristics table Changed Ispo Typ values from 0 7 uA to 1 uA and Max values from 2 5 pA to 7 pA Modified footnote 4 to include current limit Removed redundant footnote on DNU pins Changed the AC testload capacitance from 100 pF to 30 pF on page 4 Changed test load parameters R1 R2 and VrTr from 1838 994 645 and 1 75V to 1800 990 639 and 1 77V Changed from 2 5 pA to 7 pA Added Iccpr typical value Changed t zog from 3 ns to 5 ns Changed t zce and tj zyg from 6 ns to 10 ns Changed tyzcg from 22 ns to 18 ns Changed tpwe_ from 30 ns to 35 ns Changed tsp from 22 ns to 25 ns Updated the ordering information table and replaced Package Name column with Package Diagram C 4645
12. ument 38 05442 Rev F Feedback c is P CYPRESS PERFORM Package Diagrams continued Figure 2 32 pin 450 MIL Molded SOIC 51 85081 16 1 AHHHHHHEHHHHHHHH 0 546 13 868 0 566 14 376 0 440 11 176 0 450 11 430 HHBHOHUSHHBH IHH 17 32 0 793 20 142 0 817 20 751 0 006 0 152 0 012 0 304 0 101 2 565 0 118 2 997 CY62148E MoBL 0 11102 819 il pov i i H HH HEHEHEHEHE H 4 0 050 1 270 Lee 0 004 j BSC 0 014 0 355 JL 0 020 0 508 SEATING PLANE 0 047 1 193 0 063 1 600 0 023 0 584 0 039 0 990 51 85081 B MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05442 Rev F products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Page 9 of 10 Cypress Semiconductor Corporation 2006 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress produ
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