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AMD HYPERTRANSPORT 8151 User's Manual

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1. 20 0 cee eens 10 Functional Operation s 5 600565 eau ke rh oe ERROR s Ene A T RE CORSE ee eee 11 4 pdb wb waldo ee E E dd ceded E aa ES a qon ed bagel 11 4 2 Reset And Initialization 0 eee aa 11 AB pT UE 11 43 Clock Gating aie aie RSs eee Rohe eC RUE RC SOR OUR UR SCR SURE 11 44 Tunnel Lan KS gcc ance teen etes d dre Dioni db Re eps E aa Da ast 12 44 Link PHY eO PERDE spans dette 12 RI OR UR RH RAE 12 4 5 1 Tags UnitIDs And Ordering cette 12 4 5 2 Various Behaviors PX REN a HER hehe ie EE 13 4 5 2 1 AGP Compensation And Calibration Cycles eee 13 ob ip 14 5 1 Register Overview end ewok sn Uo baad dS ORM OES OAR oat a QU AR Qr pa tud Od aed da 14 5 1 Configuration Space deve ER De E EE DER IUE e Re Vedi us 14 5 1 2 Register Naming and Description Conventions 14 52 AGP Device Configuration Registers 0 ene 15 5 3 AGP Bridge Configuration Registers 0 0 cect 30 Electrical Data vocis Gis wee sd RUP E EU PVP ales 34 6 1 Absolute Ratings 0 0 hm hs 34 62 Operating Ran
2. 10 20AD SAA 17AC 3K 3R 3T 13C 13D 12E 20W 21W 22W 20Y 18AC 22B 21A 20B 19A 17A 16B 15A 14B 21E 21D 19E 19D 17D Table 15 Signal BGA positions Signal name LRACAD_N13 LRACAD_N14 LRACAD 5 LRACAD PO LRACAD PI LRACAD P2 LRACAD P3 LRACAD P4 LRACAD P5 LRACAD P6 LRACAD P7 LRACAD P8 LRACAD P9 LRACAD 0 LRACAD PII LRACAD 2 LRACAD 3 LRACAD 4 LRACAD PI5 LRACLKO N LRACLKO P LRACLKI N LRACLKI P LRACTL N LRACTL P LRBCAD NO LRBCAD NI LRBCAD N2 LRBCAD N3 LRBCAD LRBCAD N5 LRBCAD N6 LRBCAD N7 LRBCAD 0 LRBCAD PI LRBCAD P2 LRBCAD P3 LRBCAD P4 LRBCAD P5 LRBCAD P6 LRBCAD P7 LRBCLKO N LRBCLKO P LRBCTL N LRBCTL P LTACAD NO LTACAD NI LTACAD N2 LTACAD N3 LTACAD_N4 LTACAD N5 LTACAD N6 Ball 15E 15D 13E 22C 22A 20C 20A 18A 16C 16A 14C 22E 21C 20E 19C 17C 16E 15C 14E 18B 18C 17E 18E 13A 14A 23Y 24W 23V 24U 20U 21U 20R 21R 22Y 24Y 22V 24V 20V 22U 20T 22R 23T 22T 24R 24T 4A 4C 6A 6C 8C 10A 10C Signal name LTACAD N7 LTACAD 8 LTACAD N9 LTACAD NIO LTACAD NII LTACAD 2 LTACAD NI3 LTACAD 4 LTACAD 5 LTACAD PO LTACAD PI LTACAD P2 LTACAD P3 LTACAD P4 LTACAD P5 LTACAD P6 LTACAD P7 LTACAD P8 LTACAD P9 LTACAD 0 LTACAD PII LTACAD 2 LTACAD 3 LTACAD 4 LTACAD PI5 LTACLKO N LTACLKO P LTACLKI1_N LTACLK1_P LTACTL_N LTACTL_P LTBCAD_NO LTBCAD NI LTBCAD N2 LTBCAD N3 LTBCAD_N4 L
3. AGP Tunnel Data Sheet NAND tree 1 output signal is STRAPL 5 However the gate connected to the last signal in this NAND tree LDTCOMP 3 is an AND gate rather than a NAND gate so the expected output of this NAND tree is inverted compared to the other NAND trees LRBCLKO LRBCAD 1 Slol nN tn BWI LRBCAD BN LRBCAD LRBCAD BN LRBCAD LRBCAD BN LRBCAD JH 112 13 14 15 116 LRBCAD BN 7 10 LRBCTL 1 12 13 14 15 16 17 18 19 20 LTBCLKO_P LTBCLKO_N LTBCAD_P 0 LTBCAD_N 0 LTBCAD_P 1 LTBCAD_N 1 LTBCAD_P 2 LTBCAD N 2 LTBCAD P 3 LTBCAD N 3 NAND tree 2 output signal is STRAPL 4 LRACLKO LRACLK1 LRACAD LRACAD 8 LRACAD_ PNI 1 CO tn d WN j ery 5 LRACAD_ P N 9 LRACAD 0 LRACAD 3 LRACAD LRACAD_ P N 4 LRACAD BN 12 LRACAD 5 LRACAD BN 13 LRACAD LRACAD_ PN 14 LRACAD BNI 7 LRACAD BN I5 LRACTL LTACLKO P 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 LTACLKO_N LTACLK1_P N LTACAD_P 0 LTACAD NI 0 LTACAD 8 LTACAD_N 8 LTACAD LTACAD LTACAD P 9 LTACAD N 9 LTACAD 2 LTACAD N 2 LTACAD PT 10 LTACAD N 10 LTACAD P 3 LTACAD N 3 LTACAD
4. A_PCLK to active to float delay Strobe active to first edge delay Strobe final edge to float delay Receive requirement for last strobe setup time to next A_PCLK Receive requirement for first strobe hold time after A_PCLK Receive data setup time to strobe Receive data hold time after strobe Transmit rise and fall slew rate Table 14 AC data for clock forwarded operation of AGP signals 38 AMDA 24888 Rev 3 03 July 12 2004 7 AA AB AC AD Ball Designations VDD12A VSS VDD12A A_DBIH A_SBAO A_SBA2 A_SBA3 A SBAS A_SBAG A_AD31 A_AD29 A_AD28 A_AD26 A_AD25 A AD STBI P A AD23 A 2 A AD20 A ADI9 2 VDD12A VSS VDD12A VSS VDD12A A DBIL A SBAI VSS A_SBAT A_AD30 VSS A AD27 A AD24 VSS A AD STBI N A AD22 VSS A ADI VSS 2 3 LTACAD PO vss LTACAD 8 LTACAD 8 LTACAD P9 VSS VDD12A STRAPL 0 STRAPL 10 FREE1 vss STRAPL 1 1 vss FREE2 FREE3 vss A ST2 A CBE 13 vss STRAPL n A ADI8 A AD16 A CBE 12 3 4 5 6 7 8 9 10 LTACAD LTACAD LTACAD LTACLKO LTACLKO LTACAD LTACAD NO 2 M P N P5 NS LTACAD VDD18 LTACAD VSS LTACAD VDD18 LTACAD Pl P3 P4 P6 LTACAD LTACAD LTACAD LTACAD LTACAD LTACAD N N M NB N6 VDD18 LTACAD VSS VDD18 LTACAD VSS
5. Per the link protocol when the COMPAT bit is set in the transaction the IC does not ever claim the transac tion Such transactions are automatically passed to the other side of the tunnel or master aborted if the IC is at the end of the chain This is true of all transactions within address space that is otherwise claimed by the IC including the space defined by DevB 0x3C VGAEN 4 5 2 1 AGP Compensation And Calibration Cycles The AGP PHY includes one compensation circuit for the clock forwarded data signals A AD 31 0 A CBE L 3 0 and A DBI H L and one compensation circuit for the strobes A ADSTB 1 0 Each com pensation circuit calculates the required rising edge P and falling edge N signal drive strength through a free running state machine that generates a new value approximately every four microseconds These values are provided in DevA 0x 50 54 NCOMP PCOMP Programmable skew values between data signals and strobes are also provided in DevA 0x58 The compensation values provided to the AGP PHY are software selectable between the calculated compensa tion values fixed programmable bypass values or fixed programmable offsets from the calculated values Regardless of which value is selected the value presented to the PHY is never updated until there is a calibra tion cycle Calibration cycles consist of taking control of the AGP bus updating the AGP PHY compensation values and then releasing see DevA 0xA8 PCALCY
6. 21 21AA 21AB 22H 22AB 23G 23AA 23AC 24F 24G 24AB 4H 4M 4R 4V 4AA 6K 6M 6P Signal name 5 VDD15 VDD15 VDD15 5 5 5 5 5 5 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 5 5 5 5 5 5 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 5 5 5 5 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 Ball 6T 6V 7L 7R 7U 7W 8K 8M 8P 8T 8V 9L 9N 9R 9U 9W 10T 10V 10AA 11U 11W 12T 12V 13U 13W 13 14T 14V 14Y 15W 4D 5B 6F 7G 8D 8F 8H 9B 9G 10F 10H 10K 10M 10P 11G 11J IIR 12D Signal name VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 Ball 12F 12H 12K 12M 12P 13B 13G 13J 13L 13N 13R 14F 14H 14K 14M 14P 15G 15J 15L 15N 15R 16D 16F 16H 16K 16M 16P 17B 17G 17L 17N 17R 17U 18F 18M 18P 18T 18V 19G 19L 19N 19R 19U 19W 20D 20F 21B 21K 21P 21V 23J 23N Signal name VDD18 VDD33 VDD33
7. AGP Tunnel Data Sheet 3 4 Test and Miscellaneous Signals Pin name and description IO cell Power During After type plane reset reset CMPOVR Link automatic compensation override 0 Link automatic compensation Input VDD33 is enabled 1 The compensation values stored in DevA 0x E0 E4 E8 control the compensation circuit The state of this signal determines the default value for DevA 0x E0 E4 E8 ACTL and BCTL at the rising edge of PWROK FREE 7 1 These should be left unconnected LDTSTOP Link disconnect control signal This pin is also used for test mode Input VDD33 selection see section 9 NC 1 0 These should be left unconnected PWROK Power OK 1 All power planes are valid The rising edge of this signal is Input VDD33 deglitched it is not observed internally until it is high for more than 6 consecutive REFCLK cycles See section 4 2 for more details about this signal REFCLK 66 MHz reference clock This is required to be operational and valid fora Input VDD33 minimum of 200 microseconds prior to the rising edge of PWROK and always while PWROK is high RESET Reset input See section 4 2 for details Input VDD33 STRAPL 19 13 11 0 Strapping option to be tied low These pins should be tiedto IO VDDIS 3 State 3 State ground STRAPLO is used for test mode selection see section 9 STRAPL 22 20 Strapping option to be tied low These pins shou
8. The IC uses this loopback to help match the external trace delay 4 3 1 Clock Gating Internal clocks may be disabled during power managed system states such as power on suspend It is required that all upstream requests initiated by the IC be suspended while in this state To enable clock gating DevA 0xFO ICGSMAF is programmed to the values in which clock gating will be enabled Stop Grant cycles and STPCLK deassertion link broadcasts interact to define the window in which the IC is enabled for clock gating during LDTSTOP assertions The system is placed into power managed states by steps that include a broadcast over the links of the Stop Grant cycle that includes the System Management Action Field SMAF followed by the assertion of LDTSTOP When the IC detects the Stop Grant broadcast which is enabled for clock gating it enables clock gating for the next assertion of LDTSTOP While exiting the power managed state the system 1s required to broadcast a STPCLK deassertion message The IC uses this message to disable clock gating during LDTSTOP assertions This is important because an LDTSTOP asser tion is not guaranteed to occur after the Stop Grant broadcast is received The clock gating window must be closed to insure that clock gating does not occur during Stop Grant for LDTSTOP assertions that are not asso ciated with the power states specified by DevA 0xFO ICGSMAF 11 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunne
9. 17AB 18D 18G 18J 18L 18N 18R 18U 18W 18AA 19B 19F 19K 19M 19P 19T 19V 19Y 19AB 20G 20K 20AA 20AC 21F 21H 21M 21T 14AB 15B 15 15 15K 15M 15P 15T 15U 15V 16G 16J 16L 16N Ball 21Y 22D 22G 22 22 22AC 23C 23D 23F 23H 23L 23R 23W 23AB 24E 24H 24AA 41 AMDA 24888 Rev 3 03 July 12 2004 8 Package Specification A1 CORNER iim 7 X a 000 e OOOO i 1 DOQ D000 s 4 DOGO 9 1 DOOO 1 9 0000 E3 T t rE E2 E wlio N OOO gt DOG r DOO t ooo u ooo v ooo v ooo T boo we B 1 Y M 2272 2 P NUELTAEJO 33124 876542321 D2 TOP VIEW NOT TO SCALE BOTTOM VIEW SIDE VIEW GENERAL NOTES 1 All dimensions are specified in millimeters mm 2 Dimensioning and tolerancing per ASME Y 14 5M 1994 This corner which consists of a triangle on both sides of the package identifies ball A1 corner and can be used for handling and orientation purposes 4 Symbol M determines ball matrix size and N is number of balls A Dimension b is measured at maximum solder ball diameter on a plane parallel to datum C A X in front of package variation denotes non qualified package per AMD 01 002 3 7 The following features are not shown on drawings a Marking on die
10. LTACAD_N I11 LTACAD 4 21 4l 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 LTBCAD 4 LTBCAD 4 LTBCAD 5 LTBCAD NI 5 LTBCAD P 6 LTBCAD NI6 LTBCAD P 7 LTBCAD N 7 LTBCIL P LTBCTL N LTACAD LTACAD P 12 LTACAD 2 LTACAD 5 LTACAD NI5 LTACAD 3 LTACAD N 13 LTACAD P 6 LTACAD NI6 LTACAD 4 LTACAD 4 LTACAD P 7 LTACAD NI 7 LTACAD 5 LTACAD N 15 LTACTL P LTACTL N 31 LDTCOMPD 32 LDTCOMP 3 44 AMDA 24888 Rev 3 03 July 12 2004 NAND tree 3 output signal is STRAPL 3 STRAPL 1 8 STRAPL 10 STRAPL 9 A_GC8XDET A SBA 0 A SBA I A SBA 2 A SBA 3 A SBSTB N A SBSTB P 12 A SBA 4 13 A SBA 5 14 SBA 6 15 A SBA 7 16 A_GNT 17 STRAPL 11 18 A_REQ 19 STRAPI 13 20 STRAPI 7 WAND tn FW Ne j eni kea i 5 Nand tree 4 output signal is 1 CMPOVR 2 RESETZ 3 PWROK 4 REFCLK 5 A PLLCLKO Notes 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 6 7 8 9 10 A_DBIL A_DBIH A_AD 31 A_AD 30 A_AD 29 A_AD 28 A_AD 27 A_AD 26 A_AD 25 A_AD 24 A_ADSTBI_N A ADSTBI P A AD 23 A AD 22 A ADD A AD 20 A AD 19 A_AD 17 A AD I8 A AD 16 STRAPL 2 A PLLCLKI STRAPL 20 STRAPL 21 STRAPL 22 A_RESET 51 54 56 57 58 59 1 A_CBE_L 2 A_CBE_L 3 A ST 0
11. Read set by hardware write 1 to clear 17 The IC received a target abort as a PCI master on the AGP bus Note this bit is cleared by PWROK reset but not by RESET 27 STA signaled target abort Read set by hardware write 1 to clear 1 The IC generated a target abort as a PCI target on the AGP bus The IC generates target aborts if it receives a target abort a non NXA error response from the host to an AGP bus PCI master transaction request Note this bit is cleared by PWROK reset but not by RESET 26 16 Read only These bits are fixed in their default state 15 12 IOLIM IO limit address bits 15 12 See DevB 0x 30 1C above 11 8 Reserved 7 4 IOBASE IO base address bits 15 12 See DevB 0x 30 1C above 3 0 Reserved DevB 0x20 Default 0000 FFFOh Attribute Read write Bits Description 31 20 MEMLIM Non prefetchable memory limit address bits 31 20 See DevB 0x 30 1C above 19 16 Reserved 15 4 MEMBASE Non prefetchable memory base address bits 31 20 See DevB 0x 30 1C above 3 0 Reserved 32 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet DevB 0x24 Default 0000 FFFOh Attribute Read write Bits Description 31 20 PMEMLIM Prefetchable memory limit address bits 3 1 20 See DevB 0x 30 1C above 19 16 Reserved 15 4 PMEMBASE Prefetchable memor
12. label on package b Laser elements c Die and passive fudicials Figure 4 Package mechanical drawing 9000 AMD 8151 AGP Tunnel Data Sheet A b Nx Plcs Bee eee 2 159 c AMD VARIATIONS PACKAGE xOLF564 SYMBOL min max D E 30 8 312 D1 E1 29 21 BSC D2 E2 27 8 28 2 D3 E3 22 8 23 2 A 3 25 3 56 A1 0 5 0 7 A2 0 9 1 1 e 1 27 BSC b 0 6 0 9 M 24 N 564 aaa 0 2 bbb 0 25 ccc 0 125 So A1 CORNE 42 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 9 Test The IC includes the following test modes Mode TEST A_TYPEDET LDTSTOP STRAPLO Notes Operational 0 X X X High impedance 1 0 0 0 NAND tree 1 0 0 1 Table 17 Test modes 9 1 High Impedance Mode In high impedance mode all the signals of the IC are placed into the high impedance state 9 2 NAND Tree Mode There are several NAND trees in the IC Some of the inputs are differential e g LR B A pins for these the _P and _N pairs of signals are converted into a single signal that is part of the NAND tree as shown in Signal_3 in the following diagram VDD 4 Signal 1 J Py y Signal 2 o i Signal 3 P to output signal m 0 Signal 3 N Signal 41 Output signal NAND Tree Mode Figure 5 NAND tree 43 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151
13. 40 bit link address space to the AGP bus The links support 25 bits of IO space AGP supports 32 bits of IO space Host accesses to the link defined IO region are mapped to the AGP IO window with the 7 MSB always zero AGP IO accesses in which any of the 7 MSBs are other than zero are ignored The AGP IO space window is defined as follow AGP IO window 7 h00 DevB 30 24 16 DevB 0x1C 15 12 12 hFFF gt address gt 7 h00 DevB 30 8 0 DevB 0x1C 7 4 12 h000 The links support 40 bits of memory space AGP supports 32 bits of non prefetchable memory space The AGP non prefetchable window is defined to be within the lowest 4 gigabytes of link address space AGP accesses above 4 gigabytes cannot access non prefetchable memory space The AGP non prefetchable memory space window is defined as follows AGP non prefetchable memory window 32 h00 DevB 0x20 31 20 20 hF FFFF gt address gt 32 h00 DevB 0x20 15 4 200 0000 The links support 40 bits of memory space AGP supports 32 bits of prefetchable memory space The AGP prefetchable window is defined to be within the lowest 4 gigabytes of link address space The AGP prefetch able memory space window is defined as follows AGP prefetchable memory window 32 h00 DevB 0x24 31 20 20 hF FFFF gt address gt 32 h00 DevB 0x24 15 4 420 h0 0000 These windows may also be altered by DevB 0x3C VGAEN ISAEN When the address from either the host or
14. A REFGC AGP signal reference input Analog VDD15 input A_REQ AGP master request signal Input VDD15 Term Term PU PU A AGP bus reset signal This is asserted whenever Output VDD33 Low High Low High RESET is asserted or when programmed by DevB 0x3C SBRST Assertion of this pin does not reset any logic internal to the IC A_RBF AGP read buffer full signal Input VDD15 Term Term PU PU A SBSTB N AGP differential side band address strobe In Input VDD15 Term Term P PU P PU AGP 3 0 signaling mode A SBSTB P is the first strobe and N PD N PD A SBSTB N is the second strobe A SBA 7 0 AGP side band address signals Input VDDIS Term Term PU PU A ST 2 0 AGP status signals Output VDDI5 Term Low PU Low A_STOP AGP target abort signal IO VDDI5 Term Term PU PU A TRDYZ AGP target ready signal IO VDDi5 Term Term PU PU A AGP IO voltage level type detect 0 1 5 volts Input VDD33 1 3 3 volts not supported by the IC The state of this pin is provided in DevA 0x40 TY PEDET This pin is also used for test mode selection see section 9 This signal requires an external pullup resistor to VDD33 on the systemboard A_WBF AGP write buffer full signal Input VDD15 Term Term PU PU The SERR and PERR signals are not supported on the AGP bridge AMDA 24888 Rev 3 03 July 12 2004 AMD 8151
15. AGP 3 0 transfers in the downstream direction fast writes and read responses to AGP master requests For PCI transfers in the downstream direction DBI H L are held inactive and no inversion takes place 0 When the IC drives the A AD lines A DBI H L are driven low Note this bit is only valid when 8x transfer rates are enabled if 1 DevA 0xA4 AGP3MD 0 or 2 DevA 0xA4 AGP3MD 1 and DevA 0xA8 DRATE is not 010b then this field is ignored and the DBI is not enabled 18 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet AGP PHY Control Register DevA 0x 54 50 These registers apply to the compensation values of AGP clock forwarded data and strobe signals as follows DevA 0x50 data signals A_AD 31 0 A_CBE_L 3 0 A DBI H L and A SBA 7 0 DevA 0x54 strobe signals A ADSTB 1 0 P N and A SBSTB P N NCTL NDATA and NCOMP are related to 1 the falling edge drive strength of the signals as outputs and 2 the impedance of the signals as inputs PCTL PDATA and PCOMP are related to the rising edge drive strength of the signals as outputs only For the N PIDATA and N fields of these registers 00h cor responds to the weakest drive strength and the highest receive impedance For the N PIDATA and N P COMP fields of these registers the highest values corresponds to the strongest drive strength and lowest receive impedance External compensation resistors are use
16. Reserved 7 Must be low This bit is required to be low at all times setting it high results in undefined behavior 6 Must be low This bit is required to be low at all times setting it high results in undefined behavior 5 Must be low This bit is required to be low at all times setting it high results in undefined behavior 4 Must be low This bit is required to be low at all times setting it high results in undefined behavior 3 FWDIS fast write disable Read write 1 DevA 0xA4 FWSUP is low 0 DevA 0xA4 FWSUP is high 2 8XDIS AGP 3 0 signaling mode disable Read write 07 The IC drives A MB8XDET low to indicate support for AGP 3 0 signaling 1 7 The IC does not drive MB8XDET low This bit may be used in conjunction with DevB 0x3C SBRST to revert back to AGP 2 0 signaling To do this software should 1 set DevB 0x3C SBRST in order to reset the AGP card 2 set 8XDIS to cause A_MB8XDET to float high and 3 clear DevB 0x3C SBRST TYPEDET AGP voltage type detection Read only This bit reflects the state ofthe A pin O2 The AGP master supports 1 5 volt signaling 12 The AGP master requires 3 3 volt signaling and is therefore not compatible with the IC If this bit is detected high by BIOS an error should be signaled 0 DBIEN dynamic bus inversion enable Read write 1 DBI H L enabled to dynamically invert the state of the AD signals when the IC is driving these This only applies to
17. and corresponding BGA designators Signal name A_ADO 2 A_AD3 A_AD4 A ADS A AD6 A ADT7 A AD8 A AD9 ADIO A A 2 A 2 A 4 A ADIS A 6 A 7 A ADIS8 A ADI9 A AD20 A AD21 AD22 A AD23 A AD24 A AD25 A AD26 A AD27 A AD28 A AD29 A AD30 A AD31 A ADSTBO N A ADSTBO P A ADSTBI N A ADSTBI P A CALD A CALD CALS A CALS A CBE L0 A CBE LI A CBE I2 A CBE L3 A DBIH A DBIL A_DEVSEL A_FRAME A_GC8XDET A_GNT A_IRDY A_MB8XDET Ball 15 15AC 14AC 14AD 13AD 12AB 12AC 12AD 9AD 9AC 8AD 7AD 8AC 6AD 6AC 5AD 3AC 2AB 3AB 1AB 1AA 1Y 2Y 1W 2U 1U IT 2T IR 1P 2P IN 11AD 11AC 2W 6AA 6AB 7Y 8AA 10AD SAC 3AD 3W 1F 2G 9AB 9AA 4K 4L 8AB 4W Signal name A PAR A PCLK PLLCLKI A PLLCLKO A RBFZ A REFCG REFGC A REQ Z A A SBAO A SBAI A SBA2 A SBA3 A_SBA4 A_SBAS A_SBA6 A_SBA7 A_SBSTB_N A_SBSTB_P A_STO 5 A_ST2 A_STOP A_TRDY A_TYPEDET A_WBF CMPOVR FREE2 FREE3 FREE4 FREES FREE6 FREE7 LDTCOMPO LDTCOMPI LDTCOMP2 LDTCOMP3 LDTSTOP LRACAD_NO LRACAD NI LRACAD N2 LRACAD_N3 LRACAD_N4 LRACAD N5 LRACAD N6 LRACAD N7 LRACAD N8 LRACAD N9 LRACAD NIO LRACAD NII LRACAD 2 Ball 12AA 19AC 15AB 15AA 5Y 17AD 16AD 4N 19AD 1G 2H 1H 1J 2L IL IM 2N 2K 1K 4T 4U 3V
18. bridge on the HyperTransport technology chain 1 The hardware set this bit as a result of a write command from the B side of the tunnel to any of the bytes of DevA 0xC0 3 1 16 0 The hardware cleared this bit as a result of a write command from the A side of the tunnel to any of the bytes of DevA 0xC0 31 16 This bit along with DEFDIR is used to determine the side of the tunnel to which AGP master requests are sent 25 21 UnitID count Read only Specifies the number of UnitIDs used by the IC three 20 16 BUID base UnitID Read write This specifies the link protocol base UnitID The IC s logic uses this value to determine the UnitIDs for link request and response packets When a new value is written to this field the response includes a UnitID that is based on the new value in this register Note some legacy operating systems may require that this value be set to zero for normal operation so that the AGP capability block is part of device 0 Since the IC does not use the base unit ID in any link transactions there is no conflict with the host unit ID However at boot BIOS is required to temporarily change the BUID value of the IC so that the BUID values in downstream devices may be initialized After downstream BUID values are initialized this field may be set to zero to be compatible with legacy operating systems 15 8 Reserved 7 0 Capabilities ID Read only Specifies the capabilities ID for link confi
19. from an AGP bus master is inside one of the windows then the transaction targets the AGP bus Therefore the following transactions are possible 31 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet Host initiated transactions inside the windows are routed to the AGP bus PCI transactions initiated on the AGP bus inside the windows are not claimed by the IC Host initiated transactions outside the windows are passed through the tunnel or master aborted if the IC is at the end of a HyperTransport technology chain PCI transactions initiated on the AGP bus outside the windows are claimed by the IC using medium decod ing and passed to the host So for example if IOBASE gt IOLIM then no host initiated IO space transactions are forwarded to the AGP bus and all AGP bus initiated IO space not configuration transactions are forwarded to the host If MEM BASE gt MEMLIM and PMEMBASE gt PMEMLIM then no host initiated memory space transactions are for warded to the AGP bus and all AGP bus initiated memory space not configuration transactions are forwarded to the host DevB 0x1C Default 0220 01 11 Attribute See below Bits Description 31 30 Reserved 29 RMA received master abort Read set by hardware write 1 to clear 1 The IC received a master abort as a PCI master on the AGP bus Note this bit is cleared by PWROK reset but not by RESET 28 RTA received target abort
20. 5 0 ESP enumeration scratchpad Read write This field controls no hardware within the IC Note this bit is cleared by PWROK reset not by RESET 27 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet Link PHY Compensation Control Registers DevA 0x E8 E4 E0 The link PHY circuitry includes automatic compensation that is used to adjust the electrical characteristics for the link transmitters and receivers on both sides of the tunnel There is one compensation circuit for the receiv ers and one for each polarity of the transmitters These registers provide visibility into the calculated output of the compensation circuits the ability to override the calculated value with software controlled values and the ability to offset the calculated values with a fixed difference The overrides and difference values may be dif ferent between sides A and B of the tunnel These registers specify the compensation parameters as follows DevA 0xE0 transmitter rising edge P drive strength compensation DevA 0xE4 transmitter falling edge N drive strength compensation DevA 0xE8 receiver impedance compensation For DevA 0x E4 higher values represent higher drive strength the values range from O1h to 13h 19 steps For DevA 0xE8 higher values represent lower impedance the values range from 00h to 1Fh 32 steps Note the default state of these registers is set by PWROK reset assertion of RESE
21. A ST 1 A ST 2 A_MB8XDET A_RBF A_WBF STRAPL 14 STRAPL 15 STRAPL 17 STRAPL 16 A_IRDY A_DEVSEL A_FRAME STRAPL 6 A_TRDY A CBE A AD I5 A AD 14 A PCLK AMD 8151 AGP Tunnel Data Sheet 61 A AD I2 62 AD I3 63 A_AD 11 64 A_AD 10 65 A_AD 9 66 8 67 A_ADSTBO_N 68 A_ADSTBO_P 69 A_CBE_L 0 70 A_AD 7 71 A_AD 6 72 A_AD 5 73 4 74 A_AD 3 75 A_AD 1 76 A_AD 2 77 A_AD 0 78 A_STOP 79 A_PAR 80 STRAPL 18 STRAPL 19 LDTSTOP A_TYPEDET TEST STRAPL 0 A REFCG A REFGC A_CALD A_CALD A_CALS and A_CALS are not in the NAND trees While in NAND tree mode the link and AGP input compensation is placed at a mid band value While in NAND tree mode the AGP signals operate under AGP 2 0 signaling rules 10 Appendix 10 1 Revision History Revision 3 02 nitial release Revision 3 03 Removed Preliminary 45
22. AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet AMD 8151 HyperTransport AGP3 0 Graphics Tunnel Data Sheet 1 Overview The AMD 8151 HyperTransport AGP3 0 Graphics Tunnel referred to as the IC in this document is a HyperTransport technology referred to as link in this document tunnel developed by AMD that provides an AGP 3 0 compliant 8x transfer rate bridge 11 Device Features HyperTransport technology tunnel with side A and side B e Side A is 16 bits input and output side B is 8 bits Either side may connect to the host or to a downstream HyperTransport technology compliant device Each side supports HyperTransport technol ogy defined reduced bit widths 8 bit 4 bit and 2 bit Side A supports transfer rates of 1600 1200 800 and 400 mega transfers per second Side B supports transfer rates of 800 and 400 mega transfers per second e Maximum bandwidth is 6 4 gigabytes per second across side A half upstream and half downstream and 1 6 gigabytes per second across side B Independent transfer rate and bit width selection for each side Link disconnect protocol supported AMD 8151 Device SideB HyperTransport HyperTransport Side A Link 16 bits upstream 16 bits downstream Figure 1 System block diagram AGP 8x bridge Compliance with AGP 3 0 specification sig naling supporting 4x and 8x transfer rates Compliance with AG
23. APL STRAPL 4 18 A STOP A PAR VSS A AD5 A AD STBO_P A_AD6 A AD STBO_N 11 A_AD7 12 13 14 15 LRACTL LRACTL LRACAD N P LNG VDD18 LRACAD VSS N7 FREE4 LRACAD LRACAD P7 PM FREES VSS LRACAD NM LRACAD 5 LRACAD LRACAD P15 N13 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS 8 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD18 VSS 8 VSS VDD18 VSS VDD18 VSS VDD18 VSS VDD15 VSS VDD15 VSS VSS VSS VDD15 VSS VDD15 VSS VDD15 STRAPL 19 VDD15 STRAPL 20 VDD15 STRAPL A PLL 3 CLKO STRAPL VSS 2 CLKI VSS A AD2 A ADI A AD4 A AD3 A ADO 13 14 15 Top side view AMD 8151 AGP Tunnel Data Sheet 16 17 LRACAD LRACAD 6 M LRACAD N5 VDD18 LRACAD LRACAD P5 2 VDD18 LRACAD 2 LRACAD LRACLK P13 VDD18 vss 8 VDD18 VSS VDDI2A VDD18 VSS vss VDD18 VDD18 vss VDD18 VDD18 vss 8 VDDI2B VSS VDD128 VDD18 VDD12B VSS vss VDD12B STRAPL VSS n STRAPL TEST 2 REFCLK VSS vss CMP OVR A REF A REF GC tG 16 17 18 19 2 21 LRACAD LRACAD LRACAD LRACAD B4 P3 M LRACLK VSS LRACAD VDD18 N2 LRACLK LRACAD LRACAD LRACAD op PH P2 P9 VSS LRACAD VDD18 LRACAD n N9 LRACLK LRACAD LRACAD LRACAD 1P N10 P10 N8 VDD18 VS
24. C If enabled by DevA 0xBO CALDIS they occur periodically with the period specified by DevA 0xA8 PCALCYC 13 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet The first calibration cycle occurs approximately 4 milliseconds after the deassertion of RESET whether AGP 2 0 or 3 0 signaling is enabled 5 Registers 5 1 Register Overview The IC includes several sets of registers accessed through a variety of address spaces IO address space refers to register addresses that are accessed through x86 IO instructions such as IN and OUT PCI configuration space is typically accessed by the host through IO cycles to CF8h and CFCh There is also memory space and indexed address space in the IC 5 1 1 Configuration Space The address space for the IC configuration registers is broken up into busses devices functions and offsets as defined by the link specification It is accessed by HyperTransport technology defined type 0 configuration cycles The device number is mapped into bits 15 11 of the configuration address The function number is mapped into bits 10 8 of the configuration address The offset is mapped to bits 7 2 of the configuration address The following diagram shows the devices in configuration space as viewed by software Primary bus AGP Device AGP Bridge DevA 0xXX DevB 0xXX Device header Bridge header First device Second device Function 0 Function 0 AGP Slot Secondary b
25. GSZSEL page size select Read write The only legal value for these bits is 0000b which specifies a 4 kilobyte page 27 Reserved 26 16 Page size support Read only These bits are fixed in their default state to indicate that the IC supports 4 kilobyte pages 15 12 Reserved 23 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet APSIZE graphic virtual memory aperture size Read write except bits 11 7 6 and 2 0 which are read only fixed at the default value This field specifies the size of the aperture pointed to by DevA 0x10 This field also controls read only versus read write control over several bits in DevA 0x10 It is encoded as follows DevA 0x10 DevA 0x10 Bits 10 9 8 5 4 3 Aperture size read write bits read only bits 1 1 1 1 1 1 32 MB 63 25 24 0 0 64 MB 63 26 25 0 0 0 128 MB 63 27 26 0 0 256 MB 63 28 27 0 0 512 MB 63 29 28 0 0 1024 63 30 29 0 0 0 0 0 2048 MB 63 31 30 0 It is expected that the state of this field is copied into the host by software Note DevA 0x10 2 is read write once even though it is shown as read only above Also based on the state of DevA 0x10 2 DevA 0x10 63 32 may be read only all zeros AGP Device GART Pointer DevA 0xB8 This register controls no hardware in the IC It is expe
26. LDTSTOP assertion 23 Reserved 22 20 Max link width out Read only This specifies the width of the outgoing link to be 16 bits wide for side A and 8 bits wide for side B 19 Reserved 25 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 18 16 Max link width in Read only This specifies the width of the incoming link to be 16 bits wide for side A and 8 bits wide for side B Reserved EXTCTL extended control time during initialization Read write This specifies the time in which LT B A CTL is held asserted during the initialization sequence that follows an LDTSTOP deassertion after LR B A CTL is detected asserted 0 At least 16 bit times 1 About 50 microseconds Note this bit is cleared by PWROK reset but not by RESET LDT3SEN link three state enable Read write 1 During the LDTSTOP disconnect sequence the link transmitter signals are placed into the high impedance state and the receivers are prepared for the high impedance mode For the receivers this includes cutting power to the receiver differential amplifiers and ensuring that there are no resultant high current paths in the circuits 07 During the LDTSTOP disconnect sequence the link transmitter signals are driven but in an undefined state and the link receiver signals are assumed to be driven Note this bit is cleared by PWROK reset but not by RESET AMD recommends that this bit be set high in single proc
27. P 2 0 specification 1 5 volt signaling supporting 1x 2x and 4x data transfer modes Supports up to 32 outstanding requests 31 x 31 millimeter 564 ball BGA package 1 5 volt AGP signaling some 3 3 volt IO 1 2 volt link signaling 1 8 volt core Downstream Device Link 8 bits upstream 8 bits downstream AGP Graphics Controller AMDA 24888 Rev 3 03 July 12 2004 Trademarks 2004 Advanced Micro Devices Inc All rights reserved The contents of this document are provided in connec tion with Advanced Micro Devices Inc AMD products AMD makes no representations or warranties with respect to the accuracy or complete ness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice No license whether express implied arising by estoppel or other wise to any intellectual property rights is granted by this publication Except as set forth in AMD s Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including but not limited to the implied warranty of merchantability fitness for a particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in sys tems intended for surgical implant into the body or in other applicati
28. P10 P P13 LTACAD LTACAD LTACAD LTACAD LTACAD LTACAD LTACAD N9 Pli NH P12 N12 Pl NM VDD12A VSS VDD18 VSS VDD18 VSS 8 VDDI2A VDD12A VSS VDD18 VSS VDD18 vss VDDIS VSS VDDI2A VSS VDD18 vss 8 STRAPL STRAPL VSS VDDI2A VDDI2A VDD12A VSS 1 8 A GCBX VSS VDDIS VSS VDDIS VSS 8 DET ALGNT STRAPL VSS VDDIS VSS VDDI5 VSS 9 VDDIS VSS VDDIS VSS VDDIS vss 8 AREQ amp VSS VSS VDDIS VSS VDDI5 vss STRAPL STRAPL VDD15 VSS VDDIS VSS VDD18 3 7 VDDIS VSS VSS VDDIS VSS VDDI5 VSS ASTO VSS VDDIS VSS VDDIS VSS VDDI15 AST1 VSS VSS VDDIS VSS VDDIS vss VDDIS VSS VDDIS VSS VDDIS vss 5 VSS VSS VDDIS VSS VDDI5 vss DET NCO A RBF VSS A_CALS STRAPL STRAPL VSS 5 6 VDDIS A WBF A CALD VDDIS A CALS A_ VDDIS FRAME STRAPL VSS CALD STRAPL A_IRDY A_DEVS TRDY 15 E 16 EL 8 VSS A CBE A ADI4 VSS AADI2 A AD9 VSS L1 STRAPL A ADIS A AD13 A ADII AD10 A_AD8 A_CBE_ y L0 4 5 6 7 8 9 10 Figure 3 Ball designations 11 LTACAD EN 12 LTACAD N7 VSS LTACTL_ LTACAD LTACTL N5 N LTACAD P15 VDD18 FREE7 FREE6 VSS VDD18 VDD18 VSS VSS VDD18 VDD18 VSS VSS VDD18 VDD18 VSS VSS VDD18 VDD18 VSS VSS VDD18 VDD18 VSS VSS VDD15 VDD15 VSS VSS VDD15 VDD15 VSS STR
29. PACES oderint n REI Ie a iae ee eo E eaa REEERE Fee ethadediee 15 Memory mapped address spaces cccescecescescesseeeseceseceseeseeceeeceseecseecseceseeeneeseneseeesaeesseenaeensenaes 15 P E ENE E NEE NA andes 15 Albsolute maximum TANE S 2 dre ie toed 34 Operating TAN GES eve e e ete be pe pese te der e be d Eee Reed ve 34 Current and power consumption sessessseseeseeee eene ener ener 35 DC characteristics for signals on the VDD33 power plane sse 35 DC characteristics for signals on the VDD15 power plane AGP 2 0 signaling 36 DC characteristics for signals on the VDD15 power plane AGP 3 0 signaling 36 AC data fOr COCKS EE 37 AC data for common clock operation of AGP signals 37 AC data for clock forwarded operation of AGP signals sese 38 Signal BGA positions Rr e e E Ui ERE TER EE TER eere TR 40 Power and ground BGA positions sssssssessesseeee ener eren enne nennen nennen nns 41 Test AMD I E 43 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 2 Ordering Information AMD 8151 BL C Ln Case Temperature C Commercial temperature range Package Type BL Organic Ball Grid Array with lid Family Core AMD 8151 3 Signal Descriptions 3 4 Terminology See section 5 1 2 for a descrip
30. S VDD18 VSS vss VDD18 VSS VDD12A VDD12A VDD12A VDD12A VSS VSS VDD12B 2 VDD128 VDD128 VSS vss VDD18 VSS VDD18 LTBCAD LTBCAD P5 P4 VDD18 VSS LTBCAD VSS N5 VSS VDD18 LTBCAD LTBCAD P7 P6 VDD18 VSS LTBCAD VDD18 N7 VSS VDD18 LRBCAD LRBCAD N6 N7 VDD18 VSS LRBCAD VSS 6 VSS VDD18 LRBCAD LRBCAD N4 N5 VDD18 VSS LRBCAD VDD18 4 VSS VDD18 LDTCOM LDTCOM PO P1 VDD12B vss LDTCOM vss P3 VSS VDD12B VSS VDD12B RESET VSS VDD12B VDD128 LDT A PCLK VSS VDD33 STOP PWROK A ATYPE VDD33 RESET DET 18 19 20 21 22 LRACAD PL LRACAD LRACAD 0 VSS LRACAD P8 VDD12A VSS VDD12B VSS LTBCAD LTBCAD Em LTBCAD N3 LTBCAD N6 LTBCTL_ N LRBCAD P7 LRBCLK 0P LRBCAD P5 LRBCAD P2 LDTCOM P2 LRBCAD 0 vss VDD128 VSS VDDA18 22 29 24 A VDD12A B vss C vss VDDA D VDDDA vss E vss VDDDB F VDDD2B VDD28 G vss vss H VDD18 LTBCAD J 0 LTBCAD LTBCAD K PI NO vss LTBCAD L P2 LTBCAD LTBCAD M P3 M2 VDD18 LTBCLKO N P LTBCTL LTBCLKO P N VSS LRBCTL R N LRBCLK LRBCTL T ON P VDD18 LRBCAD U N3 LRBCAD LRBCAD V N2 P3 VSS LRBCAD W LRBCAD LRBCAD Y No Pl VDD28 VSS AA vss VDDD28 AB VDD128 AC AD 29 24 39 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet Alphabetical listing of signals
31. T does not alter any of the fields Default See below Attribute See below Bits Description 31 Must be low Read write This bit is required to be low at all times setting it high results in undefined behavior 30 21 Reserved 20 16 CALCCOMP calculated compensation value Read only This provides the calculated value from the auto compensation circuitry The default value of this field is not predictable 15 Reserved 14 13 BCTL link side B PHY control value Read write These two bits combine to specify the PHY compensation value that is applied to side B of the tunnel as follows BCTL Description 00b Apply CALCCOMP directly as the compensation value 01b Apply BDATA directly as the compensation value 10b Apply the sum of CALCCOMP and BDATA as the compensation value In 0 4 E0 if the sum exceeds 13h then 13h is applied In DevA 0x E8 if the sum exceeds 1Fh then 1Fh is applied 11b Apply the difference of CALCCOMP minus BDATA as the compensation value If the difference is less than 01h then O1h is applied The default value of this field from PWROK reset is controlled by the CMPOVR signal If CMPOVR 0 the default is 00b If CMPOVR 1 the default is 010 12 8 BDATA link side B data value Read write This value is applied to the side B of the tunnel PHY compensation as described in BCTL The default for DevA 0x E4 E0 is 08h The default for DevA OxES is OFh 7 Rese
32. TBCAD N5 LTBCAD N6 LTBCAD N7 LTBCAD PO LTBCAD PI LTBCAD P2 LTBCAD P3 LTBCAD P4 LTBCAD P5 LTBCAD P6 LTBCAD P7 LTBCLKO N LTBCLKO P LTBCTL N LTBCTL P NCO Ball 12A 3C 4E 6E 8E 9C 10E 11C 3A 4B 5A 6B 8B 9A 10B 3D 3E 5D SE 7E 9D 9E 11D 8A 7A 7C 7D 12C 12B 24K 22K 24M 22M 22L 20M 22N 20P 24J 23K 24L 23M 211 20L 21N 20N 24P 24N 22P 23P 4Y Signal name NCI PWROK REFCLK RESET STRAPLO STRAPLI STRAPL2 STRAPL3 STRAPL4 STRAPLS5 STRAPL6 STRAPL7 STRAPL8 STRAPL9 STRAPL10 STRAPLI1 STRAPL13 STRAPL14 STRAPLI5 STRAPL16 STRAPL17 STRAPL18 STRAPL19 STRAPL20 STRAPL21 STRAPL22 TEST Ball 3N 18AD 16AB 18AB 3H 4J 13AB 14AA 11Y 8Y 9Y 5P 5J 51 3M 4 4AB 7AB 4AD 12Y 13Y 15 16Y 16AA 17AA 40 AMDA 24888 Rev 3 03 July 12 2004 Signal name VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12A VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD12B VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Table 16 Power and ground BGA positions Ball 1C 1E 2B 2D 2F 3G 4F 4G 5G 6H 7 8J 9J 17J 18H 19H 20H 21G 22F 23B 23E 24C 24D 16T 16U 16V 17W 18K 18Y 19J 19AA 201 20
33. VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball 23U 21AC 21AD 22AD 1D 2C 2E 21 2 2R 2V 2AA 2AC 3B 3F 3L 3P 3U 3Y 4AC SF 5H 5K 5M 5N 5R 5T 5U 5V 5W 5AB 6D 6G 6J 6L 6N 6R 6U 6W 6Y 7B 7F 7H 7K 7M 7P TY 7N 7AC 8G 8L 8N Signal name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball 8R 8U 8W 9F 9H 9K 9M 9P 9T 9v 10D 10G 10L 10N 10R 10U 10W 10Y 10AC 11B 11V 11AB 12G 12J 12L 12N 12R 12U 12W 13F 13H 13K 13M 13P 13T 13V 13AC 14D 14G 14J 14L 14N 14R 14U 14W AMD 8151 AGP Tunnel Data Sheet Signal name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball Signal name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 16R VSS 16W VSS 16AC VSS 17F 17H 17K 17M 17P 17T 17V 17Y
34. action Link transaction High priority write WrSized posted channel PassPW 1 High priority read RdSized PassPW 1 response PassPW 1 Low priority write WrSized posted channel PassPW 0 Low priority read RdSized PassPW 0 response PassPW 1 Low priority flush Flush PassPW 0 Low priority fence None wait for all outstanding read responses Table 2 Translation from AGP requests to link requests 4 5 2 Various Behaviors The AGP bridge does not claim link special cycles However special cycles that are encoded in configura tion cycles to device 31 of the AGP secondary bus number per the PCI to PCI bridge specification are translated to AGP bus special cycles AGP and PCI read transactions that receive NXA responses from the host complete onto the AGP bus with the data provided by the host which is required to be all 1 s per the link specification In the translation from type 1 link configuration cycles to secondary bus type 0 configuration cycles the IC converts the device number to IDSEL AD signal as follows device 0 maps to AD 16 device 1 maps to AD 17 and so forth Device numbers 16 through 31 are not valid The compensation values for drive strength and input impedance that are assigned to non clock forwarded AGP signals are automatically determined and set by the IC during the first compensation cycle after RESET Once set they do not change until the next RESET assertion
35. ate 20 Capabilities pointer Read only This bit is fixed in the high state 19 3 Read only These bits are fixed in their default state 2 MASEN PCI master enable Read write This bit controls no hardware in the IC 1 MEMEN memory enable Read write 1 Enables access to the memory space specified by DevA 0x10 This bit controls no hardware in the IC 0 IO enable Read only This bit is fixed in the low state AGP Device Revision and Class Code Register DevA 0x08 Default 0600 00 h Attribute See below Bits Description 31 8 CLASSCODE Read write once Provides the AGP bridge class code 7 0 REVISION Read only AGP Device BIST Header Latency Cache Register DevA 0x0C Default 0000 0000h Attribute Read only Bits Description 31 24 BIST These bits fixed at their default values 23 16 HEADER These bits fixed at their default values 15 8 LATENCY These bits fixed at their default values 7 0 CACHE These bits fixed at their default values 16 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet AGP Device Graphic Virtual Memory Aperture Register DevA 0x10 It is expected that the state of this register is copied into the host by software This register controls no hard ware in the IC Default 0000 0000 0000 0008h Attribute See below Bits Description 63 32 APBARHI Read write Aperture base address register high Note bits 63 40 are required to be programmed low setting any of
36. ate clocks during S1 For mobile platforms AMD recommends setting this register to 0004 0A0Ah to gate clocks during C3 and S1 Default 0000 0000h Attribute Read write Bits Description 31 19 Reserved 18 CGEN clock gate enable 1 Internal clock gating as specified by bits 7 0 of this register is enabled 17 Must be low This bit is required to be low at all times setting it high results in undefined behavior 16 Must be low This bit is required to be low at all times setting it high results in undefined behavior 15 8 ECGSMAF external clock gating system management action fields Each of the bits of this field correspond to SMAF values that are captured in Stop Grant cycles from the host For each bit 1 When LDTSTOP is asserted prior to a Stop Grant cycle in which the SMAF field matches the ECGSMAF bit that is asserted then PCLK and internal clock grids associated with the AGP bridges are forced low 0 PCLK and the internal clock grids are active while LDTSTOP is asserted For example if A PCLK gating is required for SMAF values of 3 and 5 then ECGSMAF 3 5 must be high See section 4 3 1 for details 7 0 ICGSMAF internal clock gating system management action fields Each of the bits of this field correspond to SMAF values that are captured in Stop Grant cycles from the host For each bit 1 When LDTSTOP is asserted prior to a Stop Grant cycle in which the SMAF field matches the ICGSMAF bit
37. bits control no internal logic 7 0 INTERRUPT LINE Read write These bits control no internal logic 33 AMD 1 AMD 8151 AGP Tunnel Data Sheet 24888 Rev 3 03 July 12 2004 6 Electrical Data 6 1 Absolute Ratings The IC is not designed to operate beyond the parameters shown in the following table Parameter Minimum Maximum Comments VDD12 B A 0 5 V 1 7V VDDI5 0 5 V 2 0 V VDD18 VDDA18 0 5 V 2 3 V VDD33 0 5 V 3 6 V Under Bias 85 C TSTORAGE 65 C 150 C Table 6 Absolute maximum ratings 6 2 Operating Ranges The IC is designed to provide functional operation if the voltage and temperature parameters are within the limits defined in the following table Parameter Minimum Typical Maximum Units Comments VDD12 B A 1 14 1 2 1 26 V 5 1 425 1 5 1 575 V VDD18 VDDA18 1 71 1 8 1 89 V VDD33 3 135 3 3 3 465 V V Under Bias 85 deg C Table 7 Operating ranges 34 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 6 3 DC Characteristics See the HyperTransport Technology Electrical Specification for the DC characteristics of link signals The following table shows current consumption in amps and power in watts for each power plane Typical Max Supply Parameter Description Current Power Current Power Comments VDD12 VDD12 B A c
38. cted that the state of this register is copied into the host by software Default 0000 0000 0000 0000h Attribute Read write Bits Description 63 32 GARTHI GART base address register high 31 12 GARTLO GART base address register low 11 0 Reserved Link Command Register DevA 0xC0 Default 0060 0008h Attribute See below Bits Description 31 29 Slave primary interface type Read only 28 DOUI drop on uninitialized link Read write This specifies the behavior of transactions that are sent to uninitialized links 0 Transactions that are received by the IC and forwarded to a side of the tunnel when DevA 0x C4 C8 INITCPLT and ENDOCH for that side of the tunnel are both low remain in buffers awaiting transmission indefinitely waiting for INITCPLT to be set high 1 Trans actions that are received by the IC and forwarded to a side of the tunnel when DevA 0x C4 C8 INITCPLT and ENDOCH for that side of the tunnel are both low behave as if ENDOCH were high Note this bit is cleared by PWROK reset but not by RESET 27 DEFDIR default direction Read write 0 Send AGP master requests to the master link host as specified by DevA 0xCO MASHST 1 Send AGP master requests to the opposite side of the tunnel 24 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 26 MASHST master host Read set and cleared by hardware This bit indicates which link is the path to the master or only host
39. d by the IC to determine the proper drive strength values The resistors correlate the calculated values as follows A CALD is used to calculate DevA 0x50 PCOMP data signal rising edge drive strength A CALD is used to calculate DevA 0x50 NCOMP data signal falling edge drive strength and receive impedance e A_CALS is used to calculate DevA 0x54 PCOMP strobe rising edge drive strength A_CALS is used to calculate DevA 0x54 NCOMP strobe falling edge drive strength and receive imped ance Note when new values are written to these registers new compensation values are not updated to the AGP PHY automatically the periodic calibration cycle specified by DevA 0xA8 PCALCYC must pass in order for the AGP PHY calibration values to take effect Default 000 000 h Attribute See below Bits Description 31 30 NCTL AGP PHY N falling edge compensation control Read write These two bits combine to specify the PHY falling edge compensation value that is applied to AGP signals as follows NCTL Description 00b Apply NCOMP directly as the compensation value 01b Apply NDATA directly as the compensation value 10b Apply the sum of NCOMP and NDATA as the compensation value If the sum exceeds 3Fh then 3Fh is applied 11b Apply the difference of NCOMP minus NDATA as the compensation value If the dif ference is less than 00h then 00h is applied 29 28 Reserved 27 22 NDATA AGP falling edge drive stre
40. data rates When AGP3MD 0 this field defaults to 111b to indicate support for 4x 2x and 1x data rates AGP Command Register DevA 0xA8 Default 0000 0000h Attribute Read write Bits Description 31 13 Reserved 12 10 PCALCYC periodic calibration cycle Specifies the period between calibration cycles as follows 000b 4 milliseconds 001b 16 milliseconds 010 64 milliseconds 011b 256 milliseconds all other values are reserved When DevA 0xA4 AGP3MD 1 calibration cycles are as specified in the AGP 3 0 specification When DevA 0xA4 AGP3MD 0 calibration cycles consist of 1 the internal calibration logic requests the bus 2 once granted the calibration values are update in less than 6 A PCLK cycles while the AGP bus is in a quiescent state Note after changing this value the IC may not perform another calibration cycle until the internal counter rolls over as much as 256 microseconds later in order to avoid this DevA 0xBO CALDIS should be set high before changing PCALCYC and then DevA 0xBO CALDIS should be cleared afterward SBA EN side band address enable 1 SBA addressing is enabled Note when DevA 0xA4 AGP3MD 1 SBA addressing is enabled and the state of this bit is ignored AGPEN AGP operation enable 1 The IC accepts master initiated AGP commands 0 AGP commands are ignored Reserved R4GEN receive greater than 4 gigabyte access enable 1 The IC accepts AGP accesses to ad
41. dresses greater than 4 gigabytes FWEN fast write enable 1 Fast writes are enabled When DevA 0xA4 FWSUP 0 this bit is required to be programmed low if in this case this bit is programmed high then undefined behavior results Reserved 22 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 2 0 DRATE data transfer mode rate This field is combined with DevA 0xA4 AGP3MD to specify the AGP data rate as follows AGP3MD DRATE X 000 No AGP mode selected 0 001 Ix AGP rate AGP 2 0 signaling 0 010 2x AGP rate AGP 2 0 signaling 0 100 4x AGP rate AGP 2 0 signaling 1 001 4x AGP rate AGP 3 0 signaling 1 010 8x AGP rate AGP 3 0 signaling 1 100 Reserved AGP Control Register DevA 0xB0 Default 0000 0000h Attribute Read write Bits Description 31 10 Reserved 9 CALDIS calibration cycle disable 1 Calibration cycles as defined in DevA 0xA8 PCALCYC are disabled 8 APEREN graphics aperture enable This bit controls no hardware in the IC It is expected that the state of this bit is copied into the host by software 7 GTLBEN graphics translation look aside buffer enable This bit controls no hardware in the IC It is expected that the state of this bit is copied into the host by software 6 0 Reserved AGP Aperture Size Register DevA 0xB4 Default 0001 0F00h Attribute See below Bits Description 31 28 P
42. e A frequency Legal values are Oh 200 MHz 2h 400 MHz 4h 600 MHz and Sh 800 MHz Note this bit is cleared by PWROK reset not by RESET Note after this field is updated the link frequency does not change until either RESET is asserted or a link disconnect sequence occurs through LDTSTOP 7 0 REVISION Read only Revision A of the IC is designed to version 1 02 of the link specification Link Frequency Capability 1 Register DevA 0xD0 Default 0035 0002h Attribute See below Bits Description 31 16 FREQCAPB link B frequency capability Read only These bits indicate that that B side of the tunnel supports 200 400 600 and 800 MHz link frequencies 15 12 Reserved 11 8 FREQB link B frequency Read write Specifies the link side B frequency Legal values are Oh 200 MHz and 2h 400 MHz 4h 600 MHz and 5h 800 MHz Note although it is possible to program this field for higher frequencies the B link of the IC is only designed to support 200 and 400 MHz operation Note this bit is cleared by PWROK reset not by RESET Note after this field is updated the link frequency does not change until either RESET is asserted or a link disconnect sequence occurs through LDTSTOP 7 0 Link device feature capability indicator Read only These bits are set to indicate that the IC supports LDTSTOP Link Enumeration Scratchpad Register DevA 0xD4 Default 0000 0000h Attribute See below Bits Description 31 16 Reserved 1
43. e are passed to internal registers or to the AGP bridge See section 5 1 for details about the software view of the IC See section 5 1 2 for a description of the register naming convention See the AMD 8151 HyperTransport AGP3 0 Graphics Tunnel Design Guide for addi tional information 4 0 Reset And Initialization RESET and PWROK are both required to be low while the power planes to the IC are invalid and for at least 1 millisecond after the power planes are valid Deassertion of PWROK is referred to as a cold reset After PWROK is brought high RESET is required to stay low for at least 1 additional millisecond After RESET 15 brought high the links go through the initialization sequence After a cold reset the IC may be reset by asserting RESET while PWROK remains high This is referred to as a warm reset RESET must be asserted for no less than 1 millisecond during a warm reset 4 3 Clocking It is required that REFCLK be valid in order for the IC to operate Also the LR B A CLK inputs from the operation links must also be valid at the frequency defined DevA 0xCC FREQA and DevA 0xDO FREQB The IC provides PCLK as the clock to the AGP device The systemboard is required to include a connection from A PLLCLKO to A PLLCLKI The length of this connection is required to be approximately the same as length ofthe PCLK trace from the IC to the external AGP devices including approximately 2 5 inches of etch on the AGP card
44. essor systems and be low in multi processor systems 12 10 Reserved 9 8 CRCERR CRC Error Read set by hardware write 1 to clear Bit 9 applies to the upper byte of the link DevA 0xC4 only and bit 8 applies to the lower byte 1 The hardware detected a CRC error on the incoming link Note this bit is cleared by PWROK reset but not by RESET TXOFF transmitter off Read write 1 only 1 No output signals on the link toggle the input link receivers are disabled and the pins may float ENDOCH end of chain Read write 1 only or set by hardware 1 The link is not part of the logical HyperTransport technology chain packets which are issued or forwarded to this link are either dropped or result in an NXA error response as appropriate packets received from this link are ignored and CRC is not checked if the transmitter is still enabled TXOFF then it drives only NOP packets with good CRC ENDOCH may be set by writing a to it or it may be set by hardware if the link is determined to be disconnected at the rising edge of RESET INITCPLT initialization complete Read only This bit is set by hardware when low level link initialization has successfully completed If there is no device on the other end of the link or if the device on the other side of the link is unable to properly perform link initialization then the bit is not set This bit is cleared when RESET is asserted or after the link disconnect sequence com
45. fication for the AC characteristics of link signals The following table shows AC specification data for clocks AMD 8151 AGP Tunnel Data Sheet Symbol Parameter Description Min Max Units Comments trEF REFCLK cycle time 15 18 ns tcvc A PCLK cycle time 15 ns Matches REFCLK tHIGH A_PCLK high time 6 ns tLow A_PCLK low time 6 ns tSLEW A_PCLK slew rate 1 4 V ns Table 12 AC data for clocks The following table shows AC specification data for common clock A_PCLK operation of AGP signals Symbol Parameter Description Min Max Units tvAL A PCLK to signal valid delay 1 5 5 ns ton A_PCLK to signal float to active delay 1 6 ns torr A PCLK to signal active to float delay 1 14 ns tsu Signal input setup time to A PCLK 6 ns ty AGP signal input hold time after A PCLK 0 ns Signal output rise and fall slew rate 2 3 5 V ns Table 13 AC data for common clock operation of AGP signals 37 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet The following table shows AC specification data for clock forwarded operation of AGP signals AGP 2X AGP 4X AGP 8X Min Max Min Max Min Max Units Notes A_PCLK to transmit strobe first strobe edge A_PCLK to transmit strobe final strobe edge Data valid before strobe Data valid after strobe A_PCLK to float to active delay
46. ges AREE DE CUR bene etd Dee E 34 6 3 DC AR TCU EUR EARN EU PR P E X o RAUS Es 35 6 4 AC Characteristics 0 eee ehh hh 37 Ball Designations s ERE RO EC S Eb Fo RE Fe 39 Package Specification ra ee ERR e ER RR ACRI CREAR Inca 42 eye Lei QUEE VR EU VR RU VIRA 43 9 1 High Impedance ee 43 9 2 NAND Tree Mode RE RUE dea Ae a Ae Sel ete ea 43 QM 9 45 101 Revision History sises co de Les oce Quee RC Ede d OD M ad bie ee d 45 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 List of Figures System block ee 1 Config ration SPACE m 14 Ball designations R 39 Package mechanical drawing 42 NAND EG Ew 43 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 List of Tables IO signal types 6 Translation from AGP requests to link requests ccsceescesseeseceteceseceeeeeeeeescesesecsaeeeseenseenseeees 13 Configuration S
47. guration space Link Configuration And Control Register DevA 0xC4 and DevA 0xC8 DevA 0xC4 applies side A of the tunnel and DevA 0xC8 applies to side B of the tunnel The default value for bit 5 may vary see the definition Default 11 0020h for DevA 0xC4 and 00 0020h for DevA 0xC8 Attribute See below Bits Description 31 Reserved 30 28 LWO link width out Read write Specifies the operating width of the outgoing link Legal values are 001b 16 bits DevA 0xC4 only 000b 8 bits 101b 4 bits 100b 2 bits and 111b not connected Note this field is cleared by PWROK reset but not by RESET the default value of this field depends on the widths of the links of the connecting device per the link specification Note after this field is updated the link width does not change until either RESET is asserted or a link disconnect sequence occurs through or LDTSTOP 27 Reserved 26 24 LWI link width in Read write Specifies the operating width of the incoming link Legal values are 001b 16 bits DevA 0xC4 only 000b 8 bits 101b 4 bits 100b 2 bits and 111b not connected Note this field is cleared by PWROK reset but not by RESET the default value of this field depends on the widths of the links of the connecting device per the link specification Note after this field is updated the link width does not change until either RESET is asserted or a link disconnect sequence occurs through an
48. l Data Sheet In summary Stop Grant broadcasts with SMAF fields specified by DevA 0xFO ICGSMAF enable the clock gating window and STPCLK deassertion broadcasts disable the window If LDTSTOP is asserted while the clock gating window is enabled then clock gating occurs Also DevA 0xFO ECGSMAF may be used in a similar way to disable A_PCLK and the internal clock grids associated with the AGP bridge The same rules for the clock gating window that apply to DevA 0xFO ICGS MAF also apply to DevA 0xFO ECGSMAF If clock gating is enabled then A PCLK is forced low within two clock periods after LDTSTOP is asserted It becomes active again within two clock periods after LDT STOP is deasserted It is required that there be no AGP card initiated upstream or downstream traffic while A PCLK is gated In addition it is required that there be no host accesses to the bridge or internal registers in progress from the time that LDTSTOP is asserted for clock gating until the link reconnects after LDTSTOP is deasserted 4 4 Tunnel Links HyperTransport link A supports CLK receive and transmit frequencies of 200 400 600 and 800 MHz Link B supports frequencies of 200 and 400 MHz The side and side B frequencies are independent of each other 4 4 1 Link PHY The PHY includes automatic compensation circuitry and a software override mechanism as specified by DevA 0x E8 E4 E0 The IC only implements synchronous mode clock forwarding FIFOs So
49. ld be tied to IO VDD33 3 State 3 State ground TEST This is required to be tied low for functional operation See section 9 for Input VDD33 details 3 5 Power and Ground VDD12 B 1 2 volt power plane for the HyperTransport technology pins VDD12A provides power to the A side of the tunnel VDD12B provides power to the B side of the tunnel VDD15 1 5 volt power plane for AGP 1 8 volt power plane for the core of the IC VDDAIS Analog 1 8 volt power plane for the PLLs in the core of the IC This power plane is required to be filtered from digital noise VDD33 3 3 volt power plane for IO VSS Ground 3 5 1 Power Plane Sequencing The following are power plane requirements that may imply power supply sequencing requirements VDD33 is required to always be higher than VDD18 VDDA18 VDD15 and VDDI2 B VDD18 and VDDA18 are required to always be higher than VDD15 and VDD12 B A VDDIS is required to always be higher than VDD12 B A 10 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 4 Functional Operation 4 4 Overview The IC connects to the host through either the side A or side B HyperTransport link interface The other side of the tunnel may or may not be connected to another device Host initiated transactions that do not target the IC or the bridge flow through the tunnel to the downstream device Transactions claimed by the devic
50. memory enable Read write 1 Enables access to the AGP bus memory space 0 IOEN IO enable Read write 1 Enables access to the AGP bus IO space AGP Bridge Revision and Class Code Register DevB 0x08 Default 0604 00 h Attribute Read only Bits Description 31 8 CLASSCODE 7 0 REVISION AGP Bridge BIST Header Latency Cache Register DevB 0x0C Default 0001 0000h Attribute See below Bits Description 31 24 BIST Read only These bits fixed at their default values 23 16 IHEADER Read only These bits fixed at their default values 30 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 15 8 LATENCY Read write These bits control no hardware 7 0 CACHE Read only These bits fixed at their default values AGP Bridge Bus Numbers And Secondary Latency Register DevB 0x18 Default 0000 0000h Attribute Read write Bits Description 31 24 SECLAT Secondary latency timer These bits control no hardware 23 16 SUBBUS Subordinate bus number 15 8 SECBUS Secondary bus number 7 0 PRIBUS Primary bus number AGP Bridge Memory Base Limit Registers DevB 0x 30 1C These registers specify the IO space DevB 0x1C and DevB 0x30 non prefetchable memory space DevB 0x20 and prefetchable memory space DevB 0x24 address windows for transactions that are mapped from the
51. nctions are claimed such writes are ignored and reads always respond with all zeros The following are memory mapped spaces Base address Size Mnemonic Registers register bytes DevA 0x10 Variable None Graphic virtual memory aperture minimum of 32 megabytes DevA 0xB8 4K None GART block in physical memory Table 4 Memory mapped address spaces The following are register attributes found in the register descriptions Type Description Read or read only Capable of being read by software Read only implies that the register cannot be written to by software Write Capable of being written by software Set by hardware Register bit is set high by hardware Write once After RESET these registers may be written to once After being written they become read only until the next RESET assertion The write once control is byte based So for example software may write each byte of a write once DWORD as four individual transactions As each byte is written that byte becomes read only Write 1 to clear Software must write a 1 to the bit in order to clear it Writing a 0 to these bits has no effect Write 1 only Software can set the bit high by writing a 1 to it However subsequent writes of 0 will have no effect RESET must be asserted in order to clear the bit Table 5 Register attributes 5 AGP Device Configuration Registers These registers are located in PCI configu
52. ng is _N PD _N PD enabled A ADSTBI P is the first strobe and A ADSTBI N is the second strobe A AD 31 0 AGP address data bus IO VDDI5 Term Term PU Low A CBE L 3 0 AGP command byte enable bus IO VDDI5 Term Term PU Low A CAL D S and A CAL D S Compensation pins for Analog VDD15 matching impedance of system board AGP traces See DevA 0x 54 50 for more information These are designed to be connected through resistors as follows Signal Compensation Function External Connection A CALD Rising edge of data signals Resistor to VSS A_CALD Falling edge of data signals Resistor to VDD15 A CALS Rising edge of strobe signals Resistor to VSS A_CALS Falling edge of strobe signals Resistor to VDD15 These resistors are used by the compensation circuit The output of this circuit is combined with DevA 0x 54 50 to determine com pensation values that are passed to the link PHYs A DBI H L Data bus inversion high low When IO VDDI5 Term Term PU PU DevA 0xA4 AGP3MD 1 A DBIL applies to AD 15 0 A DBIH applies to AD 31 16 1 AD signals are inverted 0 AD signals are not inverted The IC uses these signals in determining the polarity of the AD signals when they are inputs These may also be enabled to support the DBI function of the IC output signals by DevA 0x40 DBIEN Both A DBIH and A DBIL are strobed with ADSTBI P N When DevA 0xA4 AGP3MD 0 A DBIL is pulled low
53. ngth control Read write This value is applied to the falling edge N transistor PHY compensation as described in NCTL 21 16 NCOMP AGP falling edge drive strength Read only This provides the calculated value of the falling edge N transistor drive strength of the AGP signals The default for this field varies This field is updated by the hardware approximately every 8 microseconds 19 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 15 14 PCTL AGP PHY P rising edge compensation control Read write These two bits combine to specify the PHY rising edge compensation value that is applied to AGP signals as follows PCTL Description 00b Apply PCOMP directly as the compensation value 01b Apply PDATA directly as the compensation value 10b Apply the sum of PCOMP and PDATA as the compensation value If the sum exceeds 1 Fh then 1Fh is applied 11b Apply the difference of PCOMP minus PDATA as the compensation value If the dif ference is less than 00h then 00h is applied 13 12 Reserved 11 RW read write bit Read write This controls no logic 10 6 PDATA AGP rising edge drive strength control Read write This value is applied to the rising edge P transistor PHY compensation as described in PCTL 5 Reserved 4 0 PCOMP AGP rising edge drive strength Read only This provides the calculated value of the ris ing edge P transistor drive strength
54. ns for bits 3 0 Attribute Read only Bits Description 31 24 RQ maximum number of outstanding requests This field is set to indicate support for 32 outstanding requests 23 18 Reserved 17 Isochronous support This bit fixed in the low state to indicate that the IC does not support isochronous modes 16 13 Reserved 12 10 Calibration cycle This field is set to indicate a requirement for calibration cycles every 64 millisec onds SBA support This field 15 set to indicate support for SBA Coherency This bit fixed high 64 bit GART support This bit fixed low Host translation This bit fixed low Greater than 4 gigabyte support This bit fixed high A o 21 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet FWSUP fast write support flag 0 Fast writes are not supported 1 Fast writes are supported The state of this bit is controlled by DevA 0x40 FWDIS AGP3MD AGP 3 0 signaling mode detected 1 The IC detected connection to an AGP 3 0 capable master and is programmed for AGP 3 0 signaling 0 The IC detected connection to an AGP 2 0 or earlier capable master or is not programmed for 1 5 volt AGP 2 0 signaling If DevA 0x40 8XDIS 0 and the pin A_GC8XDET 0 then this bit is high Otherwise it is low 2 0 RATE data rate When AGP3MD 1 then this field defaults to 011b to indicate support for 4x and 8x
55. of the AGP signals The default for this field varies This field is updated by the hardware approximately every 8 microseconds AGP PHY Skew Control Register DevA 0x58 DSKEW and SSKEW are designed such that when they are both programmed to the same value the AGP out put strobes transition near the center of the data eye To move the strobe to a later point in the data eye the value of SSKEW is increased To move the strobe to an earlier point in the data eye DSKEW is increased These values translate into skew approximately as follows For values Oh to 8h the skew is about D SISKEW x 80 picoseconds For values 9h to Fh the skew is about 800 D SJSKEW 8 x 400 picoseconds However these values vary with process temperature and voltage Note that the lower values provide fine res olution and the upper values provide coarse resolution Default 0000 0000h Attribute Read write Bits Description 31 8 Reserved 7 4 DSKEW AGP data skew Read write This specifies the alignment of the AGP data signal outputs A AD 31 0 A_CBE_L 3 0 and A DBI H L relative internal clocks Oh The strobe transitions earliest Fh The strobe transitions latest 3 0 SSKEW AGP strobe skew Read write This specifies the alignment of the AGP strobe signal out puts A_ADSTB 1 0 relative internal clocks Oh The strobe transitions earliest Fh The strobe tran sitions latest 20 AMDA 24888 Re
56. oltage 0 5 0 4 VDDI5 V Vig Input high voltage 0 6 VDDI5 0 5 VDDIS V Vor Output low voltage lour 1 0 mA 0 15 VDDI5 V Von Output high voltage loup 0 2 mA 0 85 VDD15 V VREFI Input reference voltage on REFGC 0 48 VDDI5 0 52 VDDI5 V Vrero Output reference voltage on A REFCG 0 48 VDDI5 0 52 VDD15 V Ij Input leakage current 10 uA Cw Input capacitance 8 pF Table 10 DC characteristics for signals on the VDD15 power plane AGP 2 0 signaling The following table shows DC characteristics for signals on the VDD15 power plane when AGP 3 0 signaling is enabled Symbol Parameter Description Min Max Units Comments Vit Input low voltage 0 3 Veer 0 1 V Vin Input high voltage 9 1 VDDIS 03 V Vor Output low voltage lour 1 5 mA 0 05 V Von Output high voltage 50 ohm load to 0 750 0 850 V ground VREFI Input reference voltage on A REFGC 0 34 0 36 V Vrero Output reference voltage on A REFCG 0 226 VDDI5 0 240 VDD15 V Corr Input die capacitance 8 pF ZrgRgM Terminator equivalent impedance Voy 45 55 Ohms 0 8V ZTARG 50 Ohm Pull up equivalent impedance Voy 39 3 46 2 Ohms 0 8V ZTARG 50 Ohm Table 11 DC characteristics for signals on the VDD15 power plane AGP 3 0 signaling 36 AMDA 24888 Rev 3 03 July 12 2004 6 4 AC Characteristics See the HyperTransport Technology Electrical Speci
57. only the link receive and transmit frequencies specified in DevA 0x D0 CC FREQB FREQA are allowed 4 5 AGP The AGP bridge supports AGP 3 0 signaling at 8x and 4x data rates and 1 5 volt AGP 2 0 signaling at 4x 2x and 1x data rates 64 bit upstream and 32 bit downstream addressing is supported AGP 3 0 dynamic bus inver sion is supported on output signals in 8X mode only not in 4X mode dynamic bus inversion on input signals is supported in both 4X and 8X modes 4 5 1 Tags UnitIDs And Ordering The IC requires three HyperTransport technology defined UnitIDs They are allocated as follows First UnitID is not used This is to avoid a potential conflict with the host because it may be zero see DevA 0xCO BUID Second UnitID is used for PCI mode upstream requests and responses to host requests Third UnitID is used for AGP high priority and low priority upstream requests The SrcTag value that is assigned to upstream non posted AGP requests increments with each request from 0 to 27 and then rolls over to 0 again the first SrcTag assigned after reset is 0 Up to 28 non posted link requests may be outstanding at a time The SrcTag value that is assigned to non posted PCI requests is always 28 12 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet All AGP transactions are compliant to AGP ordering rules APG transactions are translated into link transac tions as follows AGP trans
58. ons intended to support or sustain life or in any other application in which the failure of AMD s product could create a situation where personal injury death or severe property or environmental damage may occur AMD reserves the right to discontinue or make changes to its products at any time without notice AMD 8151 AGP Tunnel Data Sheet AMD the AMD Arrow logo and combinations thereof and AMD 8151 are trademarks of Advanced Micro Devices Inc HyperTransport is a licensed trademark of the HyperTransport Technology Consortium Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 10 Table of Contents OVERVIEW ku cda eet E EE 1 1 Device Features E ed EU dea EAR ae bu DUE antes AUR I edu Baga gua 1 Ordering Information 5 e rc iR RR RC 6 Signal Descriptions hy ey EOE 6 3l Terminoloty eps nee id LI n ed Es 6 32 Tunnel Link Signals 2 1 ence tnt e 7 3 3 AGP Signals hdd ede eh OOo hh Shon add diene Gud Siena Wand Meaning Ged deh 8 3 4 Test and Miscellaneous Signals 0 0 ccc nen 10 3 9 Powerand Ground ccc wae iaeaea Vain e RU qp wid ea eh as eae ea das 10 3 5 1 Power Plane Sequencing
59. pletes after the assertion of LDTSTOP LKFAIL link failure Read set by hardware write 1 to clear This bit is set high by the hardware when a CRC error is detected on the link if enabled by CRCFEN or if the link is not used in the system Note this bit is cleared by PWROK reset not by RESET CRCERRCMD CRC error command Read write 1 The link transmission logic generates erroneous CRC values 0 Transmitted CRC values match the values calculated per the link specification This bit is intended to be used to check the CRC failure detection logic of the device on the other side of the link Reserved CRCFEN CRC flood enable Read write 1 CRC errors in link A for DevA 0xC4 CRCFEN in link B for DevA 0xC8 CRCFEN result in sync packets to both outgoing links DevA 0x04 SSE is set and the LKFAIL bit is set O CRC errors do not result in sync packets setting of DevA 0x04 SSE or the LKFAIL bit Reserved 26 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet Link Frequency Capability 0 Register DevA 0xCC Default 0035 0022h Attribute See below Bits Description 31 16 FREQCAPA link A frequency capability Read only These bits indicate that A side of the tunnel supports 200 400 600 and 800 MHz link frequencies 15 12 Reserved 11 8 FREQA link A frequency Read write Specifies the link sid
60. ration space in the first device device A function 0 See section 5 1 2 for a description of the register naming convention AGP Vendor And Device ID Register DevA 0x00 Default 7454 1022h Attribute Read only Bits Description 31 16 AGP device ID 15 0 Vendor ID 15 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet AGP Device Status And Command Register DevA 0x04 Default 0210 0000h Attribute See below Bits Description 31 DPE detected parity error Read only This bit is fixed in the low state 30 SSE signaled system error Read set by hardware write 1 to clear 1 A system error was signaled both links were flooded with sync packets as a result of a CRC error see DevA 0x C8 C4 CRCFEN CRCERR Note this bit is cleared by PWROK reset but not by 29 RMA received master abort Read set by hardware write 1 to clear 1 A request AGP or PCI sent to the host bus received a master abort an NXA error response Note this bit is cleared by PWROK reset but not by RESET 28 RTA received target abort Read set by hardware write 1 to clear 1 A request AGP or PCI sent to the host bus received a target abort a non NXA error response Note this bit is cleared by PWROK reset but not by RESET 27 21 Read only These bits are fixed in their default st
61. rved 28 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 6 5 ACTL link side A PHY control value Read write These two bits combine to specify the PHY compensation value that is applied to side A of the tunnel as follows ACTL Description 00b Apply CALCCOMP directly as the compensation value 01b Apply ADATA directly as the compensation value 10b Apply the sum of CALCCOMP and ADATA as the compensation value In DevA 0x EF4 E0 if the sum exceeds 13h then 13h is applied In DevA 0x E8 if the sum exceeds 1Fh then 1Fh is applied 11b Apply the difference of CALCCOMP minus ADATA as the compensation value If the difference is less than 01h then O1h is applied The default value of this field from PWROK reset is controlled by the CMPOVR signal If CMPOVR 0 the default is 00b If CMPOVR 1 the default is 01b 4 0 ADATA link side A data value Read write This value is applied to the side A of the tunnel PHY compensation as described in ACTL The default for DevA 0x E4 is 08h The default for DevA OxES is OFh Clock Control Register DevA 0xF0 See section 4 3 1 for details on clock gating AMD system recommendations for System Management Action Field SMAF codes are 0 ACPI C2 1 ACPI C3 2 FID VID change 3 ACPI S1 4 ACPI 53 5 Throt tling 6 ACPI 84 55 For server and desktop platforms AMD recommends setting this register to 0004 0008h to g
62. s Pin name and description IO cell Power During After type plane reset reset LDTCOMP 3 0 Link compensation pins for both sides of the tunnel These are Analog VDD designed to be connected through resistors as follows 12B Bit Function External Connection 0 Positive receive compensation Resistor to VDD12B 1 Negative receive compensationResistor to VSS 3 2 Transmit compensation Resistor from bit 2 to bit 3 These resistors are used by the compensation circuit The output of this circuit is combined with DevA 0x E8 E4 E0 to determine compensation values that are passed to the link PHYs LRACAD N 15 0 LRBCAD N 7 0 Receive link command address Link VDD12 data bus input LRACLK 1 0 _ P N LRBCLKO_ P N Receive link clock Link VDD12 input LR B AJCTL P N Receive link control signal Link VDDI12 input LTACAD N 15 0 LTBCAD N 7 0 Transmit link command address Link VDD12 Diff Func data bus output High LTACLK I 0 P NJ LTBCLKO P N Transmit link clock Link VDDI2 Func Func output LT B AJCTL P N Transmit link control signal Link VDD12 Diff Func output Low The signals connected to the A side of the tunnel are powered by VDD12A and the signals connected to the B side of the tunnel are powered by VDD12B Diff High and Diff Low for these link pins specifies differential high and lo
63. that is asserted then the IC power is reduced through gating of internal clocks 0 power reduction while LDTSTOP is asserted For example if clock gating is required for SMAF values of 3 and 5 then ICGSMAFT 3 5 must be high See section 4 3 1 for details 29 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 5 AGP Bridge Configuration Registers These registers are located in PCI configuration space in the second device device B function 0 See section 5 1 2 for a description of the register naming convention AGP Bridge Vendor And Device ID Register DevB 0x00 Default 7455 1022h Attribute See below Bits Description 31 16 AGP bridge device ID Bits 31 20 are read only bits 19 16 are write once When the LSBs are left at the default value some operating systems may load a generic graphics driver System BIOS should program the LSBs to 6h in order to circumvent the loading of such a driver 15 0 Vendor ID Read only AGP Bridge Status And Command Register DevB 0x04 Default 0220 0000h Attribute See below Bits Description 31 9 Read only These bits are fixed in their default state 8 SERREN SERRE enable Read write This bit controls no hardware 7 3 Special cycle enable Read only This bit is hardwired low 2 MASEN PCI master enable Read write 1 Enables the AGP bus master to initiate PCI cycles to the host MEMEN
64. these bits high results in undefined behavior Note if DevA 0x10 64BIT 0 then these bits are read only all zero 31 22 APBARLO Aperture base address register low These bits are a combination of read write and read only zero based on the state of DevA 0xB4 APSIZE see that register for details 21 4 Reserved 3 Read only This bit is fixed at its default value to indicate that this register points prefetchable space 2 64BIT 64 bit pointer Read write once 1 DevA 0x10 is a 64 bit pointer O DevA 0x10 is a 32 bit pointer bits 63 32 are reserved 1 0 Read only These bits are fixed at their default value to indicate that this register points memory space AGP Device Subsystem ID and Subsystem Vendor ID Register DevA 0x2C Default 0000 0000h Attribute Read write once Bits Description 31 16 Subsystem ID This field controls no hardware 15 0 Subsystem vendor ID This field controls no hardware AGP Capabilities Pointer DevA 0x34 Default 0000 00A0h Attribute Read only Bits Description 31 8 Reserved 7 0 Capabilities pointer Specifies the offset in DevA 0 address space for the AGP capabilities block 17 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet AGP Miscellaneous Control Register DevA 0x40 Default 0000 0000h Attribute See below Bits Description 31 8
65. tion of the register naming convention used in this document See the AMD 8151 HyperTransport AGP3 0 Graphics Tunnel Design Guide for additional information Signals with a suffix are active low Signals described in this chapter utilize the following IO cell types Name Notes Input Input signal only Output Output signal only This includes outputs that are capable of being in the high impedance state OD Open drain output These signals are driven low and expected to be pulled high by external cir cuitry IO Input or output signal IOD Input or open drain output Analog Analog signal w PU With pullup The signal includes a pullup resistor to the signal s power plane The resistor value is nominally 8K ohms Table 1 IO signal types The following provides definitions and reference data about each of the IC s pins During Reset provides the state of the pin while RESET is asserted After Reset provides the state of the pin immediately after is deasserted Func means that the pin is functional and operating per its defined function AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 3 2 Tunnel Link Signals The following are signals associated with the HyperTransport links B A in the signal names below refer to the A and B sides of the tunnel P N are the positive and negative sides of differential pair
66. urrent power 0 21 A 0 25W 0 27A 0 34 W 5 VDD1S5 current power 0 05 A 0 08 W 0 08A 0 13 W VDD18 VDD18 current power operational 130A 2 34W 1 75A 1330W VDD18 VDD18 current power internal clock gating 0 40 A 0 72 W 050 0 95 W enabled DevA 0xFO ICGSMAF VDD18 VDD18 current power internal and external clock 0 21 A 0 38 W 030A 0 57 W gating enabled DevA 0xFO I ECGSMAF VDDAIS8 VDDA18 current power 0 02 A 0 04W 0 03 A 0 06 W VDD33 VDD33 current power 0 05 A 0 17W 007A 10 24 W Total power no clock gating enabled 2 88 W 4 07 W Table 8 Current and power consumption The following table shows DC characteristics for signals on the VDD33 power plane Symbol Parameter Description Min Max Units Comments Vit Input low voltage 0 5 0 3 VDD33 V ViH Input high voltage 0 6 VDD33 0 5 VDD33 V Vor Output low voltage lour 1 5 mA 0 1 VDD33 V Vou Output high voltage Iny7 0 5 mA 0 9 VDD33 V Iri Input leakage current 10 uA Cry Input capacitance 8 pF Table 9 DC characteristics for signals on the VDD33 power plane 35 AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet The following table shows DC characteristics for signals on the VDD15 power plane when AGP 2 0 signaling is enabled Symbol Parameter Description Min Max Units Comments Vit Input low v
67. us Figure 2 Configuration space Device A above is programmed to be the link base UnitID and device B is the link base UnitID plus 1 5 1 2 Register Naming and Description Conventions Configuration register locations are referenced with mnemonics that take the form of Dev A B 7 0 x FF 0 where the first set of brackets contain the device number the second set of brackets contain the function num ber and the last set of brackets contain the offset Other register locations e g memory mapped registers are referenced with an assigned mnemonic that speci fies the address space and offset These mnemonics start with two or three characters that identify the space followed by characters that identify the offset within the space Register fields within register locations are also identified with a name or bit group in brackets following the register location mnemonic 14 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet The following are configuration spaces Device Function Mnemonic Registers A 0 DevA 0xXX AGP device header link and AGP capabilities blocks B 0 DevB 0xXX PCI PCI bridge registers for AGP Table 3 Configuration spaces The IC does not claim configuration register accesses to unimplemented functions within its devices they are forwarded to the other side of the tunnel Accesses to unimplemented register locations within implemented fu
68. v 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet AGP Most Recent Request Register DevA 0x60 As each PIPE mode or SBA mode AGP request is transferred into the IC the fields are placed into this register Thus this register provides the fields of the most recent AGP requests Any sticky bits from prior requests that have not been updated in the current request are also valid Note fences are not captured by this register Default 0000 0000 0000 0000h Attribute Read only Bits Description 63 44 Reserved 43 40 MRC most recent command field Specifies the command field of the most recent AGP request Oh LP low priority read 1h HP high priority read 4h LP write 5h HP write 8h LP long read 9h HP long read Ah Flush 39 3 MRA most recent address Specifies address bits 39 3 of the most recent AGP request 2 0 MRL most recent length field Specifies the length field of the most recent AGP request AGP Revision and Capability Register DevA 0xA0 Default 0030 C002h Attribute Read only Bits Description 31 24 Reserved 23 16 AGP specification This field is hardwired to indicate that the IC conforms to AGP specification revision 3 15 8 Next capabilities block Specifies the offset to the next capabilities block 7 0 Capabilities type Specifies the AGP capabilities block AGP Status Register DevA 0xA4 Default 1 00 0B2 h see bit descriptio
69. w e g Diff High specifies that the _P signal is high and the _N signal is low If one of the sides of the tunnel is not used on a platform then the unconnected link should be treated as fol lows for every 10 differential pairs connect all of the differential inputs together and through a resistor to VSS connect all the _N differential inputs together and through a resistor to VDD 12 leave the differential out puts unconnected If there are unused link signals on an active link because the IC is connected to a device with a reduced bit width then the unused differential inputs and outputs should also be connected in this way AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet 3 3 AGP Signals In the table below Term indicates the standard AGP 3 0 termination impedance to ground PU indicates a weak pullup resistor PD indicates a weak pulldown resistor Pin name and description IO cell Power AGP 3 0 AGP 2 0 type plane Signaling Signaling During After During After reset reset reset reset A ADSTBO P N AGP differential strobe for AD 15 0 and IO VDDI5 Term Term P PU P PU A CBE L 1 0 When AGP 3 0 signaling is enabled _N PD _N PD A ADSTBO P is the first strobe and A ADSTBO N is the second strobe A ADSTBI N AGP differential strobe for AD 31 16 IO VDD15 Term Term P PU _P PU A CBE L 3 2 and A DBI H L When AGP 3 0 signali
70. with the AGP termination value and not used by the IC A DBIH is pulled up to VDD15 through a weak resistor and becomes the AGP 2 0 PIPE input signal A DEVSELZ AGP device select IO VDDIS Term Term PU PU A FRAMEZ AGP frame signal IO VDDI5 Term Term PU PU A GC8XDETT 0 Specifies that the graphics device supports Input VDDIS PU PU PU PU AGP 3 0 signaling The state of this signal is latched on the rising w PU edge of A_RESET before being passed to internal logic AMDA 24888 Rev 3 03 July 12 2004 AMD 8151 AGP Tunnel Data Sheet Pin name and description IO cell Power AGP 3 0 AGP 2 0 type plane Signaling Signaling During After During After reset reset reset reset A_GNT AGP master grant signal Output VDD15 Term Low PU High A_IRDY AGP master ready signal IO VDDI5 Term Term PU PU A_MB8XDET This pin is controlled by DevA 0x40 8XDIS It Output VDDI5 Low Low Low Low is designed to be connected to the AGP connector to indicate support for AGP 3 0 signaling A_PAR AGP parity signal IO VDDI5 Term Term PU Low A PCLK 66 MHz AGP clock Output VDD33 Func Func Func Func A_PLLCLKO PLL clock output See section 4 3 for details Output VDD33 Func Func Func Func A_PLLCLKI PLL clock input See section 4 3 for details Input VDD33 A REFCG AQP signal reference output Analog VDD15 output
71. y base address bits 31 20 See DevB 0x 30 1C above 3 0 Reserved DevB 0x30 Default 0000 FFFFh Attribute Read write Bits Description 31 16 IOLIM IO limit address bits 31 16 See DevB 0x 30 1C above 15 0 IOBASE IO base address bits 31 16 See DevB 0x 30 1C above AGP Bridge Interrupt and Bridge Control Register DevB 0x3C Default 0000 OOFFh Attribute See below Bits Description 31 23 Reserved 22 SBRST AGP bus reset Read write A_RESET asserted AGP bus placed into reset state 0 A_RESET not asserted 21 20 Reserved 19 VGAEN VGA decoding enable Read write 1 Host initiated commands targeting VGA compatible address ranges are routed to the AGP bus These include memory accesses from A0000h to BFFFFh within the bottom megabyte of memory space only IO accesses in which address bits 9 0 range from 3BOh to 3BBh or 3COh to 3DFh address bits 15 10 are not decoded regardless of DevB 0x3C ISAEN also this only applies to the first 64K of IO space i e address bits 31 16 must be low 0 The IC does not decode VGA compatible address ranges 18 ISAEN ISA decoding enable Read write 1 The IO address window specified by DevB 0x1C 15 0 and DevB 0x30 is limited to the first 256 bytes of each 1K byte block specified this only applies to the first 64K bytes of IO space 07 The PCI IO window is the whole range specified by DevB 0x1C 15 0 and DevB 0x30 17 16 Reserved 15 8 INTERRUPT PIN Read write once These

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