Dataram DTM68103B memory module
Contents
1. 1 2 3 7 tCKiave 1 25 lt 1 5 CWL 9 11 CL 11 CL 13 a Reserved ns 1 2 3 4 6 tCKiave Optional CL 12 CL 14 tCKiave 1 25 lt 1 5 1 25 lt 1 5 ns 1 2 3 6 tCK ave 1 071 lt 1 25 CWL CL 13 CL 15 F 5 8 Reserved ns 1 2 3 4 6 10 12 tCKave Optional CL 14 CL 16 tCKiave 1 071 lt 1 25 1 071 lt 1 25 ns 1 2 3 6 CL 14 CL TBD tCKiavo Reserved Reserved ns 1 2 3 4 PE cL 15 CL TBD tCK ave 0 938 lt 1 071 Reserved ns 1 2 3 4 CL 16 CL TBD tCK ave 0 938 lt 1 071 0 938 lt 1 071 ns 1 2 3 Supported CL Settings eee ies 10 12 14 16 nCK 9 10 Supported CL Settings with read DBI TBD TBD nCK Supported CWL Settings 9 10 11 12 14 9 10 11 12 14 nCK Document 06386 Revision A 08 Sep 14 Dataram Corporation 2014 Page 2 ao 4GB 288 Pin 1Rx8 Unbuffered Non ECC DDR4 DIMM Speed Bin Table Notes Absolute Specification VDDQ VDD 1 20V 0 06 V VPP 2 5V 0 25 0 125 V The values defined with above mentioned table are DLL ON case DDR4 1600 1866 2133 and 2400 Speed Bin Tables are valid only when Geardown Mode is disabled 1 9 The CL setting and CWL setting result in tCK avg MIN and tCK avg MAX requirements When making a selection of tCK avg both need to be fulfilled Requirements from CL setting as well as requirements from CWL setting tCK avg MIN limits Since CAS Latency is not purely analog data and strobe output are synchronized by the DLL all possible inter2. DR4 1866M devices supporting down binning to 1333MT s or DDR4 1600K should program 13 5ns in SPD bytes for tAAmin Byte 24 tRCDmin Byte 25 and tRPmin Byte 26 DDR4 2133P devices supporting down binning to 1333MT s or DDR4 1600K or DDR4 1866M should program 13 5ns in SPD bytes for tAAmin Byte 24 tRCDmin Byte 25 and tRPmin Byte 26 tRCmin Byte 27 29 also should be programmed accordingly For example 48 5ns tRASmin tRPmin 35ns 13 5ns is set to supporting optional down binning CL 9 and CL 11 CL number in parentheses it means that these numbers are optional 10 DDR4 SDRAM supports CL 9 as long as a system meets tAA min Document 06386 Revision A 08 Sep 14 Dataram Corporation 2014 Page 3 os 4GB 288 Pin 1Rx8 Unbuffered Non ECC DDR4 DIMM Pin Configuration Back Side 12V NC VREECA RAS_n A16 Voo CS0_n Von CAS _n A15 ODTO Von CS1_n NC Vop ODT1 NC CB2 NC Voo Vss CS2_n CO NC RESET_n DQ59 Vss Voospp Vpp Vpp Veep Document 06386 Revision A 08 Sep 14 Dataram Corporation 2014 Page 4 ao 4GB 288 Pin 1Rx8 Unbuffered Non ECC DDR4 DIMM PIN DESCRIPTION Name Function CB 7 0 Data Check Bits DQ 63 0 Data Bits DM 7 0 _n DBI 7 0 _n Inp
3. ide View gt lt 2 74mm max 1 4 1mm max Notes 1 Tolerances on all dimensions except where otherwise indicated are 13 Reference JEDEC standard MO 309C 2 All dimensions are expressed millimeters inches ET a a a a a a a PE ae Document 06386 Revision A 08 Sep 14 Dataram Corporation 2014 Page 6 rer DTM68103B 4GB 288 Pin 1Rx8 Unbuffered Non ECC DDR4 DIMM ad M Optimizing Value and Performance Functional Diagram CKO_t CKO_c CKO_t CKO_c A 0 16 BA 0 1 A 0 16 BA 0 1 ACT_n PARITY BG 0 1 ACT n PARITY BG O 1 CS0_n CSO_n ODTO _ ODTO CKEO ____ CKEO 200 7 0 Q00 7 0 RAP g Azabrvss RAT Zapwvss DQSO_t w DQs t DQS4_t w Dos t 2 DASO t v DQS c DO O DQS4 t v DSc D4 DQ 0 7 AW DQ 0 7 S DQ 32 39 W DQ 0 7 DMO_n DBIO_n w DM_n DBI_n DM4_n DBI4_n w DM_n DBI_n a Q00 7 0 Q00 FQ BAL g Azapwvss Ae g zaprvss Das1_t w Das t pass t wpas t poste H pase Q DASS t DSc D5 15 MW g DQ 40 47 DQ 0 7 DM1_n DBI1_n w4 DM_n DBI_n DM5_n DBI5_n EM Delta i QOO 7 0 Q00 7 0 RAP g Azaprvss RAP L Fzahrvss DQS2_t w DQS t pase t w Das t 2 DQS2 W DQS c D2 DQS6 c DOS c D6 DQ 16 23 DQ 0 7 3 DQ 48 55 M DQ 0 7 2 DM2_n DBI2_n w4DM_n DBI_n DM6_n DBI6_
4. mediate frequencies may not be guaranteed An application should use the next smaller JEDEC standard tCK avg value 1 5 1 25 1 071 0 938 or 0 833 ns when calculating CL nCK tAA ns tCK avg ns rounding up to the next Supported CL where tAA 12 5ns and tCK avg 1 3 ns should only be used for CL 10 calculation tCK avg MAX limits Calculate tCK avg tAA MAX CL SELECTED and round the resulting tCK avg down to the next valid speed bin i e 1 5ns or 1 25ns or 1 071 ns or 0 938 ns or 0 833 ns This result is tCK avg MAX corresponding to CL SELECTED Reserved settings are not allowed User must program a different value Optional settings allow certain devices in the industry to support this setting however it is not a mandatory feature Refer to supplier s data sheet and or the DIMM SPD information if and how this setting is supported Any DDR4 2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization DDR4 1600 AC timing apply if DRAM operates at lower than 1600 MT s data rate For devices supporting optional down binning to CL 9 CL 11 and CL 13 tAA RCD tRPmin must be 13 5ns or lower SPD settings must be programmed to match For example DDR4 1600K devices supporting down binning to 1333MT s should program 13 5ns in SPD bytes for tAAmin Byte 24 tRCDmin Byte 25 and tRPmin Byte 26 D
5. n w4DM_n DBI_n a i DOO gt oO QOO 7 0 BAL g Azaprvss RA Fzahrvss DQS3_t w DQs t DQS7_t wDQs t 7 9 DQS3 t v DAS D3 2 DQS7 t W DOS_c D7 Q DQ 24 31 M DQ 0 7 S DQ 56 63 W DQ 0 7 3 DM3_n DBI3_n 4 DM_n DBI_n DM7_n DBI7_n w4DM_n DBI_n i Notes 1 Unless otherwise noted resistor values are 150 5 2 ZQ resistors are 2400 1 For all other resistor values refer to the appropriate wiring diagram Document 06386 Revision A 08 Sep 14 Dataram Corporation 2014 Page 7 ao 4GB 288 Pin 1Rx8 Unbuffered Non ECC DDR4 DIMM Med M Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06386 Revision A 08 Sep 14 Dataram Corporation 2014 Page 8
6. o JEDEC s DDR4 2133 PC4 2133 standard The assembly is Single Rank The rank is comprised of eight Micron 512Mx8 DDR4 2133 SDRAMs One 2K bit EEPROM is used for Serial Presence Detect Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Document 06386 Revision A 08 Sep 14 Dataram Corporation 2014 Page 1 DR DATARAM P Optimizing Value and Performance DTM68103B 4GB 288 Pin 1Rx8 Unbuffered Non ECC DDR4 DIMM Speed Bin Table Speed Bin DDR4 2133P DDR4 2133R CL nRCD nRP 15 15 15 16 16 16 Unit NOTE Parameter Symbol min max min max 14 06 Internal read command to first data tAA 13 50 18 00 15 00 18 00 ns Internal read command to first data with read DBI enabled tAA_DBI TBD TBD TBD TBD ns ACT to internal read or write delay 14 06 time tRCD 13 50 15 00 ns 14 06 PRE command period tRP 13 50 15 00 ns ACT to PRE command period tRAS 33 a 33 2X ns p tREFI tREFI 47 06 ACT to ACT or REF command period tRC 46 50 48 00 ns Normal Read DBI tCK 1 5 1 2 3 4 7 10 CL 9 ss E 5 evs z 1 6 Reserved ns CWL 9 Optional tCKiave Optional CL 10 CL 12 tCK ave Reserved 1 5 1 6 ns
7. os 4GB 288 Pin 1Rx8 Unbuffered Non ECC DDR4 DIMM Features 288 pin JEDEC compliant DIMM 133 35 mm wide by 31 25 mm high Operating Voltage VDD VDDQ 1 2V 1 14V to 1 26V VPP 2 5V 2 375V to 2 75V VDDSPD 2 25V to 2 75V 1 0 Type 1 2 V signaling On board IC temperature sensor with integrated Serial Presence Detect SPD EEPROM Data Transfer Rate 17 0 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 9 10 11 12 13 14 15 and 16 Bi directional Differential Data Strobe signals Per DRAM Addressability is supported Write CRC is supported at all speed grades DBI Data Bus Inversion is supported x8 only CA parity Command Address Parity mode is supported Supports ECC error correction and detection 16 internal banks SDRAM Addressing Row Col BG BA 15 10 2 2 Fully RoHS Compliant Identification DTM68103B 512Mx64 4G 1Rx8 PC4 2133P UB0 10 Performance range Clock Module Speed CL trep trp 1067 MHz PC4 2133 16 16 16 1067MHz PC4 2133 15 15 15 933 Hz PC4 1866 14 14 14 933 Hz PC4 1866 13 13 13 800 Hz PC4 1600 12 12 12 800 Hz PC4 1600 11 11 11 667 MHz PC4 1600 10 10 10 667 MHz PC4 1600 9 9 9 Description DTM68103B is an unbuffered 512Mx64 memory module which conforms t
8. ut Data Mask and Data Bus Inversion DQS 7 0 _t DQS 7 0 _c Differential Data Strobes CK_t 1 0 CK_c 1 0 Differential Clock Inputs CKEO CKE1 Clock Enables CAS_n A15 Multiplexed Column Address Strobe or Address 15 RAS_n A16 Multiplexed Row Address Strobe or Address 16 CS0_N CS 3 1 _n Chip Selects ACT_n Activate Command Input WE_n A14 Multiplexed Write Enable or Address 14 C 2 0 Chip ID Inputs Address Inputs Bank Address select Inputs Bank Group select Inputs ODTO ODT 1 On Die Termination Inputs SA 2 0 SPD Address SCL SPD Clock Input SDA SPD Data Input Output EVENT_n Temperature Sensing RESET_n Reset for register and DRAMs PARITY Parity bit input for Addr Ctrl ALERT_n CRC Error Flag or CMD Addr Parity Flag Output A12 BC_n Combination Input Address12 Burst Chop A10 AP Combination Input Addr10 Auto precharge 12V Optional Power Supply Vpp Charge Pump Power Vss Ground Voo Power Voppspp SPD EEPROM Power VREFCA Reference Voltage for CA Vrr Termination Voltage NC No Connection RFU Reserved for Future Use Not used Document 06386 Revision A 08 Sep 14 Dataram Corporation 2014 Page 5 DRDATARAM DTM681 03 B Optimizing Value and Performance 4GB 288 Pin 1Rx8 Unbuffered Non ECC DDR4 DIMM C 7 Comforms o MO 309C 16 65 C 661 LS a C y 1 5 _ s J Sat C 061 TT C aa F DONNE TNT TENTE Munn CS S
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