Hynix HMT351U7CFR8A-PBT0 memory module
Contents
1. 4GB 512Mx72 Module 2Rank of x8 E S0 SI DQSO DQS4 DQSO DOS4 DMO 1 4 1 DM CS DQS DQS DM CSDQS DAS DM CS DQS DQS DM CSDQS DQS peo w I O0 Jo 0 DQ32 W1 0 0 00 DQi W IO1 DO JO 1 D9 DQ33 W I O 1 D4 1 0 1 D13 DQ2 W I O2 Jo 2 DQ34 WY 1 0 2 1 0 2 DQ3 Ww I O3 1 03 DQ35 W I O 3 1 0 3 DQ4 W IO4 I4 DQ36 W 1 0 4 1 0 4 DQ5 W I O5 1 05 DQ37 w 1 0 5 IO 5 DQ6 W I O6 1 06 Zo DQ38 W41 0 6 UO 6 DQ7 W 1I O7 Z yo DQ39 W 1 0 7 1 07 ZQ DQS1 2 DOS5 2971 DQS1 DQS5 DM1 1 DM5 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ8 W I O0 1 00 DQ40 11 O 0 1 0 0 DQ9 w4I O 1 D1 I O1 D10 DQ41 AI O 1 D5 yo D14 DQ10 W41 0 2 yo2 DQ42 WY 1 0 2 1 02 DQii W41 0 3 103 DQ43 W 1 0 3 1 03 DQ12 W41 0 4 yo4 DQ44 W4 1 0 4 04 DQ13 W41 0 5 105 ZQ DQ45 1 0 5 105 DQ14 W41 0 6 1 06 pun DQ46 W 1 0 6 1 06 DQ15 A I O 7 ZQ 07 DQS6 DQ47 W 1 0 7 zQ J07 Z DQS2 DQS6 7 DQS2 Q DM2 1 DM6 1 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS2. x E E SIE S mms gja 45 IIS IR IE 5 iglia amp rm o E 2 8 Mi qa 4 0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 2 1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 0 aus repeat above D Command until nRRD 1 nRRD ACT 0 0 1 1 0 1 00 0 0 0 1 nRRD 1 RDA 0 1 0 1 0 1 00 0 0 00110011 nRRD 2 D 1 0 0 0 0 1 00 0 0 F 0 T repeat above D Command until 2 nRRD 1 2 2 nRRD repeat Sub Loop 0 but BA 2 0 2 3 3 nRRD repeat Sub Loop 1 but BA 2 0 3 4 4 nRRD D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2 0 5 7 nFAW 2 nRRD repeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 S 9 nFAW 4 nRRD D 1 0 0 0 0 7 00 0 0 F 0 S r Assert and repeat above D Command until 2 nFAW 1 if necessary E z 2 nFAW 0 ACT 0 0 1 1 0 0 00 0 0 F 0 B a 10 2 nFAW 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 z SAT Repeat above D Command until 2 nFAW nRRD 1 2 nFAW nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 T 2 nFAW nRRD 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 7 seven eGR Me Repeat above D Command until 2 nFAW 2 nRRD 1 12 2 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 2 13 2 nFAW
3. DDR3L 800 Speed Bins For specific Notes See Speed Bin Table Notes on page 36 Speed Bin DDR3L 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data faa 15 20 ns ACT to internal read or write delay time cD 15 ns PRE command period fRp 15 ns ACT to ACT or REF command period fac 52 5 ns ACT to PRE command period fRas 37 5 9 tREFI ns CL 6 CWL 5 tekave 2 5 3 3 ns 1 2 3 Supported CL Settings 6 lick Supported CWL Settings 5 lick Rev 1 1 Jul 2013 32 SK yi DDR3L 1066 Speed Bins For specific Notes See Speed Bin Table Notes on page 36 Speed Bin DDR3L 1066F i N CL nRCD nRP 7 7 7 Unit ote Parameter Symbol min max Internal read command to first data thn 13 125 20 ns ACT to internal read or write delay time fRCD m ns PRE command period tap 13 125 ns ACT to ACT or REF command lac 50 625 u dg period ACT to PRE command period teas 37 5 9 tREFI ns 26 CWL 5 K AVG 2 5 3 3 ns 1 2 3 6 S CWL 6 CK AVG Reserved ns 1 2 3 4 TN CWL 5 lck AvG Reserved ns 4 7 CWL 6 iCK AVG 1 875 lt 2 5 ns 1 2 3 4 CWL 5 lck AvG Reserved ns 4 7 CWL 6 iCK AVG 1 875 lt 2 5 ns 1 2 3 Supported CL Settings 6 7 8 NK Supported CWL Settings 5 6 IK Rev 1 1 Jul 2013 33 SK yi DDR3L 1333 Speed Bins For specific Notes See Spee
4. Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VoL diff AC Vonadit AC Vouaitt acy VoLditt ac DeltaTRdi Differential output slew rate for falling edge Voudiff AC VoLaiff ac Vouditt acy Votaitt acyl DeltaTFdiff Notes 1 Output slew rate is verified by design and characterization and may not be subject to production test 73 C o VoHdiff AC d z 8 s z 0 3 S E T4 4 VOLdiff AC Differential Output slew Rate Definition Differential Output Slew Rate DDR3L 800 DDR3L 1066 DDR3L 1333 DDR3L 1600 Unit nits Parameter Symbol Min Max Min Max Min Max Min Max Differential Output Slew Rate SRQdiff 3 5 12 3 5 12 3 5 12 3 5 12 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Rev 1 1 Jul 2013 27 SK yi Reference Load for AC Timing and Output Slew Rate Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tes
5. 0 0 0 F 0 a 9 eh repeat pattern nRC 1 4 until nRC nRCE 1 truncate if necessary 8 g 1 nRC nRCD RD 0 1 0 1 0 0 00 0 0 F O 00110011 ies repeat pattern nRC 1 4 until NRC nRAS 1 truncate if necessary 1 nRC nRAS PRE 0 0 1 0 0 0 00 0 O F 0 is repeat pattern nRC 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 1 Jul 2013 45 SK yi Table 5 IDD2N and IDD3N Measurement Loop Pattern a o I Sls ea m m m ie 3 82 Ele iig i BS ERR oah 6 3 Og E k oO g g z 7 T 7 Oo lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 1 1 1 0 0 0 00 F 0 3 D 1 1 1 1 0 0 0 00 F 0 m 1 14 7 repeat Sub Loop 0 use BA 2
6. 47 Vss 167 NC 107 Vss 227 DQ60 48 NC 168 Reset 108 DQ56 228 DQ61 KEY KEY 109 DQ57 229 Vss 49 NC 169 CKE1 NC 110 Vss 230 DM7 50 CKEO 170 VDD 111 DQS7 231 NC 51 VDD 171 NC 112 DQS7 232 Vss 52 BA2 172 A14 113 Vss 233 DQ62 53 NC 173 VDD 114 DQ58 234 DQ63 54 VDD 174 A12 115 DQ59 235 Vss 55 All 175 A9 116 Vss 236 VDDSPD 56 A72 176 VDD 117 SAO 237 SA1 57 VDD 177 A8 118 SCL 238 SDA 58 A52 178 A62 119 SA2 239 Vss 59 A42 179 VDD 120 VTT 240 VTT 60 VDD 180 A32 NC No Connect RFU Reserved Future Use 1 NC pins should not be connected to anything on the DIMM including bussing within the NC group 2 Address pins A3 A8 and BAO and BA1 can be mirrored or not mirrored Rev 1 1 Jul 2013 SK yi On DIMM Thermal Sensor The DDR3L SDRAM DIMM temperature is monitored by integrated thermal sensor The integrated thermal sensor comply with JEDEC TSE2002av Serial Presence Detect with Temperature Sensor Connection of Thermal Sensor SAO EVENT spp with SA1 SCL Integrated c4 SDA TS Temperature to Digital Conversion Performance Parameter Condition Min Typ Max Unit Active Range 75 C lt Ty lt 95 C Temperature Sensor Accuracy Grade B Monitor Range 40 C lt Ta lt 125 C TEN EAREN e 20 C lt Ty lt 125 C 20 3 0 C Resolution 0 25 C Rev 1 1 Jul 2013 10 S R nix Fu
7. Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Ipp2P1 Precharge Power Down Current Fast Exit CKE Low External clock On tCK CL see Table 1 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Ipp2Q Precharge Quiet Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Jpp3N Active Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 IppsP Active Power Down Current CKE Low External clock On tCK CL see Table 1 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer
8. VSEH Single ended high level for strobes VDD 2 0 175 Note 3 V 1 2 Single ended high level for Ck CK VDD 2 0 175 Note 3 V 1 2 VSEL Single ended low level for strobes Note 3 VDD 2 0 175 V 1 2 Single ended low level for CK CK Note 3 VDD 2 0 175 V 1 2 Notes 1 For CK CK use VIH VIL ac of ADD CMD for strobes DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs 2 VIH ac VIL ac for DQs is based on VREFDQ VIH ac VIL ac for ADD CMD is based on VREFCA if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Rev 1 1 Jul 2013 on page 28 22 SK six Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the requirements in table below The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS VDD ymmo mm CK DQS v Vix SSS a NEU oed M E VDD 2 Vix ea d CK DQ
9. and RTT Enabled in Mode Registers ODT Signal stable at 0 Rev 1 1 Jul 2013 41 SK yi Symbol Description Operating Burst Read Current CKE High External clock On tCK CL see Table 1 BL 82 AL 0 CS High between RD Command Address I Bank Address Inputs partially toggling according to Table 7 Data IO seamless read data burst with different DD4R data between one burst and the next one according to Table 7 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 7 Operating Burst Write Current CKE High External clock On tCK CL see Table 1 BL 82 AL 0 CS High between WR Command Address L Bank Address Inputs partially toggling according to Table 8 Data IO seamless read data burst with different DDAW data between one burst and the next one according to Table 8 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 8 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at HIGH Pattern Details see Table 8 Burst Refresh Current CKE High External clock On tCK CL nRFC see Table 1 BL 89 AL 0 CS High between REF Command JppsB Address Bank Address Inputs partially toggling according to Table 9 Data IO MID LEVEL DM stable at 0
10. 0 1 instead 9 2 2 8 11 repeat Sub Loop 0 use BA 2 0 2 instead 2 B 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat Sub Loop 0 use BA 2 0 6 instead 7 28 31 repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Table 6 IDD2NT and IDDQ2NT Measurement Loop Pattern x 9 D g t o da REM s 8 i i Pel BIiikiiic o E 8 am lt lt q lt 0 0O D 1 0 0 0 0 0 0 0 0 0 0 z 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 1 1 1 0 0 80 0 0 F 0 3 D 1 1 1 1 0 0 0 0 0 F oOo D 1 47 repeat Sub Loop 0 but ODT 0 and BA 2 0 1 2 9 2 8 11 repeat Sub Loop 0 but ODT 1 and BA 2 0 2 2 8 3 12 15 repeat Sub Loop 0 but ODT 1 and BA 2 0 3 4 16 19 repeat Sub Loop 0 but ODT 0 and BA 2 0 4 5 20 23 repeat Sub Loop 0 but ODT 0 and BA 2 0 5 6 24 17 repeat Sub Loop 0 but ODT 1 and BA 2 0 6 7 128 31 repeat Sub Loop 0 but ODT 1 and BA 2 0 7 a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 1 Jul 2013 46 De SK hynix Table 7 IDD4R and IDDQ4R Measurement Loop Pattern 9 E o t gt o Fla olala S82 2 WEBE 8 2 2 s s Fou re 2 oZ 3 x EE EE M ME 0 0 R
11. 0 000 0 F 0 2 9 m repeat pattern 1 4 until 1 nRC nRAS 1 truncate if necessary BIB 1 mRC nRAS PRE 0 0 1 0 0 0 00 ojlo Flo n repeat pattern 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 1 Jul 2013 44 SK yi Table 4 IDD1 Measurement Loop Pattern a D E D ad emma 5 83 e Plel2isie B 83 BR 8E om 5 7 3 F z o g ggd 7 Oo lt 0 0 ACT 0 0 1 1 0 00 0 O 0 0 1 2 DD 1 0 0 0 0 00 00 0 0 3 4 DD1 1 1 i 0 00 0 0 0 0 repeat pattern 1 4 until nRCD 1 truncate if necessary nRCD RD 0 1 0 1 0 0 00 0 O 0 O 00000000 us repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 i repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 0 0 F 0 s 1 nRC 1 2 D D 1 0 0 0 0 0 00 0 O F 0 2 2 1 nRC 3 4 DD 1 1 1 1 0 0
12. 0 05 lt gt Xy a mia 2 500 200 3 ols e m S 1 00 gt lt gt 1 50 0 10 1 27 0 10 eg 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 1 Jul 2013 Units millimeters SK yi 512Mx72 HMT351U7CFR8A Front 2 1030 15 Min 1 45 pe Max RO 70 308 wig l 4x3 00 0 10 jdn 1730 DETAIL A DETAIL B 2 x 2 50 0 10 i 9 50 2x2 i Qj ner 47 00 gt 71 00 4 128 95 Pi 133 35 Back O U O Side Detail A Detail B 3 64mm Max 2 50 FULL R 0 80 0 05 lt 4 m mu 2 5040 20 amp 3 clo e E E 1 00 A t E 0 3 1 0 1 5040 10 1 27 0 10 gt lt 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev
13. 1 2 If minimum limit is exceeded input levels shall be governed by DDR3L specifications Under 1 5V operation this DDR3L device operates to the DDR3 specifications under the same speed timings as defined for this device Once initialized for DDR3 operation DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation see Figure 0 Rev 1 1 Jul 2013 14 Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK CK tCKSRX Tmin 10ns Tmin 200us T 500us za VDD VDDQ DDR3 VDD VDDQ DDR3L Tmin mm RESET CKE COMMAND BA opt 7 RTT NOTE 1 From time point Td until Tk NOP or DES commands must be applied 7 j between MRS and ZQCL commands TIME BREAK DON T CARE Figure 0 VDD VDDQ Voltage Switch Between DDR3L and DDR3 Rev 1 1 Jul 2013 15 De SK hynix AC amp DC Input Measurement Levels AC and DC Logic Input Levels for Single Ended Signals AC and DC Input Levels for Single Ended Command and Address Signals Single Ended AC and DC Input Levels for Command and Address DDR3L 800 1066 DDR3L 1333 1600 Symbol Parameter Unit Notes Min Max Min Max VIH CA DC90 DC input logic high Vref 0 09 VDD Vref 0 09 VDD V 1 VIL CA DC90 DC input logic low VSS Vref 0 09 VSS Vref 0 09 V 1 VIH CA AC160 AC input logic high Vref 0 1
14. 1 1 Jul 2013 Units millimeters 52
15. 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to WR Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Write Command Outside burst operation DQ signals are MID LEVEL Rev 1 1 Jul 2013 47 SK yi Table 9 IDD5B Measurement Loop Pattern a D E cw l lea Sel mala ie 5 Sf 8 B3 3 8 amp S amp vam eI eB 5 TJI IX 7 Oo lt 0 0 REF 0 0 0 1 0 0 0 0 0 0 1 12 D D 1 0 0 0 0 0100 0 0 0 3 4 DD 1 1 1 1 00 000 0O F 5 8 repeat cycles 1 4 but BA 2 0 1 2 9 12 repeat cycles 1 4 but BA 2 0 2 2 9 13 16 repeat cycles 1 4 but BA 2 0 2 3 2 amp 17 20 repeat cycles 1 4 but BA 2 0 4 21 24 repeat cycles 1 4 but BA 2 0 5 25 28 repeat cycles 1 4 but BA 2 0 6 29 32 repeat cycles 1 4 but BA 2 0 7 2 33 nRFC 1 repeat Sub Loop 1 until nRFC 1 Truncate if necessary a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 1 Jul 2013 48 SK six Table 10 IDD7 Measurement Loop Pattern ATTENTION Sub Loops 10 19 have inverse A 6 3 Pattern and Data Pattern than Sub Loops 0 9
16. 8 AL 0 CS High between ACT RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 4 DM stable at 0 Bank Activity Cycling with on bank active at a time 0 0 1 1 2 2 see Table 4 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 4 Rev 1 1 Jul 2013 40 De SK hynix Symbol Description Jpp2N Precharge Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Jpp2NT Precharge Standby ODT Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 6 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling according to Table 6 Pattern Details see Table 6 Ipp2P0 Precharge Power Down Current Slow Exit CKE Low External clock On tCK CL see Table 1 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed
17. DQS DQ16 W41 0 0 yoo DQ48 W 1 0 0 IO 0 DQ17 v 1 0 1 D2 yo D11 DQ49 v 1 0 1 D6 IO 1 D15 DQ18 W41 0 2 1 02 DQ50 W 1 0 2 Jo 2 DQ19 W 103 1 03 DQ51 W 1 0 3 1 03 DQ20 W1 0 4 1 04 DQ52 w I O 4 1 0 4 DQ21 w 1I O 5 105 DQ53 1 0 5 1 05 DQ22 W41 0 6 1 06 zQA DQ54 W41 0 6 1 0 6 DQ23 wv 1 07 205 V07 de DQ55 v 1 07 zo o7 ZAF D S3 gt D S7 ni DOS3 bees DM3 DM7 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ24 W41 0 0 IO 0 DQ56 W1 0 0 yoo DQ25 v 1 0 1 D3 IO 1 D12 DQ57 w I O 1 D7 IO 1 D16 DQ26 wI O 2 1 02 DQ58 WI O 2 Uo 2 DQ27 w 1 03 1 03 DQ59 W1 0 3 Io 3 DQ28 W 1 0 4 Io4 DQ60 W 1 0 4 yo4 DQ29 W4 1 0 5 1 05 DQ61 I 0O 5 1 05 DQ30 W41 0 6 1 06 DQ62 W41 0 6 IO 6 z4 DQ31 w I O 7 29 1 07 zQ DQ63 v 1 0 7 zQ 1 07 oe DQS8 rn VDDSPD SPD DQS8 ij SPD TS integrated VDD VDDQ _ D0 D17 DM8 moe L4 VREFDQ p D0 D17 DM CS DQS DQS DM CSDQS DQS EVENT lt gt SDA CB0 w 41 00 1 00 EVENT A0 Al A2 Vss 4 F p0 D17 CBE et p8 Yor pi7 I I 1 VREFCA D0 D17 CB2 w 102 1 02 vo SAY S2 CB3 wW 1 03 1 03 Notes CB4 W yO4 1 04 1 DQ to I O wiring is shown as recom CB5 w 1I 0 5 1 05 mended but may be changed CB6 W 1 06 1 06 2 DQ DQS DQS ODT DM CKE S relation cB7 W I0O7 zQ 107 zQ ships must be maintained as shown 3 DO CB DM DOS DOS resistors Refer to E p BA2 E associated topo
18. affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300mV of each other at all times and VREF must not be greater than 0 6XVDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mV DRAM Component Operating Temperature Range Temperature Range Symbol Parameter Rating Units Notes Toper Normal Operating Temperature Range 0 to 85 C 1 2 Extended Temperature Range 85 to 95 C 1 3 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For mea surement conditions please refer to the JEDEC document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported Dur ing operation the DRAM case temperature must be maintained between 0 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to the DIMM S
19. as shown in the table which are not subject to Production Tests but verified by Design Characterization DDR3 SDRAM devices supporting optional down binning to CL 7 and CL 9 and tAA tRCD tRP must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333H devices supporting down bin ning to DDR3 1066F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRP min Byte 20 DDR3 1600K devices supporting down binning to DDR3 1333H or DDR3 1600F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36 ns 13 125 ns for DDR3 1333H and 48 125ns tRASmin tRPmin 35 ns 13 125 ns for DDR3 1600K Rev 1 1 Jul 2013 36 SK yi Environmental Parameters Symbol Parameter Rating Units Notes Topr Operating temperature ambient 0 to 55 C 3 Hopr Operating humidity relative 10 to 90 TsTG Storage temperature 50 to 100 oc 1 HsrcG Storage humidity without condensation 5 to 95 96 1 PBAR Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied E
20. for Vgerpc deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with Vgcrac noise Timing and voltage effects due to ac noise on Vg up to the speci fied limit 1 of VDD are included in DRAM timings and their associated deratings Rev 1 1 Jul 2013 18 SK yi AC and DC Logic Input Levels for Differential Signals Differential signal definition VILDIFFACMIN o cree e Be es ee een nu Selle ere a ore hg VILDFEMN MERC ERES Oe ENE RECEN UNDER half cycle Mo SIM demde eem dEA Differential Input Voltage i e DQS DQS CK CK VILBIFEACMAK 4 4 tpvac Definition of differential ac swing and time above ac level tpyac Rev 1 1 Jul 2013 19 SK yi Differential swing requirements for clock CK CK and strobe DQS DQS Differential AC and DC Input Levels DDR3L 800 1066 1333 amp 1600 Symbol Parameter T 7 Unit Notes in ax Viindiff Differential input high 0 180 Note 3 V 1 Vii dirt Differential input logic low Note 3 0 180 V 1 VIHdiff ac Differential input high ac 2 x VIH ac Vref Note 3 V 2 Vit diff ac Differential input low ac Note 3 2 x VIL ac Vref V 2 Notes 1 Used to define a differential signal slew rate 2 For CK CK u
21. strobe SAO SA2 12C slave address select for EEPROM CAS SDRAM column address strobe VDD SDRAM core power supply WE SDRAM write enable VDDQ SDRAM I O Driver power supply S0 S1 DIMM Rank Select Lines VREFDQ SDRAM I O reference supply CKEO CKE1 SDRAM clock enable lines VREFCA EN oh command address reference ODTO ODT1 On die termination control lines Vss Power supply return ground DQ0 DQ63 DIMM memory data bus VDDSPD Serial EEPROM positive power supply CBO CB7 DIMM ECC check bits NC Spare pins no connect SDRAM data strobes Memory bus analysis tools PRUSIR positive line of differential pair I unused on memory DIMMS LL SDRAM data strobes DQS0 DQS8 negative line of differential pair RESET Set DRAMs to Known State SDRAM data masks high data strobes m DM0 DMS8 x8 based x72 DIMMs VIT SDRAM 1 0 termination supply CKO CK1 POPAN ands RSVD Reserved for future use positive line of differential pair SDRAM clocks CIOE negative line of differential pair g g The Vpp and VDDQ pins are tied common to a single power plane on these designs Rev 1 1 Jul 2013 SK yi Input Output Functional Descriptions Symbol Type Polarity Function CKO CK1 CKO CK1 CKEO CKE1 SSTL SSTL Differential crossing Active High CK and CK are differential clock inputs All the DDR3L SDRAM addr cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK Output read data is ref
22. 00 Unit note IDDO 522 585 mA IDD1 567 675 mA IDD2N 324 360 mA IDD2NT 414 450 mA IDD2P0 180 180 mA IDD2P1 234 270 mA IDD2Q 360 360 mA IDD3N 396 450 mA IDD3P 234 270 mA IDD4R 882 1035 mA IDD4W 837 990 mA IDD5B 1197 1260 mA IDD6 180 180 mA IDDET 216 216 mA IDD7 1647 1755 mA Rev 1 1 Jul 2013 50 SK yi Module Dimensions 256Mx72 HMT325U7CFR8A Front 2 10 0 15 Min 1 45 gt br Max RO 70 4x3 00 0 10 p A DETAIL A DETAIL B 2 x62 50 0 10 2x2 3030 Cm X 2 Li 5 175 47 00 71 00 128 95 i 133 35 Back U Side Detail A Detail B 2 50 2 51mm Max 0 80
23. 3 nRRD repeat Sub Loop 11 but BA 2 0 3 D 1 0 0 0 0 3 00 0 0 0 0 Ee SL Assert and repeat above D Command until 3 nFAW 1 if necessary 15 3 nFAW repeat Sub Loop 10 but BA 2 0 4 16 3 nFAW nRRD repeat Sub Loop 11 but BA 2 0 5 17 3 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 6 18 3 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 7 D 1 0 0 0 0 7 00 0 0 0 0 ae BPRERUREESRRIE Assert and repeat above D Command until 4 nFAW 1 if necessary a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 1 Jul 2013 49 y SK Paix IDD Specifications Tcase 0 to 95 C Module IDD values in the datasheet are only a calculation based on the component IDD spec The actual measurements may vary according to DQ loading cap 2GB 256M x 72 U DIMM HMT325U7CFR8A Symbol DDR3L 1333 DDR3L 1600 Unit note IDDO 360 360 mA IDD1 405 450 mA IDD2N 162 180 mA IDD2NT 207 225 mA IDD2PO 90 90 mA IDD2P1 117 135 mA IDD2Q 180 180 mA IDD3N 198 225 mA IDD3P 117 135 mA IDD4R 720 810 mA IDD4W 675 765 mA IDD5B 1035 1035 mA IDD6 90 90 mA IDD6ET 108 108 mA IDD7 1485 1530 mA 4GB 512M x 72 U DIMM HMT351U7CFR8A Symbol DDR3L 1333 DDR3L 16
24. 60 Note2 Vref 0 160 Note2 V 1 2 5 VIL CA AC160 AC input logic low Note2 Vref 0 160 Note2 Vref 0 160 V 1 2 5 VIH CA AC135 AC Input logic high Vref 0 135 Note2 Vref 0 135 Note2 V 1 2 5 VIL CA AC135 AC input logic low Note2 Vref 0 135 Note2 Vref 0 135 V 1 2 5 VIH CA AC125 AC Input logic high V 1 2 5 VIL CA AC125 AC input logic low V 1 2 5 VRetCA DC ee pre 049 VDD 0 51 VDD 049 VDD 0 51 VDD V 34 Notes 1 For input only pins except RESET Vref VrefCA DC 2 Refer to Overshoot and Undershoot Specifications on page 29 3 The ac peak noise on Vref may not allow Vper to deviate from VgercA pc by more than 1 VDD for refer ence approx 13 5 mV 4 For reference approx VDD 2 13 5 mV 5 These levels apply for 1 35 volt see table above operation only If the device is operated at 1 5V table Single Ended AC and DC Input Levels for DQ and DM on page 17 the respective levels in JESD79 3 VIH L CA DC100 VIH L CA AC175 VIH L CA AC150 VIH L CA AC135 VIH L CA AC125 etc apply The 1 5V levels VIH L CA DC100 VIH L CA AC175 VIH L CA AC150 VIH L CA AC135 VIH L CA AC125 etc do not apply when the device is operated in the 1 35 voltage range Rev 1 1 Jul 2013 16 De SK hynix AC and DC Input Levels for Single Ended Signals DDR3 SDRAM will support two Vih Vil AC levels for DDR3 800 and DDR3 1066s specified in table below DDR3 SDRAM will also suppo
25. Bank Activity REF command every nREF see Table 9 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 9 Self Refresh Current Normal Temperature Range Tease 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Ippe Low External clock Off CK and CK LOW CL see Table 1 BL 82 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Self Refresh Current Extended Temperature Range Tease 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended Jpp6eET CKE Low External clock Off CK and CK LOW CL see Table 1 BL 8 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Rev 1 1 Jul 2013 42 SK yi Symbol Description Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD NRRD nFAW CL see Table 1 BL 83 AL CL 1 CS High between ACT and RDA Command Address Bank Address Inputs partially toggling according to Table Ipp7 10 Data IO read data burst with different data between one burst and the
26. D 0 1 0 1 0 0 00 0 0 0 O 00000000 1 D 1 0 0 0 0 0 00 O 0 0 0 2 3 DD 1 1 11 0 0 000 0 0 0 4 RD 0 1 0 1 0 0 00 0 0 F O 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 S 6 7 DD 1 1 1 1 0 0 00 0 0O F 0 a 2 1 8 15 repeat Sub Loop 0 but BA 2 0 1 9 B 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Table 8 IDD4W Measurement Loop Pattern a ia E m m x o o9 o e ri m mM pon 8 i i fwli 5gig ajg som 3 3 O83 5 Ss FT TT az 0 10 WR 0 1 0 0 1 0 00 0 0 0 O0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 z 2 3 DD 1 1 1 11 0 00 0 olo o 4 WR 0 1 0 0 1 0 00 0 0 F O 00110011 5 D 1 0 0 0 1 0 00 0 0 F 0 g 2 6 7 D D 1 1 1 1 1 0100 0 0 F 0 9 9 1 8 15 repeat Sub Loop 0 but BA 2 0 1 g 5 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 124 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0
27. DDSPD to con figure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into or out of the SPD SDA EEPROM An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board This signal is used to clock data into and out of the SPD EEPROM An SCL external resistor may be connected from the SCL bus time to VDDspPD to act as a pullup on the system board Suppl Power supply for SPD EEPROM This supply is separate from the Vbb VbDQ PPIy power plane EEPROM supply is operable from 3 0V to 3 6V Rev 1 1 Jul 2013 De SK hynix Pin Assignments Front Side left 1 60 Back Side right 121 180 Front Side left 61 120 Back Side right 181 240 Pin x72 Pin x72 Pin x72 Pin x72 ECC ECC ECC ECC 1 VREFDQ 121 Vss 61 A2 181 Al 2 Vss 122 DQ4 62 VDD 182 VDD 3 DQO 123 DQ5 63 CK1 183 VDD 4 DQ1 124 Vss 64 CK1 184 CKO 5 Vss 125 DMO 65 VDD 185 CKO 6 DQSO 126 NC 66 VDD 186 VDD 7 DQSO 127 Vss 67 VREFCA 187 EVENT 8 Vss 128 DQ6 68 NC 188 AO 9 DQ2 129 DQ7 69 VDD 189 VDD 10 DQ3 130 Vss 70 A10 190 BA1 11 Vss 131 DQ12 7 BAO2 191 VDD 12 DQ8 132 DQ13 72 VDD 192 RAS 13 DQ9 133 Vss 73 WE 193 SO 14 Vss 134 DM1 74 CAS 194 VDD 15 DQS1 135 NC 75 VDD 195 ODTO 16 DQS1 136 Vss 76 S1 196 A13 17 Vss 137 DQ14 77 ODT1 197 VDD 18 DQ10 138 DQ15 78 VDD 198 NC 19 D
28. DQSL have to reach VSEHmin VSELmax approximately the ac levels VIH ac VIL ac for DQ signals in every half cycle preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if VIH CA AC150 VIL CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK VDD or VDDQ VSEHmin m a poe e a a a a e VDD 2 or VDDQ 2 Sete otis eee ee cee eee t CK or DQS VSELmax A t 1 VSEL VSS of VSSQ 2 22 oe re ee bet eee he See SS SSS SSeS ae ea See E ae eee Se ee EE time Single ended requirements for differential signals Note that while ADD CMD and DQ signal requirements are with respect to Vref the single ended compo nents of differential signals have a requirement with respect to VDD 2 this is nominally the same the transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Rev 1 1 Jul 2013 21 SK yi Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU DDR3L 800 1066 1333 amp 1600 Parameter Unit Notes Min Max
29. HS directive Ordering Information Part Number Density Organization Component Composition sie FDHS HMT325U7CFR8A H9 PB 2GB 256Mx72 256Mx8 H5TC2G83CFR 9 1 X HMT351U7CFR8A H9 PB 4GB 512Mx72 256Mx8 H5TC2G83CFR 18 2 X Rev 1 1 Jul 2013 3 SK six Key Parameters CAS MT s Grade E Latency m Re cate ine CL tRCD tRP ns ns ns ns ns tCK DDR3 1066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 13 5 13 5 49 5 DDR3L 1333 H9 1 5 9 13 125 13 125 36 49 125 9 9 9 13 75 13 75 48 75 DDR3L 1600 PB 1 25 11 13 125 13 125 35 48 125 11 11 11 SK hynix DRAM devices support optional downbinning to CL9 and CL7 SPD setting is programmed to match Speed Grade Frequency MHz Grade Remark CL6 CL7 CL8 CL9 CL10 CL11 G7 800 1066 1066 H9 800 1066 1066 1333 1333 PB 800 1066 1066 1333 1333 1600 Address Table 2GB 1Rx8 4GB 2Rx8 Refresh Method 8K 64ms 8K 64ms Row Address A0 A14 A0 A14 Column Address A0 A9 AO0 A9 Bank Address BAO BA2 BAO BA2 Page Size 1KB 1KB Rev 1 1 Jul 2013 De SK hynix Pin Descriptions Pin Name Description Pin Name Description A0 A15 SDRAM address bus SCL I C serial bus clock for EEPROM BAO BA2 SDRAM bank select SDA I C serial bus data line for EEPROM RAS SDRAM row address
30. Mask DDR3L DDR3L DDRS3L DDR3L Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 25 0 19 0 15 0 13 V ns Maximum undershoot area below VSS See Figure below 0 25 0 19 0 15 0 13 V ns CK CK DQ DQS DQS DM See figure below for each parameter definition Maximum Amplitude Overshoot Area VDD Volts Q VSSQ Undershoot Area Maximum Amplitude Time ns Clock Data Strobe and Mask Overshoot and Undershoot Definition Rev 1 1 Jul 2013 30 SK six Refresh parameters by device density Refresh parameters by device density Parameter RTT Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes ee tRFC 90 110 160 260 350 ns REF command time verage periodic IREFI O CX Tease lt 85 C 7 8 7 8 7 8 7 8 7 8 us Pus interval B5 C TcAspES95 C 3 9 3 9 3 9 3 9 3 9 us 1 Notes 1 Users should refer to the DRAM supplier data sheet and or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this materia Rev 1 1 Jul 2013 31 SK yi Standard Speed Bins DDR3L SDRAM Standard Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin
31. O r0 6 ZQ T1 DQ62 W 1 0 6 ZQ 1 DQS8 DQ31 4I O 7 DQ63 41 O 7 DQS8 N DM8 DM CS DQs DQS SPD TS integrated Notes CBO wea SCL gt 1 DQ to I O wiring is shown as recom E lee UM EVENT lt gt SDA mended but may be changed Su EVENT ap Ai a 2 DQ DQS DQS ODT DM CKE S rela CB4 W O4 tionships must be maintained as CB5 wW 1 05 20 SAO SA1 SA2 shown GS ies L 3 DQ CB DM DQS DQS resistors Refer H to associated topology diagram BAO BA2 BA0 BA2 SDRAMs D0 D8 4 Refer to the appropriate clock wiring dps gt AO AI5 SDRAMs D0 D8 Vppspp SPD topology under the DIMM wiring RAS RAS SDRAMs D0 D8 VDD VDDQ details section of this document o_o CASESDRAMS DODO t D0 D8 5 For each DRAM a unique ZQ resistor CKE0 CKE SDRAMs D0 D8 VREFDQ D0 D8 is connected to ground The ZQ resis WE WE SDRAMs D0 D8 fT D04 tor is 2400hm 1 ODTO ODT SDRAMs D0 D8 VSs DO D8 6 One SPD exists per module CKO gt CK SDRAMs D0 D8 F cKO TK SDRAMs D0 D8 VREFCA D0 D8 RESET RESET SDRAMs D0 D8 Rev 1 1 Jul 2013 11 SK yi
32. PD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to use the Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 0b and MR2 A7 1b DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and or the DIMM SPD for tFEFI requirements in the Extended Temperature Range Rev 1 1 Jul 2013 13 SK yi AC amp DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions DDR3L 1 35V operation Rating Symbol Parameter Units Notes Min Typ Max VDDQ Supply Voltage for Output 1 283 1 35 1 45 1 2 3 4 Notes 1 Maximum DC value may not be greater than 1 425V The DC value is the linear average of VDD VDDQ t over a very long period of time e g 1 sec If maximum limit is exceeded input levels shall be governed by DDR3 specifications Under these supply voltages the device operates to this DDR3L specification 4 Once initialized for DDR3L operation DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation see Figure 0 Recommended DC Operating Conditions DDR3 1 5V operation Rating Parameter Units Notes Min Typ Max VDD Supply Voltage 1 425 1 5 1 575 1 2 3 VDDQ Supply Voltage for Output 1 425 1 5 1 575 V 1 2 3 Notes
33. Q11 139 Vss 79 NC 199 Vss 20 Vss 140 DQ20 80 Vss 200 DQ36 21 DQ16 141 DQ21 81 DQ32 201 DQ37 22 DQ17 142 Vss 82 DQ33 202 Vss 23 Vss 143 DM2 83 Vss 203 DM4 24 DQS2 144 NC 84 DQS4 204 NC 25 DQS2 145 Vss 85 DQS4 205 Vss 26 Vss 146 DQ22 86 Vss 206 DQ38 27 DQ18 147 DQ23 87 DQ34 207 DQ39 28 DQ19 148 Vss 88 DQ35 208 Vss 29 Vss 149 DQ28 89 Vss 209 DQ44 30 DQ24 150 DQ29 90 DQ40 210 DQ45 NC No Connect RFU Reserved Future Use 1 NC pins should not be connected to anything on the DIMM including bussing within the NC group 2 Address pins A3 A8 and BAO and BA1 can be mirrored or not mirrored Rev 1 1 Jul 2013 De SK hynix Front Side left 1 60 Back Side right 121 180 Front Side left 61 120 Back Side right 181 240 Pin x72 Pin x72 Pin x72 Pin x72 ECC ECC ECC ECC 31 DQ25 151 Vss 91 DQ41 211 Vss 32 Vss 152 DM3 92 Vss 212 DM5 33 DQS3 153 NC 93 DQS5 213 NC 34 DQS3 154 Vss 94 DQS5 214 Vss 35 Vss 155 DQ30 95 Vss 215 DQ46 36 DQ26 156 DQ31 96 DQ42 216 DQ47 37 DQ27 157 Vss 97 DQ43 217 Vss 38 Vss 158 CB4 98 Vss 218 DQ52 39 CBO 159 CB5 99 DQ48 219 DQ53 40 CB1 160 Vss 100 DQ49 220 Vss 41 Vss 161 DM8 101 Vss 221 DM6 42 DQS8 162 NC 102 DQS6 222 NC 43 DQS8 163 Vss 103 DQS6 223 Vss 44 Vss 164 CB6 104 Vss 224 DQ54 45 CB2 165 CB7 105 DQ50 225 DQ55 46 CB3 166 Vss 106 DQ51 226 Vss
34. S VSEH VSEL YSS Vix Definition Cross point voltage for differential input signals CK DQS DDR3L 800 1066 1333 1600 Parameter Unit Notes Min Max Vx CK Differential Input Cross Point Voltage 150 150 mV 2 ii relative to VDD 2 for CK CK 175 175 mv 1 Differential Input Cross Point Voltage E ROSS relative to VDD 2 for DQS DQS ae ie mE 4 Notes 1 Extended range for Vy is only allowed for clock and if single ended clock input signals CK and CK are monotonic with a single ended swing VSEL VSEH of at least VDD 2 250 mV and when the differential slew rate of CK CK is larger than 3 V ns 2 The relation between Vix Min Max and VSEL VSEH should satisfy following VDD 2 Vix Min VSEL gt 25mV VSEH VDD 2 Vix Max gt 25mV Rev 1 1 Jul 2013 23 SK yi Slew Rate Definitions for Single Ended Input Signals See 7 5 Address Command Setup Hold and Derating in DDR3L Device Operation for single ended slew rate definitions for address and command signals See 7 6 Data Setup Hold and Slew Rate Derating in DDR3L Device Operation for single ended slew rate definition for data signals Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in table and figure below Differential Input Slew Rate Definition Measured Description E Defined by Min ax Dif
35. SK yi DDR3L SDRAM Unbuffered DIMMs Based on 2Gb C Die HMT325U7CFR8A HMT351U7CFR8A SK hynix Semiconductor reserves the right to change products or specifications without notice Rev 1 1 Jul 2013 1 SK yi Revision History Revision No History Draft Date Remark 0 1 Initial Release Aug 2011 0 2 Added Speed Bin Table Notes Sep 2011 0 3 JEDEC Spec Updated Mar 2012 1 0 Module Dimension Updated Jul 2012 11 Changed module maximum thickness Jul 2013 to reflect the measured maximum Rev 1 1 Jul 2013 SK yi Description SK hynix Unbuffered DDR3L SDRAM DIMMs Unbuffered Double Data Rate Synchronous DRAM Dual In Line Memory Modules are low power high speed operation memory modules that use DDR3L SDRAM devices These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as PCs and workstations Feature Power Supply VDD 1 35V 1 283V to 1 45V e VDDQ 1 35V 1 283 to 1 45V e VDDSPD 3 0V to 3 6V e Backward Compatible with 1 5V DDR3 Memory module e 8 internal banks e Data transfer rates PC3 12800 PC3 10600 e Bi directional Differential Data Strobe e 8 bit pre fetch e Burst Length BL switch on the fly BL 8 or BC Burst Chop 4 e Supports ECC error correction and detection e On Die Termination ODT supported Temperature sensor with integrated SPD Serial Presence Detect EEPROM e This product is in Compliance with the Ro
36. ac DDR3L 800 DDR3L 1066 DDR3L 1333 DDR3L 1600 Unit nits Parameter Symbol Min Max Min Max Min Max Min Max Single ended Output Slew Rate SRQse 1 75 5 1 75 5D 175 5D 175 50 Vins Description SR Slew Rate Q Query Output like in DQ whiOch stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Note 1 In two cases a maximum slew rat e of 6V ns applies for a single DQ signal within a byte lane Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane are static i e they stay at either high or low Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane switching into the opposite direction i e from low to high of high to low respectively For the remaining DQ signal switching in to the opposite direction the regular maximum limite of 5 V ns applies Rev 1 1 Jul 2013 26 SK yi Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between VOLdiff AC and VOHdiff AC for differential signals as shown in table and figure below
37. d Bin Table Notes on page 36 Speed Bin DDR3L 1333H CL nRCD nRP 9 9 9 SIME Morg Parameter Symbol min max Internal read command to 13 5 first data AA 13 125 20 ne ACT to internal read or write 13 5 e delay time RCD 13 125 13 5 PRE command period tap 13 125 59 ns ACT to ACT or REF command 49 5 fc 59 ns period 49 125 ACT to PRE command period fRas 36 9 tREFI ns CWL 5 Ick AvG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 AVG Reserved ns 1 2 3 4 7 CWL 7 IcK AvG Reserved ns 4 CWL 5 CK AVG Reserved ns 4 1 875 lt 2 5 CL 7 CWL 6 fK AVG ns 1 2 3 4 7 Optional CWL 7 AVG Reserved ns 1 2 3 4 CWL 5 fK AVG Reserved ns 4 CL 8 CWL 6 fK AVG 1 875 lt 2 5 ns 1 2 3 7 CWL 7 CK AVG Reserved ns 1 2 3 4 EM CWL 5 6 CK AVG Reserved ns 4 7 CWL 7 ck AVG 1 5 1 875 ns 12 34 CWL 5 6 fK AVG Reserved ns 4 CL 10 1 5 1 875 ns 1 2 3 CAES tekave Reserved ns Supported CL Settings 6 7 8 9 10 NK Supported CWL Settings 5 6 7 NK Rev 1 1 Jul 2013 34 SK yi DDR3L 1600 Speed Bins For specific Notes See Speed Bin Table Notes on page 36 Speed Bin DDR3L 1600K CL nRCD nRP 11 11 11 Unit Note Parameter Symbol min max 13 75 Internal B
38. d at 1 5V table above the respective levels in JESD79 3 VIH L DQ DC100 VIH L DQ AC175 VIH L DQ AC150 VIH L DQ AC135 etc apply The 1 5V levels VIH L DQ DC100 VIH L DQ AC175 VIH L DQ AC150 VIH L DQ AC135 etc do not apply when the device is operated in the 1 35 voltage range Rev 1 1 Jul 2013 17 SK yi Vref Tolerances The dc tolerance limits and ac noise limits for the reference voltages yrefca and Vpefpg are illustrated in figure below It shows a valid reference voltage Vp t as a function of time Vref stands for Vperca and Vnerpo likewise Vref DC is the linear average of Vpe t over a very long period of time e g 1 sec This average has to meet the min max requirements in the table Differential Input Slew Rate Definition on page 24 Further more Vref t may temporarily deviate from Vger pc by no more than 1 VDD voltage VDD Vrer t Vref ac noise VRef DC max _ VDD 2 VRef DC min Illustration of Vgerpc tolerance and Vref ac noise limits The voltage levels for setup and hold time measurements Vyy acy Vra pc Vr acy and Vr pc are depen dent on Vger Vref shall be understood as Vgerpc as defined in figure above This clarifies that dc variations of Vper affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account
39. e using on merged power layer in Module PCB For IDD and IDDQ measurements the following definitions apply e 0 and LOW is defined as VIN lt Vr Ac max e and HIGH is defined as VIN gt VrrCc max e MID LEVEL is defined as inputs are VREF VDD 2 e Timing used for IDD and IDDQ Measurement Loop Patterns are provided in Table 1 e Basic IDD and IDDQ Measurement Conditions are described in Table 2 e Detailed IDD and IDDQ Measurement Loop Patterns are described in Table 3 through Table 10 e IDD Measurements are done after properly initializing the DDR3L SDRAM This includes but is not lim ited to setting RON RZQ 7 34 Ohm in MR1 Qoff 0g Output Buffer enabled in MR1 RTT Nom RZQ 6 40 Ohm in MR1 RTT Wr RZQ 2 120 Ohm in MR2 TDQS Feature disabled in MR1 e Attention The IDD and IDDQ Measurement Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started e Define D CS RAS CAS WE HIGH LOW LOW LOW e Define D CS RAS CAS WE HIGH HIGH HIGH HIGH Rev 1 1 Jul 2013 38 Y lop Y DDQ optional RESET pu DDR3L CK CK SDRAM CKE bas bas RTT 25 Ohm CS E DQ DM O 1 gt Vppo 2 RAS CAS WE TDQS TDQS A BA ODT ZQ Vss Measurement Setup and Test Load for IDD and IDDQ optional Measurements Note DIMM level Output test load condition may be different from above Application specific IDDQ memory channel Test L
40. erence to the crossing of CK and CK Both directions of crossing Activates the SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode S0 S1 SSTL Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high When the command decoder is dis abled new commands are ignored but previous operations continue This signal provides for external rank selection on systems with multiple ranks RAS CAS WE ODTO ODT1 SSTL SSTL Active Low Active High RAS CAS and WE ALONG wrth S define the command being entered When high termination resistance is enabled for all DQ DQS DQS and DM pins assuming this function is enabled in the Mode Register 1 MR1 VREFDQ Supply Reference voltage for SSTL15 I O inputs VREFCA Supply Reference voltage for SSTL 15 command address inputs VDDQ Supply Power supply for the DDR3L SDRAM output buffers to provide improved noise immunity For all current DDR3L unbuffered DIMM designs VDDQ shares the same power plane as VDD pins BAO BA2 SSTL Selects which SDRAM bank of eight is activated A0 A15 SSTL During a Bank Activate command cycle Address input defines the row address RAO RA15 During a Read or Write command cycle Address input defines the column address In addition to the colu
41. ferential input slew rate for rising edge CK CK and Das DGS geog Vitdiffmax ViHdiffmin ViHdiftmin ViLdifmaxl Delta TRdiff Differential input slew rate for falling edge CK CK and Das DGS aro ViHdifmin ViLdifmax ViHdiftmin ViLditmaxl Delta TFdiff Notes The differential signal i e CK CK and DQS DQS must be linear between these thresholds Differential Input Voltage i e DQS DQS CK CK Differential Input Slew Rate Definition for DQS DQS and CK CK Rev 1 1 Jul 2013 24 SK yi AC amp DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Single ended AC and DC Output Levels DDR3L 800 1066 Symbol Parameter Unit Notes 1333 and 1600 VoH DC DC output high measurement level for IV curve linearity 0 8 x VDDQ V VoM DO DC output mid measurement level for IV curve linearity 0 5 X VDDQ V VoL DC DC output low measurement level for IV curve linearity 0 2 x Vppo V VoH AC AC output high measurement level for output SR Vrr 0 1 x Vppo V 1 VoL ac AC output low measurement level for output SR Vrr 0 1 x Vppo V 1 Notes 1 The swing of 0 1 x Vppq is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 402 and an effective test load of 259 to Vtr Vppo 2 Differential AC and DC Output Level
42. ing tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchro nized by the DLL all possible intermediate frequencies may not be guaranteed An application should use the next smaller JEDEC standard tCK AVG value 3 0 2 5 1 875 1 5 or 1 25 ns when calculat ing CL nCK tAA ns tCK AVG ns rounding up to the next Supported CL where tCK AVG 3 0 ns should only be used for CL 5 calculation tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED 4 Reserved settings are not allowed User must program a different value Optional settings allow certain devices in the industry to support this setting however it is not a man datory feature Refer to DIMM data sheet and or the DIMM SPD information if and how this setting is supported Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1600 speed bin also supports functional operation at lower frequencies
43. logy diagram 2 Hes A ae E dre 4 ODTO ODT SDRAMs D0 D8 4 Refer to Section 3 1 of this document for s Scd gt ODTi ODT SDRAMs D9 D17 details on address mirroring CKEO gt CKE SDRAMs D0 D8 CKO CK SDRAMs D0 D8 5 For each DRAM a unique ZQ resistor is CKE1 CKE SDRAMs D9 D17 CK0 gt CK SDRAMs D0 D8 connected to ground The ZQ resistor is RAS ______ RAS SDRAMs D0 D17 Cki gt CK SDRAMs D9 D17 2400hm 1 CAS CAS SDRAMs D0 D17 CKi gt CK SDRAMs D9 D17 6 One SPD exists per module WE WE SDRAMs D0 D17 RESET RESET SDRAMs DO D17 Rev 1 1 Jul 2013 12 SK yi Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss 04V 18V V 1 3 VDDQ Woltage on VDDQ pin relative to Vss 0 4V 1 8V V 1 3 Vin Vout Voltage on any pin relative to Vss 0 4V 1 8 V V 1 Tstg Storage Temperature 55 to 100 oC 1 2 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may
44. mn address AP is used to invoke autopre charge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BA1 BA2 defines the bank to be pre charged If AP is low autoprecharge is disabled During a Precharge com mand cycle AP is used in conjunction with BAO BA1 BA2 to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BA1 or BA2 If AP is low BAO BA1 and BA2 are used to define which bank to precharge A12 BC is sampled during READ and WRITE commands to determine if burst chop on the fly will be per formed HIGH no burst chop LOW burst chopped DQ0 DQ63 CB0 CB7 SSTL Data and Check Bit Input Output pins DMO DM8 SSTL Active High DM is an input mask signal for write data Input data is masked when DM is sampled High coincident with that input data during a write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loading VDD VSS Supply Power and ground for the DDR3 SDRAM input buffers and core logic VDD and VDDQ pins are tied to VbD VDDQ planes on these modules Rev 1 1 Jul 2013 SK yi Symbol Type Polarity Function DQSO0 DQS8 Differential DQS0 DOS8 SSTL DESDE Data strobe for input and output data SA0 SA2 u These signals are tied at the system planar to either Vss or V
45. nctional Block Diagram 2GB 256Mx72 Module 1Rank of x8 Dac SO T DQSO DQS4 DQSO boss DMO DM4 DM CS DQS DQS ore b CS DQs DQs DQO 4ILO0 xi WHO no ego on DQ2 W4 1 02 ec Ww ic 3 DQ35 W 1 0 3 DQ4 W lO4 DQ36 W4 1 0 4 DOS W I o5 DQ37 W4 1 0 5 DQ6 1 0 6 ZQ DQ38 W 1 0 6 ZQ mm DQ7 Ww IO7 L DQS5 DQ39 W 1 0 7 DQS1 DOS5 Dar DM5 DMI 71 pL ERN al d 2n CS DQS DQS mee as M CS DQs DOS DQ 1 00 DQ9 wW 1 0 Di DQ41 W4 1 0 1 D5 DQ10 W4 1 0 2 DQ42 W4 1 0 2 DQii I O3 DQ43 1 0 3 bas wios bows WYO 5 DQi3 Yos BOIS Ww UD 6 ZQ DQ46 W41 0 6 ZQ i DQ15 W1 0 7 as DQS6 DQ47 WI1 0 7 DOSZ DQS6 DQS2 DM 34 DM6 cese exin M DM CS DQs DQS DM CS DQS DQS DQ48 W 1 0 0 me el s i D2 DQ49 W 1 0 1 D6 DQ18 W4 1 0 2 cade wT io 5 DQ19 W41 0 3 oa Ww te s een ms e DQ53 w I O 5 DQ22 W I O 6 ZQ 4 DQ54 W4 1 0 6 ZQ DQS3 DQ23 W 4 1 07 DQS7 DQ55 W4 1 07 DOS3 ed DM3 mN L DM CS DQS DOS Ns ub CS DQs DQS DQ24 w I O 0 v DQ25 Wj1 0 1 D3 DQ57 W 1 0 1 D7 DQ26 W 1 0 2 DQ58 W 1 0 2 DQ27 W I O 3 DQ59 W1 0 3 pees wios beet WYO 5 DQ29 B
46. next one according to Table 10 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different address ing wee Table 10 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 10 a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 011B RIT Wr enable set MR2 A 10 9 10B C Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable e Self Refresh Temperature Range SRT set MR2 A7 OB for normal or 1B for extended temperature range f Read Burst Type Nibble Sequential set MRO A 3 0B Rev 1 1 Jul 2013 43 SK yi Table 3 IDDO Measurement Loop Pattern a o I X ERES re Rede Plu PSIG ISIE BS 8 ER 3 3 vay 5 3 o3 flojo z o O lt 0 0 ACT 0 O 1 1 0 0 00 0 0 0 s 1 2 DD 1 04 0 0 0 0 00 0 0 0 3 4 DD 1ji 41 41 i441 0 0 400 0 0 0 m repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 E repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 O 1 1 0 0 00 0 0 F 0 z 1 nRC 1 2 DD 1 0 0 0 0 0 00 0 0 F 0 2 1 nRC 3 4 DD 1 1 1 1 0
47. oad Ul Channel IDDQ IDDQ IO Power Simulation Simulation Simulation X Correction Channel IO Power Number Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev 1 1 Jul 2013 39 De SK hynix Table 1 Timings used for IDD and IDDQ Measurement Loop Patterns DDR3L 1333 DDR3L 1600 Symbol Unit 9 9 9 11 11 11 tx 1 5 1 25 ns CL 9 11 nCK IRCD 9 11 nCK IRC 33 39 nCK IRAS 24 28 nCK Tipp 9 11 nCK 1KB page size 20 24 nCK MEAW 2KB page size 30 32 nCK 1KB page size 4 5 nCK D 2KB page size 5 6 nCK l ggc 512Mb 60 72 nCK Pgrc l Gb 74 88 nCK lgec 2 Gb 107 128 nCK Mec 4 Gb 174 208 nCK Mec 8 Gb 234 280 nCK Table 2 Basic IDD and IDDQ Measurement Conditions Symbol Description Ippo Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 1 BL 89 AL 0 CS High between ACT and PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data IO MID LEVEL DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table 3 Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 3 Joni Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS nRCD CL see Table 1 BL
48. rt corresponding tDS values Table 43 and Table 50 in DDR3L Device Opera tion as well as derating tables Table 46 in DDR3L Device Operation depending on Vih Vil AC levels Single Ended AC and DC Input Levels for DQ and DM DDR3L 800 1066 DDR3L 1333 1600 Symbol Parameter Unit Notes Min Max Min Max VIH DQ DC90 DC input logic high Vref 0 09 VDD Vref 0 09 VDD V 1 VIL DQ DC90 DC input logic low VSS Vref 0 09 VSS Vref 0 09 V 1 VIH DQ AC160 AC input logic high Vref 0 160 Note2 V 1 2 5 VIL DQ AC160 AC input logic low Note2 Vref 0 160 V 11 2 5 VIH DQ AC135 AC Input logic high Vref 0 135 Note2 Vref 0 135 Note2 V 1 2 5 VIL DQ AC135 AC input logic low Note2 Vref 0 135 Note2 Vref 0 135 V 115 2 5 VIH DQ AC130 AC Input logic high V 1 2 5 VIL DQ AC130 AC input logic low V 11 2 5 Vgerba pc REGINE 049 VDD 0 51 VDD 049 VDD 0 51 VDD V 3 4 Notes 1 Vref VrefDQ DC 2 Refer to Overshoot and Undershoot Specifications on page 29 3 The ac peak noise on Vref may not allow Vref to deviate from Vgerpo pc by more than 1 VDD for reference approx 13 5 mV 4 For reference approx VDD 2 13 5 mV 4 For reference approx VDD 2 13 5 mV 5 These levels apply for 1 35 volt table Single Ended AC and DC Input Levels for Command and Address on page 16 operation only If the device is operate
49. s Table below shows the output levels used for measurements of single ended signals Differential AC and DC Output Levels DDR3L 800 1066 Symbol Parameter Unit Notes 1333 and 1600 VoHdiff AC AC differential output high measurement level for output SR 0 2 x Vppo AC differential output low measurement level for output SR 0 2 x VDDQ uS Notes 1 The swing of 0 2 x Vppo is based on approximately 50 of the static differential output high or low swing with a driver impedance of 40 and an effective test load of 252 to Vtr Vppo 2 at each of the differential outputs Rev 1 1 Jul 2013 25 SK six Single Ended Output Slew Rate When the Reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo ac and Vou ac for single ended signals are shown in table and Figure below Single ended Output slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VOL AC VoH AC Vouacy VoL ac l DeltaTRse Single ended output slew rate for falling edge VoH AC VoL AC Vouacy VoL ac l DeltaTFse Notes 1 Output slew rate is verified by design and characterisation and may not be subject to production test Single Ended Output Voltage l e DQ Delta TFse Vir Voto Single Ended Output slew Rate Definition Output Slew Rate single ended Vou
50. se VIH VIL ac of AADD CMD and VREFCA for DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs and VREFDQ if a reduced ac high or ac low levels is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to on page 28 Allowed time before ringback tDVAC for CK CK and DQS DQS DDR3L 800 1066 1333 1600 uS vuan aa a 320mV MENS ave 270mV min max min max 24 0 189 201 4 0 189 201 3 0 162 179 2 0 109 134 1 8 91 119 1 6 69 100 1 4 40 76 1 2 note 44 1 0 note note 1 0 note note note Rising input signal shall become equal to or greater than VIH ac level and Falling input signal shall become equal to or less than VIL ac level Rev 1 1 Jul 2013 20 SK yi Single ended requirements for differential signals Each individual component of a differential signal CK DQS DQSL DQSU CK DQS DQSL of DQSU also has to comply with certain requirements for single ended signals CK and CK have to approximately reach VSEHmin VSELmax approximately equal to the ac levels VIH ac VIL ac for ADD CMD signals in every half cycle DQS DQSL DQSU DQS
51. ter System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment Manufacturers correlate to their production test conditions generally one or more coaxial transmission lines terminated at the tester electronics VDDQ 25 Ohm DQ VIT 2 DUT VDDQ DQS Reference Load for AC Timing and Output Slew Rate Rev 1 1 Jul 2013 28 SK yi Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Address and Control Pins DDRS3L DDR3L DDR3L DDR3L Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 67 0 5 0 4 0 33 V ns Maximum undershoot area below VSS See Figure below 0 67 0 5 0 4 0 33 V ns A0 A15 BAO BA3 CS RAS CAS WE CKE ODT See figure below for each parameter definition Maximum Amplitude Overshoot Area VDD Volts yss Undershoot Area Maximum Amplitude Time ns Address and Control Overshoot and Undershoot Definition Rev 1 1 Jul 2013 29 SK yi Clock Data Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Clock Data Strobe and
52. to tan 825b 20 s ACT to internal read or write trc 13 75 u us delay time 13 125 9 PRE command period trp a ae ns ACT to ACT or REF command i 48 75 E period 48 125 9 ACT to PRE command period ikas 35 9 tREFI ns CWL 5 ck AvG 2 5 3 3 ns 1 2 3 8 CL 6 CWL 6 AVG Reserved ns 1 2 3 4 8 CWL 7 Ick AvG Reserved ns 4 CWL 2 5 fK AVG Reserved ns 4 1 875 lt 2 5 d 27 CWL 6 Ick AvG Optional ns 1 2 3 4 8 CWL 7 CK AVG Reserved ns 1 2 3 4 8 CWL 8 CK AVG Reserved ns 4 CWL 5 IcK AVG Reserved ns 4 TRES CWL 6 ECK AVG 1 875 lt 2 5 ns 1 2 3 8 CWL 7 CK AVG Reserved ns 1 2 3 4 8 CWL 8 Ick AvG Reserved ns 1 2 3 4 CWL 5 6 AVG Reserved ns 4 1 5 lt 1 875 CL 9 CWL 7 amp K AVG ns 1 2 3 4 8 Optional gt CWL 8 CK AVG Reserved ns 1 2 3 4 CWL 5 6 CK AVG Reserved ns 4 CL 10 CWL 7 CK AVG 1 5 1 875 ns 1 2 3 7 CWL 8 ck AvG Reserved ns 1 2 3 4 CL 11 CWL 5 6 7 ck avG Reserved ns 4 CWL 8 ICK AVG 1 25 1 5 ns 1 2 3 Supported CL Settings 6 7 8 9 10 11 Fick Supported CWL Settings 5 6 7 8 lick Rev 1 1 Jul 2013 35 De SK hynix Speed Bin Table Notes Absolute Specification Toper VDDQ Vpp 1 35V 0 100 0 067 V 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When mak ing a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as require ments from CWL sett
53. xpousure to absolute maximum rating conditions for extended periods may affect reliablility 2 Up to 9850 ft 3 The designer must meet the case temperature specifications for individual module components Rev 1 1 Jul 2013 37 SK yi IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter IDD and IDDQ measurement conditions such as test load and patterns are defined Figure below Measurement Setup and Test Load for IDD and IDDQ optional Measurements shows the setup and test load for IDD and IDDQ measurements e IDD currents such as IDDO IDD1 IDD2N IDD2NT IDD2PO IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET and IDD7 are measured as time averaged currents with all VDD balls of the DDR3L SDRAM under test tied together Any IDDQ current is not included in IDD currents e IDDQ currents such as IDDQ2NT and IDDQ4R are measured as time averaged currents with all VDDQ balls of the DDR3L SDRAM under test tied together Any IDD current is not included in IDDQ currents Attention IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM They can be used to support correlation of simulated IO power to actual IO power as outlined in the Figure below Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ ar
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