Hynix HMT325U7CFR8C-PBT0 memory module
Contents
1. Front 2 1030 15 Min 1 45 gt pe Max RO 70 308 wig l 4x3 00 0 10 1730 DETAIL A DETAIL B 2x2 50 0 10 i t 9 50 2x2 i Qj ner 47 00 gt 71 00 4 128 95 Pi 133 35 Back O U O Side Detail A Detail B 2 50 FULL R 3 64mm Max 0 80 0 05 qe EN h gt m mu 2 50 0 20 8 3 SIG m E E 1 00 t E 0 3 1 0 1 2720 10 Ke gt 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 2 Jul 2013 Units millimeters 572. 4GB 512Mx72 Module 2Rank of x8 E S0 SI DQSO DQS4 i DQSO DOS4 DMO 1 4 1 DM CS DQS DQS DM CSDQS DAS DM CS DQS DQS DM CSDQS DQS peo w I O0 Jo 0 DQ32 W1 0 0 1 00 DQi W IO1 DO JO 1 D9 DQ33 W I O 1 D4 1 0 1 D13 DQ2 W I O2 Jo 2 DQ34 M1 0 2 1 0 2 DQ3 wW 1 03 1 03 DQ35 W1 0 3 1 0 3 DQ4 W IO4 I4 DQ36 W1 0 4 1 0 4 DQ5 W I O5 1 05 DQ37 W1 0 5 IO 5 DQ6 M1 0 6 1 06 Zo DQ38 W1 0 6 1 06 DQ7 W1l 07 Z yo DQ39 W 1 0 7 1 07 ZQ DQS1 DOS5 2971 I DQS1 DQS5 DM1 1 DM5 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ8 W I O0 1 00 DQ40 W1 0 0 1 0 0 DQ9 W1 O0 1 Di I O1 D10 DQ41 AI O 1 D5 yo D14 DQ10 Ww1 02 1 02 DQ42 W11 0 2 1 02 DQii W41 0 3 103 DQ43 W 1 0 3 1 03 DQ12 W1 0 4 1 04 DQ44 W1 0 4 04 DQ13 W41 0 5 1 05 ZQ DQ45 W1 0 5 1 05 DQ14 W1 0 6 1 06 DQ46 W 1 0 6 1 06 DQ15 A I O 7 ZQHF 1 07 DQS6 DQ47 W 1 0 7 zQ 1 07 Z DQS2 DQS6 7 DQS2 Q DM2 1 DM6 1 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ16 W1 00 yoo DQ48 W 1 0 0 IO 0 DQ17 W1 0 1 D2 yo D11 DQ49 M1 0 1 D6 IO 1 D15 DQ18 W1 0 2 1 02 DQ50 W 1 0 2 Jo 2 DQ19 W 103 1 03 DQ51 W 1 0 3 1 03 DQ20
3. a o I X ERES re Rede Bluld 32 PSIG ISIE 5 8 ER 3 va 5 3 G GT 8 lg GT TA x o O lt 0 0 ACT 0 O 1 1 0 0 00 0 0 0 s 1 2 DD 1 04 0 0 0 0 00 0 0 0 3 4 DD 1ji 41 41 i441 0 0 400 0 0 0 m repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 E repeat pattern 1 4 until nRC 1 truncate if necessary 1 NRC 0 ACT 010 1 1 0 0 00 0 0 F 0 z 1 NRC 1 2 DD 1i 0 0 0 0 0 00 0 0 F 0 2 1 nRC 3 4 DD 1 1 1 1 0 0 000 0 F 0 2 9 m repeat pattern 1 4 until 1 nRC nRAS 1 truncate if necessary BIB 1 mRC nRAS PRE 0 0 1 0 0 0 00 ojlo Flo n repeat pattern 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 2 Jul 2013 46 SK yi Table 4 IDD1 Measurement Loop Pattern
4. a en E m m x o o9 o e vi m mM pon 8 i i Felde BS s om 3 3 03 5 oa FT Ta 0 10 WR 0 1 0 0 1 0 00 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 z 2 3 DD 1 1 1 11 0 00 0 olo o 4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011 5 D 1 0 0 0 1 0 00 0 0 F 0 g 2 6 7 D D 1 1 1 1 1 0100 0 0 F 0 9 9 1 8 15 repeat Sub Loop 0 but BA 2 0 1 2 5 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 124 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 140 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to WR Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Write Command Outside burst operation DQ signals are MID LEVEL Rev 1 2 Jul 2013 49 SK yi Table 9 IDD5B Measurement Loop Pattern a D E cw l lea Sel mala Bly I Sf Em 18 8 IEE 3 8 amp vs see eB VE TJI IX 7 Oo lt 0 0 REF 0 0 0 1 0 0 0 0 0 0 1 12 D D 1 0 0 0 0 0100 0 0 0 3 4 DD 1 1 1 1 00 000 0O F 5 8 repeat cycles 1 4 but BA 2 0 1 2 5 9 12 repeat cycles 1 4 but BA 2 0 2 2 9 13 16 repeat cycles 1 4 but BA 2 0 2 3 2 amp 17 20 repeat cycles 1 4 but BA 2 0 4 21 2
5. a D D ad emma 5 83 e Plel2isie B BR 8E om 5 7 3 G F z o g 2 TT lt 7 Oo lt 0 0 ACT 0 0 1 1 0 00 0 O 0 0 1 2 DD 1 0 0 0 0 00 00 0 0 3 4 DD1 1 1 i 0 00 01010101 repeat pattern 1 4 until nRCD 1 truncate if necessary nRCD RD 0 1 0 1 0 0 00 0 O 0 0 00000000 us repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 010 0 0 dr repeat pattern 1 4 until NRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 0 0 F 0 s 1 NRC 1 2 D D 1 0 0 0 0 0 00 010 F 0 2 amp 1 nRC 3 4 DD 1 1 1 1 0 0 0 0 0 F 0 a 9 eh repeat pattern nRC 1 4 until nRC nRCE 1 truncate if necessary 2 g 1 nRC nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011 ve repeat pattern NRC 1 4 until NRC nRAS 1 truncate if necessary 1 nRC nRAS PRE 0 0 1 0 0 0 00 0 O F 0 p repeat pattern nRC 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by
6. Input Output Functional Descriptions Symbol Type Polarity Function CKO CK1 CKO CK1 CKEO CKE1 SSTL SSTL Differential crossing Active High CK and CK are differential clock inputs All the DDR3 SDRAM addr cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK Output read data is reference to the crossing of CK and CK Both directions of crossing Activates the SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode S0 S1 SSTL Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high When the command decoder is dis abled new commands are ignored but previous operations continue This signal provides for external rank selection on systems with multiple ranks RAS CAS WE ODTO ODT1 SSTL SSTL Active Low Active High RAS CAS and WE ALONG WITH S define the command being entered When high termination resistance is enabled for all DQ DQS DQS and DM pins assuming this function is enabled in the Mode Register 1 MR1 VREFDQ Supply Reference voltage for SSTL15 I O inputs VREFCA Supply Reference voltage for SSTL 15 command address inputs VDDQ Supply Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity For all current DDR3 u
7. TE BD Be Ee er 1 DQ to I O wiring is shown as recom A0 A15 A0 A15 SDRAMs D0 DI5 SDA mended but may be changed mE TS CEE SDRAM PEDIS 0 AI A2 2 DQ DQS DQS ODT DM CKE S relation CKEO gt CKE SDRAMs D0 D7 ships must be maintained as shown RAS gt RAS SDRAMs D0 D15 SAO SAL SA2 3 DQ DM DQS DQS resistors Refer to CAS gt CAS SDRAMs D0 D15 VDDSPD SPD associated topology diagram WE gt W SDRAMsDO DIS vo v po popis Refer to Section 3 1 of this document for ODTO ODT SDRAMs D0 D7 details on address mirroring ODT ODT SDRAMs D8 DI5 VREFDQ p0 DI5 5 For each DRAM a unique ZQ resistor is CKO CK SDRAMs D0 D7 Vss D0 DI5 connected to ground The ZQ resistor is CKO CK SDRAMs D0 D7 2400hm 1 CKI CK SDRAMs D8 D15 VREFCA po pis 6 One SPD exists per module CKI CK SDRAMs D8 D15 RESET RESET SDRAMs D0 D3 Rev 1 2 Jul 2013 13 SK yi
8. Vref 0 135 Note2 V 1 2 7 VIL CA AC135 AC input logic low Note2 Vref 0 135 V 1 2 8 VIH CA AC125 AC Input logic high Vref 0 125 Note2 mV 1 2 7 VIL CA AC125 AC input logic low Note2 Vref 0 125 mV 1 2 8 Vesna Ton CME 049 VDD 0 51 VDD 0 49 VDD 0 51 VDD V 3 4 Notes 1 For input only pins except RESET Vref VrefCA DC 2 Refer to Overshoot and Undershoot Specifications on page 30 3 The ac peak noise on Vref may not allow Vref to deviate from VgercA pc by more than 1 VDD for refer ence approx 15 mV 4 For reference approx VDD 2 15 mV 5 VIH dc is used as a simplified symbol for VIH CA DC100 6 VIL dc is used as a simplified symbol for VIL CA DC100 7 VIH ac is used as simplified symbol for VIH CA AC175 VIH CA AC150 VIH CA AC135 and VIH CA AC125 VIH CA AC175 value is used when Vref 0 175V is referenced VIH CA AC150 value is used when Vref 0 150V is referenced VIH CA AC135 value is used when Vref 0 135V is referenced and VIH CA AC125 value is used when Vref 0 125V is referenced VIL ac is used as simplified symbol for VIL CA AC175 VIL CA AC150 VIL CA AC135 and VIL CA AC125 VIL CA AC175 value is used when Vref 0 175V is referenced VIL CA AC150 value is used when Vref 0 150V is referenced VIL CA AC135 value is used when Vref 0 135V is referenced and VIL CA AC125 value is used when Vref 0 125V is referenced Rev 1 2 Jul 2013
9. 1 2 Jul 2013 29 SK yi Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Address and Control Pins DDR3 DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 1866 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 67 0 5 0 4 0 33 0 28 V ns Maximum undershoot area below VSS See Figure below 0 67 0 5 0 4 0 33 0 28 V ns A0 A15 BAO BA3 CS RAS CAS WE CKE ODT See figure below for each parameter definition Maximum Amplitude Overshoot Area VDD Volts yss Undershoot Area Maximum Amplitude Time ns Address and Control Overshoot and Undershoot Definition Rev 1 2 Jul 2013 30 SK yi Clock Data Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Clock Data Strobe and Mask DDR3 DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 1866 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 04 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum overshoot area above V
10. 3 8 C26 CWL 6 lck AVG Reserved ns 1 2 3 4 8 CWL 7 fCK AVG Reserved ns 4 CWL 5 CK AVG Reserved ns 4 CWL 6 amp xave idis lois ns 1 2 3 4 8 UL Optional gt 10 CWL 7 ICK AVG Reserved ns 1 2 3 4 8 CWL 8 amp xave Reserved ns 4 CWL 5 fCK AVG Reserved ns 4 Ces CWL 6 ECK AVG 1 875 lt 2 5 ns 1 2 3 8 CWL 7 fCK AVG Reserved ns 1 2 3 4 8 CWL 8 CK AVG Reserved ns 1 2 3 4 CWL 5 6 amp xcave Reserved ns 4 1 5 lt 1 875 CL 9 CWL 7 lck AVG ns 1 2 3 4 8 Optional gt 10 CWL 8 amp xave Reserved ns 1 2 3 4 CWL 5 6 amp xkave Reserved ns 4 CL 10 CWL 7 Ick AVG 1 5 1 875 ns 1 2 3 8 CWL 8 ck AvG Reserved ns 1 2 3 4 cL 11 CWL 5 6 7 amp k ave Reserved ns 4 CWL 8 ICK AVG 1 25 lt 1 5 ns 1 2 3 Supported CL Settings 5 6 7 8 9 10 11 NCK Supported CWL Settings 5 6 7 8 NK Rev 1 2 Jul 2013 36 De SK hynix DDR3 1866 Speed Bins For specific Notes See Speed Bin Table Notes on page 38 Speed Bin DDR3 1866M CL nRCD nRP 13 13 13 DIE more Parameter Symbol min max Internal read command m 13 91 20 n to first data 13 125 9 ACT to internal read O ko 13 91 i a write delay time 13 125 9 PRE command period trp m ns N ne ras 34 9 tREFI ns ACT to ACT or PRE lc 47 91 e command period 47 125 CWL 5 ICK AVG 2 5 3 3 ns 1 2 3 9 6
11. Vrer t Vref ac noise VRef DC max VDD 2 VRef DC min Illustration of Vgerpc tolerance and Vref ac noise limits The voltage levels for setup and hold time measurements Vyy acy Vra pc Vr acy and Vr pc are depen dent on Vger Vref shall be understood as Vgerpc as defined in figure above This clarifies that dc variations of Vper affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for Vgerpc deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with Vgcrac noise Timing and voltage effects due to ac noise on Vg up to the speci fied limit 1 of VDD are included in DRAM timings and their associated deratings Rev 1 2 Jul 2013 19 SK yi AC and DC Logic Input Levels for Differential Signals Differential signal definition VILDIFFACMIN o cree e Be es ee een EEE hg VILDFEMN MERC MGE LEE RECEN UNDER half cycle Mo SIM demde eem dEA Differential Input Voltage i e DQS DQS CK CK VILBIFEACMAK EE EEE EET 4 tpvac Definition of differential ac swing and time above ac level tpyac Rev 1 2 Jul 2013 20 SK yi Differential swing requirements for clock CK CK
12. W1 0 4 1 04 DQ52 W1 0 4 1 0 4 DQ21 w 1I O 5 105 DQ53 W1 0 5 1 05 DQ22 M1 0 6 1 06 zQA DQ54 W1 0 6 1 06 DQ23 wv 1 07 205 V07 DQ55 W1 0 7 za 07 ZAF D S3 D S7 ni DOS3 bees DM3 DM7 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ24 W1 0 0 IO 0 DQ56 MW1 0 0 yoo DQ25 v 1 0 1 D3 IO 1 D12 DQ57 w I O 1 D7 IO 1 D16 DQ26 wI O 2 1 02 DQ58 WI O 2 Uo 2 DQ27 w 1 03 1 03 DQ59 M1 0 3 Io 3 DQ28 W 1 0 4 1 04 DQ60 W 1 0 4 1 04 DQ29 W11 0 5 1 05 DQ61 W1 0 5 1 05 DQ30 W41 0 6 1 06 DQ62 W1 0 6 IO 6 za DQ31 m1 07 29 1 07 zQ DQ63 w 1 07 zQ 1 07 an DQS8 VDDSPD SPD DQS8 ij SPD TS integrated VDD VDDQ _ D0 D17 DM8 er 11 gt VREFDQ D0 D17 DM CS DQS DQS DM CSDQS DQS EVENT gt SDA CB0 W1 00 1 00 EVENT A0 Al A2 Vss 4 4 4 po pi7 CBE NUT p8 Vor pi7 I I 1 VREFCA F D0 D17 82 w 102 1 02 vo S sp CB3 W1 0 3 1 03 Notes CB4 W yO4 1 04 1 DQ to I O wiring is shown as recom CB5 w 1I 0 5 1 05 mended but may be changed CB6 W1 0 6 1 06 2 DQ DQS DQS ODT DM CKE S relation CB7 wW1 07 zQ 107 zQ ships must be maintained as shown 3 DO CB DM DOS DOS resistors Refer to El gt BA2 E associated topology diagram 2 Hes A ae E dre 4 ODTO ODT SDRAMs D0 D8 4 Refer to Section 3 1 of this document for s EN gt ODTi ODT SDRAMs D9 D17 details on address mirroring CKEO gt CKE SDRAMs D0 D8 CKO
13. 1 In two cases a maximum slew rate of 6V ns applies for a single DQ signal within a byte lane Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane are static i e they stay at either high or low Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane switching into the opposite direction i e from low to high of high to low respectively For the remaining DQ signal switching in to the opposite direction the regular maximum limite of 5 V ns applies Rev 1 2 Jul 2013 27 SK yi Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between VOLdiff AC and VOHdiff AC for differential signals as shown in table and figure below Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VoL diff AC Vonadit AC Vouaitt acy VoLditt ac DeltaTRdi Differential output slew rate for falling edge Voudiff AC VoLaiff ac Vouditt acy Votaitt acyl DeltaTFdiff Notes 1 Output slew rate is verified by design and characterization and may not be s
14. 17 De SK hynix AC and DC Input Levels for Single Ended Signals DDR3 SDRAM will support two Vih Vil AC levels for DDR3 800 and DDR3 1066 as specified in the table below DDR3 SDRAM will also support corresponding tDS values Table 43 and Table 51 in DDR3 Device Operation as well as derating tables in Table 46 of DDR3 Device Operation depending on Vih Vil AC lev els Single Ended AC and DC Input Levels for DQ and DM DDR3 800 1066 DDR3 1333 1600 DDR3 1866 Symbol Parameter Unit Notes Min Max Min Max Min Max VIH DQ DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD ref 0 100 VDD V 1 5 VIL DQ DC100 DC input logic low VSS Vref 0 100 VSS l Vref 0 100 VSS Vref 0 100 V 1 6 VIH DQ AC175 AC input logic high Vref 0 175 Note2 V 1 2 7 VIL DQ AC175 AC input logic low Note2 Vref 0 175 V 11 2 8 VIH DQ AC150 AC Input logic high Vref 0 150 Note2 Vref 0 150 Note2 Vref 0 150 Note2 V 1 27 VIL DQ AC150 AC input logic low Note2 Vref 0 150 Note2 Vref 0 150 Note2 Vref 0 150 V 11 2 8 VIH CA AC135 AC input logic high Vref 0 135 Note2 mV 1 2 7 VIL CA AC135 AC input logic low Note2 Vref 0 135 mV 1 2 8 Vnerba c DG one 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD 0 49 VDD O 51 VDD V 3 4 Notes 1 Vref VrefDQ DC approx 15 mV For reference approx VDD 2 15 mV
15. Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Rev 1 2 Jul 2013 44 SK yi Symbol Description Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD NRRD nFAW CL see Table 1 BL 890 AL CL 1 CS High between ACT and RDA Command Address Bank Address Inputs partially toggling according to Table Ipp7 10 Data IO read data burst with different data between one burst and the next one according to Table 10 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different address ing wee Table 10 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 10 a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 011B RIT Wr enable set MR2 A 10 9 10B C Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable e Self Refresh Temperature Range SRT set MR2 A7 OB for normal or 1B for extended temperature range f Read Burst Type Nibble Sequential set MRO A 3 0B Rev 1 2 Jul 2013 45 SK yi Table 3 IDDO Measurement Loop Pattern
16. DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and or the DIMM SPD for tFEFI requirements in the Extended Temperature Range Rev 1 2 Jul 2013 15 SK yi AC amp DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Rating Symbol Parameter Units Notes Min Typ Max VDD Supply Voltage 1 425 1 500 1 575 1 2 Notes 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Rev 1 2 Jul 2013 16 SK yi AC amp DC Input Measurement Levels AC and DC Logic Input Levels for Single Ended Signals AC and DC Input Levels for Single Ended Command and Address Signals Single Ended AC and DC Input Levels for Command and ADDress DDR3 800 1066 1333 1600 DDR3 1866 Symbol Parameter Unit Notes Min Max Min Max VIH CA DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD V 1 5 VIL CA DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 V 1 6 VIH CA AC175 AC input logic high Vref 0 175 Note2 V 1 2 7 VIL CA AC175 AC input logic low Note2 Vref 0 175 V 1 2 8 VIH CA AC150 AC Input logic high Vref 0 150 Note2 V 1 2 7 VIL CA AC150 AC input logic low Note2 Vref 0 150 V 1 2 8 VIH CA AC135 AC input logic high
17. DQ35 W41 0 3 103 DQ4 WHI 04 104 DQ36 W41 0 4 104 DQ5 W V O5 I O 5 DQ37 MO 5 UO 5 DQ6 WHI 06 VO 6 zQ DQ38 W41 0 6 VO 6 DQ7 W1 O7 zQ UO 7 DQ39 W1 O0 7 zo UO 7 ZQ DQSI i DQS5 dil L DQS1 DQS5 DMI DM5 t DM CSDQS DQS DM CS DQS DQS DM CS DOS DQS EX CS Dos DOS DQ8 W 41 00 1 00 DQ40 W 1 00 mm Do W IO I DI JO I D9 DQ41 W 1 0 1 D5 101 D13 DQ10 W11 0 2 1 02 DQ42 zl 1 02 2 DQll W4 1 03 1 03 DQ43 103 Ms DQI2 W404 104 DQ44 E vo 1 da DQI3 W U O 5 105 zQ DQ45 mu v65 DQl4 MW 1 06 106 L me 1o 5 106 zd DQI5 W1 07 ZQ F507 z ui DQS2 Done 8 DQS2 DM2 DM DM CSDQS DQS DM CS DQS DOS PM TS DQS DQS NX CS DOS DOS D UO 0 DQ16 W41 00 JO 0 DQI7 W UO I UO I DQ49 W41 0 I D6 101 D14 DOI8 W1 0 2 p2 102 D10 DQ50 W4 1 0 2 yo2 DQI9 W 41 0 3 1 03 DQ51 W4 1 0 3 103 2 W410 4 104 RM e p Don W 1 0 5 VO 5 t c ARS ZQ DQ54 W11 0 6 106 DQ2 W UO 6 106 wtyo7 UO 7 zQ Lm DQ23 W 1 07 zQ 107 DQ55 20 IL DQS3 2071 DQS7 l ag DQS7 DM3 I DM7 t DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DQ24 W qvO0 100 DQ56 W VO 0 JO 0 DQ25 W YO1 D3 VO I Du DQ57 W410 I D7 101 Di5 DQ26 W1 0 2 1 02 DQ58 W 1 0 2 102 DQ27 W 1 03 103 DQ59 103 103 DQ28 W 1 0 4 O4 DQ60 W1 0 4 104 DQ29 MW 105 I O 5 DQ61 W1 0 5 Os DQ30 W1 0 6 106 20 DQ62 W4 1 0 6 UO 6 DQ31 WMH 07 107 d DQ63 WW 1 0 7 VO 7 z0 Zor el ZQ Qi dad Serial PD Notes i gt E
18. Input Slew Rate Definition for DQS DQS and CK CK Rev 1 2 Jul 2013 25 SK nix AC amp DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Single ended AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 VoH DC DC output high measurement level for IV curve linearity 0 8 x VDDQ V VoM DO DC output mid measurement level for IV curve linearity 0 5 X VDDQ V VoL DC DC output low measurement level for IV curve linearity 0 2 x Vppo V VoH AC AC output high measurement level for output SR Vrr 0 1 x Vppo V 1 VoL ac AC output low measurement level for output SR Vrr 0 1 x Vppo V 1 Notes 1 The swing of 0 1 x Vppq is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 402 and an effective test load of 259 to Vtr Vppo 2 Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Differential AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 Vokdiff AC AC differential output high measurement level for output SR 0 2 x Vppo AC differential output low measurement level for output SR 0 2 x VDDQ uS Notes 1 The swing of 0 2 x Vppo is based on approximately 50 of the static differe
19. Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 2 Jul 2013 47 SK yi Table 5 IDD2N and IDD3N Measurement Loop Pattern a o I Sls ea m m m ie 3 82 Ele iig i BS ERR oah 6 3 Og E k oO g g z lt 7 Oo lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 1 1 1 0 0 0 00 F 0 3 D 1 1 1 1 0 0 0 00 F 0 m 5 1 4 7 repeat Sub Loop 0 use BA 2 0 1 instead 9 2 2 8 11 repeat Sub Loop 0 use BA 2 0 2 instead 2 amp 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat Sub Loop 0 use BA 2 0 6 instead 7 28 31 repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Table 6 IDD2NT and IDDQ2NT Measurement Loop Pattern x 9 D g t o da REM s 8 i H Pel 2 g g om o E 8 am lt lt lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 z 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 1 1 1 0 0 80 0 0 F 0 3 D 1 1 1 1 0 0 0 0 0 F oOo D 5 1 4 7 repeat Sub Loop 0 but ODT 0 and BA 2 0 1 2 9 2 8 11 repeat Sub Loop 0 but ODT 1 and BA 2 0 2 2 EZ 3 12 15 repeat Sub Loop 0 but ODT 1
20. a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 30 Rev 1 2 Jul 2013 23 SK nix Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the requirements in table below The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS VDD ymmo mm CK DQS v Vix SSS a NEU oed M E VDD 2 Vix ea d CK DQS VSEH VSEL VSS Vix Definition Cross point voltage for differential input signals CK DQS DDR3 800 1066 1333 1600 1866 Parameter Unit Notes Min Max Vi CK Differential Input Cross Point Voltage 150 150 mV 2 EK relative to VDD 2 for CK CK 175 175 mv 1 Differential Input Cross Point Voltage i Vix DQS relative to VDD 2 for Das Das 130 ne No4tes 1 Extended range for Vy is only allowed for clo
21. and strobe DQS DQS Differential AC and DC Input Levels DDR3 800 1066 1333 1600 amp 1866 Symbol Parameter Wi Unit Notes in ax ViHaitt Differential input high 0 180 Note 3 V 1 Vii dirt Differential input logic low Note 3 0 180 V 1 VIHdiff ac Differential input high ac 2 x VIH ac Vref Note 3 V 2 Vit diff ac Differential input low ac Note 3 2 x VIL ac Vref V 2 Notes 1 Used to define a differential signal slew rate 2 For CK CK use VIH VIL ac of AADD CMD and VREFCA for DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs and VREFDQ if a reduced ac high or ac low levels is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 30 Allowed time before ringback tDVAC for CK CK and DQS DQS DDR3 800 1066 1333 1600 DDR3 1866 tDVAC ps Slew tDVAC ps tDVAC ps VIH Ldiff ac tDVAC ps tDVAC ps Rate VIH Ldiff ac VIH Ldiff ac 270mV VIH Ldiff ac VIH Ldiff ac V ns 350mV 300mV DQS DQS only 300mV z CK CK only Optional min max min ma
22. e a a a a e VDD 2 or VDDQ 2 Sete otis eee ee cee eee t CK or DQS VSELmax A t f VSEL VSS of VSSQ 2 ee see Lese see eat at See Se ae kr ee time Single ended requirements for differential signals Note that while ADD CMD and DQ signal requirements are with respect to Vref the single ended compo nents of differential signals have a requirement with respect to VDD 2 this is nominally the same the transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Rev 1 2 Jul 2013 22 SK yi Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU DDR3 800 1066 1333 1600 amp 1866 Parameter Unit Notes Min Max VSEH Single ended high level for strobes VDD 2 0 175 Note 3 V 1 2 Single ended high level for Ck CK VDD 2 0 175 Note 3 V 1 2 VSEL Single ended low level for strobes Note 3 VDD 2 0 175 V 1 2 Single ended low level for CK CK Note 3 VDD 2 0 175 V 1 2 Notes 1 For CK CK use VIH VIL ac of ADD CMD for strobes DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs 2 VIH ac VIL ac for DQs is based on VREFDQ VIH ac VIL ac for ADD CMD is based on VREFCA if
23. input buffers and core logic VDD and VDDQ pins are tied to VDD VDDQ planes on these modules Rev 1 2 Jul 2013 SK yi Symbol Type Polarity Function DQSO0 DQS8 Differential DQS0 DOS8 SSTL Data strobe for input and output data SA0 SA2 u These signals are tied at the system planar to either Vss or VDDSPD to con figure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into or out of the SPD SDA EEPROM An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board This signal is used to clock data into and out of the SPD EEPROM An SCL external resistor may be connected from the SCL bus time to VDDspPD to act as a pullup on the system board Suppl Power supply for SPD EEPROM This supply is separate from the Vbb VbDQ PPY power plane EEPROM supply is operable from 3 0V to 3 6V Rev 1 2 Jul 2013 SK yi Pin Assignments Front Side left 1 60 Back Side right 121 180 Front Side left 61 120 Back Side right 181 240 Pin x64 x72 Pin x64 x72 Pin x64 x72 Pin x64 x72 Non ECC ECC Non ECC ECC Non ECC ECC Non ECC ECC 1 VREFDQ VREFDQ 121 Vss Vss 61 A2 A2 181 Al Al 2 Vss Vss 122 DQ4 DQ4 62 VDD VDD 182 VDD VDD 3 DQO DQO 1123 DQ5 DQ5 63 CK1 CK1 183 VDD VDD 4 DQ1 DQ1 1124 Vss Vss 64 CK1 CK1 184 C
24. 3 RE se tie DQ29 DQ30 W1 0 6 ZQ E DQ62 W1 0 6 ZQ LL DQ31 w1 0 7 DQ63 W 1 0 7 Serial PD Notes otes SCL spa 1 DQ to 1 0 wiring is shown as recom WP E mended but may be changed GE 2 DQ DQS DQS ODT DM CKE S relation BAO BA2 p BAO BA2 SDRAMs D0 D7 sho di ub ships must be maintained as shown A0 A15 A0 A15 SDRAMs D0 D7 3 DQ DM DQS DQS resistors Refer to Le associated topology diagram RAS gt RAS SDRAMS DO D7 4 Refer to the appropriate clock wiring CAS CAS SDRAMs D0 D7 T topology under the DIMM wiring details DDSPD SPD section of this document p CKE SDRAMs D0 D7 t pon VDD VDDQ po p gt Refer to Section 3 1 of this document for WE p WE SDRAMs D0 D7 T c 1 details on address mirroring ODTO p ODT SDRAMsDO D7 X VREFDQ D0 D7 6 For each DRAM a unique ZQ resistor is CKO gt CK SDRAMs DO D7 Vs i i E po p7 bands oe ZQ resistor is CKO CK SDRAMs D0 D7 BONA ad VREFCA PE D0 D7 7 One SPD exists per module RESET RESET SDRAMs D0 D7 Rev 1 2 Jul 2013 11 SK yi 2GB 256Mx72 Module 1Rank of x8 DQSO 2 DQS4 DQSO DOS4 DMO w DM4 DM C
25. 3 55 SK nix 512Mx64 HMT351U6CFR8C Front 2 10 0 15 Min 1 45 gt SPD DETAIL A Max R0 70 2x 2 50 0 10 9 50 Q 5 175 47 00 71 00 4 128 95 p 133 35 Back O yu O Side Detail A Detail B 2 50 FULL R 3 64mm Max 0 80 0 05 lt gt r m nun 2 505020 S di m E d 1 00 t lt E 0 31 0 1 50 0 10 41272910 EO Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 2 Jul 2013 Units millimeters 56 SK nix 512Mx72 HMT351U7CFR8C
26. 4 repeat cycles 1 4 but BA 2 0 5 25 28 repeat cycles 1 4 but BA 2 0 6 29 32 repeat cycles 1 4 but BA 2 0 7 2 133 nRFC 1 repeat Sub Loop 1 until nRFC 1 Truncate if necessary a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 2 Jul 2013 50 SK six Table 10 IDD7 Measurement Loop Pattern ATTENTION Sub Loops 10 19 have inverse A 6 3 Pattern and Data Pattern than Sub Loops 0 9 x v E SIE S mms gja 45 IIS 8 IE 8 amp rm o E gt 8 Mi qa 4 0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 2 1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 0 aus repeat above D Command until nRRD 1 nRRD ACT 0 0 1 1 0 1 00 0 0 0 1 nRRD 1 RDA 0 1 0 1 0 1 00 0 0 00110011 nRRD 2 D 1 0 0 0 0 1 00 0 0 F 0 T repeat above D Command until 2 nRRD 1 2 2 nRRD repeat Sub Loop 0 but BA 2 0 2 3 3 nRRD repeat Sub Loop 1 but BA 2 0 3 4 4 nRRD D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2 0 5 7 nFAW 2 nRRD r
27. 5 SDRAMs D0 D8 yppspp SPD Refer to the appropriate clock wiring RAS RAS SDRAMs D0 D8 i topology under the DIMM wiring CAS CAS SDRAMs Do D8 VPD VDDQ D D0 D8 details section of this document CKEO gt CKE SDRAMs D0 D8 VREFDQ TI For each DRAM a unique ZQ resistor WE WE SDRAMs D0 D8 up es is connected to ground The ZQ resis ODTO ODT SDRAMs D0 D8 VSS 4 D0 D8 tor is 2400hm 1 CKO gt CK SDRAMs D0 D8 m One SPD exists per module Cko Ck SDRAMs D0 D8 VREFCA a RESET RESET SDRAMs D0 D8 Rev 1 2 Jul 2013 12 SK nix 4GB 512Mx64 Module 2Rank of x8 S S1 SO r DQSO DQS4 DQSO 1 DQS4 DMO 1 DM4 1 DM CS DQS DQS DM CS DQS DQS zem DM CS DQS DQS NT CS DOs DOS DQ0 W lO0 100 DQ32 1 00 BOI mvo 1 DO VO I D8 DQ33 M VO I D4 Tol D12 DQ2 W 1 02 102 DQ34 102 us WN 1 03 L 1 0 3
28. 57 DQ57 229 Vss Vss 49 NC NC 169 CKE1 NC CKE1 NC 110 Vss Vss 230 DM7 DM7 50 CKEO CKEO 170 VoD VDD 111 DQS7 DQS7 231 NC NC 51 VDD VDD 171 NC NC 112 DQS7 DQS7 232 Vss Vss 52 BA2 BA2 172 A14 A14 113 Vss Vss 233 DQ62 DQ62 53 NC NC 173 VDD VDD 114 DQ58 DQ58 234 DQ63 DQ63 54 VDD VDD 174 A12 A12 115 DQ59 DQ59 235 Vss Vss 55 All All 175 A9 A9 116 Vss Vss 236 VDDSPD VDDSPD 56 AZ A72 176 VDD VDD 117 SAO SAO 237 SA1 SA1 57 VDD VoD 177 Ag Ag 118 SCL SCL 238 SDA SDA 58 A52 A5 1178 A62 A62 119 SA2 SA2 239 Vss Vss 59 A42 A4 179 VDD VDD 120 VTT VIT 240 VTT VTT 60 VDD VDD 1180 A32 A32 NC No Connect RFU Reserved Future Use 1 NC pins should not be connected to anything on the DIMM including bussing within the NC group 2 Address pins A3 A8 and BAO and BA1 can be mirrored or not mirrored Rev 1 2 Jul 2013 9 SK yi On DIMM Thermal Sensor The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor The integrated thermal sensor comply with JEDEC TSE2002av Serial Presence Detect with Temperature Sensor Connection of Thermal Sensor SAO EVENT spp with SA1 SCL Integrated c4 SDA TS Temperature to Digital Conversion Performance Parameter Condition Min Typ Max Unit Active Range 75 C lt Ta lt 95 C Temperature Sensor Accuracy Grade
29. 8 368 400 mA IDD3N 432 480 480 mA IDD3P 240 272 288 mA IDDAR 880 1080 1240 mA IDD4W 840 1000 1200 mA IDD5B 1080 1200 1200 mA IDD6 192 192 192 mA IDDET 224 224 224 mA IDD7 1600 1720 1840 mA 4GB 512M x 72 U DIMM HMT351U7CFR8C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 540 675 675 mA IDD1 630 765 810 mA IDD2N 360 450 450 mA IDD2NT 450 540 540 mA IDD2PO 216 216 216 mA IDD2P1 270 270 306 mA IDD2Q 414 414 450 mA IDD3N 486 540 540 mA IDD3P 270 306 324 mA IDDAR 990 1215 1395 mA IDD4W 945 1125 1350 mA IDD5B 1215 1350 1350 mA IDD6 216 216 216 mA IDDET 252 252 252 mA IDD7 1800 1935 2070 mA Rev 1 2 Jul 2013 SK yi Module Dimensions 256Mx64 HMT325UGCFRSC Front 2 10 0 15 Min 1 45 4 Max R0 70 ae spp 30 00 4x3 00 0 10 E 1730 DETAIL A DETAIL B 2x 2 50 0 10 EX 9 50 sadi gt Q 5 1754 9 47 00 NN 71 00 1 128 95 bel gt 133 35 Back O O Side
30. B Monitor Range 40 C Ta 125 C TEN Ee e 20 C Ta 125 C 20 3 0 C Resolution 0 25 C Rev 1 2 Jul 2013 10 SK nix Functional Block Diagram 2GB 256Mx64 Module 1Rank of x8 DQSO dn DQs4 DQSO DQS4 ER IM DMO vw DM4 DM CS DQS DQS iis E CS DQS DQS DQ0 W1 00 wy DOI WH 1O 1 po E w 1 1 D4 DQ2 W1 0 2 mw des M Wo 3 DQ35 1 0 3 DQ4 W11 0 4 DQ36 W 1 0 4 DQ5 MW1 0 5 ed ms is 3i DQ6 W1 0 6 Z D DQ7 W41 0 7 Q mu DOSS DQ39 v 1 0 7 pee DQS1 H DQS5 DQS1 DMI w 4 DM5 DM CS DQS DQS e DN CS DQS DOS DQ8 W IO0 Be WHY i 1 pi DO41 W4YO1 ps DQ10 W 1 0 2 DQ42 W4 1 0 2 DQii W11 0 3 DQ43 W4 1 0 3 s i e s hes 1 0 5 DOIA mE 6 ZQ DQ46 W41 0 6 ZQ 1 DQ15 1 0 7 DQS6 DQ47 W1 0 7 DQS2 DQS6 DQS2 DM sy vw DM6 DM CS DQS DQS a CS DQS DOS Dal NOI pa poss MoI pg PEE EAE DQ19 I O 3 Q kem pass wmo 5 Mm w Uo 6 s DQ54 W1 0 6 ZQ F3 AC DQ23 W11 0 7 ZQ DQS7 DQ55 W41 0 7 EB DQS3 L DOS7 DMS DM DQ24 W4 1 0 Fa CS POR ROS DQ56 wron ERE DQ25 W IO 1 D3 Pen m I O1 D7 DQ26 W I O 2 Q I O 2 DQ27 W11 0 3 DQ59 MW1 0
31. CK SDRAMs D0 D8 5 For each DRAM a unique ZQ resistor is CKE1 CKE SDRAMs D9 D17 CK0 gt CK SDRAMs DO D8 connected to ground The ZQ resistor is RAS ______ RAS SDRAMs D0 D17 CK1 gt CK SDRAMs D9 D17 2400hm 1 CAS CAS SDRAMs D0 D17 CKi gt CK SDRAMs D9 D17 6 One SPD exists per module WE WE SDRAMs D0 D17 RESET RESET SDRAMs DO D17 Rev 1 2 Jul 2013 14 SK nix Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss 0 4 V 18V V 1 3 VDDQ Woltage on VDDQ pin relative to Vss 0 4V 18V V 1 3 Vin Vout Voltage on any pin relative to Vss 0 4V 18V V 1 Tstg Storage Temperature 55 to 100 oC 1 2 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300mV of each other at all
32. CWL 6 ICK AVG Reserved ns 1 2 3 4 9 CWL 7 8 9 tekave Reserved ns 4 CWL 5 ck ANG Reserved ns 4 7 OWL 6 xavo im Duns ns 1 2 3 4 9 CWL 7 8 9 lck avG Reserved ns 4 CWL 5 K AVG Reserved ns 4 8 CWL 6 ICK AVG 1 875 lt 2 5 ns 1 2 3 9 CWL 7 IcK AVG Reserved ns 1 2 3 4 9 CWL 8 9 amp kave Reserved ns 4 CWL 5 6 amp k ave Reserved ns 4 g CWL 7 o peer Spionen kand ns 1 2 3 4 9 CWL 8 f amp K AVG Reserved ns 1 2 3 4 9 CWL 9 ck AVG Reserved ns 4 CWL 5 6 amp k ave Reserved ns 4 10 CWL 7 ICK AVG 1 5 lt 1 875 ns 1 2 3 9 CWL 8 ICK AVG Reserved ns 1 2 3 4 9 CWL 5 6 7 lck avG Reserved ns 4 11 CWL 8 ck AVG bes Optional Shs ns 1 2 3 4 9 CWL 9 fK AVG Reserved ns 1 2 3 4 12 CWL 5 6 7 8 fck avG Reserved ns 4 CWL 9 ICK AVG Reserved ns 1 2 3 4 13 CWL 5 6 7 8 tekave Reserved NS 4 CWL 9 ICK AVG 1 07 lt 1 25 ns 1 2 3 Supported CL Settings 6 7 8 9 10 11 13 MK Supported CWL Settings 5 6 7 8 9 cK Rev 1 2 Jul 2013 37 De SK hynix Speed Bin Table Notes Absolute Specification Toper VDDQ Vpp 1 5V 0 075 V 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When mak ing a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as require ments from CWL setting tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchro nize
33. DD See Figure below 0 25 0 19 0 15 0 13 0 11 V ns Maximum undershoot area below VSS See Figure below 0 25 0 19 0 15 0 13 0 11 V ns CK CK DQ DQS DQS DM See figure below for each parameter definition Maximum Amplitude DD Volts Q v VSSQ Maximum Amplitude Time ns Overshoot Area Undershoot Area Clock Data Strobe and Mask Overshoot and Undershoot Definition Rev 1 2 Jul 2013 31 SK six Refresh parameters by device density Refresh parameters by device density Parameter RTT Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes Geer IRFC 90 110 160 260 350 ns REF command time verage periodic IREFI O CX Tease lt 85 C 7 8 7 8 7 8 7 8 7 8 us Pus interval B5 C lt Toase lt 95 C 3 9 3 9 3 9 3 9 3 9 US Notes 1 Users should refer to the DRAM supplier data sheet and or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this materia Rev 1 2 Jul 2013 32 SK yi Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin DDR3 800 Speed Bins For specific Notes See Speed Bin Table Notes on page 38 Speed Bin DDR3 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data lan 15 20 ns ACT to internal read or
34. Detail A Detail B 2 51mm Max 2 50 FULL R a gt la 0 80 0 05 gt ol mig 2 50 0 20 8 SIG e m E 1 00 A gt gt e AP 0 31 0 1 27 0 10 1 50 0 10 bs 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 2 Jul 2013 Units millimeters 54 SK yi 256Mx72 HMT325U7CFR8C Front 2 10 0 15 min 1 45 gt hr Max RO0 70 35 00 Vv 4x3 00 0 10 je 4 1730 DETAIL A DETAIL B 2x 2 50 0 10 fo 2x2 i ner 128 95 133 35 Back 3 U O Side Detail A Detail B 2 50 FULL R 2 51mm Max 0 80 0 05 KE 4 gt a nun 2 505020 S di m E S 1 00 A t E 0 31 0 1 50 0 10 1 27 0 10 P lt 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 2 Jul 201
35. KO CKO 5 Vss Vss 125 DMO DMO 65 VDD voo 185 CKO CKO 6 DQSO DQSO 126 NC NC 66 VDD VDD 186 VDD VDD 7 DQSO DQSO 127 Vss Vss 67 VREFCA VREFCA 187 NC EVENT 8 Vss Vss 128 DQ6 DQ6 68 NC NC 188 A0 A0 9 DQ2 DQ2 129 DQ7 DQ7 69 VDD VDD 189 VDD VDD 10 DQ3 DQ3 11130 Vss Vss 70 A10 A10 190 BA1 BA1 11 Vss Vss 131 DQ12 DQ12 71 BAO BAO2 191 VDD VDD 12 DQ8 DQ8 1 132 DQ13 DQ13 72 VDD Voo 192 RAS RAS 13 DQ9 DQ9 1133 Vss Vss 73 WE WE 193 So So 14 Vss Vss 134 DM1 DM1 74 CAS CAS 194 VpD VDD 15 DQS1 DQS1 1135 NC NC 75 VDD Voo 1195 ODTO ODTO 16 DQS1 DQS1 136 Vss Vss 76 Si S1 196 A13 A13 17 Vss Vss 137 DQ14 DQ14 77 ODT1 ODT1 197 VDD VDD 18 DQ10 DQ10 138 DQ15 DQ15 78 VDD VDD 198 NC NC 19 DQ11 DO11 139 Vss Vss 79 NC NC 199 Vss Vss 20 Vss Vss 140 DQ20 DQ20 80 Vss Vss 200 DQ36 DQ36 21 DQ16 DQ16 141 DQ21 DQ21 81 DQ32 DQ32 201 DQ37 DQ37 22 DQ17 DQ17 142 Vss Vss 82 DQ33 DQ33 202 Vss Vss 23 Vss Vss 143 DM2 DM2 83 Vss Vss 203 DM4 DM4 24 DQS2 DQS2 144 NC NC 84 DQS4 DQS4 204 NC NC 25 DQS2 DQS2 145 Vss Vss 85 DQS4 DQS4 205 Vss Vss 26 Vss Vss 146 DQ22 DQ22 86 Vss Vss 206 DQ38 DQ38 27 DQ18 DQ18 147 DQ23 DQ23 87 DQ34 DQ34 207 DQ39 DQ39 28 DQ19 DQ19 148 Vss Vss 88 DQ35 DQ35 208 Vss Vss 29 Vss Vss 149 DQ28 DQ28 89 Vss Vss 209 DQ44 DQ44 30 DQ24 DQ24 150 DQ29 DQ29 90 DQ40 DQ40 210 DQ45 DQ45 NC No Connect RFU Reserved Future Use 1 NC pins shoul
36. Q2NT and IDDQ4R are measured as time averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together Any IDD current is not included in IDDQ cur rents Attention IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM They can be used to support correlation of simulated IO power to actual IO power as outlined in the Figure below Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ are using on merged power layer in Module PCB For IDD and IDDQ measurements the following definitions apply e 0 and LOW is defined as VIN lt Vr Ac max e and HIGH is defined as VIN gt VrrCc max e MID LEVEL is defined as inputs are VREF VDD 2 e Timing used for IDD and IDDQ Measurement Loop Patterns are provided in Table 1 e Basic IDD and IDDQ Measurement Conditions are described in Table 2 e Detailed IDD and IDDQ Measurement Loop Patterns are described in Table 3 through Table 10 e IDD Measurements are done after properly initializing the DDR3 SDRAM This includes but is not lim ited to setting RON RZQ 7 34 Ohm in MR1 Qoff Og Output Buffer enabled in MR1 RTT Nom RZQ 6 40 Ohm in MR1 RTT Wr RZQ 2 120 Ohm in MR2 TDQS Feature disabled in MR1 e Attention The IDD and IDDQ Measurement Loop Patterns need to be executed at least one time before actu
37. S DQS DQS DM CS DQs DQS DQ0 W1 0 0 DQ32 W4 1 0 0 G ei DOs Ww Uo 3 DQ35 1 03 DQ4 W1 04 DQ36 W 41 0 4 DQ5 wW1 0 5 DQ37 W41 0 5 DQ6 vV1 0 6 ZQ DQ38 W11 0 6 ZQ m DQ7 W I O 7 l Dos QS5 DQ39 W4 1 0 7 E DOSI DQS5 En DM5 2 FN a CS DQs DQS sols s DH Cs DQS DAS DQ8 W I O0 MW DQ9 W1 0 Di Bede W 103 D5 DQ10 I O 2 pte S Ds DQ11 W1 0 3 bs SN Qs gs M DQi4 w I O 6 ZQ E E NT V6 3 Es DOS2 DQ15 w I O 7 DQS6 Q47 v DS B DM vi cs DOS DM CS DQS DQS DM CS pas DQS p le uon DQ16 W1 0 0 bod xd oi pg uc p DQ50 Ww 1 0 2 one Uz DQ51 MW11 0 3 see DQ52 W1 0 4 EUM aw ie DQ53 W 1 0 5 DQ22 M1 O 6 ZQ DQ54 W1 0 6 ZQ 1 L Doc DQ55 W41 0 7 DQ23 W1 0 7 DQS7 DQS3 DOS7 m DM7 MAN 3 DM CS DQS DOS iss D CS DQS DQS DQ24 W1 0 0 mg DQ25 W1 01 p3 pa WW 1a D7 peus mw is DQ59 MW11 0 3 un aw Dos Dro v10 4 oo re mU 555 Dost wdyor E pass wlyo7 p DQS8 DQ31 1 DQS8 SSF DM8 DM fS poe DOS SPD TS integrated Nates AA cB WY yo 1 pg lt gt SDA DQ to I O wiring is shown as recom 82 wW11 0 2 EVENT ll M AQ mended but may be changed CB3 Su DQ DQS DQS ODT DM CKE S rela cB4 W1 0 p dn CBE 05 SAO SM SA2 Or must be maintained as cB6 W41 06 Z RN CB7 Bu p DQ CB DM DQS DGS resistors Refer BA0 BA2 BA0 BA2 SDRAMs D0 D8 to associated topology diagram A0 A15 A0 Ai
38. S directive Ordering Information Part Number Density Organization Component Composition n FDHS HMT325U6CFR8C H9 PB RD 2GB 256Mx64 256Mx8 H5TQ2G83CFR 8 1 X HMT325U7CFR8C H9 PB RD 2GB 256Mx72 256Mx8 H5TQ2G83CFR 9 1 X HMT351U6CFR8C H9 PB RD 4GB 512Mx64 256Mx8 H5TQ2G83CFR 16 2 X HMT351U7CFR8C H9 PB RD 4GB 512Mx72 256Mx8 H5TQ2G83CFR 18 2 X Rev 1 2 Jul 2013 3 SK six Key Parameters CAS MT s Grade E Latency m RE MUS m CL tRCD tRP ns ns ns ns ns tCK DDR3 1066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 13 5 13 5 49 5 DDR3 1333 H9 1 5 9 13 125 13 125 36 49 125 9 9 9 13 75 13 75 48 75 DDR3 1600 PB 1 25 11 13 125 13 125 35 48 125 11 11 11 13 91 13 91 47 91 DDR3 1866 RD 1 07 13 13 125 13 125 34 47 125 13 13 13 SK hynix DRAM devices support optional downbinning to CL11 CL9 and CL7 SPD setting is programmed to match Speed Grade Frequency MHz Grade Remark CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13 G7 800 1066 1066 H9 800 1066 1066 1333 1333 PB 800 1066 1066 1333 1333 1600 RD 800 1066 1066 1333 1333 1600 1866 Address Table 2GB 1Rx8 2GB 1Rx8 4GB 2Rx8 4GB 2Rx8 Refresh Method 8K 64ms 8K 64ms 8K 64ms 8K 64ms Row Address A0 A14 A0 A14 A0 A14 A0 A14 Column Address A0 A9 A0 A9 A0 A9 A0 A9 Bank Address BA0 BA2 BA0 BA2 BAO BA2 BAO BA2 Page
39. SK nix DDR3 SDRAM Unbuffered DIMMs Based on 2Gb C Die HMT325U6CFR8C HMT325U7CFR8C HMT351U6CFR8C HMT351U7CFRSC SK hynix reserves the right to change products or specifications without notice Rev 1 2 Jul 2013 1 SK nix Revision History Revision No History Draft Date Remark 0 1 Initial Release Apr 2011 0 2 Typo Collected Jul 2011 0 3 Added IDD Specification Aug 2011 0 4 Revised 1866 Speed Bins Sep 2011 1 0 Module Dimension Updated Jul 2012 1 1 JEDEC Spec Updated Sep 2012 1 2 Changed module maximum thickness Jul 2013 to reflect the measured maximum Rev 1 2 Jul 2013 De SK hynix Description SK hynix Unbuffered DDR3 SDRAM DIMMs Unbuffered Double Data Rate Synchronous DRAM Dual In Line Memory Modules are low power high speed operation memory modules that use DDR3 SDRAM devices These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as PCs and workstations Feature VDD 1 5V 0 075V VDDQ 1 5V 0 075V VDDSPD 3 0V to 3 6V 8 internal banks Data transfer rates PC3 14900 PC3 12800 PC3 10600 Bi directional Differential Data Strobe 8 bit pre fetch Burst Length BL switch on the fly BL 8 or BC Burst Chop 4 Supports ECC error correction and detection On Die Termination ODT supported Temperature sensor with integrated SPD Serial Presence Detect EEPROM This product is in Compliance with the RoH
40. Size 1KB 1KB 1KB 1KB Rev 1 2 Jul 2013 De SK hynix Pin Descriptions Pin Name Description Pin Name Description A0 A15 SDRAM address bus SCL I C serial bus clock for EEPROM BAO BA2 SDRAM bank select SDA I C serial bus data line for EEPROM RAS SDRAM row address strobe SAO SA2 12C slave address select for EEPROM CAS SDRAM column address strobe VDD SDRAM core power supply WE SDRAM write enable VDDQ SDRAM I O Driver power supply S0 S1 DIMM Rank Select Lines VREFDQ SDRAM I O reference supply CKEO CKE1 SDRAM clock enable lines VREFCA EN oh command address reference ODTO ODT1 On die termination control lines Vss Power supply return ground DQ0 DQ63 DIMM memory data bus VDDSPD Serial EEPROM positive power supply CBO CB7 DIMM ECC check bits NC Spare pins no connect SDRAM data strobes Memory bus analysis tools PRUSIR positive line of differential pair I unused on memory DIMMS LL SDRAM data strobes DQS0 DQS8 negative line of differential pair RESET Set DRAMs to Known State SDRAM data masks high data strobes m DM0 DM8 X8 based x72 DIMMS VIT SDRAM I O termination supply CKO CK1 SPE ands RSVD Reserved for future use positive line of differential pair SDRAM clocks CIOE negative line of differential pair i The VDD and VDDQ pins are tied common to a single power plane on these designs Rev 1 2 Jul 2013 SK yi
41. VIH dc is used as a simplified symbol for VIH DQ DC100 VIL dc is used as a simplified symbol for VIL DQ DC100 VIH ac is used as simplified symbol for VIH DQ AC175 VIH DQ AC150 and VIH DQ AC135 VIH DQ AC175 Refer to Overshoot and Undershoot Specifications on page 30 The ac peak noise on Vref may not allow Vref to deviate from Vgerpo pc by more than 1 VDD for reference value is used when Vref 0 175V is referenced VIH DQ AC150 value is used when Vref 0 150V is referenced and VIH DQ AC135 value is used when Vref 0 135V is referenced VIL ac is used as simplified symbol for VIL DQ AC175 VIL DQ AC150 and VIL DQ AC135 VIL DQ AC175 value is used when Vref 0 175V is referenced VIL DQ AC150 value is used when Vref 0 150V is referenced and VIL DQ AC135 value is used when Vref 0 135V is referenced Rev 1 2 Jul 2013 18 SK yi Vref Tolerances The dc tolerance limits and ac noise limits for the reference voltages vrefca and Vrefpg are illustrated in figure below It shows a valid reference voltage Vp t as a function of time Vref stands for Vrefca and Vnerpo likewise Vref DC is the linear average of Vpef t over a very long period of time e g 1 sec This average has to meet the min max requirements in the table Differential Input Slew Rate Definition on page 25 Further more Vref t may temporarily deviate from Vger pc by no more than 1 VDD voltage VDD
42. al IDD or IDDQ measurement is started e Define D CS RAS CAS WE HIGH LOW LOW LOW e Define D CS RAS CAS WE HIGH HIGH HIGH HIGH Rev 1 2 Jul 2013 40 Y lop Y IDDQ optional RESET a DDR3 CK CK SDRAM CKE bas bas RTT 25 Ohm CS DQ DM 01 gt Vppo 2 RAS CAS WE TDQS TDQS A BA ODT ZQ Vss Measurement Setup and Test Load for IDD and IDDQ optional Measurements Note DIMM level Output test load condition may be different from above Application specific IDDQ memory channel Test Load Ul Channel IDDQ IDDQ IO Power Simulation Simulation Simulation X Correction Channel IO Power Number Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev 1 2 Jul 2013 41 SK yi Table 1 Timings used for IDD and IDDQ Measurement Loop Patterns DDR3 1333 DDR3 1600 DDR3 1866 Symbol Unit 9 9 9 11 11 11 13 13 13 tk 1 5 1 25 1 07 ns CL 9 11 13 nCK rcp 9 11 13 nCK MRC 33 39 45 nCK IRAS 24 28 32 nCK App 9 11 13 nCK 1KB page size 20 24 26 nCK FAW 2K8 page size 30 32 33 nck 1KB page size 4 5 5 nCK FRED 2KB page size 5 6 nCK Igrc 512Mb 60 72 85 nCK fgpc i Gb 74 88 103 nCK Igrc 2 Gb 107 128 150 nCK Irc 4 Gb 174 208 243 nCK Irc 8 Gb 234 280 328 nCK Table 2 Basic IDD and IDDQ Measurement Conditions Symbol Descripti
43. and BA 2 0 3 4 16 19 repeat Sub Loop 0 but ODT 0 and BA 2 0 4 5 20 23 repeat Sub Loop 0 but ODT 0 and BA 2 0 5 6 24 17 repeat Sub Loop 0 but ODT 1 and BA 2 0 6 7 28 31 repeat Sub Loop 0 but ODT 1 and BA 2 0 7 a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 2 Jul 2013 48 De SK hynix Table 7 IDD4R and IDDQ4R Measurement Loop Pattern 9 E o t gt o Fla olala S82 2 WEBE 8 2 2 s s Fou 2 oZ 3 x EE EE M ME 0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 O 0 0 0 2 3 DD 1 1 11 0 0 000 0 0 0 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 S 6 7 DD 1 1 1 1 0 0 00 0 0O F 0 a 2 1 8 15 repeat Sub Loop 0 but BA 2 0 1 9 B 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 124 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 140 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Table 8 IDD4W Measurement Loop Pattern
44. ck and if single ended clock input signals CK and CK are monotonic with a single ended swing VSEL VSEH of at least VDD 2 250 mV and when the differential slew rate of CK CK is larger than 3 V ns 2 The relation between Vix Min Max and VSEL VSEH should satisfy following VDD 2 Vix Min VSEL gt 25mV VSEH VDD 2 Vix Max gt 25mV Rev 1 2 Jul 2013 24 SK nix Slew Rate Definitions for Single Ended Input Signals See 7 5 Address Command Setup Hold and Derating in DDR3 Device Operation for single ended slew rate definitions for address and command signals See 7 6 Data Setup Hold and Slew Rate Derating in DDR3 Device Operation for single ended slew rate definition for data signals Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in table and figure below Differential Input Slew Rate Definition Measured Description E Defined by Min ax Differential input slew rate for rising edge CK CK and Das DGS geog ViLdiffimax ViHdiffmin ViHdiftmin ViLdifmaxl Delta TRdiff Differential input slew rate for falling edge CK CK and bas DAS pe ViHdifmin ViLdifmax ViHdiftmin ViLditmaxl Delta TFdiff Notes The differential signal i e CK CK and DQS DQS must be linear between these thresholds Differential Input Voltage i e DQS DQS CK CK Differential
45. clock On tCK CL see Table 1 BL 87 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 6 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling according to Table 6 Pattern Details see Table 6 Ipp2P0 Precharge Power Down Current Slow Exit CKE Low External clock On tCK CL see Table 1 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Ipp2P1 Precharge Power Down Current Fast Exit CKE Low External clock On tCK CL see Table 1 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Ipp2Q Precharge Quiet Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Jpp3N Active Standby Current CKE H
46. ctual measurements may vary according to DQ loading cap 2GB 256M x 64 U DIMM HMT325U6CFR8C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 320 360 380 mA IDD1 400 440 480 mA IDD2N 160 200 200 mA IDD2NT 200 240 240 mA IDD2PO 96 96 96 mA IDD2P1 120 120 136 mA IDD2Q 184 184 200 mA IDD3N 216 240 240 mA IDD3P 120 136 14 ma IDDAR 720 840 1000 mA IDD4W 680 760 960 mA IDD5B 920 960 960 mA ID6 96 96 96 m IDD6ET 112 112 112 mA IDD7 1440 1480 1600 mA 2GB 256M x 72 U DIMM HMT325U7CFR8C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 360 405 405 mA IDD1 450 495 540 mA IDD2N 180 225 225 mA IDDINT 225 27 1 2700 m IDD2PO 108 108 108 mA IDD2P1 135 135 153 mA IDD2Q 207 207 225 mA IDD3N 243 270 270 mA IDD3P 135 153 162 mA IDDAR 810 945 1125 mA IDD4W 765 855 1080 mA IDD5BB 1035 1 10800 100 m IDD6 108 108 108 mA IDD6ET 126 126 126 mA IDD7 1620 1665 1800 mA Rev 1 2 Jul 2013 y SK Paix 4GB 512M x 64 U DIMM HMT351U6CFR8C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 480 600 600 mA IDD1 560 680 720 mA IDD2N 320 400 400 mA IDD2NT 400 480 480 mA IDD2PO 192 192 192 mA IDD2P1 240 240 272 mA IDD2Q 36
47. d by the DLL all possible intermediate frequencies may not be guaranteed An application should use the next smaller JEDEC standard tCK AVG value 3 0 2 5 1 875 1 5 or 1 25 ns when calculat ing CL nCK tAA ns tCK AVG ns rounding up to the next Supported CL where tCK AVG 3 0 ns should only be used for CL 5 calculation tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED 4 Reserved settings are not allowed User must program a different value 10 11 Optional settings allow certain devices in the industry to support this setting however it is not a man datory feature Refer to DIMM data sheet and or the DIMM SPD information if and how this setting is supported Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterizatio
48. d not be connected to anything on the DIMM including bussing within the NC group 2 Address pins A3 A8 and BAO and BA1 can be mirrored or not mirrored Rev 1 2 Jul 2013 8 SK yi Front Side left 1 60 Back Side right 121 180 Front Side left 61 120 Back Side right 181 240 Pin x64 x72 Pin x64 x72 Pin x64 x72 Pin x64 x72 Non ECC ECC Non ECC ECC Non ECC ECC Non ECC ECC 31 DQ25 DQ25 151 Vss Vss 91 DQ41 DQ41 211 Vss Vss 32 Vss Vss 152 DM3 DM3 92 Vss Vss 212 DM5 DM5 33 DQS3 DQS3 153 NC NC 93 DQS5 DQS5 213 NC NC 34 DQS3 DQS3 154 Vss Vss 94 DQS5 DQS5 214 Vss Vss 35 Vss Vss 155 DQ30 DQ30 95 Vss Vss 215 DQ46 DQ46 36 DQ26 DQ26 156 DQ31 DQ31 96 DQ42 DQ42 216 DQ47 DQ47 37 DQ27 DQ27 157 Vss Vss 97 DQ43 DQ43 217 Vss Vss 38 Vss Vss 158 NC CB4 98 Vss Vss 218 DQ52 DQ52 39 NC CBO 1159 NC CB5 99 DQ48 DQ48 219 DQ53 DQ53 40 NC CB1 160 Vss Vss 100 DQ49 DQ49 220 Vss Vss 41 Vss Vss 161 DM8 DM8 101 Vss Vss 221 DM6 DM6 42 NC DQS8 162 NC NC 102 DQS6 DQS6 222 NC NC 43 NC DQS8 163 Vss Vss 103 DQS6 DQS6 223 Vss Vss 44 Vss Vss 164 NC CB6 104 Vss Vss 224 DQ54 DQ54 45 NC CB2 165 NC CB7 105 DQ50 DQ50 225 DQ55 DQ55 46 NC CB3 166 Vss Vss 106 DQ51 DQ51 226 Vss Vss 47 Vss Vss 167 NC NC 107 Vss Vss 227 DQ60 DQ60 48 NC NC 168 Reset Reset 108 DQ56 DQ56 228 DQ61 DQ61 KEY KEY 109 DQ
49. epeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 S 9 nFAW 4 nRRD D 1 0 0 0 0 7 00 0 0 F 0 E I Assert and repeat above D Command until 2 nFAW 1 if necessary E z 2 nFAW 0 ACT 0 0 1 1 0 0 00 0 0 F 0 B a 10 2 nFAW 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 z ENE Repeat above D Command until 2 nFAW nRRD 1 2 nFAW nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 T 2 nFAW nRRD 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 7 ea eGR Me Repeat above D Command until 2 nFAW 2 nRRD 1 12 2 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 2 13 2 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 3 D 1 0 0 0 0 3 00 0 0 0 0 a SL Assert and repeat above D Command until 3 nFAW 1 if necessary 15 3 nFAW repeat Sub Loop 10 but BA 2 0 4 16 3 nFAW nRRD repeat Sub Loop 11 but BA 2 0 5 17 3 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 6 18 3 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 7 D 1 0 0 0 0 7 00 0 0 0 0 Ea Assert and repeat above D Command until 4 nFAW 1 if necessary a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 2 Jul 2013 51 y SK Paix IDD Specifications Tcase 0 to 95 C Module IDD values in the datasheet are only a calculation based on the component IDD spec The a
50. ernal read or 13 5 E n write delay time RED 13 125 310 13 5 PRE i f command period RP 13 125 5 10 ns ACT to ACT or REF t 49 5 s command period RE 49 125 5 10 ACT to PRE command fens 36 9 tREFI fig period CWL 5 K AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 K AVG Reserved ns 1 2 3 4 7 CWL 7 CK AVG Reserved ns 4 CWL 5 amp xave Reserved ns 4 1 875 lt 2 5 CL 7 CWL 6 CK AVG ns 1 2 3 4 7 Optional gt 10 CWL 7 ICK AVG Reserved ns 1 2 3 4 CWL 5 lck AVG Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 lck AvG Reserved ns 1 2 3 4 tw CWL 5 6 amp xave Reserved ns 4 7 CWL 7 f amp xave 1 5 lt 1 875 ns 1 2 3 4 CWL 5 6 amp kave Reserved ns 4 CL 10 1 5 1 875 ns 1 2 3 CWL 7 fave Reserved ns Supported CL Settings 6 7 8 9 10 TICK Supported CWL Settings 5 6 7 ACK Rev 1 2 Jul 2013 35 SK yi DDR3 1600 Speed Bins For specific Notes See Speed Bin Table Notes on page 38 Speed Bin DDR3 1600K CL nRCD nRP 11 11 11 Unit Note Parameter Symbol min max Internal read command ba 13 75 20 is to first data 13 125 gt 10 ACT to internal read or bcD 13 75 _ EE write delay time 13 125 310 PRE command period trp a 35d ns ACT to ACT or REF lc 48 75 u ae command period 48 125 5 10 PE fie oda tras 35 9 tREFI ns CWL 5 lck AvG 2 5 3 3 ns 1 2
51. igh External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 IppsP Active Power Down Current CKE Low External clock On tCK CL see Table 1 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Rev 1 2 Jul 2013 43 SK yi Symbol Description Operating Burst Read Current CKE High External clock On tCK CL see Table 1 BL 82 AL 0 CS High between RD Command Address L Bank Address Inputs partially toggling according to Table 7 Data IO seamless read data burst with different DD4R data between one burst and the next one according to Table 7 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 7 Operating Burst Write Current CKE High External clock On tCK CL see Table 1 BL 82 AL 0 CS High between WR Command Address L Bank Address Inputs partially toggling according
52. l Parameters Symbol Parameter Rating Units Notes Topr Operating temperature ambient 0 to 55 C 3 Hopr Operating humidity relative 10 to 90 TsTG Storage temperature 50 to 100 oc 1 Hste Storage humidity without condensation 5 to 95 96 1 PBAR Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Expousure to absolute maximum rating conditions for extended periods may affect reliablility 2 Up to 9850 ft 3 The designer must meet the case temperature specifications for individual module components Rev 1 2 Jul 2013 39 SK yi IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter IDD and IDDQ measurement conditions such as test load and patterns are defined Figure below Measurement Setup and Test Load for IDD and IDDQ optional Measurements shows the setup and test load for IDD and IDDQ measurements e IDD currents such as IDDO IDD1 IDD2N IDD2NT IDD2PO IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET and IDD7 are measured as time averaged currents with all VDD balls of the DDR3 SDRAM under test tied together Any IDDQ current is not included in IDD currents e IDDQ currents such as IDD
53. n Any DDR3 1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization DDR3 SDRAM devices supporting optional down binning to CL 7 and CL 9 and tAA tRCD tRP must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333H devices supporting down binning to DDR3 1066F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600K devices supporting down binning to DDR3 1333H or DDR3 1600F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36 ns 13 125 ns for DDR3 1333H and 48 125ns tRASmin tRPmin 35 ns 13 125 ns for DDR3 1600K DDR3 SDRAM devices supporting optional down binning to CL 11 CL 9 and CL 7 tAA tRCD tRPmin must be 13 125ns SPD setting must be programed to match For example DDR3 1866 devices supporting down binning to DDR3 1600 or DDR3 1333 or 1066 should program 13 125ns in SPD bytes for tAAmin byte 16 tRCDmin byte 18 and tRPmin byte 20 is programmed to 13 125ns tRCmin byte 21 23 also should be programmed accord ingly For example 47 125ns tRASmin tRPmin 34ns 13 125ns Rev 1 2 Jul 2013 38 SK nix Environmenta
54. nbuffered DIMM designs VDDQ shares the same power plane as VDD pins BAO BA2 SSTL Selects which SDRAM bank of eight is activated A0 A15 SSTL During a Bank Activate command cycle Address input defines the row address RAO RA15 During a Read or Write command cycle Address input defines the column address In addition to the column address AP is used to invoke autopre charge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BA1 BA2 defines the bank to be pre charged If AP is low autoprecharge is disabled During a Precharge com mand cycle AP is used in conjunction with BAO BA1 BA2 to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BA1 or BA2 If AP is low BAO BA1 and BA2 are used to define which bank to precharge A12 BC is sampled during READ and WRITE commands to determine if burst chop on the fly will be per formed HIGH no burst chop LOW burst chopped DQ0 DQ63 CB0 CB7 SSTL Data and Check Bit Input Output pins DM0 DM8 SSTL Active High DM is an input mask signal for write data Input data is masked when DM is sampled High coincident with that input data during a write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loading VDD Vss Supply Power and ground for the DDR3 SDRAM
55. ntial output high or low swing with a driver impedance of 4062 and an effective test load of 252 to Vi Vppo 2 at each of the differential outputs Rev 1 2 Jul 2013 26 SK nix Single Ended Output Slew Rate When the Reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo ac and Vou ac for single ended signals are shown in table and Figure below Single ended Output slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VOL AC VoH AC Vouacy VoL ac l DeltaTRse Single ended output slew rate for falling edge VoH AC VoL AC Vouacy VoL ac l DeltaTFse Notes 1 Output slew rate is verified by design and characterisation and may not be subject to production test gt SSS SSS SSS SE Vor ac Vir Single Ended Output Voltage l e DQ Vowacy Delta TFse Single Ended Output slew Rate Definition Output Slew Rate single ended DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Unit nits Parameter Symbol Min Max Min Max Min Max Min Max Min Max Single ended Output Slew Rate SRQse 2 5 5 2 5 5 2 5 5 2 5 5 2 5 50 Vins Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Note
56. on Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 1 BL 82 AL 0 CS High between ACT and Ippo PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data IO MID LEVEL DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table 3 Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 3 Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS nRCD CL see Table 1 BL 8 AL 0 CS High between ACT bbi RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 4 DM stable at 0 Bank Activity Cycling with on bank active at a time 0 0 1 1 2 2 see Table 4 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 4 Rev 1 2 Jul 2013 42 De SK hynix Symbol Description Jpp2N Precharge Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Jpp2NT Precharge Standby ODT Current CKE High External
57. times and VREF must not be greater than 0 6XVDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mV DRAM Component Operating Temperature Range Temperature Range Symbol Parameter Rating Units Notes Topen NOrmal Operating Temperature Range 01088 C 12 Extended Temperature Range 85 to 95 C 1 3 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For mea surement conditions please refer to the JEDEC document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported Dur ing operation the DRAM case temperature must be maintained between 0 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to use the Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 0b and MR2 A7 1b
58. to Table 8 Data IO seamless read data burst with different DDAW data between one burst and the next one according to Table 8 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 8 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at HIGH Pattern Details see Table 8 Burst Refresh Current CKE High External clock On tCK CL nRFC see Table 1 BL 89 AL 0 CS High between REF Command JppsB Address Bank Address Inputs partially toggling according to Table 9 Data IO MID LEVEL DM stable at 0 Bank Activity REF command every nREF see Table 9 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 9 Self Refresh Current Normal Temperature Range Tease 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Ippe Low External clock Off CK and CK LOW CL see Table 1 BL 82 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Self Refresh Current Extended Temperature Range Tease 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended dopet CKE Low External clock Off CK and CK LOW CL see Table 1 BL 82 AL 0 CS Command Address Bank
59. ubject to production test 2 og n UD Q VOHdiff AC d v o B s O 2 E T 5 c 3 D B VOLdiff AC a Differential Output slew Rate Definition Differential Output Slew Rate DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Differential Output Slew Rate SRQdiff 5 10 5 10 5 10 5 10 5 12 Vins Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Units Rev 1 2 Jul 2013 28 SK yi Reference Load for AC Timing and Output Slew Rate Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment Manufacturers correlate to their production test conditions generally one or more coaxial transmission lines terminated at the tester electronics VDDQ 25 Ohm DQ VIT 2 DUT VDDQ DQS Reference Load for AC Timing and Output Slew Rate Rev
60. write delay time CD 15 ns PRE command period lap 15 ns ACT to ACT or REF command period fac 52 5 ns ACT to PRE command period faas 37 5 9 tREFI ns CL 6 CWL 5 amp K AVG 2 5 3 3 ns 1 2 3 Supported CL Settings 6 lick Supported CWL Settings 5 lick Rev 1 2 Jul 2013 33 SK yi DDR3 1066 Speed Bins For specific Notes See Speed Bin Table Notes on page 38 Speed Bin DDR3 1066F Unit Note CL nRCD nRP 7 7 7 Parameter Symbol min max Internal read command to first data lag 13 125 20 ns ACT to internal read or write delay time RCD 13 125 gt i PRE command period tap 13 125 ns ACT to ACT or REF bc 50 625 u ng command period ACT to PRE command bras 37 5 9 tREFI ing period aes CWL 5 CK AVG 2 5 3 3 ns 1 2 3 6 7 CWL 6 fK AVG Reserved ns 1 2 3 4 Eee CWL 5 K AVG Reserved ns 4 7 CWL 6 kavo 1 875 2 5 ns 1 2 3 4 m CWL 5 fCK AVG Reserved ns 4 7 CWL 6 qvo 1 875 lt 2 5 ns 1 2 3 Supported CL Settings 6 7 8 Ik Supported CWL Settings 5 6 IKK Rev 1 2 Jul 2013 34 SK yi DDR3 1333 Speed Bins For specific Notes See Speed Bin Table Notes on page 38 Speed Bin DDR3 1333H CL nRCD nRP 9 9 9 DIE DP Parameter Symbol min max Internal read command 13 5 20 m to first data m 13 125 510 ACT to int
61. x min max min max min max 24 0 75 175 214 134 139 4 0 57 170 214 134 139 3 0 50 167 191 112 118 2 0 38 119 146 67 77 1 8 34 102 131 52 63 1 6 29 81 113 33 45 1 4 22 54 88 9 23 1 2 13 19 56 note note 1 0 0 note 11 note note 1 0 0 note note note note note Rising input differential signal shall become equal to or greater than VIHdiff ac level and Falling input differential signal shall become equal to or less than VIL ac level Rev 1 2 Jul 2013 21 SK yi Single ended requirements for differential signals Each individual component of a differential signal CK DQS DQSL DQSU CK DQS DQSL of DQSU also has to comply with certain requirements for single ended signals CK and CK have to approximately reach VSEHmin VSELmax approximately equal to the ac levels VIH ac VIL ac for ADD CMD signals in every half cycle DQS DQSL DQSU DQS DQSL have to reach VSEHmin VSELmax approximately the ac levels VIH ac VIL ac for DQ signals in every half cycle preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if VIH CA AC150 VIL CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK VDD or VDDQ VSEHmin m a poe
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