Arduino A000053 peripheral controller
Contents
1. OxA4 Reserved OxA3 Reserved OxA2 Reserved OxA1 Reserved OxA0 Reserved Ox9F Reserved Ox9E Reserved 0x9D OCR3CH Timer Counter3 Output Compare Register C High Byte Ox9C OCR3CL Timer Counter3 Output Compare Register C Low Byte 0x9B OCR3BH Timer Counter3 Output Compare Register B High Byte 0x9A OCR3BL Timer Counter3 Output Compare Register B Low Byte 0x99 OCR3AH Timer Counter3 Output Compare Register A High Byte 0x98 OCR3AL Timer Counter3 Output Compare Register A Low Byte 0x97 ICR3H Timer Counter3 Input Capture Register High Byte 0x96 ICR3L Timer Counter3 Input Capture Register Low Byte 0x95 TCNT3H Timer Counter3 Counter Register High Byte 0x94 TCNT3L Timer Counter3 Counter Register Low Byte 0x93 Reserved 0x92 TOCR3C FOC3A 0x91 TCCR3B ICNC3 ICES3 WGM33 WGM32 CS32 CS31 CS30 0x90 TCCR3A COM3A1 COM3A0 COMS3B1 COM3BO COM3C1 COM3CO WGM31 WGM30 0x8F Reserved 0x8E Reserved 0x8D OCR1CH Timer Counter1 Output Compare Register C High Byte Ox8C OCRI1CL Timer Counter1 Output Compare Register C Low Byte 0x8B OCR1BH Timer Counter1 Output Compare Register B High Byte 0x8A OGR1BL Timer Counter1 Output Compare Register B Low Byte 0x89 OCR1AH Timer Counter1 Output Compare Register A High Byte 0x88 OCR1AL Ti2. ees Tmega16 32U4 4 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page OxFF Reserved OxFE Reserved OxFD Reserved OxFC Reserved OxFB Reserved OxFA Reserved OxF9 Reserved OxF8 Reserved OxF7 Reserved OxF6 Reserved OxF5 Reserved OxF4 UEINT EPINT6 0 OxF3 UEBCHX BYCT10 8 OxF2 UEBCLX BYCT7 0 OxF 1 UEDATX DAT7 0 0xFO UEIENX FLERRE NAKINE NAKOUTE RXSTPE RXOUTE STALLEDE TXINE OxEF UESTA1X CTRLDIR CURRBK1 0 OxEE UESTAOX CFGOK OVERFI UNDERFI DTSEQ1 0 NBUSYBK1 0 OxED UECFG1X EPSIZE2 0 EPBK1 0 ALLOC 0xEC UECFGOX EPTYPE1 0 EPDIR OxEB UECONX STALLRQ STALLRQC RSTDT EPEN OxEA UERST EPRST6 0 OxE9 UENUM EPNUM2 0 OxE8 UEINTX FIFOCON NAKINI RWAL NAKOUTI RXSTPI RXOUTI STALLEDI TXINI OxE7 Reserved OxE6 UDMFN FNCERR OxE5 UDFNUMH FNUM10 8 OxE4 UDFNUML FNUM7 0 OxE3 UDADDR ADDEN UADD6 0 OxE2 UDIEN UPRSME EORSME WAKEUPE EORSTE SOFE MSOFE SUSPE OxE1 UDINT UPR
3. Do not enable this interrupt Firmware must process this USB event by polling VBUSTI 4 Timer 4 11 bits enhanced PWM mode Timer 4 11 bits enhanced mode is not functional Problem Fix work around None 21 ATmega16 32U4 uuu sm Tmega16 32U4 8 5 ATmega16U4 ATmega32U4 Rev A 7766FS AVR 11 10 Spike on TWI pins when TWI is enabled High current consumption in sleep mode Increased power consumption in power down mode Internal RC oscillator start up may fail Internal RC oscillator calibration Incorrect execution of VBUSTI interrupt Timer 4 enhanced mode issue Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled Problem Fix work around Enable ATmega16U4 ATmega32U4 TWI before the other nodes of the TWI network High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode the current consump tion will increase during sleep when executing the SLEEP instruction directly after a SEI instruction Problem Fix work around Before entering sleep interrupts not used to wake up the part from the sleep mode should be disabled Increased power comsumption in power down mode The typical power consumption is increased by about 30 uA in power down mode Problem Fix work around None Internal RC oscillator start up may fail When the part is configured to start on internal RC oscillator the oscillator may not start properly
4. Ooo 0000 a Bb A O Q Q O ti EE es 22 aw Q S zte ETET REL ZO xoaqtqoaaeaoaaa Oo gt tT I O TN oe lO 1 0 NJ oO fw Tpit psy Ist Pt My my oy my e eo 33 32 INDEX CORNER 31 E 29 ATmega32U4 28 ATmega16U4 27 44 pin QFN TQFP 26 25 24 23 m 0 0 IN O O r N el fel fel jeji e IQ A IA O Q N r j S ep SO xn mo Q w Oz Qa A A 4 40 on gt of Ea ea aa tr a X SERAT E BEE z 22 zlo 3 55 5E o na X 0 DD xxO m ck gt Q Q Q PCINT7 OC0A OC1C RTS PB7 PE2 HWB PC7 ICP3 CLK0 OC4A PC6 OC3A OC4A PB6 PCINT6 OC1B OC4B ADC13 PB5 PCINT5 OC1A OC4B ADC12 PB4 PCINT4 ADC11 27 PD7 T0 OC4D ADC10 PD6 T1 0C4D ADC9 25 PD4 ICP1 ADC8 24 AVCC GND The ATmega16U4 ATmega32U4 is a low power CMOS 8 bit microcontroller based on the AVR enhanced RISC architecture By executing powerful instructions in a single clock cycle the ATmega16U4 ATmega32U4 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed 7766FS AVR 11 10 AMEL ees Tmega16 32U4 2 1 Block Diagram Figure 2 1 Block Diagram PF7 PF4 PF1 PFO PC7 PC6 1 1 i VCC PORTF DRIVERS PORTC DRIVERS T 1 1 1 DATA REGISTER DATA DIR DATA REGISTER DATA DIR PORTF REG PORTF PORTC REG PORTC 8 BIT DA TA BUS POR BOD f RESET i i i 1 i I 1 I I I 1
5. 1 408 487 2600 HONG KONG Tel 49 89 31970 0 Tel 81 3 3523 3551 www atmel com Tel 852 2245 6100 Fax 852 2722 1369 Fax 49 89 3194621 Fax 81 3 3523 7581 2010 Atmel Corporation All rights reserved Rev CORP072610 Atmel logo and combinations thereof and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries Other terms and product names may be trademarks of others Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDENTAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS AND PROF ITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or com p
6. I I I 1 I I I i I Ka caum ose i INTERNAL OSCILLATOR CALIB OSC OSCILLATOR WATCHDOG STACK TIMER POINTER i i SRAM i I i I I I 1 I 1 I 1 1 I 1 i T i 1 i 1 i 1 i PROGRAM COUNTER JTAG TAP ON CHIP DEBUG PROGRAM FLASH MCU CONTROL TIMING AND REGISTER gt j CONTROL h TIMERS BOUNDARY INSTRUCTION COUNTERS SCAN re GENERAL PURPOSE REGISTERS INTERRUPT lt x UNIT pa UVec PROGRAMMING INSTRUCTION DECODER ON CHIP l EEPROM USB PAD 3V l REGULATOR UCap TEMPERATURE SENSOR CONTROL s LINES 1uF AVCC HIGHSPEED lt 1 Pet ug al gt ADC o TIMER PWM AGND lt STATUS gt REGISTER Fr vBus AREF i DP i USB 2 0 Lom ANALOG TWO WIRE SERIAL COMPARATOR sd SPI INTERFACE Sa DATA REGISTER DATA DIR DATA REGISTER DATA DIR DATA REGISTER DATA DIR PORTE REG PORTE PORTB REG PORTB PORTD REG PORTD PORTE DRIVERS PORTB DRIVERS PORTD DRIVERS PEG PE2 PB7 PBO PD7 PDO The AVR core combines a rich instruction set with 32 general purpose working registers All the 32 registers are directly connected to the Arithmetic Logic Unit ALU allowing two independent registers to be accessed in one single instructi
7. after power on Problem Fix work around Do not configure the part to start on internal RC oscillator Internal RC oscillator calibration 8 MHz frequency can be impossible to reach with internal RC even when using maximal OSCAL value Problem Fix work around None Incorrect execution of VBUSTI interrupt The CPU may incorrectly execute the interrupt vector related to the VBUSTI interrupt flag Problem fix work around Do not enable this interrupt Firmware must process this USB event by polling VBUSTI AMEL 2 AMEL 7 Timer 4 11 bits enhanced PWM mode Timer 4 11 bits enhanced mode is not functional Problem Fix work around None 23 ATmega16 32U4 sum 7766FS AVR 11 10 ees Tmega16 32U4 9 Datasheet Revision History for ATmega16U4 ATmega32U4 Please note that the referring page numbers in this section are referred to this document The referring revision in this section are referring to the document revision 9 1 Rev 7766F 11 10 9 2 Rev 7766E 04 10 o ONO A BOND Ut O 12 13 9 3 Rev 7766D 01 09 AR END 9 4 Rev 7766C 11 08 7766FS AVR 11 10 Replaced the QFN44 on page 19 by an updated drawing Updated ADC Control and Status Register B ADCSRB on page 289 Defined the ADCSRB register as in ADC Control and Status Register B ADCSRB on page 312 Updated the last page according to Atmel new Brand Style Guide Updated Feature
8. 2 CS41 CS40 0xCO TCCR4A COM4A1 COM4A0 COM4B1 COM4BO FOC4A FOC4B PWM4A PWM4B 0xBF TC4H Timer Counter4 High Byte 7766FS AVR 11 10 AMEL T ees Tmega16 32U4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0xBE TCNT4 Timer Counter4 Counter Register Low Byte 0xBD TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAMO 0xBC TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE 0xBB TWDR 2 wire Serial Interface Data Register 0xBA TWAR TWA6 TWAS TWA4 TWA3 TWA2 TWA1 TWAO TWGCE 0xB9 TWSR TWS7 TWS6 TWS5 TWS4 TWS3 TWPS1 TWPSO OxB8 TWBR 2 wire Serial Interface Bit Rate Register 0xB7 Reserved 0xB6 Reserved 0xB5 Reserved 0xB4 Reserved 0xB3 Reserved 0xB2 Reserved 0xB1 Reserved OxBO Reserved OxAF Reserved OxAE Reserved OxAD Reserved gt 0xAC Reserved 0xAB Reserved OxAA Reserved OxAQ Reserved OxA8 Reserved 0xA7 Reserved OxA6 Reserved OxA5 Reserved
9. 66FS AVR 11 10 AMEL 16 ees Tmega16 32U4 6 2 ATmega32U4 Speed MHz Power Supply Ordering Code Default Oscillator Package Operation Range ATmega32U4 AU External XTAL i ATmega32U4RC AU Internal Calib RC 16 2 7 5 5V Industrial 40 to 85 C ATmega32U4 MU External XTAL en ATmega32U4RC MU Internal Calib RC Package Type ML 44 Lead 10 x 10 mm Body Size 1 0 mm Body Thickness 44ML 0 8 mm Lead Pitch Thin Profile Plastic Quad Flat Package TQFP PW 44 Lead 7 0 x 7 0 mm Body 0 50 mm Pitch 44PW Quad Flat No Lead Package QFN 7766FS AVR 11 10 AMEL 17 ees Tmega16 32U4 7 Packaging Information 7 1 TQFP44 DEE AE SE E 0 09 0 20 ai lt 12 OG BSC re ES p eos oo Tom LEA 10 00 BSC COPLANARITY 07 27 07 TITLE DRAWING No REV Atmel N SA AME thn ee ee ML 44 Lead 10x10 mm Body Size 1 0 mm Body Thickness SmI 44306 Nantes Cedex 3 France 0 8 mm Lead Pitch Thin Profile Plastic Quad Flat Package TQFP ML G AMEL i8 7766FS AVR 11 10 ATmega16 32U4 7 2 QFN44 SEATING PLANE 2 hj 7 Dot lon Option B Oot lon G BOTTOM VIEW Gs ED D CEEA LENEN Pin i Chanfer Pin iF totch Pin 1H lt C D 307 020 Triangle Compliant JEDEC Standard MO 220 variation WKKD 1L AMEL i 7766FS AVR 1 1 10 ees Tmega16 32U4 8 Errata The revision letter in this sec
10. BRANCH INSTRUCTIONS RJMP k Relative Jump PC lt PC k 1 None 2 IJMP Indirect Jump to Z PCez None 2 EIJMP Extended Indirect Jump to Z PC lt EIND Z None 2 JMP Direct Jump PC lt k None 3 RCALL Relative Subroutine Call PC PC k 1 None 4 ICALL Indirect Call to Z PC Z None 4 EICALL Extended Indirect Call to Z PC EIND 2 None 4 CALL k Direct Subroutine Call PC lt k None 5 RET Subroutine Return PC lt STACK None 5 RETI Interrupt Return PC lt STACK l 5 CPSE Rd Rr Compare Skip if Equal if Rd Rr PC lt PC 20r3 None 1 2 3 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry Rd Rr C Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 20r3 None 1 2 3 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 20r3 None 1 2 3 SBIC P b Skip if Bit in I O Register Cleared if P b 0 PC PC 20r3 None 1 2 3 SBIS P b Skip if Bit in I O Register is Set if P b 1 PC PC 20r3 None 1 2 3 BRBS s k Branch if Status Flag Set if SREG s 1 then PC lt PC k 1 None 1 2 BRBC s k Branch if Status Flag Cleared if SREG s 0 then PC lt PC k 1 None 1 2 BREQ k Branch if Equal if Z 1 then PC PC k 1 None 1 2 BRNE k Branch if Not Equal if Z 0 then PC PC k 1 None 1 2 BRCS k Branch if Carry Set if C 1 then PC PC k 1 None 1 2 BRCC k Branch if Carry Cleared if C 0 then PC PC k 1 None 1 2 BRSH k Branch if Same or Highe
11. DIVO 0x31 0x51 hei OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDRO Monitor Data Register 0x30 0x50 ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACISO Ox2F 0x4F Reserved Ox2E 0x4E SPDR SPI Data Register 0x2D 0x4D SPSR SPIF WCOL SPI2X Ox2C 0x4C SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPRO 0x2B 0x4B GPIOR2 General Purpose I O Register 2 Ox2A 0x4A GPIOR1 General Purpose I O Register 1 0x29 0x49 PLLCSR PINDIV PLLE PLOCK 0x28 0x48 OCROB Timer CounterO Output Compare Register B 0x27 0x47 OCROA Timer CounterO Output Compare Register A 0x26 0x46 TCNTO Timer Counter0 8 Bit 0x25 0x45 TCCROB FOCOA FOCOB WGM02 CS02 CSO01 CS00 0x24 0x44 TCCROA COMOA1 COMOAO COMOB1 COMOBO WGMO1 WGM00 0x23 0x43 GTCCR TSM PSRASY PSRSYNC 0x22 0x42 EEARH EEPROM Address Register High Byte 0x21 0x41 EEARL EEPROM Address Register Low Byte 0x20 0x40 EEDR EEPROM Data Register Ox1F 0x3F EECR EEPM1 EEPMO EERIE EEMPE EEPE EERE Ox1E 0x3E GPIORO General Purpose I O Register 0 0x1D 0x3D EIMSK INT6 INT3 INT2 INT1 INTO 0x1C 0x3C EIFR INTF6 INTF3 INTF2 INTF1 INTFO AMEL ti 7766FS AVR 11 10 T ees Tmega16 32U4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1B 0x3B PCIFR 5 E 2 E PCIFO 0x1A 0x3A Re
12. Features e High Performance Low Power AVR 8 Bit Microcontroller Advanced RISC Architecture 135 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On Chip 2 cycle Multiplier Non volatile Program and Data Memories 16 32K Bytes of In System Self Programmable Flash ATmega16U4 ATmega32U4 1 25 2 5K Bytes Internal SRAM ATmega16U4 ATmega32U4 512Bytes 1K Bytes Internal EEPROM ATmega16U4 ATmega32U4 Write Erase Cycles 10 000 Flash 100 000 EEPROM Data retention 20 years at 85 C 100 years at 25 C Optional Boot Code Section with Independent Lock Bits In System Programming by On chip Boot Program True Read While Write Operation All supplied parts are preprogramed with a default USB bootloader Programming Lock for Software Security JTAG IEEE std 1149 1 compliant Interface Boundary scan Capabilities According to the JTAG Standard Extensive On chip Debug Support Programming of Flash EEPROM Fuses and Lock Bits through the JTAG Interface e USB 2 0 Full speed Low Speed Device Module with Interrupt on Transfer Completion Complies fully with Universal Serial Bus Specification Rev 2 0 Supports data transfer rates up to 12 Mbit s and 1 5 Mbit s Endpoint 0 for Control Transfers up to 64 bytes 6 Programmable Endpoints with IN or Out Directions and with Bulk Interrupt o
13. OCIE4B TOIE4 0x71 TIMSK3 ICIE3 OCIE3C OCIE3B OCIE3A TOIE3 0x70 Reserved Ox6F TIMSK1 ICIE1 OCIE1C OCIE1B OCIE1A TOIE1 Ox6E TIMSKO OCIEOB OCIEOA TOIEO 0x6D Reserved Ox6C Reserved 0x6B PCMSKO PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINTO Ox6A EICRB ISC61 ISC60 0x69 EICRA ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISCO1 ISC00 0x68 PCICR PCIEO 0x67 RCCTRL RCFREQ 0x66 OSCCAL RC Oscillator Calibration Register 0x65 PRR1 PRUSB PRTIM4 PRTIM3 PRUSART1 0x64 PRRO PRTWI PRTIMO PRTIM1 PRSPI PRADC 0x63 Reserved 0x62 Reserved 0x61 CLKPR CLKPCE CLKPS3 CLKPS2 CLKPS1 CLKPSO 0x60 WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDPO Ox3F 0x5F SREG l T H S Vv N Z C Ox3E 0x5E SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 0x3D 0x5D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO 0x3C 0x5C Reserved 0x3B 0x5B RAMPZ RAMPZ1 RAMPZO Ox3A 0x5A Reserved 0x39 0x59 Reserved 0x38 0x58 Reserved 0x37 0x57 SPMCSR SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN 0x36 0x56 Reserved 0x35 0x55 MCUCR JTD PUD IVSEL IVCE 0x34 0x54 MCUSR USBRF JTRF WDRF BORF EXTRF PORF 0x33 0x53 SMCR SM2 SM1 SMO SE 0x32 0x52 PLLFRQ PINMUX PLLUSB PLLTM1 PLLTMO PDIV3 PDIV2 PDIV1 P
14. SMI EORSMI WAKEUPI EORSTI SOFI MSOFI SUSPI OxE0 UDCON RSTCPU LSM RMWKUP DETACH OxDF Reserved OxDE Reserved OxDD Reserved OxDC Reserved OxDB Reserved OxDA USBINT VBUSTI 0xD9 USBSTA ID VBUS 0xD8 USBCON USBE FRZCLK OTGPADE VBUSTE 0xD7 UHWCON UVREGE 0xD6 Reserved 0xD5 Reserved 0xD4 DT4 DT4H3 DT4H2 DT4H1 DT4HO DT4L3 DT4L2 DT4L1 DT4LO 0xD3 Reserved 0xD2 OCR4D Timer Counter4 Output Compare Register D 0xD1 OCR4C Timer Counter4 Output Compare Register C 0xDO OCR4B Timer Counter4 Output Compare Register B OxCF OCR4A Timer Counter4 Output Compare Register A OxCE UDR1 USART1 I O Data Register OxCD UBRR1H USART1 Baud Rate Register High Byte OxCC UBRRI1L USART1 Baud Rate Register Low Byte OxCB Reserved OxCA UCSR1C UMSEL11 UMSEL10 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 OxC9 UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 OxC8 UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 PE1 U2X1 MPCM1 0xC7 CLKSTA RCON EXTON OxC6 CLKSEL1 RCCKSEL3 RCCKSEL2 RCCKSEL1 RCCKSELO EXCKSEL3 EXCKSEL2 EXCKSEL1 EXCKSELO OxC5 CLKSELO RCSUT1 RCSUTO EXSUT1 EXSUTO RCE EXTE CLKS OxC4 TCCR4E TLOCK4 ENHC4 OC40E5 OC40E4 OC40E3 OC40E2 OC40E1 OC40E0 OxC3 TCCR4D FPIE4 FPEN4 FPNC4 FPES4 FPAC4 FPF4 WGM41 WGM40 OxC2 TCCR4C COM4A1S COM4A0S COM4B1S COM4B0S COM4D1S COM4DOS FOC4D PWM4D OxC1 TCCR4B PWM4X PSR4 DTPS41 DTPS40 CS43 CS4
15. buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port B pins that are externally pulled low will source current if the pull up resistors are activated The Port B pins are tri stated when a reset condition becomes active even if the clock is not running Port B has better driving capabilities than the other ports Port B also serves the functions of various special features of the ATmega16U4 ATmega32U4 as listed on page 72 2 2 4 Port C PC7 PC6 7766FS AVR 11 10 Port C is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port C output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port C pins that are externally pulled low will source current if the pull up resistors are activated The Port C pins are tri stated when a reset condition becomes active even if the clock is not running AMEL s ees Tmega16 32U4 Only bits 6 and 7 are present on the product pinout Port C also serves the functions of special features of the ATmega16U4 ATmega32U4 as listed on page 75 2 2 5 Port D PD7 PDO Port D is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port D output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port D pins that are externally pulled low will source current if the pull up
16. d Wake up on Pin Change On chip Temperature Sensor e Special Microcontroller Features Power on Reset and Programmable Brown out Detection Internal 8 MHz Calibrated Oscillator Internal clock prescaler amp On the fly Clock Switching Int RC Ext Osc External and Internal Interrupt Sources Six Sleep Modes Idle ADC Noise Reduction Power save Power down Standby and Extended Standby I O and Packages All I O combine CMOS outputs and LVTTL inputs 26 Programmable I O Lines 44 lead TQFP Package 10x10mm 44 lead QFN Package 7x7mm e Operating Voltages 2 7 5 5V Operating temperature Industrial 40 C to 85 C Maximum Frequency 8 MHz at 2 7V Industrial range 16 MHz at 4 5V Industrial range Note 1 See Data Retention on page 8 for details AMEL 2 7766FS AVR 11 10 ees Tmega16 32U4 1 Pin Configurations Figure 1 1 INT 6 AINO PE6 UVcc D D UGnd UCap VBus SS PCINTO PBO PCINT1 SCLK PB1 PDI PCINT2 MOSI PB2 PDO PCINT3 MISO PB3 2 Overview Pinout ATmega16U4 ATmega32U4 Ni AL oF BL wo o ert T a O as O a a Se es HE de i E or XY M O KN
17. he ADC is used it should be connected to Vec through a low pass filter This is the analog reference pin input for the A D Converter AMEL 7 ees Tmega16 32U4 3 About 3 1 Disclaimer 3 2 Resources Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology Min and Max values will be available after the device is characterized A comprehensive set of development tools application notes and datasheets are available for download on http www atmel com avr 3 3 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent Please confirm with the C compiler documen tation for more details These code examples assume that the part specific header file is included before compilation For I O registers located in extended I O map IN OUT SBIS SBIC CBI and SBI instructions must be replaced with instructions that allow access to extended I O Typically LDS and STS combined with SBRS SBRC SBR and CBR 3 4 Data Retention 7766FS AVR 11 10 Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85 C or 100 years at 25 C AMEL e
18. hese reg isters the value of single bits can be checked by using the SBIS and SBIC instructions 3 Some of the status flags are cleared by writing a logical one to them Note that the CBI and SBI instructions will operate on all bits in the I O register writing a one back into any flag read as set thus clearing the flag The CBI and SBI instructions work with registers 0x00 to Ox1F only 4 When using the I O specific commands IN and OUT the I O addresses 00 3F must be used When addressing I O regis 7766FS AVR 11 10 ters as data space using LD and ST instructions 20 must be added to these addresses The ATmega16U4 ATmega32U4 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions For the Extended I O space from 60 1FF in SRAM only the ST STS STD and LD LDS LDD instructions can be used AMEL 12 es Tmega16 32U4 5 Instruction Set Summary Mnemonics Operands Description Operation Flags Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd Rr Add two Registers Rd Rd Rr Z C N V H 1 ADC Rd Rr Add with Carry two Registers Rd Rd Rr C Z C N V H 1 ADIW Rdl K Add Immediate to Word Rdh Rdl Rdh Rdl K Z C N V S 2 SUB Rd Rr Subtrac
19. in sleep mode If a pending interrupt cannot wake the part up from the selected mode the current consump tion will increase during sleep when executing the SLEEP instruction directly after a SEI instruction Problem Fix work around Before entering sleep interrupts not used to wake up the part from the sleep mode should be disabled AMEL 20 AMEL 3 Timer 4 11 bits enhanced PWM mode Timer 4 11 bits enhanced mode is not functional Problem Fix work around None 8 3 ATmega16U4 ATmega32U4 Rev C Not sampled 8 4 ATmega16U4 ATmega32U4 Rev B Spike on TWI pins when TWI is enabled High current consumption in sleep mode Incorrect execution of VBUSTI interrupt Timer 4 11 bits enhanced PWM mode 1 Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled Problem Fix work around Enable ATmega16U4 ATmega32U4 TWI before the other nodes of the TWI network 2 High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode the current consump tion will increase during sleep when executing the SLEEP instruction directly after a SEI instruction Problem Fix work around Before entering sleep interrupts not used to wake up the part from the sleep mode should be disabled 3 Incorrect execution of VBUSTI interrupt The CPU may incorrectly execute the interrupt vector related to the VBUSTI interrupt flag Problem fix work around
20. irect and Pre Dec X lt X 1 Rd lt X None 2 LD Rd Y Load Indirec Rd lt Y None 2 LD Rd Y Load Indirect and Post Inc Rd lt Y Y lt Y 1 None 2 LD Rd Y Load Indirect and Pre Dec Y lt Y 1 Rd lt Y None 2 LDD Rd Y q Load Indirect with Displacement Rd lt Y q None 2 LD Rd Z Load Indirec Rd lt 2 None 2 LD Rd Z Load Indirect and Post Inc Rd lt Z Z lt Z 1 None 2 LD Rd Z Load Indirect and Pre Dec Z lt Z 1 Rd lt Z None 2 LDD Rd Z q Load Indirect with Displacement Rd Z q None 2 LDS Rd k Load Direct from SRAM Rd lt k None 2 ST X Rr Store Indirect X lt Rr None 2 ST X Rr Store Indirect and Post Inc X Rr XX 1 None 2 ST X Rr Store Indirect and Pre Dec X lt X 1 X lt Rr None 2 ST Y Rr Store Indirect Y lt Rr None 2 ST Y Rr Store Indirect and Post Inc Y lt Rr Y lt Y 1 None 2 ST Y Rr Store Indirect and Pre Dec Y lt Y 1 Y lt Rr None 2 STD Y q Rr Store Indirect with Displacement Y q lt Rr None 2 ST Z Rr Store Indirect Z lt Rr None 2 ST Z Rr Store Indirect and Post Inc Z lt lt Rr Z lt Z 1 None 2 ST Z Rr Store Indirect and Pre Dec Z lt Z 1 Z lt Rr None 2 STD Z q Rr Store Indirect with Displacement Z q lt Rr None 2 STS k Rr Store Direct to SRAM k Rr None 2 LPM Load Program Memory RO lt 2 None 3 LPM Rd Z Load Program Memory Rd lt 2 None 3 LPM Rd Z Load Program Memory and Post Inc Rd lt Z Z Z 1 None 3 ELPM Extended Load Program Me
21. ize switching noise during ADC conversions In Standby mode the Crystal Resonator Oscillator is running while the rest of the device is sleeping This allows very fast start up combined with low power consumption The device is manufactured using ATMEL s high density nonvolatile memory technology The On chip ISP Flash allows the program memory to be reprogrammed in system through an SPI serial interface by a conventional nonvolatile memory programmer or by an On chip Boot pro gram running on the AVR core The boot program can use any interface to download the application program in the application Flash memory Software in the Boot Flash section will continue to run while the Application Flash section is updated providing true Read While Write operation By combining an 8 bit RISC CPU with In System Self Programmable Flash on a monolithic chip the ATMEL ATmega16U4 ATmega32U4 is a powerful microcontroller that pro vides a highly flexible and cost effective solution to many embedded control applications The ATmega16U4 ATmega32U4 AVR is supported with a full suite of program and system development tools including C compilers macro assemblers program debugger simulators in circuit emulators and evaluation kits 2 2 Pin Descriptions 2 2 1 VCC 2 2 2 GND Digital supply voltage Ground 2 2 3 Port B PB7 PB0 Port B is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port B output
22. leteness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suit able for and shall not be used in automotive applications Atmel products are not intended authorized or warranted for use as components in applica tions intended to support or sustain life 7766FS AVR 11 10
23. mer Counter1 Output Compare Register A Low Byte 0x87 ICR1H Timer Counter1 Input Capture Register High Byte 0x86 ICR1L Timer Counter1 Input Capture Register Low Byte 0x85 TCNT1H Timer Counter1 Counter Register High Byte 0x84 TCNT1L Timer Counter1 Counter Register Low Byte 0x83 Reserved 0x82 TCCR1IC FOC1A FOC1B FOC1C 0x81 TCCR1B ICNC1 ICES1 WGM13 WGM12 CS12 CS11 CS10 0x80 TCCRIA COM1A1 COM1A0 COM1B1 COM1BO COM1C1 COM1C0 WGM11 WGM10 0x7F DIDR1 AINOD 0x7E DIDRO ADC7D ADC6D ADC5D ADC4D ADC1D ADCOD 0x7D DIDR2 ADC13D ADC12D ADC11D ADC10D ADC9D ADC8D AMEL 10 7766FS AVR 11 10 T ees Tmega16 32U4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x7C ADMUX REFS1 REFSO ADLAR MUX4 MUX3 MUX2 MUX1 MUXO 0x7B ADCSRB ADHSM ACME MUX5 ADTS3 ADTS2 ADTS1 ADTSO 0x7A ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPSO 0x79 ADCH ADC Data Register High byte 0x78 ADCL ADC Data Register Low byte 0x77 Reserved 0x76 Reserved 0x75 Reserved 0x74 Reserved 0x73 Reserved 0x72 TIMSK4 OCIE4D OCIE4A
24. mory RO lt RAMPZ Z None 3 ELPM Rd Z Extended Load Program Memory Rd lt 2 None 3 ELPM Rd Z Extended Load Program Memory Rd RAMPZ Z RAMPZ Z lt RAMPZ Z 1 None 3 7766FS AVR 11 10 AMEL T 14 ees Tmega16 32U4 Mnemonics Operands Description Operation Flags Clocks SPM Store Program Memory Z lt R1 RO None IN Rd P In Port Rd lt P None 1 OUT P Rr Out Port P lt Rr None 1 PUSH Rr Push Register on Stack STACK lt Rr None 2 POP Rd Pop Register from Stack Rd lt STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep see specific description for Sleep function None 1 WDR Watchdog Reset see specific description for WDR timer None 1 BREAK Break For On chip Debug Only None N A AMEL 15 7766FS AVR 11 10 T ees Tmega16 32U4 6 Ordering Information 6 1 ATmega16U4 Speed MHz Power Supply Ordering Code Default Oscillator Package Operation Range ATmega16U4 AU External XTAL rer ATmega16U4RC AU Internal Calib RC 16 2 7 5 5V Industrial 40 to 85 C ATmega16U4 MU External XTAL ads ATmega16U4RC MU Internal Calib RC Package Type ML 44 Lead 10 x 10 mm Body Size 1 0 mm Body Thickness 44ML 0 8 mm Lead Pitch Thin Profile Plastic Quad Flat Package TQFP PW 44 Lead 7 0 x 7 0 mm Body 0 50 mm Pitch 44PW Quad Flat No Lead Package QFN 77
25. on executed in one clock cycle The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con ventional CISC microcontrollers The ATmega16U4 ATmega32U4 provides the following features 16 32K bytes of In System Programmable Flash with Read While Write capabilities 512Bytes 1K bytes EEPROM 1 25 2 5K bytes SRAM 26 general purpose I O lines CMOS outputs and LVTTL inputs 32 general purpose working registers four flexible Timer Counters with compare modes and PWM one more high speed Timer Counter with compare modes and PLL adjustable source one USART including CTS RTS flow control signals a byte oriented 2 wire Serial Interface a 12 AMEL a 7766FS AVR 11 10 es Tmega16 32U4 channels 10 bit ADC with optional differential input stage with programmable gain an on chip calibrated temperature sensor a programmable Watchdog Timer with Internal Oscillator an SPI serial port IEEE std 1149 1 compliant JTAG test interface also used for accessing the On chip Debug system and programming and six software selectable power saving modes The Idle mode stops the CPU while allowing the SRAM Timer Counters SPI port and interrupt system to continue functioning The Power down mode saves the register contents but freezes the Oscillator disabling all other chip functions until the next interrupt or Hardware Reset The ADC Noise Reduction mode stops the CPU and all I O modules except ADC to minim
26. r Isochronous Transfers Configurable Endpoints size up to 256 bytes in double bank mode Fully independent 832 bytes USB DPRAM for endpoint memory allocation Suspend Resume Interrupts CPU Reset possible on USB Bus Reset detection 48 MHz from PLL for Full speed Bus Operation USB Bus Connection Disconnection on Microcontroller Request Crystal less operation for Low Speed mode Peripheral Features On chip PLL for USB and High Speed Timer 32 up to 96 MHz operation One 8 bit Timer Counter with Separate Prescaler and Compare Mode Two 16 bit Timer Counter with Separate Prescaler Compare and Capture Mode One 10 bit High Speed Timer Counter with PLL 64 MHz and Compare Mode Four 8 bit PWM Channels Four PWM Channels with Programmable Resolution from 2 to 16 Bits Six PWM Channels for High Speed Operation with Programmable Resolution from 2 to 11 Bits Output Compare Modulator 12 channels 10 bit ADC features Differential Channels with Programmable Gain Programmable Serial USART with Hardware Flow Control Master Slave SPI Serial Interface AMEL T O 8 bit AVR Microcontroller with 16 32K Bytes of ISP Flash and USB Controller ATmega16U4 ATmega32U4 Preliminary Summary 7766FS AVR 11 10 ees Tmega16 32U4 Byte Oriented 2 wire Serial Interface Programmable Watchdog Timer with Separate On chip Oscillator On chip Analog Comparator Interrupt an
27. r if C 0 then PC PC k 1 None 1 2 BRLO k Branch if Lower if C 1 then PC PC k 1 None 1 2 BRMI k Branch if Minus if N 1 then PC PC k 1 None 1 2 BRPL k Branch if Plus if N 0 then PC PC k 1 None 1 2 BRGE k Branch if Greater or Equal Signed if N V 0 then PC PC k 1 None 1 2 BRLT k Branch if Less Than Zero Signed if N V 1 then PC e PC k 1 None 1 2 BRHS k Branch if Half Carry Flag Set if H 1 then PC PC k 1 None 1 2 BRHC k Branch if Half Carry Flag Cleared if H 0 then PC PC k 1 None 1 2 BRTS k Branch if T Flag Set if T 1 then PC PC k 1 None 1 2 BRTC k Branch if T Flag Cleared if T 0 then PC PC k 1 None 1 2 BRVS k Branch if Overflow Flag is Set if V 1 then PC PC k 1 None 1 2 7766FS AVR 11 10 AMEL T gt 13 ees Tmega16 32U4 Mnemonics Operands Description Operation Flags Clocks BRVC k Branch if Overflow Flag is Cleared if V 0 then PC lt PC k 1 None 1 2 BRIE k Branch if Interrupt Enabled if l 1 then PC e PC k 1 None 1 2 BRID k Branch if Interrupt Disabled if I 0 then PC PC k 1 None 1 2 BIT AND BIT TEST INSTRUCTIONS SBI P b Set Bit in I O Register I O P b 1 None 2 CBI P b Clear Bit in I O Register I O P b 0 None 2 LSL Rd Logical Shif
28. resistors are activated The Port D pins are tri stated when a reset condition becomes active even if the clock is not running Port D also serves the functions of various special features of the ATmega16U4 ATmega32U4 as listed on page 77 2 2 6 Port E PE6 PE2 Port E is an 8 bit bi directional I O port with internal pull up resistors selected for each bit The Port E output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port E pins that are externally pulled low will source current if the pull up resistors are activated The Port E pins are tri stated when a reset condition becomes active even if the clock is not running Only bits 2 and 6 are present on the product pinout Port E also serves the functions of various special features of the ATmega16U4 ATmega32U4 as listed on page 80 2 2 7 Port F PF7 PF4 PF1 PF0 2 2 8 D 2 2 9 D 2 2 10 UGND 7766FS AVR 11 10 Port F serves as analog inputs to the A D Converter Port F also serves as an 8 bit bi directional I O port if the A D Converter channels are not used Port pins can provide internal pull up resistors selected for each bit The Port F output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port F pins that are externally pulled low will source current if the pull up resistors are activated The Port F pins are tri stated when a reset condition becomes acti
29. s on page 1 Updated Features on page 253 Updated Figure 21 9 on page 258 Updated Section 21 8 on page 260 Updated Features on page 292 Updated ATmega16U4 ATmega32U4 Boundary scan Order on page 327 Updated Program And Data Memory Lock Bits on page 346 Updated Table 28 5 on page 348 Updated Electrical Characteristics on page 378 Updated Figure 29 2 on page 381 Added Typical Characteristics on page 386 Updated Ordering Information on page 16 Updated Errata on page 20 Updated Memory section in Features on page 1 Added section Resources on page 8 Added section Data Retention on page 8 Updated Ordering Information on page 16 Updated Memory section in Features on page 1 AMEL 2 AMEL 9 5 Rev 7766B 11 08 1 Added ATmega16U4 device 2 Created errata section and added ATmega16U4 3 Updated High Speed Timer asynchronous description Section 15 on page 139 9 6 Rev 7766A 07 08 1 Initial revision 25 ATmega16 32U4 uuu AIMEL ey Atmel Corporation 2325 Orchard Parkway Atmel Asia Limited Unit 1 5 amp 16 19 F Atmel Munich GmbH Business Campus Atmel Japan 9F Tonetsu Shinkawa Bldg San Jose CA 95131 BEA Tower Millennium City5 Parkring 4 1 24 8 Shinkawa USA 418 Kwun Tong Road D 85748 Garching b Munich Chuo ku Tokyo 104 0033 Tel 1 408 441 0311 Kwun Tong Kowloon GERMANY JAPAN Fax
30. served 0x19 0x39 TIFR4 OCF4D OCF4A OCF4B TOV4 0x18 0x38 TIFR3 ICF3 OCF3C OCF3B OCF3A TOV3 0x17 0x37 Reserved 0x16 0x36 TIFR1 ICF1 OCF1C OCF1B OCF1A TOV1 0x15 0x35 TIFRO OCFOB OCFOA TOVO 0x14 0x34 Reserved 0x13 0x33 Reserved 0x12 0x32 Reserved Ox11 0x31 PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF1 PORTFO 0x10 0x30 DDRF DDF7 DDF6 DDF5 DDF4 DDF1 DDFO OxOF 0x2F PINF PINF7 PINF6 PINF5 PINF4 PINF1 PINFO OxOE 0x2E PORTE PORTE6 PORTE2 OxOD 0x2D DDRE DDE6 DDE2 Ox0C 0x2C PINE PINE6 PINE2 Ox0B 0x2B PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTDO Ox0A 0x2A DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDDO 0x09 0x29 PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PINDO 0x08 0x28 PORTC PORTC7 PORTC6 0x07 0x27 DDRC DDC7 DDC6 0x06 0x26 PINC PINC7 PINC6 0x05 0x25 PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTBO 0x04 0x24 DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDBO 0x03 0x23 PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINBO 0x02 0x22 Reserved 0x01 0x21 Reserved 0x00 0x20 Reserved Note 1 For compatibility with future devices reserved bits should be written to zero if accessed Reserved I O memory addresses should never be written 2 I O registers within the address range 00 1F are directly bit accessible using the SBI and CBI instructions In t
31. t Left Rd n 1 lt Rd n Rd 0 0 Z C N V 1 LSR Rd Logical Shift Right Rd n Rd n 1 Rd 7 lt 0 Z C N V 1 ROL Rd Rotate Left Through Carry Rd 0 lt C Rd n 1 lt Rd n C lt Rd 7 Z C N V 1 ROR Rd Rotate Right Through Carry Rd 7 lt C Rd n lt Rd n 1 C lt Rd 0 Z C N V 1 ASR Rd Arithmetic Shift Right Rd n Rd n 1 n 0 6 Z C N V 1 SWAP Rd Swap Nibbles Rd 3 0 lt Rd 7 4 Rd 7 4 lt Rd 3 0 None 1 BSET s Flag Set SREG s lt 1 SREG s 1 BCLR s Flag Clear SREG s 0 SREG s 1 BST Rr b Bit Store from Register to T T lt Rr b T 1 BLD Rd b Bit load from T to Register Rd b T None 1 SEC Set Carry C lt 1 C 1 CLC Clear Carry c lt 0 C 1 SEN Set Negative Flag Nei N 1 CLN Clear Negative Flag N lt 0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z 0 Z 1 SEI Global Interrupt Enable l amp e1 l 1 CLI Global Interrupt Disable le0 l 1 SES Set Signed Test Flag S lt 1 S 1 CLS Clear Signed Test Flag S 0 S 1 SEV Set Twos Complement Overflow Vel Vv 1 CLV Clear Twos Complement Overflow Ve0 V 1 SET Set T in SREG Tei T 1 CLT Clear T in SREG T lt 0 T 1 SEH Set Half Carry Flag in SREG H lt 1 H 1 CLH Clear Half Carry Flag in SREG H lt 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd Rr Move Between Registers Rd lt Rr None 1 MOVW Rd Rr Copy Register Word Rd 1 Rd Rr 1 Rr None 1 LDI Rd K Load Immediate Rd lt K None 1 LD Rd X Load Indirec Rd lt X None 2 LD Rd X Load Indirect and Post Inc Rd lt X XX 1 None 2 LD Rd X Load Ind
32. t two Registers Rd lt Rd Rr Z C N V H 1 SUBI Rd K Subtract Constant from Register Rd Rd K Z C N V H 1 SBC Rd Rr Subtract with Carry two Registers Rd Rd Rr C Z C N V H 1 SBCI Rd K Subtract with Carry Constant from Reg Rd Rd K C Z C N V H 1 SBIW Rdl K Subtract Immediate from Word Rdh Rdl Rdh Radl K Z C N V S 2 AND Rd Rr Logical AND Registers Rd Rd e Rr Z N V 1 ANDI Rd K Logical AND Register and Constant Rd RdeK ZN V 1 OR Rd Rr Logical OR Registers Rd Rd v Rr ZNV 1 ORI Rd K Logical OR Register and Constant Rd Rdv K Z N V 1 EOR Rd Rr Exclusive OR Registers Rd Rd Rr Z N V 1 COM Rd One s Complement Rd lt OxFF Rd Z C N V 1 NEG Rd Two s Complement Rd lt 0x00 Rd Z C N V H 1 SBR Rd K Set Bit s in Register Rd RdvK Z N V 1 CBR Rd K Clear Bit s in Register Rd lt Rd e OxFF K ZNV 1 INC Rd Increment Rd Rd 1 Z N V 1 DEC Rd Decrement Rd e Rd 1 Z N V 1 TST Rd Test for Zero or Minus Rd lt Rde Rd ZNV 1 CLR Rd Clear Register Rd Rd amp Rd ZNV 1 SER Rd Set Register Rd lt OxFF None 1 MUL Rd Rr Multiply Unsigned R1 RO Rd x Rr Z C 2 MULS Rd Rr Multiply Signed R1 RO Rd x Rr Z C 2 MULSU Rd Rr Multiply Signed with Unsigned R1 RO Rd x Rr Z C 2 FMUL Rd Rr Fractional Multiply Unsigned R1 RO lt Rd x Rr lt lt 1 Z C 2 FMULS Rd Rr Fractional Multiply Signed R1 RO lt Rd x Rr lt lt 1 Z C 2 FMULSU Rd Rr Fractional Multiply Signed with Unsigned R1 RO lt Rd x Rr lt lt 1 Z C 2
33. tion refers to the revision of the ATmega16U4 ATmega32U4 device 8 1 ATmega16U4 ATmega32U4 Rev E e Spike on TWI pins when TWI is enabled High current consumption in sleep mode MSB of OCR4A B D is write only in 11 bits enhanced PWM mode 1 Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled Problem Fix work around Enable ATmega16U4 ATmega32U4 TWI before the other nodes of the TWI network High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected mode the current consump tion will increase during sleep when executing the SLEEP instruction directly after a SEI instruction Problem Fix work around Before entering sleep interrupts not used to wake up the part from the sleep mode should be disabled MSB of OCR4A B D is write only in 11 bits enhanced PWM mode In the 11 bits enhanced PWM mode the MSB of OCR4A B D is write only A read of OCR4A B D will always return zero in the MSB position Problem Fix work around None 8 2 ATmega16U4 ATmega32U4 Rev D e Spike on TWI pins when TWI is enabled High current consumption in sleep mode Timer 4 11 bits enhanced PWM mode 7766FS AVR 11 10 Spike on TWI pins when TWI is enabled 100 ns negative spike occurs on SDA and SCL pins when TWI is enabled Problem Fix work around Enable ATmega16U4 ATmega32U4 TWI before the other nodes of the TWI network High current consumption
34. ve even if the clock is not running Bits 2 and 3 are not present on the product pinout Port F also serves the functions of the JTAG interface If the JTAG interface is enabled the pull up resistors on pins PF7 TDI PF5 TMS and PF4 TCK will be activated even if a reset occurs USB Full speed Low Speed Negative Data Upstream Port Should be connected to the USB D connector pin with a serial 22 Ohms resistor USB Full speed Low Speed Positive Data Upstream Port Should be connected to the USB D connector pin with a serial 22 Ohms resistor USB Pads Ground AMEL e ees Tmega16 32U4 2 2 11 UVCC 2 2 12 UCAP 2 2 13 VBUS 2 2 14 RESET 2 2 15 XTAL1 2 2 16 XTAL2 2 2 17 AVCC 2 2 18 AREF 7766FS AVR 11 10 USB Pads Internal Regulator Input supply voltage USB Pads Internal Regulator Output supply voltage Should be connected to an external capac itor 1uF USB VBUS monitor input Reset input A low level on this pin for longer than the minimum pulse length will generate a reset even if the clock is not running The minimum pulse length is given in Table 8 1 on page 50 Shorter pulses are not guaranteed to generate a reset Input to the inverting Oscillator amplifier and input to the internal clock operating circuit Output from the inverting Oscillator amplifier AVCC is the supply voltage pin input for all the A D Converter channels If the ADC is not used it should be externally connected to Vec If t
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