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NEC Xeon E5-2420 v2

1. Table 8 1 Land Name Sheet 9 of 37 Table 8 1 Land Name Sheet 10 of 37 Land Name Buffer Direction Land Name Buffer Direction Number Number DDR2_DQS_DN 14 H8 SSTL 1 0 DDR2_MA 08 D24 SSTL DDR2_DQS_DN 15 R5 SSTL 1 0 DDR2_MA 09 H24 SSTL DDR2 DQS 0 161 AB5 SSTL 1 0 DDR2 MA 10 F18 SSTL DDR2 DQS DN 17 D32 SSTL DDR2 MA 11 E25 SSTL DDR2_DQS_DP 00 AA38 SSTL 1 0 DDR2_MA 12 F25 SSTL DDR2_DQS_DP 01 P38 SSTL 1 0 DDR2 MA 13 E13 SSTL DDR2_DQS_DP 02 G38 SSTL DDR2_MA 14 D26 SSTL DDR2_DQS_DP 03 B38 SSTL 1 0 DDR2 MA 15 G26 SSTL DDR2 DQS DP 04 E7 SSTL 1 0 DDR2_MA_PAR E18 SSTL DDR2_DQS_DP 05 H7 SSTL 1 0 DDR2_ODT 0 16 SSTL DDR2_DQS_DP 06 5 SSTL 1 0 DDR2_ODT 1 12 SSTL DDR2_DQS_DP 07 5 SSTL 1 0 DDR2_ODT 2 H12 SSTL DDR2_DQS_DP 08 D31 SSTL 1 0 DDR2_ODT 3 E12 SSTL DDR2 DQS DP 09 AB39 SSTL 1 0 DDR2_PAR_ERR_N G25 SSTL DDR2 DQS DP 10 R39 SSTL 1 0 DDR2_RAS_N F17 SSTL DDR2 005 DP 11 H39 SSTL 1 0 DDR2_WE_N F15 SSTL DDR2_DQS_DP 12 B39 SSTL 1 0 DDR23_RCOMP 0 H35 Analog DDR2_DQS_DP 13 D8 SSTL 1 0 DDR23_RCOMP 1 E36 Analog DDR2_DQS_DP 14 G8 SSTL 1 0 DDR23_RCOMP 2 L38 Analog DDR2_DQS_DP 15 R6 SSTL 1 0 DDR3 BA 0 B16 SSTL 0 DDR2_DQS_DP 16 AB6 SSTL 1 0 DDR3 BA
2. 200 10 1 2 Intel Thermal Solution STS100C Passive Active Combination Heat Sink Solution 200 10 1 3 Intel Thermal Solution STS100A Active Heat Sink Solution 201 10 1 4 Intel Thermal Solution STS100P Boxed 25 5 mm Tall Passive Heat Sink Solution 202 10 2 Mechanical Specifications eee eee eaten 203 10 2 1 Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones 203 10 2 2 Boxed Processor Retention Mechanism and Heat Sink Support URS 212 10 3 Fan Power Supply STS100C and 5 5100 212 10 3 1 Boxed Processor Cooling Requirements 24 2 2 4 213 10 3 1 1 STS100C Passive Active Combination Heat Sink Solution 213 10 3 1 2 STS100A Active Heat Sink Solution Pedestal only 213 10 3 1 3 STS100P 25 5mm Passive Heat Sink Blade 10 20 Rack 214 10 4 Boxed Processor lt ene sene nen 216 Figures 1 1 Processor Two Socket Platform 14 1 2 PCI Express Lane Partitioning and Direct Media Interface Gen 2 DMI2 17 2 1 PCI Express Layering Dlagralm iere Ex meer era EE dens CEPR UR EVE 25 2 2 Packet F
3. eere Deuda S d Pla FE RUE 75 225 152 Interpretation so voip itx emere gae e MER tug 76 2 5 7 3 Temperature 76 2 5 7 4 Reserved 5 76 3 Technologies eere e rens ek al vdd Feud 77 3 1 Intel Virtualization Technology Intel VT sss 77 3 5 1 Objectives enge lacer Fee eb Peers vendre d dados 77 3 1 2 Intel VT x 78 3 1 3 Intel VT d 78 3 1 3 1 Intel VT d Features 79 3 1 4 Intel Virtualization Technology Processor Extensions 79 3 2 Security Technologies noit a EE REA xa 79 3 2 1 Intel Trusted Execution 79 3 2 2 Intel Trusted Execution Technology Server Extensions 80 ccu cma Em 80 3 2 4 Execute Disable eie eie des cre dee iu 81 3 3 Key mde 81 3 4 Intel OS G ard 81 3 5 Intel Hyper Threading Technology memes 81 3 6 Intel Turbo Boos
4. 210 10 12 4 Pin Base Baseboard Fan Header For Active Heat 211 10 13 Fan Cable Connector Pin Out For 4 Pin Active Thermal Solution 213 Tables 1 1 Code Name to Product Family Name eee eee emen 13 1 2 Volume Structure and 5 E uE NE ENNER EDEN sene nemen se nnn 13 1 3 Related Documents and 5 5 22 2 1 Summary of Processor specific 29 2 2 Minor Revision Number IH e e emen 32 2 3 GetTemp Response 11 emnes eene enne nenas 34 2 4 RdPkgConfig Response Definition nme 35 2 5 WrPkgConfig Response 1 1 1 0 37 2 6 RdPkgConfig amp WrPkgConfig DRAM Thermal Power Optimization Services SUMMAY Debe bebe dede sek erat upr ee debiti n 38 2 7 Channel amp DIMM Index 40 2 8 RdPkgConfig amp WrPkgConfig CPU Thermal and Power Optimization Services Sumtalbyau ss siestbex geben ute auxit
5. 27 2 2311 DMI2 Error FlOW 27 2 3 2 Processor PCH Compatibility 27 2 3 3 DMI2 Link E ME 27 2 4 Intel QuickPath Interconnect Intel nnne 28 2 5 Platform Environment Control Interface PECI cesses 29 2 5 1 Client Capabilities 29 2 5 1 1 Thermal 30 2 5 1 2 Platform Manageability 00100 30 2 5 2 Client Command Suite sedere drawer pergens awe 30 2 572 MERE JI RT 30 2 5 2 2 GetDIB cere RR ERE EI NIME 31 2 5 2 3 GetTemp uiii ode Reese ap RM sx M PUR DM 33 2 5 2 4 RdPkgConftig ettet einen a a E i 34 2 52 5 WrPkgConfig seed cioe ced ei e er E YER cen 35 2 5 2 6 Package Configuration Capabilities 37 2 5 2 7 5 s cei coc nime eter e epe ie gode nua petiere lei 59 25 28 RdPCI Gonfig cierto Dt ee D AN DA 63 2 5 2 9 RdPCIConfigLocal 64 2 5 2 10 WrPClGontiglocal hn er ER UT 66 2 5 3 Client Management oiii tix pex
6. eee ened 89 42 4 CaStates CRGA OUR AER a ene RD n kc RR naan 90 4 2 4 1 Core 5 rori oiire Gan die len Corda x dn a eru Ebr ERA 90 42 4 2 Core CI CIE State ies iterari caa aad CORR 90 4 2 4 3 Core State eene av A EE A EE 91 Intel Xeon Processor E5 2400 v2 Product Family 4 Datasheet Volume One 4 2 4 4 Core 91 4 2 4 5 Delayed Deep 5 0 91 4 25 Package C 5tates coco o Tesi Fw de Pav usto e paca eis 91 4 2 5 1 Package eed eee rx enn quera et Ra ERE ROC ORE i E FLUR sue 93 4252 Package CLE ie aps ec iae s e Dre Pages 93 4 2 5 3 Package C2 State memes ens 94 4 2 5 4 Package State ka dea reat da 94 4 2 5 5 Package State 94 4 2 6 Package C State Power Specifications 95 4 2 7 Processor Pmax Power Specifications 95 4 3 System Memory Power 96 4 3 1 CRE neat ect n kno EC eee Rr thm 96
7. 130 7 3 VR12 0 Reference Code Voltage Identification VID 130 7 4 Signal Description Buffer 5 132 7 5 Signal Groups ics E ER PEE ee 132 7 6 Signals with On Die Termination 135 7 7 Power On Configuration Option Lands sss 1 135 7 8 Fault Resilient Booting Output Tri State Signals 136 7 9 Processor Absolute Minimum and Maximum 5 137 7 10 Storage Condition Ratings 138 7 11 Voltage Specification iiie RES ERR ERE R ER PERRA AR ER 139 7 12 Processor Supply Current Specifications 140 7 13 Processor VCC Static and Transient Tolerance 140 7 14 VCC Overshoot 5 5 143 7 15 DDR3 DDR3L Signal DC 5 144 7 16 PECI DC SpeciflCabiO is cereo mite s E 146 7 17 System Reference Clock BCLK 0 1 DC 146 7 18 SMBUS DC SpecifiCablOFs RXEREARK RA REGN eee 147 7 19 J
8. RR RU RUE ME ROUEN UR KU 19 135 Jntel amp iioc eee eder Poen wee eb edet 19 1 4 Thermal Management Support 19 1 5 Package SUMMAN e oorr rerit eoe RR DR RUM EFE 20 1 6 UU 20 1 7 Related DOCUMENKS 22 1 8 Statement of Volatility 5 2 440 2 2 4 4 44 5 23 1 State Of A 23 2 Pande aca 24 2 1 System Memory 2 2 REA A 24 2 1 1 System Memory Technology Support 24 2 1 2 System Memory Timing 5 24 2 2 PCI Express Interface Dens ilar MCA P KE Fr 25 221 Express ArchitectUre cheney 25 2 2 1 1 Transaction b bee bed a Fa diana 26 2 2 1 2 Data LINK Layer screen estin LEE dub ade 26 2 2 1 3 Physical Layer rael 26 2 2 2 PCI Express Configuration 2 2 27 2 3 DMI2Z PCI Express Interface ort
9. PSI Minimum Maximum Maximum Count C W C o o Tease Tease LV70W 10C 10 50 0 65 0 0 383 5 0 76 8 91 8 LV60W 8C 8 52 0 67 0 0 369 5 0 74 1 89 1 LV60W 6C 15 6 52 0 67 0 0 383 5 0 75 0 90 0 LV50W 6C 6 52 0 67 0 0 505 5 0 77 2 92 2 LV40W 2C 15 2 52 0 67 0 0 612 5 0 76 5 91 5 Embedded Case Temperature Thermal Profile Short Term Profile operation during excursions to higher ambient temperature not to exceed 360 hours per year a 5 case PSl P T ast 2 dam E H T ast 51 Nominal Short 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Embedded Digital Thermal Sensor DTS thermal profiles The thermal solution is expected to be developed in accordance with the Tcase thermal profile Operational compliance monitoring of thermal specifications and fan speed modulation may be done via the DTS based thermal profile Each DTS thermal profile is unique to each TDP and core count combination These Tprs profiles are fully defined by the simple linear equation Tprs PSI pa P TLA Where PSI pa is the Processor to Ambient thermal resistance of the processor thermal solution 105 Datasheet Volume One intel designates the Local Ambient temperature for Short Term operation is the Local Ambient temperature for the Nominal thermal profile
10. STATUS Read OxOOFF CPU consumed by just Csr ppo_ENERGY_STATUS package the VCC power plane MSR 611h PACKAGE_ENERGY_STATUS CSR STATUS Power Limit for 25 0x0000 N A Power Limit Data Program power limit MSR 638h POWER LIMIT the VCC Power for VCC power plane CSR PPO POWER LIMIT Plane Write x Power Limit for 25 0x0000 Power Limit N A Read power limit MSR 638h PPO_POWER_LIMIT the VCC Power Data data for VCC power CSR PPO POWER LIMIT Plane Write plane 26 0x0000 N A Power Limit 1 Write power limit MSR 610h Limits For Data data 1 in multiple PACKAGE_POWER_LIMIT Multiple Turbo turbo mode CSR PACKAGE_POWER_LIMIT Modes 27 0 0000 Power Limit 2 Write power limit MSR 610h Limits For Data data 2 in multiple PACKAGE_POWER_LIMIT Multiple Turbo turbo mode CSR PACKAGE_POWER_LIMIT Modes 26 0 0000 Power Limit 1 N A Read power limit 1 MSR 610h Limits For Data data in multiple PACKAGE_POWER_LIMIT Multiple Turbo turbo mode CSR PACKAGE_POWER_LIMIT Modes E E Package Power 27 0x0000 Power Limit 2 N A Read power limit 2 MSR 610h Limits For Data data in multiple PACKAGE POWER LIMIT Multiple Turbo turbo mode CSR PACKAGE POWER LIMIT Modes m 08 OxOOFF Accumulated Read the total time CS
11. tel Figure 4 1 Figure 4 2 4 2 3 Idle Power Management Breakdown of the Processor Cores Thread 0 Thread 1 Thread 0 Thread 1 Core 0 State Core N State Processor Package State Thread and Core C State Entry and Exit MWAIT C1 27 MWAIT C6 Read MWAIT C3 P_LVL2 1 0 Read 7 k ar MWAIT C1 HLT C1E Ej dh gt gt C While individual threads can request low power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from CO is required before entering any other C state Requesting Low Power Idle States The core C state will if all actives cores have also resolved a core C1 state or higher The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub state hints and the HLT instruction for C1 However software may make C state requests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P_LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions via 1 reads Intel Xeon Processor E5 2400 v2 Product Family 89 Datasheet Volume One intel Note
12. COMP Resistance 128 7 130 131 3 Q 9 12 DDR23 RCOMP 1 COMP Resistance 25 839 26 1 26 361 Q 9 12 DDR23 RCOMP 2 COMP Resistance 198 200 202 Q 9 12 DDR3 Miscellaneous Signals Input Low Voltage 0 55 VCCD V 2 3 DRAM PWR OK C 01 23 0 2 11 13 Input High Voltage 0 55 VCCD V 2 4 5 DRAM_PWR_OK_C 01 23 0 3 11 13 Notes 1 Unless otherwise noted all specifications in this tab 2 The voltage rail Vccp which will be set to 1 50 V or 1 35 V nominal depending on the vo processor e apply to all processor frequencies 3 is the maximum voltage level at a receiving agent that will be interpreted as a logical low value 4 is the minimum voltage level at a receiving agent that will be interpreted as a logical high value 5 and Voy may experience excursions above However input signal drivers must comply with the signal quality specifications Refer to Section 7 9 6 This is the pull down driver resistance Refer to processor signal integrity models for I V characteristics Reset drive does not have a termination 7 Ryrr is the termination the DIMM and not controlled by the processor Please refer to the applicable DI MM datasheet 8 The minimum and maximum values for these signals are programmable by BIOS to one of the pairs See Intel Xeon Processor E5 1600 2400 2600 4600 and Intel Xeon Processor E5 1600 2400 2600 4600 v2 Product Families System Agent BIOS Spec
13. Symbol Parameter Min Max Units Notes Vit Input Low Voltage 0 3 Vrr V Input High Voltage 0 7 VIT V Vuysteresis Hysteresis 0 1 VIT V VoL Output Low Voltage 0 2 VrT V Buffer Resistance 4 14 Q IL Leakage Current 50 200 uA Output Edge Rate 50 ohm to between Vi 0 05 0 6 V ns and Table 7 19 TAP Signals DC Specifications Symbol Parameter Min Max Units Notes Input Low Voltage 0 3 V V Input High Voltage 0 7 Vir V Input Low Voltage 0 4 V V Input High Voltage PREQ 0 8 VrT V VoL Output Low Voltage 0 2 V V Vuysteresis Hysteresis 0 1 V Buffer On Resistance 4 14 Q BPM_N 7 0 PRDY_N TDO Input Leakage Current 50 200 Input Edge Rate 0 05 V ns 1 2 Signals BPM_N 7 0 EAR_N PREQ_N TCK TDI TMS TRST_N Output Edge Rate 50 ohm to 0 2 1 5 V ns 1 Signal BPM_N 7 0 PRDY_N TDO Note 1 These signals are measured between VIL 2 The signal edge rate must be met or the signal must transition monotonically to the asserted state Table 7 20 Serial VID Interface SVID DC Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Units Notes CPU I O Voltage 3 1 0 VTT 3 V Input Low Voltage 0 4 Vir V 1 Signals SVIDDATA SVIDALERT N Input High Voltage 0 7 V 1 Signals SVIDDATA SVIDALERT N VoL Output Low Voltage 0 3 V 1 Signals SVIDCLK SVIDDATA V Hysteresis Hyste
14. Revision Description Revision Date Number 001 Initial Release January 2014 002 Added Protected Processor Inventory Number PPIN January 2014 Intel Xeon Processor E5 2400 v2 Product Family 11 Datasheet Volume One Intel Xeon Processor 5 2400 v2 Product Family Datasheet Volume One 12 Overview 1 intel Overview 1 1 Introduction Datasheet Volume One provides DC specifications land and signal definitions and an overview of additional processor feature interfaces This document is intended to be distributed as a part of a document set The structure and scope of the volumes are provided in Table 1 2 Table 1 1 Code Name to Product Family Name Code Name Product Family IVB EN Intel Xeon processor E5 2400 v2 product family The Intel Xeon processor E5 2400 v2 product family is the next generation of 64 bit multi core enterprise processors built on 22 nanometer process technology Throughout this document the Intel Xeon processor E5 2400 v2 product family may be referred to as simply the processor Based on the low power high performance processor microarchitecture the processor is designed for a two chip platform as opposed to the traditional three chip platforms processor and ICH The two chip platform consists of a processor and the Platform Controller Hub PCH and enables higher performance easier validation and improved
15. Icc A V Vcc V Notes 0 VID 0 015 VID 0 000 VID 0 015 1 2 3 4 5 VID 0 009 VID 0 006 VID 0 021 1 2 3 4 Intel Xeon Processor E5 2400 v2 Product Family 140 Datasheet Volume One Table 7 13 Processor VCC Static and Transient Tolerance Sheet 2 of 2 Icc A Vcc V Vcc V Vcc Notes 10 VID 0 003 VID 0 013 VID 0 028 1 2 3 4 15 VID 0 004 VID 0 019 VID 0 034 1 2 3 4 20 VID 0 010 VID 0 025 VID 0 040 1 2 3 4 25 VID 0 016 VID 0 031 VID 0 046 1 2 3 4 30 VID 0 023 VID 0 038 VID 0 053 1 2 3 4 35 VID 0 029 VID 0 044 VID 0 059 1 2 3 4 40 VID 0 035 VID 0 050 VID 0 065 1 2 3 4 45 VID 0 041 VID 0 056 VID 0 071 1 2 3 4 50 VID 0 048 VID 0 063 VID 0 078 1 2 3 4 55 VID 0 054 VID 0 069 VID 0 084 1 2 3 4 60 VID 0 060 VID 0 075 VID 0 090 1 2 3 4 65 VID 0 066 VID 0 081 VID 0 096 1 2 3 4 70 VID 0 073 VID 0 088 VID 0 103 1 2 3 4 75 VID 0 079 VID 0 094 VID 0 109 1 2 3 4 80 VID 0 085 VID 0 100 VID 0 115 1 2 3 4 85 VID 0 091 VID 0 106 VID 0 121 1 2 3 4 90 VID 0 098 VID 0 113 VID 0 128 1 2 3 4 95 VID 0 104 VID 0 119 VID 0 134 1 2 3 4 100 VID 0 110 VID 0 125 VID 0 140 1 2 3 4 105 VID 0 116 VID 0 131 VID 0 146 1 2 3 4 110 VID 0 123 VID 0 138 VID 0 153 1 2 3 4 11
16. t E 3 e SE 157 ele Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 208 Boxed Processor Specifications Figure 10 10 Boxed Processor Heat Sink Volumetric 2 of 2 F j E 22 28 _ T is im 5 22 mj gm K ms 5 5 Se a E E 5 BOE N TON C S ae M 7 um m E Q1 ER m Intel Xeon Processor E5 2400 v2 Product Family 209 Datasheet Volume One intel Boxed Processor Specifications Figure 10 11 4 Pin Fan Cable Connector For Active Heat Sink Ws 15 34 5812833101 ONY ANINOISNIMIA v 09 810 JO ALIM EVMHYAS 10 mORINIA TIVHS 1894 0348181 42210 TI YN 140103 NOIN 710183100 1 3108 UNS 1992000 a 0T 0 MUNA n 1914 43912109 2 072 1 vs 6 X6 1 210 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One intel Boxed Processor
17. 15 VCC PWR AM20 VSS GND AN16 VCC PWR AM21 VCC PWR AN17 VSS GND AM22 VCC PWR AN18 VCC PWR 23 196 GND mo VCC PWR Intel Xeon Processor E5 2400 v2 Product Family 179 Datasheet Volume One Processor Land Listing intel Table 8 2 Land Number Sheet 11 of 37 Table 8 2 Land Number Sheet 12 of 37 Palco Land Name 2 Direction bs Land Name rc Direction AN2 QPI1 0 1071 Intel 15 VCC PWR AN20 VSS GND AP16 VCC PWR AN21 VCC PWR AP17 VSS GND AN22 PWR AP18 VCC PWR AN23 vss GND AP19 PWR AN24 PWR AP2 QPI1 DRX DP 05 Intel QPI 25 PWR AP20 VSS GND AN26 vss GND AP21 VCC PWR AN27 PWR AP22 PWR AN28 PWR AP23 VSS GND AN29 VSS GND AP24 VCC PWR AN3 QPI1_DRX_DP 07 Intel QPI 25 VCC PWR AN30 BCLK1_DP CMOS AP26 VSS GND AN31 vss GND AP27 PWR AN32 RSVD AP28 VCC PWR AN33 RSVD AP29 VSS GND AN34 RSVD AP3 PWR AN35 PWR AP30 PEHPSDA ODCMOS AN36 RSVD AP31 RSVD AN37 1 0 AP32 RSVD AN38 VSS GND AP33 PWR AN39 PE3B TX DN 5 PCIEX3 4 PWR AN4 vss GND AP35 VITA PWR 40 PE3B TX DP 5 PCIEX3 AP36 RSVD AN41 VSA PWR AP37 RSVD AN42 PE3C_TX_DN 11 PCIEX3 AP38 PE3B TX DN 6 PCIEX3 AN43 PE3C TX DP 11 PCIEX3 AP39 PE3B TX DP 6 PCIEX3 5 QPI1 DP 08 Intel QPI
18. 55 GND R9 DDR1 DQS DP 14 SSTL 4 DDR1_DQ 14 SSTL T1 DDR3_DQS_DN 16 SSTL 35 DDR1 DQS DN 01 SSTL 10 VSS GND P36 DDR1 DQS DP 01 SSTL T11 VCC PWR P37 VSS GND T2 DDR3_DQS_DP 16 SSTL P38 DDR2_DQS_DP 01 SSTL 1 0 T3 DDR3 005 DN 07 SSTL 1 0 P39 DDR2_DQS_DN 01 SSTL T33 VCC PWR P4 VSS GND T34 VSS GND P40 VSS GND T35 DDR1_DQ 08 SSTL 41 DDR3_DQ 10 SSTL 136 DDR1_DQ 09 SSTL 42 DDR3_DQ 15 SSTL 137 VSS GND P43 DDR3_DQ 14 SSTL 138 DDR2 001091 SSTL 5 DDR2_DQ 49 SSTL 39 DDR2_DQ 08 SSTL 6 DDR2_DQ 48 SSTL T4 VSS GND P7 VSS GND 40 VSS GND P8 DDR1 DQ 41 SSTL 141 DDR3_DQS_DP 10 SSTL 9 DDR1_DQ 45 SSTL 142 VSS GND R1 DDR3 DQ 57 SSTL T43 DDR3_DQ 09 SSTL R10 VSS GND 5 DDR2_DQS_DP 06 SSTL R11 VCC PWR T6 DDR2 005 DN 06 SSTL R2 DDR3 DQ 56 SSTL 7 VSS GND R3 DDR3 DQ 61 SSTL T8 DDR1_DQS_DP 05 SSTL R33 VCC PWR T9 DDR1_DQS_DN 05 SSTL 1 0 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 191 Processor Land Listing tel Table 8 2 Land Number Sheet 35 of 37 Table 8 2 Land Number Sheet 36 of 37 Land Direction
19. nemen meme 102 5 2 Digital Thermal Sensor DTS Thermal Profile sss 103 5 3 Embedded Case Temperature Thermal 105 5 4 Embedded DTS Thermal 000 1 107 5 5 Case Temperature TCASE Measurement Location 108 5 6 Frequency and Voltage 1 neta 111 7 1 Input Device Hysteresis cored a taken DUE ARR RACER RUE AKA 125 7 2 VR Power State Transitions sss s meme sen emen nnn 130 7 3 VCC Static and Transient Tolerance 142 7 4 Load Current Versus Time 143 7 5 Overshoot Example 1 144 7 6 0 1 Differential Clock Crosspoint Specification 150 7 7 BCLK 0 1 Differential Clock Measurement Points for Duty Cycle and Period 151 7 8 BCLK10 1 Differential Clock Measurement Points for Edge 151 7 9 0 1 Differential Clock Measurement Point for Ringback 151 7 10 BCLK 0 1 Single Ended Clock Measurement Points for Absolute Cross Point NEU 152 7 11 BCLK 0 1 Single Ended Clock Measurement Po
20. E A Sali 45 2 9 Power Control Register Unit 50 2 10 RdIAMSR Response 1 nemen meme nnne nn nnn 61 2 11 RdlAMSR Services Summary 62 2 12 RdPCIConfig Response Definition 1 64 2 13 RdPCIConfigLocal Response Definition 41 66 2 14 WrPCIConfigLocal Response 1 nn 67 2 15 WrPClConfigLocal Memory Controller and Device Function Support 68 2 16 Client Response During 010 69 2 17 ID 5 70 2 18 Power Impact Commands vs C states 70 2 19 Domain ID keen EE Er Ferd s 73 2 20 Multi Domain Command Code Reference 73 2 21 Completion Code Pass Fail 2 2 022 1011 74 2 22 Device Specific Completion Code CC 4 74 2 23 Originator Response Guidelines memes
21. 4 DDR2_ECC 5 SSTL 04 55 GND E35 DDR2_ECC 4 SSTL 040 55 GND E36 DDR23_RCOMP 1 Analog 041 DDR3_DQ 31 SSTL 7 DDR2_DQ 27 SSTL 042 DDR3 DQS DP 03 SSTL 1 0 E38 DDR2_DQ 28 SSTL 1 0 D43 DDR3 005 DN 03 SSTL 1 0 E39 DDR2_DQ 29 SSTL 1 0 D5 DDR2_DQ 35 SSTL 4 VSS GND D6 DDR2_DQ 38 SSTL 1 0 E40 VSS GND D7 DDR2_DQS_DN 04 SSTL 41 DDR3 DQ 25 SSTL D8 DDR2 DQS DP 13 SSTL 1 0 E42 DDR3 DQS DN 12 SSTL 1 0 09 DDR2_DQ 32 SSTL E43 DDR3_DQS_DP 12 SSTL El DDR3 DQS DN 14 SSTL 5 DDR2_DQ 34 SSTL 10 DDR2_DQ 37 SSTL E6 DDR2_DQ 39 SSTL 11 VSS GND E7 DDR2_DQS_DP 04 SSTL 12 DDR2 ODT 3 SSTL 8 DDR2_DQS_DN 13 SSTL 1 DDR2 MA 13 SSTL 0 E9 DDR2_DQ 33 SSTL 14 DDR2 CS N 5 SSTL 1 DDR3_DQS_DP 05 SSTL 1 0 E15 DDR2_CS_N 4 SSTL 10 VSS GND E16 VSS GND 11 DDR2_CS_N 2 SSTL E17 DDR2 BA O0 SSTL 0 12 DDR2_ODT 1 SSTL E18 DDR2_MA_PAR SSTL 1 DDR2_CAS_N SSTL E19 DDR2_CLK_DN 0 SSTL 0 F14 VCCD PWR E2 DDR3 DQS DP 14 SSTL 1 0 F15 DDR2_WE_N SSTL E20 DDR2_CLK_DP 0 SSTL 0 F16 DDR2_ODT 0 SSTL 1 vcb DDR2 RAS N SSTL Intel Xeon Processor E5 2400 v2 Product Family 186 Datasheet Volume One Processor Land Listing intel Table 8 2 Land Number Sheet 25 of 37 Ta
22. Land 7 Direction abs Land Name zi Direction AL29 vss GND AM24 VCC PWR AL3 QPI1_DRX_DP 11 Intel QPI 25 VCC PWR AL30 RSVD AM26 VSS GND AL31 PE_RBIAS PCI EX3 1 0 AM27 VCC PWR AL32 PE_RBIAS_ SENSE PCIEX3 28 VCC PWR AL33 ERROR_N 2 ODCMOS 29 VSS GND AL34 ERROR N 0 ODCMOS CPU_ONLY_RESET ODCMOS 1 0 AL35 VSS GND AM30 BCLK1 DN CMOS AL36 DMI_TX_DN 1 PCIEX 1 5 _ AL37 DMI_TX_DP 1 PCIEX 2 PCIEX3 1 0 AL38 VSA PWR AM33 VSS GND AL39 PE3A_TX_DN 3 PCIEX3 AM34 ERROR N 1 ODCMOS AL4 vss GND AM35 40 TX DP 3 PCIEX3 AM36 DMI_TX_DP 0 PCIEX AL41 VSA PWR AM37 VSA PWR AL42 PE3C_TX_DN 9 PCIEX3 8 PE3B_TX_DN 4 PCIEX3 AL43 PE3C_TX_DP 9 PCIEX3 9 PE3B_TX_DP 4 PCIEX3 AL5 QPI1 CLKRX DN Intel AM4 QPI1 DRX DP 10 Intel AL6 QPI1 CLKRX DP Intel AM40 VSS GND AL7 SVIDALERT_N CMOS 41 PE3C_TX_DN 10 PCIEX3 AL8 vss GND AM42 PE3C_TX_DP 10 PCIEX3 AL9 RSVD AM43 VSS GND AM1 QPI1_DRX_DN 09 Intel QPI 5 QPI1 DRX DN 10 Intel 10 VSS GND AM6 VSS GND AM11 _ 7 ODCMOS 1 0 AM7 SVIDCLK ODCMOS 12 TDI CMOS 8 RSVD AM13 QPI_VREF_CAP Intel QPI 1 0 9 RSVD AM14 RSVD AN1 vss GND 15 VCC PWR AN10 BPM_N 6 ODCMOS 1 0 AM16 VCC PWR AN11 BPM_N 3 ODCMOS 1 0 AM17 vss GND AN12 VSS GND AM18 VCC PWR AN13 VSS GND AM19 VCC PWR AN14 RSVD AM2 QPI1_DRX_DP 09 Intel
23. CC 0x83 8F Reserved CC 0x90 Unknown Invalid Illegal Request CC 0x91 PECI control hardware firmware or associated logic error The processor is unable to process the request CC 0x92 9F Reserved Intel Xeon Processor E5 2400 v2 Product Family 74 Datasheet Volume One Note 2 5 6 Table 2 23 2 5 7 2 5 7 1 intel The codes explicitly defined in Table 2 22 may be useful in PECI originator response algorithms Reserved or undefined codes may also be generated by a PECI client device and the originating agent must be capable of tolerating any code The Pass Fail mask defined in Table 2 21 applies to all codes and general response policies may be based on this information Refer to Section 2 5 6 for originator response policies and recommendations Originator Responses The simplest policy that an originator may employ in response to receipt of a failing completion code is to retry the request However certain completion codes or FCS responses are indicative of an error in command encoding and a retry will not result in a different response from the client Furthermore the message originator must have a response policy in the event of successive failure responses Refer to Table 2 22 for originator response guidelines Refer to the definition of each command in Section 2 5 2 for a specific definition of possible command codes or FCS responses for a given command The following response policy
24. EAR N 68 Intel Xeon Processor E5 2400 v2 Product Family 3 Datasheet Volume One 2 5 3 1 68 2 5 3 2 Device Discovery 1 69 2 5 3 3 Client Addressing eie ere tem 69 2 5 3 4 CESLatGS eere PR ERU URB regs 70 2 5 2 SASLACCS 71 2 5 3 6 Processor Reset escis o RE KERN IR ER RR d 71 2 5 3 7 System Service Processor SSP Mode 71 2 5 3 8 Processor Error 72 2 5 3 9 Originator Retry and Timeout Policy 72 2 5 3 10 Enumerating Client Capabilities 73 2 5 4 Multi Domain Commands 73 2 5 5 Client 1 2 eene ener rne nnn nnn 74 2 5 5 1 Abort osea I 74 2 5 5 2 Completion 04 5 rerums xt E user FERMER MM RES 74 2 5 6 Originator RESPONSES scis OUR CHR eens martes A DNE d 75 2 5 7 DTS Temperature Data eerie bx hA RUN ERE CIA ER E 75 2 5 7
25. The RdIAMSR command will complete normally unless the targeted core is C state that is C3 or deeper The PECI client will respond with a completion code of 0x82 see Table 2 22 for definition for RdIAMSR accesses in core C states that are C3 or deeper The RdPCI ConfigLocal WrPCI ConfigLocal and RdPCI Config commands will not impact the core C states but may have a measurable impact on the package C state The PECI client will successfully return data without impacting package C state if the resources needed to service the command are not in a low power state f the resources required to service the command are in a low power state the PECI client will respond with a completion code of 0x82 see Table 2 22 for definition If this is the case setting the Wake on PECI mode bit as described in Section 2 5 2 6 can cause a package pop up to the C2 state and enable successful completion of the command The exact power impact of a pop up to C2 will vary by product SKU the C state from which the pop up is initiated and the negotiated PECI bit rate Table 2 18 Power Impact of PECI Commands vs C states Sheet 1 of 2 Command Power I mpact Ping Not measurable GetDI B Not measurable GetTemp Not measurable RdPkgConfig Not measurable WrPkgConfig Not measurable RdIAMSR Not measurable PECI client will not return valid data in core C state that is C3 or deeper
26. DP 16 4 Intel 1 DTX DP 14 7 Intel 1 DP 17 AH2 Intel QPI QPI1 DTX DP 15 AY4 Intel QPI QPI1 181 AG5 Intel QPI1_DTX_DP 16 AW6 Intel QPI 1 DRX DP 19 AG3 Intel 1 DTX DP 17 AW3 Intel QPI1 DTX 00 AW14 Intel QPI QPI1_DTX_DP 18 AV5 Intel QPI QPI1 DTX 01 1 Intel QPI1 DTX DP 19 AV2 Intel QPI QPI1 DTX DN 02 AU13 Intel RESET_N AU2 CMOS QPI1 DTX DN 03 AW12 Intel 0 RSVD AP37 QPI1_DTX_DN 04 AT12 Intel QPI 0 RSVD AT39 QPI1_DTX_DN 05 AY11 Intel QPI 0 RSVD AU6 QPI1 DTX DN 06 AU11 Intel QPI RSVD AV42 QPI1 DTX DN 07 AW10 Intel RSVD AR8 QPI1 DTX DN 08 AT10 Intel RSVD QPI1 DTX DN 09 AW8 Intel QPI RSVD N4 QPI1 DTX DN 10 09 Intel RSVD AR7 QPI1 DTX DN 11 AY7 Intel RSVD AN34 QPI1 DTX DN 12 AT8 Intel RSVD AN33 QPI1 DTX DN 13 4 Intel RSVD AN36 QPI1 DTX DN 14 AU7 Intel RSVD AP36 QPI1 DTX DN 15 AY3 Intel RSVD AH11 QPI1 DTX DN 16 AW5 Intel 0 RSVD AG10 QPI1_DTX_DN 17 AW2 Intel QPI RSVD AK10 QPI1 DTX DN 18 AV4 Intel QPI RSVD AM9 QPI1_DTX_DN 19 AV1 Intel QPI 0 RSVD AK11 QPI1_DTX_DP 00 AY14 Intel QPI 0 RSVD AL9 QPI1_DTX_DP 01 BA13 Intel QPI 0 RSVD 10 QPI1 DTX DP 02 AV13 Intel RSVD AG9 Intel Xeon Processor E5 2400 v2 Product Family 1
27. 10 CTL2 0 0 0 0444 1 32 17 0 0 0 040 1A32_MC3_ADDR 0x0 0xF 0x0429 1A32_MC10_STATUS 0x0 0xF 0x0291 1A32_MC17_CTL2 0x0 0xF 0x040F 1A32_MC3_MISC 0x0 0xF 0x042A 1A32_MC10_ADDR 0 0 0 0445 1A32_MC17_STATUS 0 0 0 0410 1 32 0 0 0x042B 2 10 5 0 0 0 0446 1432 17 ADDR 0 0 0 0284 2 CTL2 0 0 0 042 2 0 0 0 0447 2 MC17 MISC 0 0 0 0411 2 STATUS 0 028 1A32_MC11_CTL2 0x0 0xF 0x0448 1A32_MC18_CTL 0x0 0xF 0x0412 1A32_MC4_ADDR 0 0 0x042D 1A32_MC11_STATUS 0 0 0x0292 1A32_MC18_CTL2 Ox0 OxF 0x0413 1A32 MISC 0x0 0xF 0x042E 1A32_MC11_ADDR 0x0 0xF 0x0449 1A32_MC18_STATUS 0x0 0xF 0x0414 1 2 5 0 0 0x042F 1 32 11 MISC 0 0 0 044 1432 18 ADDR 0 0 0 0285 2 5 CTL2 0 0 0 0430 2 12 0 0 0 044 2 18 MISC Ox0 OxF 0x0415 2 MC5 STATUS 0 028 2 12 CTL2 0x0 0xF 0x044C 2 19 0x0 0xF 0x0416 1A32_MC5_ADDR 0x0 0xF 0x0431 1A32_MC12_STATUS 0x0 0xF 0x0293 1A32_MC19_CTL2 0x0 0xF 0x0417 1A32_MC5_MISC 0x0 0xF 0x0432 1A32_MC12_ADDR 0x0 0xF 0 0440 1A32_MC19_STATUS 0x0 0xF 0x0418 1A32_MC6_CTL 0x0 0xF 0x0433 1A32_MC12_MISC 0x0 0xF 0x044E 1A32_MC19_ADDR 0x0 0xF 0x0286 1A32_MC6_CTL2 0x0 0xF 0x0434 1A32_MC1
28. P is the processor power dissipation Table 5 4 provides the 51 and parameters that define Tprs thermal profile for each TDP Core count combination Figure 5 4 illustrates the general form of the resulting linear graph resulting from Tprs 51 P The slope of a DTS profile assumes full fan speed which is not required over much of the power range Tcontrol is the temperature above which fans must be at maximum speed to meet the thermal profile requirements Tcontrol is different for each SKU and may be slightly above or below Tprs wax of the DTS nominal thermal profile for a particular SKU At many power levels on most embedded SKU s temperatures of the nominal profile are less than Tcontrol as indicated by the blue shaded region in the DTS profile graph of Figure 5 4 As a further simplification operation at DTS temperatures up to Tcontrol is permitted at all power levels Compliance to the DTS profile is required for any temperatures exceeding Tcontrol Table 5 4 Embedded DTS Thermal Specifications Nominal Short Term TDP W 5 W Maximum Maximum Tprs Tprs C LV70W 10C 10 50 0 65 0 0 483 83 8 98 8 LV60W 8C 8 52 0 67 0 0 487 81 2 96 2 LV60W 6C 15 6 52 0 67 0 0 527 83 6 98 6 LV50W 6C 6 52 0 67 0 0 640 84 0 99 0 LV40W 2C 15 2 52 0 67 0 0 792 83 7 98 7 Intel Xeon Processor E5 2400 v2 Product Family 106 Datasheet Volume One
29. PWR AW11 SOCKET_ID 0 CMOS AW8 QPI1 DTX DN 09 Intel 12 QPI1 DTX DN 03 Intel AW9 PWR AW13 RSVD AY10 QPI1_DTX_DP 07 Intel AW14 QPI1_DTX_DN 00 Intel QPI 11 QPI1_DTX_DN 05 Intel 15 VCC PWR AY12 QPI1_DTX_DP 03 Intel QPI AW16 VCC PWR AY13 QPI1_DTX_DN 01 Intel QPI AW17 vss GND AY14 QPI1_DTX_DP 00 Intel AW18 VCC PWR 15 VCC PWR AW19 VCC PWR AY16 VCC PWR AW2 QPI1 DTX DN 17 Intel 17 VSS GND AW20 VSS GND AY18 VCC PWR AW21 VCC PWR AY19 VCC PWR AW22 VCC PWR AY2 VTTA PWR AW23 VSS GND AY20 VSS GND AW24 VCC PWR 24 VCC PWR AW25 VCC PWR AY25 VCC PWR aw26 vss 1426 VSS GND Intel Xeon Processor E5 2400 v2 Product Family 183 Datasheet Volume One Processor Land Listing tel Table 8 2 Land Number Sheet 19 of 37 Table 8 2 Land Number Sheet 20 of 37 edu Land Name 7 Direction b Land Name y ed Direction AY27 VCC PWR B27 VSS GND AY28 VCC PWR B28 DDR3_CKE 0 SSTL 29 PE3D_RX_DP 15 PCIEX3 B29 DDR3 CKE 1 SSTL 0 AY3 QPI1_DTX_DN 15 Intel QPI 0 B3 VSS GND AY30 PE3D_RX_DN 14 PCI EX3 B30 DDR3_ECC 2 SSTL 1 PE3D_RX_DP 13 PCIEX3 B31 DDR3_ECC 6 SSTL 2 PE3D_RX_DN 12 PCIEX3 B32 DDR3 DQS DN 08 SSTL VSS GND B33 DDR3_DQS_DN 17
30. Table 8 1 Land Name Sheet 3 of 37 Table 8 1 Land Name Sheet 4 of 37 Land Name Land Buffer Type Direction Land Name Land Buffer Type Direction Number Number DDR1_DQ 09 T36 SSTL 1 0 DDR1_DQ 47 U8 SSTL 1 0 DDR1 DQ 10 N36 SSTL 1 0 DDR1 001481 AA9 SSTL 1 0 DDR1_DQ 11 N35 SSTL 1 0 DDR1 DQ 49 SSTL 1 0 DDR1 DQ 12 U35 SSTL 1 0 DDR1 DQ 50 AE9 SSTL 1 0 DDR1 001131 U36 SSTL 1 0 DDR1 DQ 51 AE8 SSTL 1 0 DDR1 DQ 14 P34 SSTL 1 0 DDR1 DQ 52 Y9 SSTL 1 0 DDR1 DQ 15 N34 SSTL 1 0 DDR1 DQ 53 Y8 SSTL 1 0 DDR1 DQ 16 K35 SSTL 1 0 DDR1 DQ 54 AD9 SSTL 1 0 DDR1_DQ 17 K36 SSTL 1 0 DDR1 DQ 55 AD8 SSTL 1 0 DDR1 001181 K33 SSTL 1 0 DDR1 DQ 56 Y1 SSTL 1 0 DDR1 DQ 19 L33 SSTL 1 0 DDR1_DQ 57 AA3 SSTL 1 0 DDR1 DQ 20 L36 SSTL 1 0 DDR1 DQ 58 AE1 SSTL 1 0 DDR1_DQ 21 135 SSTL 1 0 DDR1 DQ 59 AE2 SSTL 1 0 DDR1_DQ 22 134 SSTL 1 0 DDR1 001601 Y3 SSTL 1 0 DDR1_DQ 23 133 SSTL 1 0 DDR1 DQ 61 Y2 SSTL 1 0 DDR1 DQ 24 L31 SSTL 1 0 DDR1_DQ 62 AD2 SSTL 1 0 DDR1 DQ 25 K31 SSTL 1 0 DDR1 001631 AD3 SSTL 1 0 DDR1 DQ 26 L27 SSTL 1 0 DDR1_DQS_DN 00 AA35 SSTL 1 0 DDR1_DQ 27 K27 SSTL 1 0 DDR1_DQS_DN 01 P35 SSTL DDR1 001281 132 SSTL 1 0 DDR1_DQS_DN 02 H33 SSTL 1 0 DDR1 DQ 29 K32 SSTL 1 0 DDR1_DQS_DN 03 L29 SSTL 1 0 DDR1 DQ 30 L28 SSTL 1 0 DDR1_DQS_DN 04 K7 SSTL 1 0 DDR1_DQ 31 K28 SSTL 1 0 DDR1_DQS_DN 05 T9 SSTL 1 0 DDR1_DQ 32 K9 SSTL 1 0 DDR1 005 DN 06 AC9 SSTL 1 0 DDR1_DQ 33 19 SSTL 1 0 DDR1_DQS_DN 07 AC2 SSTL 1 0 DDR1 DQ 34 K5 SSTL 1 0
31. Tabsolute storage The minimum maximum device storage temperature 25 125 beyond which damage latent or otherwise may occur when subjected to for any length of time Tsustained storage The minimum maximum device storage temperature 5 40 for a sustained period time Tshort term storage The ambient storage temperature in shipping media 20 85 for short period time RH custained storage The maximum device storage relative humidity for a 60 24 26 sustained period of time Timesustained storage A prolonged or extended period of time typically 0 30 months associated with sustained storage conditions Unopened bag includes 6 months storage time by customer Timeshort term storage short period of time in shipping media 0 72 hours Notes 1 Storage conditions are applicable to storage environments only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications These ratings apply to the Intel component and do not include the tray or packaging Failure to adhere to this specification can affect the long term reliability of the processor Non operating storage limits post board attach Storage condition limits for the component once attached to the a
32. 1 SSTL 1 0 DDR1_ODT 2 14 SSTL DDR1_DQS_DP 08 G29 SSTL 1 0 DDR1_ODT 3 G13 SSTL DDR1_DQS_DP 09 AB34 SSTL 1 0 DDR1_PAR_ERR_N 21 SSTL DDR1_DQS_DP 10 R35 SSTL 1 0 DDR1_RAS_N K17 SSTL DDR1_DQS_DP 11 L34 SSTL 1 0 DDR1_RCOMP 0 14 Analog DDR1_DQS_DP 12 L30 SSTL 1 0 DDR1_RCOMP 1 N7 Analog DDR1_DQS_DP 13 K8 SSTL 1 0 DDR1_RCOMP 2 M4 Analog DDR1_DQS_DP 14 R9 SSTL 1 0 DDR1_WE_N K14 SSTL DDR1_DQS_DP 15 9 SSTL 1 0 DDR2 BA 0 E17 SSTL 0 DDR1_DQS_DP 16 AB3 SSTL 1 0 DDR2 BA 1 G18 SSTL DDR1_DQS_DP 17 H30 SSTL 1 0 DDR2 BA 2 F26 SSTL DDR1 G32 SSTL DDR2 CAS F13 SSTL DDR1_ECC 1 G31 SSTL 1 0 DDR2_CKE 0 D27 SSTL DDR1_ECC 2 H27 SSTL 1 0 DDR2_CKE 1 E28 SSTL DDR1_ECC 3 G27 SSTL 1 0 DDR2_CKE 2 E27 SSTL DDR1_ECC 4 H31 SSTL 1 0 DDR2_CKE 3 D28 SSTL DDR1_ECC 5 H32 SSTL 1 0 DDR2_CLK_DN 0 E19 SSTL 0 DDR1_ECC 6 H28 SSTL 1 0 DDR2_CLK_DN 1 H21 SSTL DDR1_ECC 7 G28 SSTL DDR2_CLK_DN 2 G20 SSTL DDR1_MA 00 K19 SSTL 0 DDR2_CLK_DN 3 F21 SSTL 0 DDR1 MA 01 L20 SSTL DDR2_CLK_DP 0 E20 SSTL DDR1_MA 02 K20 SSTL DDR2 CLK DP 1 G21 SSTL DDR1 MA 03 L21 SSTL DDR2_CLK_DP 2 F20 SSTL 0 DDR1_MA 04 M22 SSTL 0 DDR2_CLK_DP 3 F22 SSTL 0 DDR1 MA 05 K22 SSTL DDR2 CS N 0 G16 SSTL DDR1 061 L22 SSTL DDR2 CS N 1 G14 SSTL DDR1_MA 07 L23 SSTL DDR2_CS_N 2 11 SSTL DDR1_MA 08 K23 SSTL DDR2_CS_N 3 111 SSTL DDR1_MA 09 L25 SSTL
33. 75 90 LV60W 8C LV60W 6C 15 75 90 LV50W 6C 65 80 LV40W 2C 15 40 50 Notes 1 Unless otherwise noted all specifications in this table apply to all processors These specifications are based on silicon characterization 2 Launch to FMB See Section 7 6 Flexible Motherboard Guidelines FMB for details 3 TDC Thermal Design Current is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator thermal assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please refer to the VR12 IMVP7 Pulse Width Modulation Specification for further details 4 Specification is at 50 C Characterized by design not tested 5 specifications are current draw of processor only and do not include current consumption by memory devices 6 Minimum VCC and maximum ICC are specified at the maximum processor case temperature shown in Section 5 Thermal Management Specifications is specified at the relative MAX point the VCC load line processor is capable of drawing ICC MAX for up to 5 seconds Refer to Section 7 4 Load Current Versus Time for details on processor current draw over various durations Table 7 13 Processor VCC Static and Transient Tolerance Sheet 1 of 2
34. Figure 5 4 Embedded DTS Thermal Profile temperature not to exceed 360 hours per year PSl P Tia sr Tabsolute C 4 4 gt 2 Power W Short Term Profile operation during excursionsto higher ambient PTa Nominal Short 5 1 5 Thermal Metrology The minimum and maximum case temperatures are measured at the geometric top center of the processor integrated heat spreader IHS Figure 5 5 illustrates the location where Tcase temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG Intel Xeon Processor E5 2400 v2 Product Family 107 Datasheet Volume One Figure 5 5 Case Temperature Measurement Location Measure Tease geometric center of Ehe top surface of the IHS Notes 2 1 2 IOUT Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One Figure is not to scale and is for reference Max 45 07 mm Min 44 93 mm Max 42 57 mm Min 42 43 mm Max 39 1 mm Min 38 9 mm Max 36 6 mm Min 36 4 mm Max 2 3 mm Min 2 2 mm Max 2 3 mm Min 2 2 mm 108 5 2 5 2 1 5 2 2 Processor Core Thermal Features Processor Temperature A new feature in t
35. LSB Data 8 bytes 14 15 16 17 18 oe BE Note The 2 byte MSR Address field and read data field defined in Figure 2 43 are sent in standard PECI ordering with LSB first and MSB last 2 5 2 7 3 Supported Responses The typical client response is a passing FCS a passing Completion Code and valid data Under some conditions the client s response will indicate a failure Table 2 10 AMSR Response Definition Response Meaning Bad FCS Electrical error Abort FCS Illegal command formatting mismatched RL WL Command Code CC 0x40 Command passed data is valid CC 0x80 Response timeout The processor was not able to generate the required response in a timely fashion Retry is appropriate CC 0x81 Response timeout The processor is not able to allocate resources for servicing this command at this time Retry is appropriate CC 0x82 The processor hardware resources required to service this command are in a low power state Retry may be appropriate after modification of PECI wake mode behavior if appropriate CC 0x90 Unknown Invalid lllegal Request CC 0x91 PECI control hardware firmware or associated logic error The processor is unable to process the request 2 5 2 7 4 AMSR Capabilities The processor client allows RdIAMSR access to the registers listed in Table 2 11 These registers pertain to the processor core and uncore error banks mach
36. 7 8 3 3 7 8 3 4 7 8 3 5 PCI Express DC Specifications The processor DC specifications for the PCI Express are available in the PCI Express Base Specification Revision 3 0 This document will provide only the processor exceptions to the PCI Express Base Specification Revision 3 0 DMI 2 PCI Express DC Specifications The processor DC specifications for the DMI2 PCI Express are available in the PCI Express Base Specification 2 0 and 1 0 This document will provide only the processor exceptions to the PCI Express Base Specification 2 0 and 1 0 Intel QuickPath nterconnect DC Specifications Intel QuickPath Interconnect specifications are defined at the processor lands Please refer to the appropriate platform design guidelines for specific implementation details In most cases termination resistors are not required as these are integrated into the processor silicon The processor DC specifications for the Intel interface are available in the Intel QuickPath Interconnect V1 1 Base Electrical Specification and Validation Methodologies This document will provide only the processor exceptions to the Intel amp QuickPath Interconnect V1 1 Base Electrical Specification and Validation Methodologies Reset and Miscellaneous Signal DC Specifications For a power on Reset RESET N must stay active for at least 3 5 millisecond after Vcc and BCLK 0 1 have reached their proper specifications RESET must not be kept a
37. Descriptor table exiting allows VMM to protect a guest OS from internal malicious software based attack by preventing relocation of key system data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector A VMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software Pause Loop Exiting PLE PLE aims to improve virtualization performance and enhance the scaling of virtual machines with multiple virtual processors PLE attempts to detect lock holder preemption in a VM and helps the VMM to make better scheduling decisions APIC Virtualization API Cv APICv adds hardware support in the processor to reduce the overhead of virtual interrupt processing APIC accesses and interrupt delivery This benefits mostly interrupt intensive workloads n a virtualized environment the virtual machine manager VMM must emulate nearly all guest OS accesses to the advanced programmable interrupt controller APIC registers which requires VM exits time consuming transitions to the VMM for emulation and back These exits are a major source of overhead in a virtual environment Intel s Advanced Programmable Interrupt Controller virtualization reduces the number of exits by redirecting most guest OS APIC reads writes to a virtual APIC p
38. Table 4 8 Note 4 2 4 4 2 4 1 4 2 4 2 For legacy operating systems P LVLx 1 0 reads are converted within the processor to the equivalent MWAIT C state request Therefore P LVLx reads do not directly result in I O reads to the system The feature known as I O redirection must be enabled in the BIOS To enable it refer to the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers The P LVLx 1 0 Monitor address needs to be set up before using the P LVLx I O read interface Each P LVLx is mapped to the supported MWAIT CX instruction as follows P LVLx to MWAI T Conversion P LVLx MWAI T Cx Notes P 2 The P LVL2 base address is defined in the IO CAPTURE MSR described in the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers P LVL3 MWAI T C6 C6 No sub states allowed The BIOS can write to the C state range field of the IO CAPTURE MSR to restrict the range of I O addresses that are trapped and emulate MWAIT like functionality Any P LVLx reads outside of this range does not cause 1 redirection to MWAIT Cx like request They fall through like a normal 1 0 instruction When P LVLx 1 instructions are used MWAIT substates cannot be defined The MWAIT substate is always zero if I O MWAIT redirection is used By default P LVLx 1 0 redirections enable the MWAIT break on EFLAGS IF feature which trigge
39. 1 also includes variable data transfer rate established with every message In this way it is highly flexible even though underlying logic is simple The interface design was optimized for interfacing to Intel processor and chipset components in both single processor and multiple processor environments The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components Bus speed error checking and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information The PECI bus offers A wide speed range from 2 Kbps to 2 Mbps CRC check byte used to efficiently and atomically confirm accurate data delivery Synchronization at the beginning of every message minimizes device timing accuracy requirements Generic PECI specification details are out of the scope of this document and instead can be found in the RS Platform Environment Control Interface PECI Specification Rev 3 0 What follows is a processor specific PECI client definition and is largely an addendum to the PECI Network Layer and Design Recommendations sections for the PECI specification The commands described in this document apply primarily to the Intel Xeon processor E5 2400 v2 product family The processors utilizes the capabilities described in this document to
40. 1 1 1 Processor Feature Details Up to 10 execution cores Each core supports two threads Intel amp Hyper Threading Technology up to 20 threads per socket 46 bit physical addressing and 48 bit virtual addressing 1 GB large page support for server applications A 32 KB instruction and 32 KB data first level cache L1 for each core A 256 KB shared instruction data mid level L2 cache for each core Up to 25 MB last level cache LLC up to 2 5 MB per core instruction data last level cache LLC shared among all cores Protected Processor Inventory Number PPIN A solution for inventory management available on Intel Xeon processor E5 product families for use in server platforms 1 1 2 Supported Technologies ntel amp Virtualization Technology Intel amp VT e Intel Virtualization Technology for Directed I O Intel VT d Intel Xeon Processor E5 2400 v2 Product Family 14 Datasheet Volume One Overview Intel Virtualization Technology Processor Extensions Intel Trusted Execution Technology Intel TXT Intel 64 Architecture Intel Streaming SIMD Extensions 4 1 Intel 55 4 1 Intel Streaming SIMD Extensions 4 2 Intel 55 4 2 Intel Advanced Vector Extensions Intel AVX Intel Hyper Threading Technology Execute Disable Bit Intel Turbo Boost Technology ntel amp Intelligent Power Technology Enhanced Intel SpeedStep Technology ntel amp Dynamic Po
41. 1 12500 1 30000 F6 1 47500 48 0 60500 6B 0 78000 8E 0 95500 B1 1 13000 D4 1 30500 F7 1 48000 49 0 61000 6C 0 78500 8F 0 96000 B2 1 13500 D5 1 31000 F8 1 48500 4A 0 61500 6D 0 79000 90 0 96500 B3 1 14000 D6 1 31500 F9 1 49000 4B 0 62000 6E 0 79500 91 0 97000 B4 1 14500 D7 1 32000 FA 1 49500 4C 0 62500 6F 0 80000 92 0 97500 B5 1 15000 D8 1 32500 FB 1 50000 4D 0 63000 70 0 80500 93 0 98000 B6 1 15500 D9 1 33000 FC 1 50500 4E 0 63500 71 0 81000 94 0 98500 B7 1 16000 DA 1 33500 FD 1 51000 4F 0 64000 72 0 81500 95 0 99000 B8 1 16500 DB 1 34000 FE 1 51500 50 0 64500 73 0 82000 96 0 99500 B9 1 17000 DC 1 34500 FF 1 52000 51 0 65000 74 0 82500 97 1 00000 BA 1 17500 DD 1 35000 52 0 65500 75 0 83000 98 1 00500 BB 1 18000 DE 1 35500 53 0 66000 76 0 83500 99 1 01000 BC 1 18500 DF 1 36000 54 0 66500 77 0 84000 9A 1 01500 BD 1 19000 1 36500 Notes 1 00h Off State 2 VID Range HEX 01 32 are not used by the processor 3 For VID Ranges supported see Table 7 12 4 VCCD is a fixed voltage of 1 35V or 1 5V 7 1 10 Reserved or Unused Signals Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One All Reserved RSVD signals must not be connected Connection of these signals to Vcc Vira Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 8 Processor Land Listing for a land listing of the processor and the
42. 105 5 4 Embedded DTS Thermal Specifications 106 6 1 Memory Channel DDR1 DDR2 neta eene 115 6 2 Memory Channel Miscellaneous 2 0 4 6 6 nunan nannan nnna 116 6 3 PCI Express Port Y Signals 116 6 4 PCI Express Port 3 Signals eer 116 6 5 PCI Express Miscellaneous Signals 117 6 6 2 and PCI Express Port 0 Signals sss memes 117 6 7 Intel Port 5 118 6 8 Intel Miscellaneous Signals 6 nnn nnns 118 6 9 PECI SignalS 118 6 10 System Reference Clock BCLK Signals 118 6 11 TAG and Stghals terit iore Ka Nue eC E 119 6 12 5 5 eR E DE EI IN EE 119 6 13 Processor Asynchronous Sideband Signals 119 6 14 Miscellaneous Signals 122 6 15 Power and Ground 5 2 2 1 123 7 1 Power and Ground Lands cc senes eem een 127 722 5 Address Usage petere that epu r Rx REM EE
43. Actual current limit data is contained only in the lower 13 bits of the response data The default return value of 0x438 corresponds to a current limit value of 135A Figure 2 33 Current Config Limit Read Data 31 13 12 0 RESERVED Current Limit for processor VCC Current Config Limit Data 2 5 2 6 24 Accumulated Energy Status Read This service can return the value of the total energy consumed by the entire processor package or just the logic supplied by the VCC power plane as specified through the parameter field in Table 2 8 This information is tracked by a 32 bit counter that wraps around and continues counting on reaching its limit Energy units for this read are determined as per the Package Power SKU Unit settings described in Section 2 5 2 6 13 While Intel requires reading the accumulated energy data at least once every 16 seconds to ensure functional correctness a more realistic polling rate recommendation is once every 100mS for better accuracy This feature assumes 150W processor In general as the power capability decreases so will the minimum polling rate requirement Intel Xeon Processor E5 2400 v2 Product Family 54 Datasheet Volume One Figure 2 34 2 5 2 6 25 intel When determining energy changes by subtracting energy values between successive reads Intel advocates using the 2 s complement method to account for counter wrap arounds Alternatively adding all F s OxFFFFFFFF t
44. Deep C states are defined as CC3 through CC6 refer to Table 4 3 for supported deep c states The Delayed Deep C states are intended to allow a staged entry into deeper C states whereby the processor enters a lighter short exit latency C state core C1 for a period of time before committing to a long exit latency deep C state core C3 and core C6 This is intended to allow the processor to get past the cluster of short duration idles providing each of those with a very fast wake up time but to still get the power benefit of the deep C states on the longer idles Package C States The processor supports CO C1 CIE C2 C3 and C6 power states The following is a summary of the general rules for package C state entry These apply to all package C states unless specified otherwise package C state request is determined by the lowest numerical core C state amongst all cores A package C state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C state The platform may allow additional power savings to be realized in the processor For package C states the processor is not required to enter CO before entering any other C state Intel Xeon Processor E5 2400 v2 Product Family 91 Datasheet Volume
45. Failure to adhere to this specification can shorten processor lifetime 8 Minimum Vcc and maximum are specified at the maximum processor case temperature TcAsg shown in Chapter 5 Thermal Management Specifications Icc max is specified at the relative Vcc max point on the Vcc load line The processor is capable of drawing Icc max for up to 5 seconds Refer to Figure 7 4 for further details the average processor current draw over various time durations 9 processor should not be subjected to any static level that exceeds the associated with any particular current Failure to adhere to this specification can shorten processor lifetime 10 This specification represents the Vcc increase or decrease due to each VID transition see Section 7 1 9 3 Voltage Identification VI D 11 Baseboard bandwidth is limited to 20 MHz 12 FMB is the flexible motherboard guidelines See Section 7 4 Fault Resilient Booting FRB for FMB details 13 DC AC Ripple specification Intel Xeon Processor E5 2400 v2 Product Family 139 Datasheet Volume One 14 15 16 17 18 19 intel For Power State Functions see Section 7 1 9 3 5 Vsa does not have a loadline the output voltage is expected to be the VID value tolerance at processor pins Tolerance for VR at remote sense is 3 3 Vccp The Vecp voltage specification requirements are measured across vias
46. O3AYTI4SIO 0350125 38 LON AVIV 205 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One Figure 10 7 Boxed Processor Motherboard Keepout Zones 3 of 4 E LEGEND THIS SHEET ONLY _ d i g i n T Z _BAS NI Datasheet Volume intel Boxed Processor Specifications 8 Boxed Processor Motherboard Keepout Zones 4 of 4 Figure 10 S3NOZ NOILOIHIS33 06 3015 035 S3NOZ NOLLOIMIS3M LHOISH 06 3015 207 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One Boxed Processor Specifications Figure 10 9 Boxed Processor Heat Sink Volumetric 1 of 2 t REVISION HISTORY FEDT EOWETRY To FIT FIDENCE ENT OF INTEL AIRFLOW DIRECTION ISCLOSED TI THE FIDENTIAL La iT INTEL n T 8E DISCLOSE THI TOP VIEW i TE 2 55 s 28
47. SSTL AY34 PE3C_RX_DN 10 PCIEX3 B34 DDR3 DQS DP 17 SSTL 5 VSS GND B35 DDR3_ECC 5 SSTL AY36 PE3C_RX_DN 8 PCIEX3 B36 VSS GND AY37 VSS GND B37 DDR2_DQ 31 SSTL AY38 RX DN 6 PCIEX3 B38 DDR2 DQS DP 03 SSTL AY39 PE1B_RX_DP 5 PCIEX3 B39 DDR2 DQS DP 12 SSTL AY4 QPI1 DTX DP 15 Intel OPI 4 DDR3 DQ 35 SSTL AY40 PE1B_RX_DN 4 PCIEX3 B40 VSS GND AY41 RSVD B41 DDR3_DQ 27 SSTL 42 VSA PWR B42 VSS GND AY5 VSS GND B5 DDR3 DQ 34 SSTL RSVD B6 DDR3 DQ 39 SSTL 7 QPI1_DTX_DN 11 Intel QPI 7 DDR3 005 DP 04 SSTL AY8 QPI1 DTX DP 09 Intel QPI B8 DDR3 DQS DN 13 SSTL 1 0 AYO QPI1 CLKTX DN Intel OPI B9 DDR3 DQ 33 SSTL 10 DDR3_DQ 37 SSTL 10 VSS GND B11 DDR3_CS_N 2 SSTL 11 QPI1 DTX DP 05 Intel QPI 12 VSS GND BA12 VSS GND B13 DDR3_CS_N 1 SSTL BA13 QPI1 DTX DP 01 Intel QPI 14 DDR3_CS_N 5 SSTL 14 VSS GND B15 DDR3_CAS_N SSTL 15 VCC PWR B16 DDR3_BA 0 SSTL 0 BA16 VCC PWR B17 VSS GND BA17 VSS GND B18 DDR3_CLK_DP 2 SSTL 18 VCC PWR B19 DDR3_CLK_DN 0 SSTL 19 VCC PWR B2 RSVD BA20 VSS GND B20 DDR3_CLK_DP 1 SSTL 0 BA24 VCC PWR B24 DDR3_MA 08 SSTL 25 VCC PWR B25 DDR3 MA 09 SSTL 26 VSS GND B26 DDR3 MA 12 SSTL 27 VCC PWR Intel Xeon Processor E5 2400 v2 Product Family 184 Datasheet Volume One Processor Land Listing tel Tab
48. Status Read DIMM has been throttled Notes 1 Time energy and power units should be assumed where applicable to be based on values returned by a read of the PACKAGE_POWER_SKU_UNIT MSR or through the Package Power SKU Unit PCS read service 2 For the Intel Xeon processor E5 2400 v2 product family accumulated DRAM energy status would be reflected the DRAM ENERGY STATUS CH 1 3 CSR 2 5 2 6 2 DRAM Thermal Estimation Configuration Data Read Write This feature is relevant only when activity based DRAM temperature estimation methods are being utilized and would apply to all the DIMMs on all the memory channels The write allows the host to configure the and 8 variables in Figure 2 12 for DRAM channel temperature filtering as per the equation below Ty 1 0 AEnergy Ty and are the current and previous DRAM temperature estimates respectively in degrees Celsius is the DRAM temperature decay factor AEnergy is the energy difference between the current and previous memory transactions as determined by the processor power control unit and 6 is the DRAM energy to temperature translation coefficient The default value of is Ox3FF 6 is defined by the equation 0 1 Thermal Resistance Scaling Factor The Thermal Resistance serves as a multiplier for translation of DRAM energy changes to corresponding temperature change
49. Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive Compliance to Overshoot Undershoot Specifications The overshoot undershoot specifications listed in the table specify the allowable overshoot undershoot for a single overshoot undershoot event However most systems will have multiple overshoot and or undershoot events that each have their own set of parameters duration AF and magnitude While each overshoot on its own may meet the overshoot specification when you add the total impact of all overshoot events the system may fail A guideline to ensure a system passes the overshoot and undershoot specifications is shown below 1 If only one overshoot undershoot event magnitude occurs ensure it meets the over undershoot specifications in the following tables OR 2 If multiple overshoots and or multiple undershoots occur measure the worst case pulse duration for each magnitude and compare the results against the AF 0 1 specifications If all of these worst case overshoot or undershoot events meet the specifications measured time lt specifications in the table where AF 0 1 then the system passes Table 7 24 Processor Sideband Signal Group Overshoot Undershoot Tolerance Absolute Maximum Overshoot Absolute Maximum Undershoot Pulse Duration ns Pulse Duration ns V V AF 0 1 AF 0 01 1 3335 0 2835 V 3 ns 5 ns 1 2600 V 0 210 V 5 ns 5 ns Intel Xeon
50. _ 2 ANQ ODCMOS 1 0 DDR1_CLK_DN 3 H18 SSTL BPM N 3 AN11 ODCMOS 1 0 DDR1_CLK_DP 0 117 SSTL BPM_N 4 AP10 ODCMOS 1 0 DDR1_CLK_DP 1 H19 SSTL BPM_N 5 AP11 ODCMOS 1 0 DDR1_CLK_DP 2 116 SSTL BPM N 6 AN10 ODCMOS DDR1 DPI 3 118 SSTL o BPM 71 11 ODCMOS 1 0 DDR1 CS NIO 115 SSTL _ _ AT6 ODCMOS DDR1 CS NI1 L15 SSTL o CPU ONLY RESET AM3 ODCMOS DDR1 CS NI2 L11 SSTL DDR RESET C1 N L26 CMOS 1 5V DDR1 CS NI3 K12 SSTL o DDR RESET C23 N C29 CMOS 1 5V e DDR1 CS NI4 K15 SSTL DDR_SCL_Cl W7 ODCMOS DDR1 CS NI5 14 SSTL DDR_SCL_C23 v40 ODCMOS 1 0 DDR1_CS_N 6 L12 SSTL DDR SDA w8 ODCMOS 1 0 DDR1_CS_N 7 112 SSTL DDR_SDA_C23 41 ODCMOS 1 0 DDR1_DQ 00 4 SSTL 1 0 DDR_VREFDQRX_C N10 DC DDR1_DQ 01 AC35 SSTL 1 0 s DDR1_DQ 02 W35 SSTL 1 0 PPR VRERDORA G DDR1_DQ 03 W36 SSTL 1 0 DDR VREFDQTX 1 4 DC DDR1_DQ 04 AD34 SSTL 1 0 DDR VREFDQTX C2 V37 DC DDR1_DQ 05 AD35 SSTL 1 0 DDR1_DQ 06 Y35 SSTL 1 0 DDR1_BA 0 L17 SSTL DDR1_DQ 07 Y36 SSTL 1 0 DDR1_BA 1 L18 SSTL pf DDR1_DQ 08 T35 SSTL 1 0 DDR1_BA 2 124 SSTL Intel Xeon Processor E5 2400 v2 Product Family 157 Datasheet Volume One Processor Land Listing intel
51. and even some nonstandard or future variants Beyond improving performance the AES instructions provide important security benefits Since the instructions run in data independent time and do not use lookup tables they help in eliminating the major timing and cache based attacks that threaten table based software implementations of AES In addition these instructions make AES simple to implement with reduced code size This helps reducing the risk of inadvertent introduction of security flaws such as difficult to detect side channel leaks Execute Disable Bit Intel s Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system Allows the processor to classify areas in memory by where application code can execute and where it cannot When a malicious worm attempts to insert code in the buffer the processor disables code execution preventing damage and worm propagation I ntel Secure Key This was formerly known as Digital Random Number Generator DRNG The processor supports an on die digital random number generator DRNG This implementation is based on the ANSI X9 82 2007 draft and the NIST SP800 90 specification The X9 82 standard describes two components necessary to generate high quality random numbers an Entropy Source and a Deterministic Random Bit Generator DRBG The Entropy Source is also referred to as a Non Determini
52. designed to enumerate discrete features 2 5 4 Multi Domain Commands The processor does not support multiple domains but it is possible that future products will and the following tables are included as a reference for domain specific definitions Table 2 19 Domain I D Definition Domain ID Domain Number 0501 0 0010 1 Table 2 20 Multi Domain Command Code Reference Sheet 1 of 2 Command Name 0 z GetTemp 0x01 0x02 RdPkgConfig 1 Oxa2 WrPkgConfig 5 AMSR Oxb1 0 2 RdPCI Config 0x61 0x62 RdPCI ConfigLocal 1 Oxe2 Intel Xeon Processor E5 2400 v2 Product Family 73 Datasheet Volume One Table 2 20 Multi Domain Command Code Reference Sheet 2 of 2 2 5 5 2 5 5 1 2 5 5 2 Command Name Domain 0 Domain 1 Code Code WrPCI ConfigLocal Oxe5 Client Responses Abort FCS The Client responds with an Abort FCS refer to RS Platform Environment Control Interface PECI Specification Rev 3 0 for details under the following conditions The decoded command is not understood not supported on this processor this includes good command codes with bad Read Length or Write Length bytes Assured Write FCS AW FCS failure Under most circumstances an Assured Write failure will appear as a bad FCS However when an originator issues a poorly formatted command with a miscalculated
53. for example fan is going to fail other system devices are exceeding their thermal target The input sense period of these signals are programmable 100 us is the default value The input sense assertion time recognized by the processor is programmable 1 us is the default value If the sense assertion time is programmed to zero then the processor ignores all external assertions of MEM HOT 1 C1 C23 signals in effect they become outputs Intel Xeon Processor E5 2400 v2 Product Family 113 Datasheet Volume One e Output Function The output behavior the MEM HOT C1 C23 signals supports Level mode In this mode HOT 1 23 event temperatures are programmable via TEMP OEM HI TEMP LOW TEMP MID and TEMP HI threshold settings in the iMC In Level mode when asserted the signal indicates to the platform that a BIOS configured thermal threshold has been reached by one or more DIMMs in the covered channel pair 5 2 6 4 I ntegrated SMBus Master Controllers for Memory I nterface The processor includes two integrated SMBus master controllers running at 100 KHz for dedicated PCU access to the serial presence detect SPD devices and thermal sensors TSoD on the DIMMs Each controller is responsible for a pair of memory channels and supports up to four SMBus slave devices Note that clock low stretching is not supported by the processor To avoid design complexity and minimize package C state transitions the SMBus interfac
54. overshoot undershoot events of that magnitude ONLY A platform with an overshoot undershoot that just meets the pulse duration for a specific magnitude where the AF 0 1 means that there can be no other overshoot undershoot events even of lesser magnitude note that if AF 0 1 then the event occurs at all times and no other events can occur Intel Xeon Processor E5 2400 v2 Product Family 154 Datasheet Volume One 7 9 5 4 7 9 5 5 intel The overshoot undershoot specification for the processor is not a simple single value Instead many factors are needed to determine the over undershoot specification In addition to the magnitude of the overshoot the following parameters must also be known the width of the overshoot and the activity factor AF To determine the allowed overshoot for a particular overshoot event the following must be done Reading Overshoot Undershoot Specification Tables 1 Determine the signal group a particular signal falls into Determine the magnitude of the overshoot or the undershoot relative to VSS won Determine the activity factor How often does this overshoot occur Next from the appropriate specification table determine the maximum pulse duration in nanoseconds allowed 5 Compare the specified maximum pulse duration to the signal being measured If the pulse duration measured is less than the pulse duration shown in the table then the signal meets the specifications
55. that includes additional pass fail status information Refer to Section 2 5 5 2 for details regarding completion codes Figure 2 45 RdPCI Config Byte 0 1 2 3 White Length Read Length Code inition 4 5 6 7 8 3 amp LSB PCI Configuration Address MSB 11 12 13 14 15 10 Completion LSB Data 4 bytes MSB F Code Note The 4 byte configuration address and read data field defined in Figure 2 45 are sent in standard PECI ordering with LSB first and MSB last 2 5 2 8 2 Supported Responses The typical client response is a passing FCS a passing Completion Code and valid data Under some conditions the client s response will indicate a failure The PECI client response can also vary depending on the address and data It will respond with a passing completion code if it successfully submits the request to the appropriate location and gets a response Exactly what the receiving agent does with the data or how it responds is up to that agent and is outside the scope of PECI 3 0 Table 2 12 RdPCI Config Response Definition Response Meaning Bad FCS Electrical error Abort FCS Illegal command formatting mismatched RL WL Command Code CC 0x40 Command passed data is valid CC 0x80 Response timeout The processor was not able to generate the required response in a timely fashion Retry is appropriate CC 0x81 Response timeout The processor is not able to allocate resources fo
56. thermal profile but they will have separate Tprs based thermal profiles The processor fan speed control is managed by comparing DTS thermal readings via PECI against the processor specific fan speed control reference point or Tcontrol Both Tcontrol and DTS thermal readings are accessible via the processor PECI client At a one time readout only the Fan Speed Control firmware will read the following TEMPERATURE TARGET MSR Tcontrol via RdPkgConfig via PECI RdPkgConfig Core Count RdPCI ConfigLocal DTS PECI commands will also support DTS temperature data readings Please see Section 2 5 7 DTS Temperature Data for PECI command details Also refer to the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG for details on DTS based thermal solution design considerations Intel Xeon Processor E5 2400 v2 Product Family 100 Datasheet Volume One intel 5 1 3 Processor Operational Thermal Specifications Each SKU has a unique thermal profile that ensures reliable operation for the intended form factor over the processor s service life These specifications are based on final silicon characterization 5 1 3 1 Minimum operating case temperature Minimum case operating temperature is specified at 5 C for every Intel Xeon processor E5 2400 v2 product family processor SKU 5 1 3 2 Maximum operating case temperature thermal prof
57. 1 0 DDR3_DQS_DN 00 AB41 SSTL 1 0 DDR3_DQ 27 B41 SSTL 1 0 DDR3_DQS_DN 01 R43 SSTL 1 0 DDR3 001281 F42 SSTL 1 0 DDR3_DQS_DN 02 K41 SSTL 1 0 DDR3_DQ 29 SSTL 1 0 DDR3_DQS_DN 03 D43 SSTL 1 0 DDR3_DQ 30 C42 SSTL 1 0 DDR3_DQS_DN 04 7 SSTL DDR3_DQ 31 D41 SSTL 1 0 DDR3_DQS_DN 05 F2 SSTL 1 0 DDR3_DQ 32 AQ SSTL 1 0 DDR3 DQS DN 06 L1 SSTL 1 0 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 162 Processor Land Listing intel Table 8 1 Land Name Sheet 13 of 37 Table 8 1 Land Name Sheet 14 of 37 Land Name Fra Buffer Type Direction Land Name un Buffer Type Direction DDR3 005 DN O07 T3 SSTL 1 0 DDR3 MA 01 D21 SSTL DDR3_DQS_DN 08 B32 SSTL DDR3 MA 02 D22 SSTL DDR3_DQS_DN 09 AB43 SSTL DDR3 MA 03 C22 SSTL DDR3_DQS_DN 10 R41 SSTL 1 0 DDR3_MA 04 D23 SSTL DDR3_DQS_DN 11 K43 SSTL 1 0 DDR3 MA 05 C24 SSTL DDR3_DQS_DN 12 E42 SSTL 1 0 DDR3 MA 06 C23 SSTL DDR3_DQS_DN 13 B8 SSTL 1 0 DDR3_MA 07 D25 SSTL DDR3 005 DN 14 SSTL 1 0 DDR3_MA 08 B24 SSTL DDR3_DQS_DN 15 L3 SSTL 1 0 DDR3_MA 09 B25 SSTL DDR3 DQS 0 161 T1 SSTL 1 0 DDR3 MA 10 A17 SSTL DDR3_DQS_DN 17 B
58. 38 0 52500 5B 0 70000 7E 0 87500 Al 1 05000 1 22500 7 1 40000 39 0 53000 5 0 70500 0 88000 2 1 05500 5 1 23000 E8 1 40500 Intel Xeon Processor E5 2400 v2 Product Family 130 Datasheet Volume One Electrical Specifications intel Table 7 3 VR12 0 Reference Code Voltage Identification VID Table Sheet 2 of 2 Veen HEX Veep HEX Veen HEX cep Veep HEX Veco 3A 0 53500 5D 0 71000 80 0 88500 A3 1 06000 C6 1 23500 E9 1 41000 3B 0 54000 5E 0 71500 81 0 89000 A4 1 06500 C7 1 24000 EA 1 41500 3C 0 54500 5F 0 72000 82 0 89500 A5 1 07000 C8 1 24500 EB 1 42000 3D 0 55000 60 0 72500 83 0 90000 A6 1 07500 C9 1 25000 EC 1 42500 3E 0 55500 61 0 73000 84 0 90500 A7 1 08000 CA 1 25500 ED 1 43000 3F 0 56000 62 0 73500 85 0 91000 A8 1 08500 CB 1 26000 EE 1 43500 40 0 56500 63 0 74000 86 0 91500 A9 1 09000 1 26500 1 44000 41 0 57000 64 0 74500 87 0 92000 1 09500 CD 1 27000 FO 1 44500 42 0 57500 65 0 75000 88 0 92500 AB 1 10000 CE 1 27500 Fl 1 45000 43 0 58000 66 0 75500 89 0 93000 AC 1 10500 CF 1 28000 F2 1 45500 44 0 58500 67 0 76000 8A 0 93500 AD 1 11000 DO 1 28500 F3 1 46000 45 0 59000 68 0 76500 8B 0 94000 AE 1 11500 D1 1 29000 F4 1 46500 46 0 59500 69 0 77000 8C 0 94500 AF 1 12000 D2 1 29500 F5 1 47000 47 0 60000 6A 0 77500 8D 0 95000
59. 49 While in this phase the PECI client will respond normally to the Ping and GetDIB commands and return the highest processor die temperature of 0x0000 to the GetTemp command All other commands will get a Response Timeout completion in the DNR phase as shown in Table 2 16 All PECI services with the exception of core MSR space accesses become available 500 uS after RESET_N de assertion as shown in Figure 2 49 will be fully functional with all services including core accesses being available when the core comes out of reset upon completion of the RESET microcode execution In the event of the occurrence of fatal or catastrophic error all services with the exception of core MSR space accesses will be available during the DNR phase to facilitate debug through configuration space accesses Intel Xeon Processor E5 2400 v2 Product Family 68 Datasheet Volume One intel Table 2 16 PECI Client Response During Power Up Command Response During Response During Data Not Ready Available Except Core Services Ping Fully functional Fully functional GetDIB Fully functional Fully functional GetTemp Client responds with a hot reading or 0x0000 Fully functional RdPkgConfig Client responds with a timeout completion Fully functional code of 0x81 WrPkgConfig Client responds with a timeout completion Fully functional code of 0x81 RdlAMSR Client responds
60. 5 3 8 Processor Error Handling Availability of services may be affected by the processor client error status Server manageability requirements place a strong emphasis on continued availability of PECI services to facilitate logging and debug of the error condition Most processor PECI client services are available the event of a CAT ERR assertion though they cannot be guaranteed The Ping GetDIB GetTemp RdPkgConfig and WrPkgConfig commands will be serviced if the source of the CAT ERR N assertion is not in the processor power control unit hardware firmware or associated register logic Additionally the RdPCI ConfigLocal WrPCI ConfigLocal commands may also be serviced in this case t is recommended that the originator read Index 0 Parameter 5 using the RdPkgConfig command to debug the CAT ERR N assertion The PECI client will return the 0x91 completion code if the CAT ERR N assertion is caused by the PCU hardware firmware or associated logic errors In such an event only the Ping GetTemp and GetDIB PECI commands may be serviced All other processor services will be unavailable and further debug of the processor error status will not be possible f the PECI client returns a passing completion code the originator should use the response data to determine the cause of the ERR assertion such an event it is also recommended that the PEC
61. 5 Output Low Voltage 0 2 12 Vuysteresis Hysteresis 0 1 V V 1 2 Signals MEM HOT 01 23 PROCHOT N VHysteresis Hysteresis 0 05 Var 1 2 Signal CAT ERR Input Leakage Current 50 200 pA Ron Buffer On Resistance 4 14 Q 1 2 Output Edge Rate 0 05 0 60 V ns 3 Signal MEM_HOT_C 1 23 _N ERROR_N 2 0 THERMTRIP PROCHOT_N Output Edge Rate 0 2 1 5 V ns 3 Signal CAT ERR N Notes 1 This table applies to the processor sideband and miscellaneous signals specified in Table 7 5 2 Unless otherwise noted all specifications in this table apply to all processor frequencies 3 These signals are measured between VIL and VIH Table 7 22 Miscellaneous Signals DC Specifications Sheet 1 of 2 Symbol Parameter Min Typical Max Units Notes IVT ID N Signal Intel Xeon Processor E5 2400 v2 Product Family 148 Datasheet Volume One Table 7 22 Miscellaneous Signals DC Specifications Sheet 2 of 2 Symbol Parameter Min Typical Max Units Notes Vo_ABS_MAX Output Absolute Max Voltage 1 80 V 1 2 lo Output Current N A 1 2 SKTOCC Signal 5 Output Absolute Max Voltage 3 30 3 50 V 1 loMAX Output Max Current 1 1 Notes 1 For specific routing guidelines see the Platform Design Guide for details 2 VT ID N land is connected to the Vss plane within the package substrate 7 8 3 1 7 8 3 2
62. 75 2 24 Error Codes and 5 76 4 1 System States eri in a ber erga t tected Pad Fi E RU Ea Eg CRUDO KR T E aa 85 4 2 Package C State 1 sese ese mememe is e n n nnns 85 4 3 Core C State 5 ciii Less hene dre E cite ca EUER EH 86 4 4 System Memory Power 5 5 86 4 5 DMI2 PCI Express Link States reme eed eee be e a ere dl aw lee ea 87 4 6 Intel 5 1 1 1 aae annee nnn nnn 87 4 7 5 State Combinations 87 4 8 P LVLx to MWAIT 5 90 4 9 Coordination of Core Power States at the Package 92 4 10 Package C State Power Specifications 95 4 11 Pmax Specifications Table eere e b o 95 5 1 Case Temperature Thermal 5 101 Intel Xeon Processor E5 2400 v2 Product Family 9 Datasheet Volume One 5 2 Digital Thermal Sensor Specification 103 5 3 Embedded Case Temperature Thermal Specifications
63. 8 90 LV60W 6C 15 6 90 LV50W 6C 6 75 LV40W 2C 1S 2 50 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 95 n tel 4 3 System Memory Power Management The DDR3 power states can be summarized as the following Normal operation highest power consumption CKE Power Down Opportunistic per rank control after idle time There may be different levels Active Power Down Precharge Power Down with Fast Exit Precharge power Down with Slow Exit Self Refresh In this mode no transaction is executed The DDR consumes the minimum possible power 4 3 1 CKE Power Down The CKE input land is used to enter and exit different power down modes The memory controller has a configurable activity timeout for each rank Whenever no reads are present to a given rank for the configured interval the memory controller will transition the rank to power down mode The memory controller transitions the DRAM to power down by de asserting CKE and driving a NOP command The memory controller will tri state all DDR interface lands except CKE de asserted and ODT while in power down The memory controller will transition the DRAM out of power down state by synchronously asserting CKE and driving a NOP command When CKE is off the internal DDR clock is disabled and the DDR power is significantly reduced The DDR defines three levels of power down Active power down This mode
64. AD11 VCC PWR AE6 DDR2_DQ 58 SSTL 1 0 AD2 DDR1_DQ 62 SSTL 1 0 AE7 RSVD AD3 DDR1_DQ 63 SSTL 1 0 AE8 DDR1 DQ 51 SSTL 1 0 AD33 vss GND 9 DDR1 DQ 50 SSTL 1 0 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 176 Processor Land Listing intel Table 8 2 Land Number Sheet 5 of 37 Table 8 2 Land Number Sheet 6 of 37 Meu Land Name T Direction b Land Name je Direction AF1 BMCINIT CMOS AG43 PE1B_TX_DP 5 PCIEX3 10 VSS GND AG5 QPI1 DRX DP 18 Intel QPI 11 RSVD AG6 QPI1 DRX DN 18 Intel QPI 2 vss GND AG7 THERMTRIP_N ODCMOS FRMAGENT CMOS RSVD AF33 VSA PWR AG9 RSVD AF34 DMI_RX_DP 3 PCIEX 1 QPI1_DRX_DN 17 Intel 5 DMI_RX_DN 3 PCIEX 10 RSVD AF36 VSA PWR 11 RSVD AF37 VSA PWR AH2 QPI1_DRX_DP 17 Intel AF38 PE1A_TX_DN 2 PCIEX3 AH3 EAR_N ODCMOS 1 0 AF39 PE1A_TX_DP 2 PCIEX3 AH33 VSS GND AF4 BIST_ENABLE CMOS DP 1 PCIEX 40 VSS GND AH35 DMI_RX_DN 1 PCIEX 41 PE1B_TX_DN 4 PCIEX3 AH36 vss GND AF42 PE1B_TX_DP 4 PCIEX3 AH37 VSA PWR AF43 VSS GND AH38 PCIEX3 AF5 VSS GND AH39 PE3A_TX_DP 0 PCIEX3 AF6 55 GND AH4 QPI1_DRX_DP 16 Intel 7 RSVD AH40 vss GND AF8 VSS GND AH41 PE1B_TX_DN 6 PCIEX3 AF9 VTTD PWR AH42 PE1B_TX
65. AW FCS the client will intentionally abort the FCS in order to guarantee originator notification Completion Codes Some PECI commands respond with a completion code byte These codes are designed to communicate the pass fail status of the command and may also provide more detailed information regarding the class of pass or fail For all commands listed in Section 2 5 2 that support completion codes the definition in the following table applies Throughout this document a completion code reference may be abbreviated with CC An originator that is decoding these commands can apply a simple mask as shown in Table 2 21 to determine a pass or fail Bit 7 is always set on a command that did not complete successfully and is cleared on a passing command Table 2 21 Completion Code Pass Fail Mask Oxxx xxxxb Command passed 1 xxxxb Command failed Table 2 22 Device Specific Completion Code CC Definition Completion Code Description 0x40 Command Passed CC 0x80 Response timeout The processor was not able to generate the required response in a timely fashion Retry is appropriate CC 0x81 Response timeout The processor was not able to allocate resources for servicing this command Retry is appropriate CC 0x82 The processor hardware resources required to service this command are in a low power state Retry may be appropriate after modification of PECI wake mode behavior if appropriate
66. Code Byte 0x02 0x03 0x05 Definition 4 5 6 7 8 Host ID 7 1 amp Retry 0 LSB PCI Configuration Address MSB FCS 9 10 11 12 13 14 Completion LSB Data 1 2 or 4 bytes MSB FCS Intel Xeon Processor E5 2400 v2 Product Family 65 Datasheet Volume One 2 5 2 9 2 Table 2 13 2 5 2 10 2 5 2 10 1 intel Note The 3 byte configuration address and read data field defined in Figure 2 47 are sent in standard ordering with LSB first and MSB last Supported Responses The typical client response is a passing FCS a passing Completion Code and valid data Under some conditions the client s response will indicate a failure The PECI client response can also vary depending on the address and data It will respond with a passing completion code if it successfully submits the request to the appropriate location and gets a response Exactly what the receiving agent does with the data or how it responds is up to that agent and is outside the scope of PECI 3 0 RdPCI ConfigLocal Response Definition Response Meaning Bad FCS Electrical error Abort FCS Illegal command formatting mismatched RL WL Command Code CC 0x40 Command passed data is valid CC 0x80 Response timeout The processor was not able to generate the required response in a timely fashion Retry is appropriate CC 0x81 Response timeout The processor is not able to allocate resources for servicing this command a
67. DRAM Power I nfo Read This read returns the minimum typical and maximum DRAM power settings and the maximum time window over which the power can be sustained for the entire DRAM domain and is inclusive of all the DIMMs within all the memory channels Any power values specified by the power limiting entity that is outside of the range specified through these settings cannot be guaranteed Since this data is 64 bits wide PECI facilitates access to this register by allowing two requests to read the lower 32 bits and upper 32 bits separately as shown in Table 2 6 Power and time units for this read are defined as per the Package Power SKU Unit settings described in Section 2 5 2 6 11 Intel Xeon Processor E5 2400 v2 Product Family 42 Datasheet Volume One intel The minimum DRAM power in Figure 2 18 corresponds to a minimum bandwidth setting of the memory interface It does not correspond to a processor DLE or memory self refresh state The time window in Figure 2 18 is representative of the rate at which the power control unit PCU samples the DRAM energy consumption information and reactively takes the necessary measures to meet the imposed power limits Programming too small a time window may not give the PCU enough time to sample energy information and enforce the limit while too large a time window runs the risk of the PCU not being able to monitor and take timely action on energy excursions While the DRAM power setting in Fi
68. Figure 2 41 intel Bit 11 is the Read Mode bit and should be set to 0 for TOR reads The Read Mode bit can alternatively be set to 1 to read the Core ID with associated valid bit as shown in Figure 2 40 that points to the first core that asserted the IERR In this case bits 10 0 of the parameter field are ignored The Core 10 read may not return valid data until at least 1 mS after the IERR assertion Caching Agent TOR Read Data 31 0 Read Mode bit 11 0 within the Paramenter 31 4 3 0 Read Mode bit 11 1 within the Parameter Note Reads to caching agents that are not enabled will return all zeroes Refer to the debug handbook for details on methods to interpret the crash dump results using the Cbo TOR data shown in Figure 2 40 Thermal Margin Read This service allows the PECI host to read the margin to the processor thermal profile or load line Thermal margin data is returned in the format shown in Figure 2 41 with a sign bit an integer part and a fractional part A negative thermal margin value implies that the processor is operating in violation of its thermal load line and may be indicative of a need for more aggressive cooling mechanisms through a fan speed increase or other means This PECI service will continue to return valid margin values even when the processor die temperature exceeds Tprgchot DTS Thermal Margin Read 31 16
69. Max 60 6 0 299 51 1 Pedestal 90 x 90 x 64 RPM N A 95 10 0 180 62 9 95 8 0 184 62 5 STS100C with fan 80 6 4 0 197 60 2 60 10 0 177 57 4 60 6 0 198 57 1 Notes 1 Local ambient temperature of the air entering the heatsink or fan System ambient and altitude are assumed 35C and sea level 2 Max target mean 3 sigma for thermal characterization parameter 3 Airflow through the heatsink fins with zero bypass Max target for pressure drop dP measured in inches 4 Dimensions of heatsinks do not include socket or processor 5 This is a tray product only Alternate thermal profiles are available with higher see specific processor specifications for details Intel Xeon Processor E5 2400 v2 Product Family 215 Datasheet Volume One m Boxed Processor Specifications n tel 10 4 Boxed Processor Contents The Boxed Processor and Boxed Thermal Solution contents are outlined below Boxed Processor Intel Xeon processor E5 2400 v2 product family nstallation and warranty manual ntel Inside Logo Boxed Thermal Solution Thermal solution assembly Thermal interface material pre applied Installation and warranty manual Intel Xeon Processor E5 2400 v2 Product Family 216 Datasheet Volume One
70. Max Units Notes Input Leakage Current 1 4 1 4 mA 10 Data Signals Vu Input Low Voltage 0 43 Vccp 2 3 Input High Voltage 0 57 Vccp 2 4 5 DDR3 Data Buffer 21 6 Resistance Data ODT On Die Termination for Data 45 55 Q 8 Signals 90 110 PAR_ERR_N ODT On Die Termination for Parity 100 Q Error Signals Reference Clock Signals Command and Data Signals Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 144 Table 7 15 DDR3 and DDR3L Signal DC Specifications Sheet 2 of 2 Symbol Parameter Min Typ Max Units Notes VoL Output Low Voltage Vccp V 2 7 2 Ron Rytt_term Output High Voltage Vccp V 2 5 7 2 Reference Clock Signal Ron DDR3 Clock Buffer On 21 31 Q 6 Resistance Command Signals Ron DDR3 Command Buffer On 16 24 Q 6 Resistance Ron DDR3 Reset Buffer On 25 75 Q 6 Resistance VoL CMOS1 5v Output Low Voltage Signals 0 2 Vccp V 1 2 S DDR RESET 1 23 51 5 Output High Voltage Signals 0 9 Vccp V 1 2 DDR RESET C 1 23 _N cMOS1 5v Input Leakage Current 100 100 1 2 Control Signals Ron DDR3 Control Buffer On 21 31 Q 6 Resistance DDR1_RCOMP 0 COMP Resistance 128 7 130 131 3 Q 9 12 DDR1 RCOMP 1 COMP Resistance 25 839 26 1 26 361 Q 9 12 DDR1 RCOMP 2 COMP Resistance 198 200 202 Q 9 12 DDR23
71. PCIEX3 Intel Xeon Processor 5 2400 v2 Product Family 164 Datasheet Volume One Processor Land Listing intel Table 8 1 Land Name Sheet 17 of 37 Table 8 1 Land Name Sheet 18 of 37 Land Name Land Buffer Type Direction Land Name Land Buffer Type Direction Number Number PE3B_TX_DP 4 AM39 PCI EX3 0 PEHPSDA AP30 ODCMOS 1 0 PE3B_TX_DP 5 AN40 PCIEX3 5 PE3B_TX_DP 6 AP39 PCIEX3 PRDY 11 CMOS PE3B_TX_DP 7 AR40 PCIEX3 PREQ AR10 CMOS 1 0 PE3C_RX_DN 10 AY34 PCIEX3 PROCHOT_N AH7 ODCMOS 1 0 PE3C_RX_DN 11 AW33 PCIEX3 PWRGOOD AK6 CMOS PE3C_RX_DN 8 AY36 PCIEX3 RBIAS 1 Analog 1 0 PE3C_RX_DN 9 AW35 PCIEX3 RBIAS SENSE AL13 Analog DP 10 AW34 PCIEX3 VREF CAP AM13 Intel QPI 1 0 PE3C_RX_DP 11 AV33 PCIEX3 1 CLKRX DN AL5 Intel PE3C_RX_DP 8 AW36 PCIEX3 QPI1 CLKRX DP AL6 Intel DPI 9 AV35 PCIEX3 QPI1 CLKTX DN AY9 Intel PE3C TX 10 41 PCI EX3 QPI1 CLKTX DP BA9 Intel PE3C TX 11 42 PCIEX3 QPI 1 DRX DN O0O 4 Intel PE3C_TX_DN 8 AK41 PCIEX3 1 011 1 Intel PE3C_TX_DN 9 AL42 PCI
72. PWR VSA AG41 PWR VCC U33 PWR VSA AH37 PWR VCC V11 PWR VSA AJ41 PWR VCC v33 PWR VSA AL38 PWR VCC Wil PWR VSA AL41 PWR VCC w33 PWR VSA AM37 PWR VCC Y11 PWR VSA 41 PWR VCC Y33 PWR VSA AR41 PWR VCC_SENSE P11 VSA AT40 PWR VCCD E21 PWR VSA AV40 PWR 6 AV43 PWR Intel Xeon Processor E5 2400 v2 Product Family 169 Datasheet Volume One Processor Land Listing tel Table 8 1 Land Name Sheet 27 of 37 Table 8 1 Land Name Sheet 28 of 37 Land Name Minnie Buffer Type Direction Land Name up Buffer Type Direction VSA AY42 PWR VSS AE3 GND VSA SENSE AE33 VSS AF10 GND VSS A14 GND VSS AF2 GND VSS A19 GND VSS AF40 GND VSS A24 GND VSS AF43 GND VSS A29 GND VSS AF5 GND VSS A4 GND VSS AF6 GND VSS A40 GND VSS AF8 GND VSS A41 GND VSS AG1 GND VSS A5 GND VSS AG35 GND VSS AA10 GND VSS AG38 GND VSS AA34 GND VSS 4 GND VSS 7 GND VSS AH33 GND VSS AA4 GND VSS AH36 GND VSS AA40 GND VSS AH40 GND VSS AA7 GND VSS AH43 GND VSS AB10 GND VSS AH6 GND VSS AB36 GND VSS AJ1 GND VSS AB37 GND VSS 11 GND VSS ABA GND VSS AJ35 GND VSS 40 GND VSS 38 GND VSS AB7 GND VSS 4 GND VSS AC10 GND VSS 9 GND VSS AC33 GND VSS AK14 GND VSS AC36 GND
73. Processor Asynchronous Sideband Miscellaneous and Power Other signals Refer to Table 7 5 for details Detailed layout routing and termination guidelines corresponding to these signal groups can be found in the applicable platform design guide Refer to Section 1 7 Related Documents Intel strongly recommends performing analog simulations of all interfaces Please refer to Section 1 7 Related Documents for signal integrity model availability 7 1 1 System Memory I nterface Signal Groups The system memory interface utilizes DDR3 technology which consists of numerous signal groups These include Reference Clocks Command Signals Control Signals and Data Signals Each group consists of numerous signals which may utilize various signaling technologies Please refer to Table 7 5 for further details Throughout this chapter the system memory interface maybe referred to as DDR3 7 1 2 Express Signals The PCI Express Signal Group consists of PCI Express ports land 3 and PCI Express miscellaneous signals Please refer to Table 7 5 for further details 7 1 3 DMI 2 PCI Express Signals The Direct Media I nterface Gen 2 DMI 2 sends and receives packets and or commands to the PCH The DMI2 is an extension of the standard PCI Express Specification The DMI 2 PCI Express Signals consist of DMI2 receive and transmit input output signals and a control signal to select DMI2 or PCle 2 0 operation for port 0 Please refer to Tabl
74. Processor E5 2400 v2 Product Family 155 Datasheet Volume One Figure 7 12 Maximum Acceptable Overshoot Undershoot Waveform Over Shoot Duration Under Shoot Duration Under Shoot Intel Xeon Processor E5 2400 v2 Product Family 156 Datasheet Volume One Processor Land Listing tel 8 Processor Land Listing This chapter provides sorted land list in Section 8 1 and Section 8 2 Table 8 1 is a listing of all Intel Xeon processor E5 2400 v2 product family lands ordered alphabetically by land name Table 8 2 is a listing of all processor lands ordered by land number 8 1 Listing by Land Name Table 8 1 Land Name Sheet 1 of 37 Table 8 1 Land Name Sheet 2 of 37 Land TE Land irecti Land Name Number Buffer Type Direction Land Name Number Buffer Type Direction BCLKO DN AP13 CMOS DDR1_CAS_N K13 SSTL 0 BCLKO DP AR13 CMOS DDR1_CKE 0 K25 SSTL BCLK1_DN AM30 CMOS DDR1_CKE 1 126 SSTL o DP AN30 CMOS DDR1_CKE 2 125 SSTL BIST_ENABLE AF4 CMOS DDR1_CKE 3 H26 SSTL BMCINIT AF1 CMOS CLK DNIO H17 SSTL _ 0 110 ODCMOS 1 0 DDR1_CLK_DN 1 G19 SSTL BPM_N 1 AL11 ODCMOS 1 0 DDR1_CLK_DN 2 H16 SSTL
75. QuickPath Interconnect Intel The Intel QuickPath Interconnect is a high speed packetized point to point interconnect used in the processor The narrow high speed links stitch together processors in distributed shared memory and integrated I O platform architecture It offers much higher bandwidth with low latency The Intel QuickPath Interconnect has an efficient architecture allowing more interconnect performance to be achieved in real systems It has a snoop protocol optimized for low latency and high scalability as well as packet and lane structures enabling quick completions of transactions Reliability availability and serviceability features RAS are built into the architecture The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a differential forwarded clock Each port supports a link pair consisting of two uni directional links to complete the connection between two components This supports traffic in both directions simultaneously To facilitate flexibility and longevity the interconnect is defined as having five layers Physical Link Routing Transport and Protocol The Physical layer consists of the actual wires carrying the signals as well as circuitry and logic to support ancillary features required in the transmission and receipt of the 1s and Os The unit of transfer at the Physical layer is 20 bits which is called a Phit for Physical unit The Lin
76. RdPCI ConfigLocal May require package pop up to C2 state WrPCI ConfigLocal May require package pop up to C2 state Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 70 Table 2 18 Power Impact of PECI Commands vs C states Sheet 2 of 2 Command Power I mpact RdPCI Config May require package pop up to C2 state 2 5 3 5 S states The processor PECI client is always guaranteed to be operational in the SO sleep state The Ping GetDIB GetTemp RdPkgConfig WrPkgConfig RdPCI ConfigLocal and WrPCI ConfigLocal will be fully operational in SO and S1 Responses in S3 or deeper states are dependent on POWERGOOD assertion status e The RdPCI Config and RdIAMSR responses are guaranteed SO only Behavior in S1 or deeper states is indeterminate PECI behavior is indeterminate in the S3 S4 and S5 states and responses to PECI originator requests when the PECI client is in these states cannot be guaranteed 2 5 3 6 Processor Reset The processor PECI client is fully reset on all RESET N assertions Upon deassertion of RESET where power is maintained to the processor otherwise known as warm reset the following are true The PECI client assumes a bus Idle state The Thermal Filtering Constant is retained PECI SOCKET ID is retained GetTemp reading resets to 0x0000 Any transaction in progress is aborted by the client as measured by
77. SSTL 1 0 DDR2 001161 38 SSTL 1 0 DDR2_DQ 54 U6 SSTL 1 0 DDR2_DQ 17 39 SSTL 1 0 DDR2 DQ 55 U5 SSTL 1 0 DDR2 001181 H36 SSTL 1 0 DDR2 DQ 56 AA6 SSTL 1 0 DDR2_DQ 19 G36 SSTL 1 0 DDR2 DQ 57 AA5 SSTL 1 0 DDR2 DQ 20 K38 SSTL 1 0 DDR2_DQ 58 AE6 SSTL DDR2_DQ 21 K39 SSTL 1 0 DDR2_DQ 59 AE5 SSTL 1 0 DDR2 001221 H37 SSTL 1 0 DDR2 001601 Y6 SSTL 1 0 DDR2_DQ 23 G37 SSTL 1 0 DDR2 DQ 61 Y5 SSTL 1 0 DDR2_DQ 24 D39 SSTL 1 0 DDR2_DQ 62 AD6 SSTL 1 0 DDR2 DQ 25 C39 SSTL 1 0 DDR2 DQ 63 AD5 SSTL 1 0 DDR2 001261 C37 SSTL 1 0 DDR2 DQS DN 00 AA39 SSTL 1 0 DDR2_DQ 27 E37 SSTL 1 0 DDR2_DQS_DN 01 P39 SSTL 1 0 DDR2 001281 E38 SSTL 1 0 DDR2_DQS_DN 02 G39 SSTL 1 0 DDR2_DQ 29 E39 SSTL 1 0 DDR2_DQS_DN 03 C38 SSTL 1 0 DDR2 DQ 30 D37 SSTL 1 0 DDR2_DQS_DN 04 D7 SSTL 1 0 DDR2 DQ 31 B37 SSTL 1 0 DDR2_DQS_DN 05 G7 SSTL 1 0 DDR2_DQ 32 09 SSTL 1 0 DDR2 005 DN 06 T6 SSTL 1 0 DDR2_DQ 33 E9 SSTL 1 0 DDR2_DQS_DN 07 AC6 SSTL 1 0 DDR2_DQ 34 5 SSTL 1 0 DDR2_DQS_DN 08 E31 SSTL 1 0 DDR2 DQ 35 D5 SSTL 1 0 DDR2_DQS_DN 09 AB38 SSTL 1 0 DDR2 DQ 36 D10 SSTL 1 0 DDR2_DQS_DN 10 R38 SSTL 1 0 DDR2 DQ 37 E10 SSTL 1 0 DDR2_DQS_DN 11 H38 SSTL 1 0 DDR2_DQ 38 D6 SSTL 1 0 DDR2 DQS DN 12 A39 SSTL DDR2 0901391 SSTL 1 0 DDR2_DQS_DN 13 E8 SSTL 1 0 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 160 Processor Land Listing intel
78. Specifications Figure 10 12 4 Pin Base Baseboard Fan Header For Active Heat Sink 1 2 20 830 11 29455 VANES 400 5 ws 04 daw 30317027 1511 518 4 WO 14149530 W38MhN 1894 ni 401 RG PIL 34 ONY ONINOISNIWIG i O APEIN 30 ALOIGYAMYTS 11 WOK INIM JAYH TIVHS 1 4 13 51 134 11111 14 AWOAL 200709 2 A NOTAN OY S31 1 15310453109 620 W 1720499 L 525028 3N1 802 203291 6271 9 rit ETUR CT LAOH Kt 211 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One Boxed Processor Specifications 10 2 2 10 3 Boxed Processor Retention Mechanism and Heat Sink Support URS Baseboards designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor Refer to Figure 10 5 through Figure 10 8 for LGA1356 mounting hole dimensions LGA1356 Unified Retention System URS and the Unified Backplate Assembly The URS is designed to extend air cooling capability through the use of larger heat sinks with minimal airflow blockage and bypass URS retention transfers load to the baseboard via th
79. T42 GND VTTA AY2 PWR VSS T7 GND VTTA AN35 PWR VSS U10 GND VTTA AP33 PWR VSS U2 GND AP34 PWR vss U34 GND 5 PWR vss U37 GND AV34 PWR VSS U4 GND VTTD 9 PWR vss 040 GND VTTD 7 PWR vss U7 GND VTTD AK3 PWR VSS V10 GND VTTD AK30 PWR VSS V35 GND VTTD AN7 PWR VSS V36 GND VTTD AP3 PWR VSS V38 GND VTTD AV30 PWR vss v39 GND VTTD AV32 PWR VSS V4 GND VTTD BA30 PWR VSS V42 GND VTTD M14 PWR vss V43 GND VTTD M15 PWR VSS V7 GND VTTD M17 PWR wi cn VTTD M25 PWR Intel Xeon Processor E5 2400 v2 Product Family 174 Datasheet Volume One Processor Land Listing Table 8 2 Land Number Sheet 2 of 37 Land Name pos Direction 11 VCC PWR DDR1 001571 SSTL 1 0 AA33 PWR AA34 vss GND AA35 DDR1_DQS_DN 00 SSTL 1 0 AA36 DDR1 DQS DP 00 SSTL 1 0 AA37 vss GND AA38 DDR2 DQS DP 00 SSTL 1 0 AA39 DDR2_DQS_DN 00 SSTL 1 0 AAA vss GND AA4O VSS GND AA41 DDR3_DQS_DP 00 SSTL 1 0 AA5 DDR2 001571 SSTL 1 0 AAG DDR2_DQ 56 SSTL 1 0 AAT VSS GND DDR1 01491 SSTL 1 0 AAQ DDR1_DQ 48 SSTL 1 0 AB10 VSS GND AB11 PWR AB3 DDR1 DQS DP 16 SSTL 1 0 AB33 VCC PWR AB34 DDR1_DQS_DP 09 SSTL 1 0 AB35 DDR1_DQS_DN 09 SSTL 1 0 AB36 VSS GND AB37 VSS GND AB38 DDR2
80. Unknown I Illegal Request CC 0x91 control hardware firmware or associated logic error The processor is unable to process the request CC 0x93 Pcode MCA access allowed but access cannot be completed CC 0x94 Pcode MCA access allowed and access completes Will respond with the data along with the response code 2 5 2 5 WrPkgConfig The WrPkgConfig command provides write access to the package configuration space PCS within the processor including various power and thermal management functions Typical PCS write services supported by the processor may include power limiting thermal averaging constant programming and so on Refer to Section 2 5 2 6 for more details on processor specific services supported through this command Intel Xeon Processor E5 2400 v2 Product Family 35 Datasheet Volume One 2 5 2 5 1 The WrPkgConfig format is as follows Write Length 0x0a dword Read Length 0x01 Command 0xa5 AW FCS Support Yes Description Writes data to the processor PCS entry as specified by the index and parameter fields This command supports only dword data writes on the processor PECI clients All command responses include a completion code that provides additional pass fail status information Refer to Section 2 5 5 2 for details regarding completion codes The Assured Write FCS AW FCS support provides the pr
81. VSS AK17 GND VSS AC4 GND VSS AK20 GND VSS AC40 GND VSS AK23 GND VSS AC43 GND VSS AK26 GND VSS AC7 GND VSS AK29 GND VSS GND VSS AK31 GND VSS AD10 GND VSS AK37 GND VSS AD33 GND VSS AK40 GND VSS AD36 GND VSS AK43 GND VSS AD38 GND VSS AL1 GND VSS AD4 GND VSS AL14 GND VSS AD41 GND VSS AL17 GND VSS AD7 GND VSS AL20 GND Ws GND vss AL23 GND Intel Xeon Processor E5 2400 v2 Product Family 170 Datasheet Volume One Processor Land Listing tel Table 8 1 Land Name Sheet 29 of 37 Table 8 1 Land Name Sheet 30 of 37 Land Name Buffer Direction Land Name Buffer Type Direction VSS AL26 GND VSS AR17 GND VSS AL29 GND VSS AR20 GND VSS AL35 GND VSS AR23 GND VSS AL4 GND VSS AR26 GND VSS AL8 GND VSS AR29 GND VSS AM10 GND VSS AR32 GND VSS AM17 GND VSS AR34 GND VSS AM20 GND VSS AR38 GND VSS AM23 GND VSS AR4 GND VSS AM26 GND VSS AT11 GND VSS AM29 GND VSS AT13 GND VSS AM33 GND VSS AT17 GND VSS AM40 GND VSS AT20 GND VSS AM43 GND VSS AT23 GND VSS AM6 GND VSS AT26 GND VSS AN1 GND VSS AT29 GND VSS AN12 GND VSS AT31 GND VSS AN13 GND VSS AT43 GND VSS AN17 GND VSS AT9 GND VSS AN20 GND VSS AU1 GND VSS AN23 GND VSS AU17 GND VSS AN26 GND VSS AU20 GND
82. VSS AN29 GND VSS AU23 GND VSS AN31 GND VSS AU26 GND VSS AN38 GND VSS AU33 GND VSS AN4 GND VSS AU35 GND VSS AP14 GND VSS AU37 GND VSS AP17 GND VSS AU41 GND VSS AP20 GND VSS AU5 GND VSS AP23 GND VSS AV10 GND VSS AP26 GND VSS AV12 GND VSS AP29 GND VSS AV14 GND VSS AP40 GND VSS AV17 GND VSS AP43 GND VSS AV20 GND VSS AP6 GND VSS AV23 GND VSS AP9 GND VSS AV26 GND VSS 1 GND VSS AV3 GND Wvs VSS AV6 GND Intel Xeon Processor E5 2400 v2 Product Family 171 Datasheet Volume One Processor Land Listing tel Table 8 1 Land Name Sheet 31 of 37 Table 8 1 Land Name Sheet 32 of 37 Land Name Frana Buffer Type Direction Land Name un Buffer Type Direction VSS AV8 GND VSS C25 GND VSS AW1 GND VSS C30 GND VSS AW17 GND VSS C31 GND VSS AW20 GND vss C32 GND vss AW23 GND VSS C36 GND vss AW26 GND VSS C40 GND VSS AW29 GND vss C43 GND vss AW31 GND VSS 5 GND vss AW39 GND VSS C6 GND VSS AWA GND VSS C7 GND VSS AW42 GND VSS C8 GND VSS AY17 GND VSS C9 GND VSS AY20 GND VSS 01 GND VSS AY26 GND VSS D13 GND VSS AY33 GND VSS D18 GND VSS AY35 GND VSS D20 GND VSS AY37 GND VSS D33 GND VSS AY5 GND VSS D34 GND VSS B12 GND VSS D35 GND VSS B17 GND VSS D36 GND VSS B27 GND V
83. VSS GND AD35 DDR1_DQ 05 SSTL 1 0 AB41 DDR3 DQS DN 00 SSTL 1 0 AD36 VSS GND AB42 DDR3 DQS DP 09 SSTL 1 0 AD37 DDR2 001041 SSTL 1 0 AB43 DDR3 DQS DN 09 SSTL 1 0 AD38 VSS GND AB5 DDR2_DQS_DN 16 SSTL 1 0 AD39 VSA PWR AB6 DDR2 DQS DP 16 SSTL 1 0 AD4 VSS GND AB7 VSS GND AD40 DRAM PWR OK C23 CMOS 1 5 V 8 DDR1_DQS_DN 15 SSTL 1 0 AD41 VSS GND AB9 DDR1_DQS_DP 15 SSTL 1 0 AD42 DDR3 DQ 04 SSTL 1 0 1 DDR1_DQS_DP 07 SSTL 1 0 AD43 DDR3_DQ 05 SSTL 1 0 AC10 VSS GND AD5 DDR2 DQ 63 SSTL 1 0 11 VCC PWR AD6 DDR2_DQ 62 SSTL 2 DDR1_DQS_DN 07 SSTL 1 0 AD7 VSS GND AC3 DDR1 DQS DN 16 SSTL 1 0 AD8 DDR1 DQ 55 SSTL 1 0 AC33 VSS GND AD9 DDR1 DQ 54 SSTL 1 0 AC34 DDR1_DQ 00 SSTL 1 0 1 DDR1 DQ 58 SSTL 1 0 AC35 DDR1_DQ 01 SSTL 1 0 AE10 VSS GND AC36 vss GND 11 VCC PWR 7 DDR2_DQ 05 SSTL 1 0 AE2 DDR1 DQ 59 SSTL 1 0 AC38 DDR2_DQ 01 SSTL 1 0 AE3 VSS GND AC39 DDR2_DQ 00 SSTL 1 0 AE33 VSA_SENSE AC4 VSS GND AE34 VSS_VSA_SENSE AC40 VSS GND AE35 VSA PWR AC41 DDR3_DQ 00 SSTL 1 0 AE36 VSA PWR AC42 DDR3_DQ 01 SSTL 1 0 AE37 VSA PWR AC43 vss GND AE38 VSA PWR AC5 DDR2 DQS DP 07 SSTL 1 0 AE39 PE1A_TX_DP 0 PCIEX3 6 DDR2 DQS DN 07 SSTL 1 0 AE4 TXT_AGENT CMOS 7 VSS GND AE40 1 _ _ 0 1 DDR1 DQS DP 06 SSTL 41 VSA PWR 9 DDR1 DQS DN 06 SSTL 1 0 AE42 VSA PWR AD1 VSS GND AE43 VSA PWR AD10 VSS GND AE5 DDR2_DQ 59 SSTL 1 0
84. Volume Two Registers for details The processor extends the FRB capability to the core granularity by maintaining a register in the uncore so that BIOS or another entity can disable one or more specific processor cores Additional details can be found in the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers Table 7 8 Fault Resilient Booting Output Tri State Signals Output Tri State Signal Groups Signals Intel QPI QPIO_CLKTX_DN 1 0 QPIO_CLKTX_DP 1 0 QPIO_DTX_DN 19 00 QPIO_DTX_DP 19 00 QPI1 CLKTX DN 1 0 QPI1 CLKTX DP 1 0 QPI1 DTX DN 19 00 QPI1 DTX DP 19 00 SMBus DDR SCL DDR SDA C1 DDR SCL C23 DDR SDA C23 PEHPSCL PEHPSDA Processor Sideband CAT ERR N ERROR N 2 0 BPM N 7 0 PRDY N PROCHOT SVID SVIDCLK 7 5 Mixing Processors Intel supports and validates twoprocessor configurations only in which all processors operate with the same Intel QuickPath Interconnect frequency core frequency power segment and have the same internal cache sizes Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel Combining processors from different power segments is also not supported Note Processors within a system must operate at the same frequency per bits 15 8 of the FLEX_RATIO MSR Address 194h however this does not apply to frequency transitions initiated due to thermal events Extended HALT Enhanced
85. can be made to the LLC in this state the cores must break out to the internal state package C2 for snoops to occur Intel amp Xeon Processor E5 2400 v2 Product Family 94 Datasheet Volume One 4 2 6 Package C State Power Specifications intel The table below lists the processor package C state power specifications for various processor SKUs Table 4 10 Package C State Power Specifications TDP SKUs C1E W c3 W c6 W 95W 10 core 46 20 14 95W 8 core 50 35 14 19 E5 2440 v2 80W 6 core 37 27 13 16 E5 2420 v2 80W 4 core 37 27 13 80W 4 core 15 42 24 13 80W 2 15 42 24 14 60W 10 core 34 16 13 60W 6 core 34 16 12 LV70W 10C 10 core 43 20 13 LV60W 8C 8 core 34 16 13 LV60W 8C 6 core 15 34 16 12 LV50W 6C 6 core 18 12 12 LV40W 2C 2 core 15 19 14 12 Notes 1 SKU s are subject to change Please contact your Intel Field Representative to obtain the latest SKU information 2 Package CIE power specified at Tcase 60 C 3 Package C3 C6 power specified at Tcase 50 4 2 7 The Pmax values are subject to change Table 4 11 Pmax Specifications Table Processor P max Power Specifications Processor TDP W Core Count Pmax W 95W 10 160 95W 8 145 80W 6 105 80W 4 105 80W 15 4 90 80W 15 2 90 60W 10 90 60W 6 90 LV70W 10C 10 110 LV60W 8C
86. capacitance and 1 MO minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe 5 and voltage specification requirements are measured across the remote sense pin pairs SENSE and VSS vib SENSE on the processor package Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit or DC to 20 MHz for older model oscilloscopes using a 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe 6 The Vs voltage specification requirements are measured across the remote sense pin pairs VSA_SENSE and VSS VSA SENSE on the processor package Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit or DC to 20 MHz for older model oscilloscopes using a 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe 7 Forthe Intel Xeon processor E5 2400 v2 product family processor refer to Table 7 13 and corresponding Figure 7 3 The processor should not be subjected to any static Vcc level that exceeds the associated with any particular current
87. disabled by BIOS the Processor ID mapping will not change The total number of Processor IDs on a CPU is product specific Processor ID enumeration involves discovering the logical processors enabled within the CPU package This can be accomplished by reading the Max Thread ID value through the RdPkgConfig command Index 0 Parameter 3 described in Section 2 5 2 6 12 and subsequently querying each of the supported processor threads Unavailable processor threads will return a completion code of 0x90 Alternatively this information may be obtained from the RESOLVED CORES MASK register readable through the RdPCIConfigLocal command described in Section 2 5 2 9 or other means Bits 7 0 and 9 8 of this register contain the Core Mask and Thread Mask information respectively The Thread Mask applies to all the enabled cores within the processor package as indicated by the Core Mask For the processor PECI clients the Processor ID may take on values in the range 0 through 15 Figure 2 42 Processor I D Construction Example C7 C6 5 2 1 15 14 1 12 11 10 9 8 7 6 5 4 3 2 1 0 Processor ID 0 15 Thread 0 1 Mask for Core4 Intel Xeon Processor E5 2400 v2 Product Family 60 Datasheet Volume One Figure 2 43 Rdl AMSR Byte 0 1 2 3 Write Length Read Length Cmd Code inition 5 6 7 8 4 rt LSB MSR Address FCS 9 10 11 12 13
88. function of the guaranteed exit latency requirement from the platform There is also a concept of Execution Allowed EA when EA status is O the cores in a Socket are in C3 or a deeper state a socket initiates a request to enter a coordinated package C state The coordination is across all sockets and the PCH Table 4 9 shows an example of a dual core processor package C state resolution Figure 4 3 summarizes package C state transitions with package C2 as the interim between PCO and 1 prior to PC3 and PC6 Table 4 9 Coordination of Core Power States at the Package Level Core 1 Package C State co Ci 6 CO CO CO CO o cii CH cii 5 1 8 CO C1 C3 C3 C6 CO cii C3 C6 Notes 1 The package C state will be CIE if all actives cores have resolved a core C1 state or higher Intel Xeon Processor E5 2400 v2 Product Family 92 Datasheet Volume One tel Figure 4 3 Package C State Entry and Exit 4 2 5 1 4 2 5 2 N T NS 4 b 4 d N Ve YF y 2 The normal operating state for the processor The processor remains the normal state when at least one of its cores is in the CO or C1 state or when the platform has not granted permission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in C
89. ignoring ECC These devices are usually but not always mounted on a single side of a DDR3 DIMM 5 System Control Interrupt Used ACPI protocol SSE Intel Streaming SIMD Extensions Intel SSE SKU A processor Stock Keeping Unit SKU to be installed in either server or workstation platforms Electrical power and thermal specifications for these SKU s are based on specific use condition assumptions Server processors may be further categorized as Efficient Performance server workstation and HPC SKUs For further details on use condition assumptions please refer to the latest Product Release Qualification PRQ Report available via your Customer Quality Engineer CQE contact SMBus System Management Bus A two wire interface through which simple system and power management related devices can communicate with the rest of the system It is based on the principals of the operation of the I2C two wire serial bus from Philips Semiconductor Storage Conditions A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any 1 5 biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensi
90. indicate support for three memory channels Refer to Table 2 1 for the list of PECI commands supported by the processors Summary of Processor specific PECI Commands Command Supported on the Processor Ping Yes GetDI B Yes GetTemp Yes RdPkgConfig Yes WrPkgConfig Yes RdlAMSR Yes WrlAMSR No RdPCI Config Yes WrPCI Config No RdPCI ConfigLocal Yes WrPCI ConfigLocal Yes PECI Client Capabilities The processor PECI client is designed to support the following sideband functions Intel amp Xeon Processor E5 2400 v2 Product Family 29 Datasheet Volume One 2 5 1 1 2 5 1 2 2 5 2 2 5 2 1 2 5 2 1 1 intel Platform manageability functions including thermal power and error monitoring Processor and DRAM thermal management The platform power management includes monitoring and control for both the processor and DRAM subsystem to assist with data center power limiting Thermal Management Processor fan speed control is managed by comparing Digital Thermal Sensor DTS thermal readings acquired via PECI against the processor specific fan speed control reference point or Both and DTS thermal readings are accessible via the processor PECI client These variables are referenced to a common temperature the TCC activation point and are both defined as negative offsets from that reference PECI based access to the pr
91. is used only when no DIMM temperature information is available from on board or on die DIMM thermal sensors It is also possible for the PECI host controller to read back the DIMM ambient reference temperature Since the ambient temperature may vary over time within a system it is recommended that systems monitoring and updating the ambient temperature at a fast rate use the maximum temperature value while those updating the ambient temperature at a slow rate use an average value The ambient temperature assumes a single value for all memory channel DIMM locations and does not account for possible temperature variations based on DIMM location Ambient Temperature Reference Data 31 Ambient Temperature in Degrees C Ambient Temperature Reference Data DRAM Channel Temperature Read This feature enables a PECI host read of the maximum temperature of each channel This would include all the DIMMs within the channel and all the ranks within each of the DIMMs Channels that are not populated will return the ambient temperature on systems using activity based temperature estimations or alternatively return a zero for systems using sensor based temperatures Intel Xeon Processor E5 2400 v2 Product Family 41 Datasheet Volume Figure 2 16 2 5 2 6 7 Figure 2 17 2 5 2 6 8 DRAM Channel Temperature Channel 3 Channel 2 Channel 1 Maximum Temperature Maximum Temperature Ma
92. lbs 9 5 Package Insertion Specifications The processor can be inserted into and removed from an 1356 socket 15 times The socket should meet the 1356 requirements detailed in the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG Intel Xeon Processor E5 2400 v2 Product Family 198 Datasheet Volume One Package Mechanical Specifications tel 9 6 Processor Mass Specification The typical mass of the processor is currently 35 grams This mass weight includes all the components that are included in the package 9 7 Processor Materials Table 9 3 lists some of the package components and associated materials Table 9 3 Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Halogen Free Fiber Reinforced Resin Substrate Lands Gold Plated Copper 9 8 Processor Markings Figure 9 4 shows the topside markings on the processor This diagram is to aid in the identification of the processor Figure 9 4 Processor Top Side Markings Legend Mark Text Engineering Mark GRPILINE1 i M C YY GRP2LINE2 INTEL CONFIDENTIAL GRP3LINE3 QDFES SPEED GRP4LINE4 GRP1LINE1 GRPSLINES FPO e4 GRP 1LINE2 GRP 1ILINES GRP 111 Legend Mark Text Production Mark GRP1ILINES GRP1ILINE1 i M C YY GRP2LINE2 SUB BRAND PROC GRP3LINE3 SSPEC SPEED GRP4LINE4 5 5 FPO e
93. management system uses as a control set point 15 also defined as negative number below Tprochot May be extracted from the processor by issuing a PECI RdPkgConfig command as described in Section 2 5 2 4 or using a RDMSR instruction application to fan speed control management is defined in the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG Please refer to Section 2 5 7 for details regarding PECI temperature data formatting Command Format The GetTemp format is as follows Write Length 0x01 Read Length 0x02 Command 0x01 Description Returns the highest die temperature for addressed processor PECI client GetTemp Byte 0 1 2 3 Write Length Read Length Cmd Code Definition 4 5 6 7 FCS Temp 7 0 Temp 15 8 FCS Intel Xeon Processor E5 2400 v2 Product Family 33 Datasheet Volume One intel Example bus transaction for a thermal sensor device located at address 0x30 returning a value of negative 10 counts is show in Figure 2 9 Figure 2 9 GetTemp Example 2 5 2 3 2 Table 2 3 2 5 2 4 2 5 2 4 1 Byte 0 1 2 3 Definition 4 5 6 7 Supported Responses The typical client response is a passing FCS and valid thermal data Under some conditions the client s response will indicate a failure GetTemp response definitions are listed in Table 2 3 Refer to Section 2 5 7 4 for more
94. on the platform Choose vias close to the socket and measure with a DC to 100MHz bandwidth oscilloscope limit DC to 20 MHz for older model oscilloscopes using 1 5 pF maximum probe capacitance and 1M Q minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe Vcc has a Vboot setting of 0 0V and is not included in the PWRGOOD indication Refer to the VR12 I Pulse Width Modulation Specification lt has a Vboot setting of 0 9V Refer to the VR12 IMVP7 Pulse Width Modulation Specification Table 7 12 Processor Supply Current Specifications Parameter and Definition Processor TDP Core count pr res Notes Termination Supply 16 20 Processor Current on Isa System Agent Supply 18 19 Processor Current 2 3 6 l PLL Supply All Intel Xeon Processor E5 2400 v2 Product 2 2 Processor Current Family Memory Controller DDR3 Supply 5 7 Processor Current on Vccp 53 Memory Controller Supply 1 45 Processor Current while in System 53 Standby State 95W 10 core 8 core 106 135 80W 6 core 4 core 80 85 80W 4 core 1S 2 core 1S 70 80 Icc LV70W 10C 90 110 Core Processor Supply 2 3 6 Processor Current on Vcc 60W 10 6
95. plane enables turbo modes for associated logic External VR protection is guaranteed during boot through operation at safe voltage and frequency RAPL parameter values including the power limit value control time window clamp mode and enable bit will have to be specified correctly even if the intent is to change just one parameter value when programming over PECI The usefulness of the VCC power plane RAPL may be somewhat limited if the platform has a fully compliant external voltage regulator However platforms using lower cost voltage regulators may find this feature useful The VCC RAPL value is generally expected to be a static value after initialization and there may not be any use cases for dynamic control of VCC plane power limit values during run time BIOS may be ideally used to read the VR and associated heat sink capabilities and program the PCU with the power limit information during boot No matter what the method is Intel recommends exclusive use of just one entity or interface PECI for instance to manage VCC plane power limiting needs If PECI is being used to manage VCC plane power limiting activities BIOS should lock out all subsequent inband VCC plane power limiting accesses by setting bit 31 of the POWER LIMIT MSR and CSR to 1 The same conversion formula used for DRAM Power Limiting see Section 2 5 2 6 9 should be applied for encoding or programming the Control Time Window in bits 23 17 Intel Xeon
96. power limit value outside of the range specified through these settings power regulation cannot be guaranteed Since this data is 64 bits wide facilitates access to this register by allowing two requests to read the lower 32 bits and upper 32 bits separately as shown in Table 2 8 Power units for this read are determined as per the Package Power SKU Unit settings described in Section 2 5 2 6 13 Package Power SKU data is programmed by the PCU firmware during boot time based on SKU dependent power on default values set during manufacturing The TDP package power specified through bits 14 0 in Figure 2 28 is the maximum value of the Power Limit1 field in Section 2 5 2 6 26 while the maximum package power in bits 46 32 is the maximum value of the Power Limit2 field Intel Xeon Processor E5 2400 v2 Product Family 50 Datasheet Volume One intel The minimum package power in bits 30 16 is applicable to both the Power Limit1 Power Limit2 fields and corresponds to a mode when all the cores are operational and in their lowest frequency mode Attempts to program the power limit below the minimum power value may not be effective since BIOS OS and not the PCU controls disabling of cores and core activity The maximum time window in bits 54 48 is representative of the maximum rate at which the power control unit PCU can sample the package energy consumption and reactively take the necessary measures to
97. processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point via the intermediate SVI D frequency points Transition of the SVID code will occur first to insure proper operation once the processor reaches its normal operating frequency Refer to Figure 5 6 for an illustration of this ordering Intel Xeon Processor E5 2400 v2 Product Family 110 Datasheet Volume One Figure 5 6 Frequency and Voltage Ordering Frequency 5 2 2 2 Clock Modulation Clock modulation is performed by alternately turning the clocks off and on at a duty cycle specific to the processor factory configured to 37 5 on and 62 5 off for TM1 The period of the duty cycle is configured to 32 microseconds when the TCC is active Cycle times are independent of processor frequency A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases Clock modulation is automatically engaged as part of the TCC activation when the Freq
98. substrate 5 Capacitors Figure 9 1 Processor Package Assembly Sketch Die TIM IHS N substrate 3 S Capacitor l4 1356 Socket System Board 1 Socket and baseboard are included for reference and are not part of the processor package 9 1 Package Mechanical Drawing The package mechanical drawing is shown in Figure 9 2 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include 1 Package reference with tolerances total height length width and so forth 2 IHS parallelism and tilt 3 Land dimensions 4 Top side and back side component keep out dimensions 5 Reference datums 6 All drawing dimensions are in mm Intel Xeon Processor E5 2400 v2 Product Family 194 Datasheet Volume One Package Mechanical Specifications tel 7 Guidelines on potential 5 flatness variation with socket load plate actuation installation of the cooling solution is available in the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG Intel Xeon Processor E5 2400 v2 Product Family 195 Datasheet Volume One intel Package Mechanical Specifications Sheet 1 of 2 Processor Package Drawi 2 9 Figure 196 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One Package Mechanical Specifications Figure 9 3 Processor Packa
99. the Data Link Layer serves as intermediate stage between the Transaction Layer and the Physical Layer Responsibilities of Data Link Layer include link management error detection and error correction The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer calculates and applies data protection code and TLP sequence number and submits them to Physical Layer for transmission across the Link The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing On detection of TLP error s this layer is responsible for requesting retransmission of TLPs until information is correctly received or the Link is determined to have failed The Data Link Layer also generates and consumes packets which are used for Link management functions Physical Layer The Physical Layer includes all circuitry for interface operation including driver and input buffers parallel to serial and serial to parallel conversion PLL s and impedance matching circuitry It also includes logical functions related to interface initialization and maintenance The Physical Layer exchanges data with the Data Link Layer in an implementation specific format and is responsible for converting this to an appropriate serialized format and transmitting it across the Express Link at a frequency and width compatible with the remote device Int
100. the client no longer participating in the response The processor client is otherwise reset to a default configuration PECI commands that utilize processor resources being reset will receive a resource unavailable response till the reset sequence is completed 2 5 3 7 System Service Processor SSP Mode Support Sockets in SSP mode have limited PECI command support Only the following PECI commands will be supported while in SSP mode Other PECI commands are not guaranteed to complete in this mode Ping RdPCI ConfigLocal WrPCI ConfigLocal all uncore and CSRs within the processor PCI configuration space will be accessible RdPkgConfig Index only Sockets remain in SSP mode until the Go handshake is received This is applicable to the following SSP modes Intel Xeon Processor E5 2400 v2 Product Family 71 Datasheet Volume One 2 5 3 7 1 INIT Mode The BMC INIT boot mode is used to provide a quick and efficient means to transfer responsibility for uncore configuration to a service processor like the BMC In this mode the socket performs a minimal amount of internal configuration and then waits for the BMC or service processor to complete the initialization 2 5 3 7 2 Link I nit Mode In cases where the Firmware Agent socket cannot be resolved the socket is placed in Link Init mode The socket performs a minimal amount of internal configuration and waits for complete configuration by BIOS 2
101. this field With any client at least one domain Domain 0 must exist Therefore the Number of Domains reported is defined as the number of domains in addition to Domain 0 For example if bit 2 of the Device Info byte returns a 1 that would indicate that the PECI client supports two domains Device I nfo Device I nfo Field Definition Byte 5 76543210 Reserved of Domains Reserved Revision Number All clients that support the GetDIB command also support Revision Number reporting The revision number may be used by a host or originator to manage different command suites or response codes from the client Revision Number is always reported in the second byte of the GetDIB response The Major Revision number in Figure 2 7 always maps to the revision number of the specification that the client processor is designed to The Minor Revision number value depends on the exact command suite supported by the PECI client as defined in Table 2 2 Revision Number Definition Bytes 6 7 4 3 0 Major Revision Minor Revision Minor Revision Number Meaning Minor Revision Supported Command Suite 0 Ping GetDIB GetTemp Ping GetDIB GetTemp WrPkgConfig RdPkgConfig 1 2 Ping GetDIB GetTemp WrPkgConfig RdPkgConfig RdIAMSR 3 Ping GetDIB GetTemp WrPkgConfig RdPkgConfig RdIAMSR RdPCI ConfigLo
102. with ECC un buffered DIMM configurations 2 1 2 System Memory Timing Support The IMC supports the following DDR3 Speed Bin CAS Write Latency CWL and command signal mode timings on the main memory interface tCL CAS Latency tRCD Activate Command to READ or WRITE Command delay tRP PRECHARGE Command Period CWL CAS Write Latency Command Signal modes 1n indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks Command launch mode programming depends on the transfer rate and memory configuration Intel Xeon Processor E5 2400 v2 Product Family 24 Datasheet Volume One Interfaces 2 2 PCI Express Interface This section describes the Express 3 0 interface capabilities of the processor See the PCI Express Base Specification for details of 55 3 0 2 2 1 PCI Express Architecture Compatibility with the addressing model is maintained to ensure that all existing applications and drivers operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The PCI Express architecture is specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries Refer to Figure 2 1 for the Express Layering Diagram Figure 2 1 Express Layering Diagram Transaction Transaction
103. with a timeout completion Client responds with a timeout code of 0x81 completion code of 0x81 RdPCI ConfigLocal Client responds with a timeout completion Fully functional code of 0x81 WrPCI ConfigLocal Client responds with a timeout completion Fully functional code of 0x81 RdPCI Config Client responds with a timeout completion Fully functional code of 0x81 In the event that the processor is tri stated using power on configuration controls the PECI client will also be tri stated Processor tri state controls are described in Section 7 3 Power On Configuration POC Options Figure 2 49 The Processor Power up Timeline PWRGOOD RESET_N Core execution In Reset Reset uCode Boot BIOS PECI Client Available except core In Reset Data Not Ready Fully Operational services Status SOCKET 1011 01 x X SOCKET ID Valid 2 5 3 2 Device Discovery The PECI client is available on all processors The presence of a PECI enabled processor in a CPU socket can be confirmed by using the Ping command described in Section 2 5 2 1 Positive identification of the PECI revision number can be achieved by issuing the GetDIB command The revision number acts as a reference to the PECI specification document applicable to the processor client definition Please refer to Section 2 5 2 2 for details on GetDIB response formatting 2 5 3 3 Client Addressing The PECI client assumes a defa
104. x y footprint The Intel Xeon processor E5 2400 v2 product family is designed for server embedded and storage applications This processor features one Intel QuickPath Interconnect point to point link capable of up to 8 0 GT s up to 24 lanes of PCI Express 3 0 links capable of 8 0 GT s and 4 lanes of DMI2 PCI Express 2 0 interface with a peak transfer rate of 5 0 GT s The processor supports up to 46 bits of physical address space and 48 bit of virtual address space Included in this family of processors is an integrated memory controller IMC and integrated 1 0 such as PCI Express and 2 on a single silicon die This single die solution is known as a monolithic processor Table 1 2 Volume Structure and Scope Sheet 1 of 2 Volume 1 Electrical Mechanical and Thermal Specification Overview nterfaces Technologies Power Management Thermal Management Specifications Signal Descriptions Electrical Specifications Processor Land Listing Package Mechanical Specifications Intel Xeon Processor E5 2400 v2 Product Family 13 Datasheet Volume One intel Table 1 2 Volume Structure and Scope Sheet 2 of 2 Boxed Processor Specifications Volume 2 Register nformation Configuration Process and Registers Processor Integrated I O IIO Configuration Registers Processor Uncore Configuration Registers Figure 1 1 Processor Two Socket Platform
105. 1 D17 SSTL DDR2_DQS_DP 17 E32 SSTL 1 0 DDR3 BA 2 C27 SSTL DDR2_ECC 0 E33 SSTL 1 0 DDR3_CAS_N B15 SSTL DDR2_ECC 1 F34 SSTL DDR3_CKE 0 B28 SSTL DDR2_ECC 2 E29 SSTL DDR3_CKE 1 B29 SSTL DDR2_ECC 3 D29 SSTL DDR3_CKE 2 A28 SSTL DDR2_ECC 4 E35 SSTL 1 0 DDR3_CKE 3 C28 SSTL DDR2_ECC 5 E34 SSTL 1 0 DDR3_CLK_DN 0 B19 SSTL DDR2_ECC 6 E30 SSTL DDR3_CLK_DN 1 A20 SSTL DDR2_ECC 7 D30 SSTL 1 0 DDR3_CLK_DN 2 18 SSTL 0 DDR2_MA 00 019 SSTL DDR3_CLK_DN 3 C21 SSTL DDR2 MA 01 E22 SSTL DDR3_CLK_DP 0 C19 SSTL DDR2_MA 02 H22 SSTL DDR3_CLK_DP 1 B20 SSTL DDR2_MA 03 G23 SSTL DDR3_CLK_DP 2 B18 SSTL DDR2_MA 04 F23 SSTL DDR3_CLK_DP 3 C20 SSTL DDR2_MA 05 H23 SSTL DDR3 CS N 0 D16 SSTL DDR2_MA 06 E24 SSTL DDR3 CS N 1 B13 SSTL DDR2 MA 07 G24 SSTL DDR3_CS_N 2 B11 SSTL Intel Xeon Processor 5 2400 v2 Product Family 161 Datasheet Volume One Processor Land Listing intel Table 8 1 Land Name Sheet 11 of 37 Table 8 1 Land Name Sheet 12 of 37 Land Name Buffer Direction Land Name un Buffer Type Direction DDR3 CS N 3 D11 SSTL 0 DDR3_DQ 33 B9 SSTL 1 0 DDR3_CS_N 4 15 SSTL DDR3 DQ 34 B5 SSTL
106. 1 0 DDR3_CS_N 5 B14 SSTL 0 DDR3_DQ 35 B4 SSTL 1 0 DDR3 CS N 6 C11 SSTL DDR3_DQ 36 10 SSTL DDR3_CS_N 7 D12 SSTL DDR3 DQ 37 B10 SSTL 1 0 DDR3 001001 41 SSTL DDR3 DQ 38 A6 SSTL 1 0 DDR3_DQ 01 AC42 SSTL DDR3_DQ 39 B6 SSTL 1 0 DDR3_DQ 02 W42 SSTL 1 0 DDR3 DQ 40 E3 SSTL 1 0 DDR3_DQ 03 W43 SSTL 1 0 DDR3 DQ 41 D2 SSTL 1 0 DDR3 001041 AD42 SSTL 1 0 DDR3_DQ 42 G1 SSTL 1 0 DDR3_DQ 05 AD43 SSTL 1 0 DDR3_DQ 43 G2 SSTL 1 0 DDR3 001061 Y41 SSTL 1 0 DDR3 DQ 44 C3 SSTL 1 0 DDR3 DQ O07 W41 SSTL 1 0 DDR3 DQ 45 D3 SSTL 1 0 DDR3 001081 U42 SSTL 1 0 DDR3 DQ 46 F3 SSTL 1 0 DDR3_DQ 09 T43 SSTL 1 0 DDR3_DQ 47 G3 SSTL 1 0 DDR3 DQ 10 41 SSTL 1 0 DDR3_DQ 48 12 SSTL 1 0 DDR3 DQ 11 N43 SSTL 1 0 DDR3 DQ 49 K1 SSTL 1 0 DDR3 DQ 12 941 SSTL 1 0 DDR3 DQ 50 M3 SSTL 1 0 DDR3_DQ 13 043 SSTL 1 0 DDR3 DQ 51 N3 SSTL DDR3 DQ 14 P43 SSTL 1 0 DDR3 DQ 52 SSTL 1 0 DDR3 DQ 15 42 SSTL 1 0 DDR3 DQ 53 jl SSTL 1 0 DDR3 DQ 16 L43 SSTL 1 0 DDR3_DQ 54 M2 SSTL 1 0 DDR3_DQ 17 L42 SSTL 1 0 DDR3 DQ 55 1 SSTL 1 0 DDR3 DQ 18 H43 SSTL 1 0 DDR3 DQ 56 R2 SSTL 1 0 DDR3 DQ 19 41 SSTL 1 0 DDR3 DQ 57 R1 SSTL 1 0 DDR3 DQ 20 M41 SSTL 1 0 DDR3 DQ 58 V1 SSTL 1 0 DDR3_DQ 21 141 SSTL 1 0 DDR3 DQ 59 SSTL 1 0 DDR3_DQ 22 43 SSTL 1 0 DDR3 001601 Pl SSTL 1 0 DDR3_DQ 23 H42 SSTL 1 0 DDR3 DQ 61 R3 SSTL 1 0 DDR3 DQ 24 41 SSTL 1 0 DDR3_DQ 62 91 SSTL 1 0 DDR3 DQ 25 E41 SSTL 1 0 DDR3 DQ 63 V2 SSTL 1 0 DDR3_DQ 26 C41 SSTL
107. 1 Activity Factor cetero TR ER ECRIRE 154 7 9 5 4 Reading Overshoot Undershoot Specification Tables 155 7 9 5 5 Compliance to Overshoot Undershoot Specifications 155 8 Processor Land Listing teretes RR tae XR Ru Rr Men EN E NE aU 157 8 1 Listing by Land ee ce EET Ra FER aed 157 8 22 Listing Land exeun ER EA RAE 175 9 Package Mechanical Specifications 4 194 9 1 Package Mechanical 194 9 2 Processor Component Keep Out 0 5 198 9 3 Package Loading Specifications eee ee eene memes 198 9 4 Package Handling 2 4 000 0 198 Intel Xeon Processor E5 2400 v2 Product Family 6 Datasheet Volume One 9 5 Package Insertion 5 5 198 9 6 Processor Mass 5 199 9 7 Processor Materials ode D da yay 199 9 8 Processor Markings isis cie arenes eere BEER inde 199 10 Boxed Processor Specifications 200 WWE 200 10 1 1 Available Boxed Thermal Solution
108. 15 14 6 5 0 Sign Thermal Margin Thermal Margin RESERVED Bit Integer Value Fractional Value 2 5 2 7 AMSR The 5 command provides read access to Model Specific Registers MSRs defined in the processor s Intel Architecture IA MSR definitions may be found in the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers Refer to Table 2 11 for the exact listing of processor registers accessible through this command 2 5 2 7 1 Command Format The RdlAMSR format is as follows Write Length 0x05 Read Length 0x09 qword Command 1 Intel Xeon Processor E5 2400 v2 Product Family 59 Datasheet Volume One 2 5 2 7 2 Description Returns the data maintained in the processor MSR space as specified by the Processor ID and MSR Address fields The Read Length dictates the desired data return size This command supports only qword responses All command responses are prepended with a completion code that contains additional pass fail status information Refer to Section 2 5 5 2 for details regarding completion codes Processor 1 D Enumeration The Processor 10 field that is used to address the MSR space refers to a specific logical processor within the CPU The Processor ID always refers to the same physical location in the processor silicon regardless of configuration as shown in the example in Figure 2 42 For example if certain logical processors are
109. 23 ODCMOS 1 0 Y36 DDR1_DQ 07 SSTL 1 0 42 vss GND Y37 VSS GND Intel Xeon Processor E5 2400 v2 Product Family 192 Datasheet Volume One Processor Land Listing Table 8 2 Land Number Sheet 37 of 37 Sed Land Name pend Direction Y38 DDR2 001071 SSTL 1 0 Y39 DDR2 001061 SSTL 1 0 YA VSS GND 40 vss GND 41 DDR3 001061 SSTL 1 0 Y5 DDR2_DQ 61 SSTL 1 0 Y6 DDR2 DQ 60 SSTL 1 0 Y7 VSS GND Y8 DDR1_DQ 53 SSTL 1 0 Y9 DDR1 DQ 52 SSTL 1 0 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 193 Package Mechanical Specifications n tel 9 Package Mechanical Specifications The processor is packaged in a Flip Chip Land Grid Array FCLGA12 package that interfaces with the baseboard via an 1356 2 socket The package consists of a processor mounted on a substrate land carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 9 1 shows a sketch of the processor package components and how they are assembled together Refer to the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG for complete details on the 1356 socket The package components shown in Figure 9 1 include the following 1 Integrated Heat Spreader IHS 2 Thermal Interface Material TI M 3 Processor core die 4 Package
110. 24 PWR VCC AP28 PWR VCC AV25 PWR VCC AR15 PWR VCC AV27 PWR VCC AR16 PWR VCC AV28 PWR VCC AR18 PWR VCC AW15 PWR VCC AR19 PWR VCC AW16 PWR ami VCC AW18 PWR Intel Xeon Processor E5 2400 v2 Product Family 168 Datasheet Volume One Processor Land Listing tel Table 8 1 Land Name Sheet 25 of 37 Table 8 1 Land Name Sheet 26 of 37 Land Name Land Buffer Type Direction Land Name Buffer Direction Number Number VCC AW19 PWR VCCD F14 PWR VCC AW21 PWR VCCD F19 PWR VCC AW22 PWR VCCD F24 PWR VCC AW24 PWR VCCD G12 PWR VCC AW25 PWR VCCD G17 PWR VCC AW27 PWR VCCD G22 PWR VCC AW28 PWR VCCD H15 PWR VCC AY15 PWR VCCD H20 PWR VCC AY16 PWR VCCD H25 PWR VCC AY18 PWR VCCD J13 PWR VCC AY19 PWR VCCD K11 PWR VCC 24 PWR VCCD K16 PWR VCC AY25 PWR VCCD K18 PWR VCC AY27 PWR VCCD K26 PWR VCC AY28 PWR VCCPLL AR36 PWR VCC BA15 PWR VCCPLL AV36 PWR VCC BA16 PWR VSA AD39 PWR VCC BA18 PWR VSA 5 PWR VCC BA19 PWR VSA AE36 PWR VCC BA24 PWR VSA AE37 PWR VCC BA25 PWR VSA 8 PWR VCC BA27 PWR VSA 41 PWR VCC BA28 PWR VSA 42 PWR VCC R11 PWR VSA 4 PWR VCC R33 PWR VSA AF33 PWR VCC T11 PWR VSA AF36 PWR VCC T33 PWR VSA AF37 PWR VCC U11
111. 3 Deep Sleep On Deep Sleep GO SO C6 Deep Power On Deep Power Down Down G1 S3 Power off Off except RTC Suspend to RAM G1 S4 Power off Off except RTC Suspend to Disk G2 55 Power off Off except RTC Soft Off G3 N A Power off Power off Hard off Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 87 intel 4 2 4 2 1 4 2 2 Processor Core Package Power Management While executing code Enhanced Intel SpeedStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P state When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C state In general lower power C states have longer entry and exit latencies Enhanced ntel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology Multiple frequency and voltage points for optimal performance and power efficiency These operating points are known as P states Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on temperature leakage power delivery loadline and dynamic capacitance f the target frequency is higher than the current frequency Vcc is ramped up to an optimized voltage This voltage is signaled by the SVID Bus to the voltage regulator Once the voltage is established the
112. 3 _DQS_DP 17 00 DDR 1 2 3 _DQS_DN 17 00 Data strobes Differential pair Data ECC Strobe Differential strobes latch data ECC for each DRAM Different numbers of strobes are used depending on whether the connected DRAMs are x4 x8 Driven with edges in center of data receive edges are aligned with data edges DDR 1 2 3 _ECC 7 0 Check bits An error correction code is driven along with data on these lines for DIMMs that support that capability DDR 1 2 3 MA 15 00 Memory Address Selects the Row address for Reads and writes and the column address for activates Also used to set values for DRAM configuration registers DDR 1 2 3 MA PAR Odd parity across Address and Command DDR 1 2 3j ODT 3 0 On Die Termination Enables DRAM on die termination during Data Write or Data Read transactions DDR 1 2 3 PAR ERR N Parity Error detected by Registered DIMM one for each channel DDR 1 2 3 RAS Row Address Strobe DDR 1 2 3 WE N Write Enable Datasheet Volume One 115 Signal Descriptions Table 6 2 6 2 Note Table 6 3 Table 6 4 intel Memory Channel Miscellaneous Signal Name Description DDR RESET C1 N DDR RESET C23 N System memory reset Reset signal from processor to DRAM devices on the DIMMs DDR RESET 1 is used for memory channel 1 while DDR RESET C23 is used for memory channels 2 and 3 DDR SCL C1 SMBus clock for th
113. 32_MC14_CTL2 0 0 0 0403 1 32 0 5 1 0x0 OxF 0 041 1A32_MC7_ADDR 0 0 0 0439 1A32_MC14_STATUS 0 0 0x0404 2 0x0 0xF 0x041F 1 2 MC7 MISC 0 0 0x043A 1432 14 ADDR 0 0 0 0281 2 1 CTL2 0 0 0 0420 2 MC8 0 0 0x043B 1A32_MC14_MISC 0x0 OxF 0x0405 2 1 STATUS 0 0 0x0288 2 MC8 CTL2 0x0 OxF 0x043C 2 15 0x0 0xF 0x0406 1A32_MC1_ADDR 0x0 0xF 0x0421 1A32_MC8_STATUS 0x0 0xF 0x028F 1A32_MC15_CTL2 0x0 0xF 0x0407 1A32_MC1_MISC 0x0 0xF 0x0422 1A32_MC8_ADDR 0x0 0xF 0x043D 2 15 5 5 0x0 OxF 0x0408 32 MC2 0 0 0 0423 1A32_MC8_MISC 0x0 0xF 0x043E 1A32_MC15_ADDR 0 0 0 0282 1 32 2 2 0x0 OxF 0x0424 2 9 0 0 0x043F 1A32_MC15_MISC 0 0 0 0409 2 MC2 STATUS 0 0289 2 9 CTL2 0 0 0 0440 2 16 0 0 0 040 32 2 ADDR 0 0 0 0425 1A32_MC9_STATUS 0 0 0 0290 2 16 CTL2 0 0 0x040B 1A32 MC2 MISC 0x0 OxF 0x0426 2 MC9 ADDR 0x0 OxF 0x0441 2 16 STATUS 0 0 0 040 2 MC3 0 0 0 0427 1A32_MC9_MISC 0 0 0 0442 1A32_MC16_ADDR 0 0 0 0283 2 CTL2 0x0 OxF 0x0428 2 10 0 0 0x0443 1A32_MC16_MISC 0 0 0x040D 2 MC3 STATUS 0 0 0 0x028A 2
114. 33 SSTL 1 0 DDR3 MA 11 A25 SSTL DDR3_DQS_DP 00 41 SSTL 1 0 DDR3 MA 12 B26 SSTL DDR3_DQS_DP 01 R42 SSTL 1 0 DDR3 MA 13 D14 SSTL DDR3_DQS_DP 02 141 SSTL 1 0 DDR3 MA 14 C26 SSTL DDR3_DQS_DP 03 D42 SSTL 1 0 DDR3 MA 15 A27 SSTL DDR3 DQS DP 04 B7 SSTL 1 0 DDR3_MA_PAR 18 SSTL DDR3_DQS_DP 05 Fl SSTL 1 0 0071101 015 SSTL 0 DDR3_DQS_DP 06 L2 SSTL DDR3_ODT 1 C12 SSTL DDR3_DQS_DP 07 U3 SSTL 1 0 DDR3_ODT 2 C14 SSTL DDR3_DQS_DP 08 A32 SSTL DDR3_ODT 3 C13 SSTL DDR3 005 DP 09 AB42 SSTL 1 0 DDR3_PAR_ERR_N A26 SSTL DDR3 DQS DP 10 T41 SSTL 1 0 DDR3_RAS_N A16 SSTL DDR3 DQS DP 11 K42 SSTL 1 0 DDR3_WE_N C16 SSTL DDR3_DQS_DP 12 E43 SSTL 1 0 DMI_RX_DN 0 34 PCIEX DDR3_DQS_DP 13 A8 SSTL 1 0 DMI_RX_DN 1 AH35 PCIEX DDR3_DQS_DP 14 E2 SSTL 1 0 DMI_RX_DN 2 AG34 PCIEX DDR3_DQS_DP 15 K3 SSTL 1 0 DMI_RX_DN 3 AF35 PCIEX DDR3_DQS_DP 16 T2 SSTL 1 0 DMI_RX_DP 0 33 PCIEX DDR3_DQS_DP 17 B34 SSTL 1 0 DMI_RX_DP 1 AH34 PCIEX DDR3 ECC 0 C34 SSTL 1 0 DMI_RX_DP 2 AG33 PCIEX DDR3_ECC 1 C33 SSTL 1 0 DMI_RX_DP 3 AF34 PCIEX DDR3_ECC 2 B30 SSTL 1 0 DMI TX DN O0 AM35 PCI EX DDR3_ECC 3 A30 SSTL 1 0 DMI_TX_DN 1 AL36 PCIEX DDR3_ECC 4 C35 SSTL 1 0 DMI_TX_DN 2 AK35 PCIEX DDR3_ECC 5 B35 SSTL 1 0 DMI_TX_DN 3 36 PCIEX DDR3_ECC 6 B31 SSTL 1 0 DMI TX DP 0 AM36 PCIEX DDR3_ECC 7 A31 SSTL 1 0 DMI_TX_DP 1 AL37 PCIEX DDR3 17 SSTL
115. 3_CTL 0x0 0xF 0x0179 1A32_MCG_CAP 0x0 0xF 0x0419 1A32_MC6_STATUS 0x0 0xF 0x028D 1A32_MC13_CTL2 0 0 0x017A 1A32_MCG_STATUS 0 0 0 041 1A32_MC6_ADDR 0 0 0 0435 1 2_ 1 _5 5 0 0 0 0178 1 2_ _ Intel Xeon Processor 5 2400 v2 Product Family 62 Datasheet Volume One intel Notes 1 2 8 9 10 11 12 The MCi_ADDR MCi_MISC registers for machine check banks 2 amp 4 are not implemented on the processors The MCi_CTL register for machine check bank 2 is also not implemented The PECI host must determine the total number of machine check banks and the validity of the MCi_ADDR and MCi_MISC register contents prior to issuing a read to the machine check bank similar to standard machine check architecture enumeration and accesses The information presented in Table 2 11 is applicable to the processor only No association between bank numbers and logical functions should be assumed for any other processor devices past present or future based on the information presented in Table 2 11 The processor banks 7 6 8 corresponding to QPI 1 iMC 0 are not available on this processor Reading any registers within these banks will return all 05 The processor machine check banks 4 through 19 reside in the processor uncore and hence will return the same value independent of the processor ID used to access these banks The 2 5 0
116. 4 Notes 1 Country of Origin 2 SPEED Format X XXGHz and no rounding Intel Xeon Processor E5 2400 v2 Product Family 199 Datasheet Volume One Boxed Processor Specifications tel 10 Boxed Processor Specifications 10 1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels The Intel Xeon processor E5 2400 v2 product family LGA1356 processors will be offered as Intel boxed processors however the thermal solutions will be sold separately Boxed processors will not include a thermal solution in the box Intel will offer boxed thermal solutions separately through the same distribution channels Please reference Section 10 1 1 Section 10 1 4 for a description of Boxed Processor thermal solutions 10 1 1 Available Boxed Thermal Solution Configurations Intel will offer three different Boxed Heat Sink solutions to support LGA1356 Boxed Processors Boxed Intel Thermal Solution STS100C Order Code BXSTS100C A Passive Active Combination Heat Sink Solution that is intended for Intel Xeon processor E5 2400 v2 product family processors with TDP up to 95W a pedestal or 2U chassis with appropriate ducting Boxed Intel Thermal Solution STS100A Order Code BXSTS100A An Active Heat Sink Solution that is intended for Intel Xeon processor E5 2400 v2 product family processors
117. 4 3 2 Self Refresh Rt ied EEn dte adeat d 96 4 3 2 1 Self Refresh Entry eiusd bee etm et retten es ted 97 4 3 2 2 Self Refresh De 97 4 3 2 3 arid PEE ShUtdOWLD it eterne Done ret eere phi ck 97 4 3 3 DRAM I O Power msn enne 97 4 4 DMI2 PCI Express Power Management 97 5 Thermal Management 5 98 5 1 Package Thermal 5 5 98 5 1 1 Thermal Specifications 98 5 1 2 TCASE DTS Based Thermal 100 5 1 3 Processor Operational Thermal 101 5 1 3 1 Minimum operating case 101 5 1 3 2 Maximum operating case temperature thermal profiles 101 5 1 3 3 Digital Thermal Sensor DTS thermal profiles 102 5 1 3 4 Processor Digital Thermal Sensor DTS Specifications 103 5 1 4 Embedded Server Thermal Profiles 104 5 1 4 1 Embedded operating case temperature thermal profiles 104 5 1 4 2 Embedded Digital Thermal
118. 4 or x8 DRAM device failure Independent channel mode supports x4 SDDC x8 SDDC requires lockstep mode Lockstep mode where channels 2 amp 3 are operated in lockstep mode Data scrambling with address to ease detection of write errors to an incorrect address Error reporting via Machine Check Architecture Read Retry during CRC error handling checks by iMC Channel mirroring within a socket See Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers for complete list of RAS features Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling CLTT Memory thermal monitoring support for DIMM temperature via two memory signals MEM_HOT_C 1 23 _N 1 2 2 Express The PCI Express port s are fully compliant to the Express Base Specification Revision 3 0 PCle 3 0 Support for PCI Express 3 0 8 0 GT s 2 0 5 0 GT s and 1 0 2 5 GT s Up to 24 lanes of PCI Express interconnect for general purpose PCI Express devices at PCle 3 0 speeds that are configurable for up to 6 x4 independent ports 4 lanes of PCI Express at PCle 2 0 speeds when not using DMI2 port Port 0 also can be downgraded to x2 or x1 Negotiating down to narrower widths is supported see Figure 1 2 x16 port Port 3 may negotiate down to x8 x4 x2 or x1 x8 port Port 1 may negotiate down to x4 x2 or x1 x4 port Port 0 may negotiate down to x2 or x1 When nego
119. 5 2 CONTAIN and 2 MCG CAP are located in the uncore and will return the same value independent of the processor ID used to access them The processor machine check banks 0 through 3 are core specific Since the processor ID is thread specific and not core specific machine check banks 0 through 3 will return the same value for a particular core independent of the thread referenced by the processor ID PECI accesses to the machine check banks may not be possible in the event of a core hang A warm reset of the processor may be required to read any sticky machine check banks Valid processor ID values may be obtained by using the enumeration methods described in Section 2 5 2 7 2 Reads to a machine check bank within a core or thread that is disabled will return all zeroes with a completion code of 0x90 For SKUs where Intel is disabled or absent reads to the corresponding machine check banks will return all zeros with a completion code of 0x40 Table entries that are shaded represent services that are reserved MC6 MC8 MC13 14 15 MC16 2 5 2 8 RdPCI Config The RdPCI Config command provides sideband read access to the PCI configuration space maintained in downstream devices external to the processor PECI originators may conduct a device function register enumeration sweep of this space by issuing reads in the same manner that the BIOS would A response of all 1 s may indicate that the device function regist
120. 5 VID 0 129 VID 0 144 VID 0 159 1 2 3 4 120 VID 0 135 VID 0 150 VID 0 165 1 2 3 4 125 VID 0 141 VID 0 156 VID 0 171 1 2 3 4 130 VID 0 148 VID 0 163 VID 0 178 1 2 3 4 135 VID 0 154 VID 0 169 VID 0 184 1 2 3 4 Notes 1 The loadline specification includes both static and transient limits 2 This table is intended to aid in reading discrete points on graph in Figure 7 3 3 The loadlines specify voltage limits at the die measured at the Vcc sense and Vss Vcc sense lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor Vcc sense and Vss Vcc sense lands Refer to the VR12 IMVP7 Pulse Width Modulation Specification for loadline guidelines and VR implementation details 4 The Icc ranges extend to IccMax of the target processor as follows as documented in Table 7 12 Intel Xeon Processor E5 2400 v2 Product Family 141 Datasheet Volume One Figure 7 3 Static and Transient Tolerance Loadlines Vcc Tolerance Relative to VID Volts 0 020 0 040 0 060 0 080 0 100 0 120 0 140 0 160 0 180 0 200 10 20 Icc Processor Core Current Amps 30 40 50 60 70 80 90 100 110 120 130 VccMax VccTyp VccMin Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 142 7 8 2 intel Die Voltage Validation Core voltage Vcc overshoot events at the proces
121. 66 Datasheet Volume One Processor Land Listing intel Table 8 1 Land Name Sheet 21 of 37 Table 8 1 Land Name Sheet 22 of 37 Land Name Land Buffer Type Direction Land Name Buffer Type Direction Number Number RSVD AG11 SVIDALERT_N AL7 CMOS RSVD AH10 SVIDCLK AM7 ODCMOS RSVD AF11 SVIDDATA AK7 ODCMOS 1 0 RSVD 9 TCK AR12 CMOS RSVD AH9 TDI AM12 CMOS RSVD AJ8 TDO AK12 ODCMOS RSVD 8 TESTO H4 RSVD AH8 TEST1 RSVD AG8 TEST2 N33 RSVD AK8 TEST3 G40 RSVD AY41 TEST4 AK32 RSVD AV38 7 ODCMOS RSVD AR31 TMS AP12 CMOS RSVD AP31 TRST_N AL12 CMOS RSVD BA38 VCC 11 PWR RSVD AP32 VCC AA33 PWR RSVD AN32 VCC 11 PWR RSVD AY6 VCC AB33 PWR RSVD AW13 VCC 11 PWR RSVD AT14 VCC AD11 PWR RSVD AU14 VCC 11 PWR RSVD AM14 VCC AK15 PWR RSVD AN14 VCC AK16 PWR RSVD BA6 VCC AK18 PWR RSVD AU3 VCC AK19 PWR RSVD AU4 VCC AK21 PWR RSVD AL30 VCC AK22 PWR RSVD M20 VCC AK24 PWR RSVD M19 VCC AK25 PWR RSVD L16 VCC AK27 PWR RSVD M12 VCC AK28 PWR RSVD M21 VCC AL15 PWR RSVD AF7 VCC AL16 PWR RSVD AE7 VCC AL18 PWR RSVD B2 VCC AL19 PWR SAFE_MODE_BOOT AU40 CMOS VCC AL21 PWR SKTOCC_N AM31 VCC AL22 PWR SOCKE
122. ATUS Read DIMMs consumed by CSR DRAM_ENERGY_STATUS Channel all the DIMMs E 04 Index malene DRAM ENERGY STATUS CHI OxOOFF AII channels or all 0 311 Channels the DIMMs within a specified channel DRAM Power Typical and N A Read DRAM MSR 61Ch Info Read minimum DRAM power settings DRAM_POWER_INFO 35 0x0000 power settings info to be used CSR DRAM POWER INFO by power B limiting entity DRAM Power Maximum DRAM N A Read DRAM MSR 61Ch Info Read power settings amp power settings DRAM_POWER_INFO 36 0x0000 maximum time info to be used CSR DRAM POWER INFO window by power limiting entity Intel Xeon Processor E5 2400 v2 Product Family 38 Datasheet Volume One intel Table 2 6 RdPkgConfig 6 WrPkgConfig DRAM Thermal and Power Optimization Services Summary Sheet 2 of 2 Parameter RdPkgConfig WrPkgConfig Alternate Index Value Data Data I nband Service Value d d d d d Description MSR or CSR i wor wor wor decimal Access DRAM Power N A DRAM Plane Write DRAM MSR 618h Limit Data 34 0x0000 Power Limit Data Power Limit DRAM POWER LIMIT Write Read x Data CSR DRAM_PLANE_POWER_LIMIT DRAM Power DRAM Plane Power N A Read DRAM MSR 618h Limit Data 34 Limit Data Power Limit DRAM_POWER_LIMIT Write Read 0x0000 Data CSR DRAM_PLANE_POWER_LIMIT DRAM Power Accumulated DRAM N A Read sum of all CSR Limit throttle time time durations DRAM_RAPL_PERF_STATUS Performance 38 0x0000 for which each
123. A_RX_DN 2 PCIEX3 AV3 vss GND AU35 vss GND AV30 PWR Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 182 Processor Land Listing tel Table 8 2 Land Number Sheet 17 of 37 Table 8 2 Land Number Sheet 18 of 37 Med ole Land Name 7 Direction mentee Land Name rci Direction AV31 PE3B DN 5 PCIEX3 AW27 VCC PWR AV32 VTTD PWR AW28 VCC PWR AV33 PE3C_RX_DP 11 PCI EX3 AW29 VSS GND AV34 VTTA PWR AW3 QPI1_DTX_DP 17 Intel QPI AV35 PE3C_RX_DP 9 PCIEX3 AW30 PE3D_RX_DP 14 PCIEX3 AV36 VCCPLL PWR AW31 vss GND AV37 PE1B_RX_DP 7 PCIEX3 AW32 PE3D_RX_DP 12 PCIEX3 AV38 RSVD AW33 PE3C_RX_DN 11 PCIEX3 AV39 PE1A_RX_DN 1 PCIEX3 AW34 PE3C_RX_DP 10 PCIEX3 AV4 QPI1 DTX DN 18 Intel AW35 PE3C_RX_DN 9 PCIEX3 AV40 VSA PWR AW36 PE3C_RX_DP 8 PCIEX3 AV41 PE1A_RX_DP 0 PCIEX3 AW37 PE1B RX DNI7 PCIEX3 AV42 RSVD AW38 PE1B_RX_DP 6 PCIEX3 AV43 VSA PWR AW39 vss GND AV5 QPI1 DTX DP 18 Intel AW4 VSS GND AV6 VSS GND AW40 PE1B_RX_DP 4 PCI EX3 7 QPI1 DTX DP 14 Intel AW41 PE1A_RX_DN 0 PCIEX3 AV8 vss GND AW42 vss GND AV9 QPI1 DTX DP 10 Intel AW5 QPI1 DTX DN 16 Intel AW1 vss GND AW6 QPI1 DTX DP 16 Intel AW10 QPI1 DTX 0 1071 Intel AW7
124. A_RX_DP 1 AR35 PCIEX3 AM32 PCIEX3 1 0 PE3A_RX_DP 2 AT34 PCIEX3 PE1A_RX_DN 0 AW41 PCIEX3 PCIEX3 PE1A_RX_DN 1 AV39 PCIEX3 TX 0 AH38 PCI EX3 PE1A_RX_DN 2 AU38 PCI EX3 PE3A_TX_DN 1 39 PCIEX3 PE1A_RX_DN 3 AT37 PE3A_TX_DN 2 AK38 PCIEX3 PE1A_RX_DP 0 AV41 PE3A_TX_DN 3 AL39 PCIEX3 PE1A_RX_DP 1 AU39 PE3A_TX_DP 0 AH39 PCIEX3 PE1A_RX_DP 2 AT38 PE3A_TX_DP 1 AJ 40 PCIEX3 PE1A_RX_DP 3 AR37 PE3A_TX_DP 2 AK39 PCIEX3 PE1A_TX_DN O AE40 PE3A_TX_DP 3 AL40 PCIEX3 PE1A_TX_DN 1 AG37 PCI EX3 DN 4 AU32 PCIEX3 PE1A_TX_DN 2 AF38 PE3B RX DN 5 AV31 PCIEX3 PE1A_TX_DN 3 AG39 DN 6 AU30 PCIEX3 PE1A TX DP O AE39 PCI EX3 PE3B_RX_DNI 7 AV29 PCIEX3 PE1A_TX_DP 1 AG36 PCIEX3 PE3B_RX_DP 4 AT32 PCIEX3 PE1A_TX_DP 2 AF39 DP 5 AU31 PCIEX3 PE1A_TX_DP 3 AG40 PE3B_RX_DP 6 PCIEX3 PE1B RX DN 4 AY40 71 AU29 PCIEX3 PE1B RX DN 5 BA39 PE3B_TX_DN 4 AM38 PCIEX3 PE1B RX DN 6 AY38 PCI EX3 PE3B_TX_DN 5 AN39 PCIEX3 PE1B RX DNI 7 AW37 PCI EX3 PE3B_TX_DN 6 AP38 PCIEX3 PE1B_RX_DP 4 AW40 PE3B_TX_DN 7 AR39 PCIEX3 PE1B_RX_DP 5 AY39
125. D AT19 VCC PWR AR24 VCC PWR AT2 QPI1_DRX_DP 01 Intel QPI 25 VCC PWR AT20 VSS GND AR26 VSS GND AT21 VCC PWR AR27 VCC PWR AT22 VCC PWR AR28 VCC PWR AT23 VSS GND AR29 VSS GND 24 VCC PWR AR3 QPI1 DP 03 Intel 25 VCC PWR AR30 PEHPSCL ODCMOS 1 0 AT26 vss GND AR31 RSVD AT27 VCC PWR AR32 VSS GND AT28 VCC PWR AR33 PE3A_RX_DP 3 PCI EX3 29 VSS GND AR34 VSS GND AT3 PMSYNC CMOS AR35 PE3A_RX_DP 1 PCIEX3 6 PCIEX3 AR36 VCCPLL PWR AT31 VSS GND AR37 PE1A_RX_DP 3 PCIEX3 2 PE3B_RX_DP 4 PCIEX3 AR38 VSS GND AT33 PE3A_RX_DN 3 PCI EX3 AR39 PE3B_TX_DN 7 PCIEX3 4 DPI 2 PCIEX3 4 vss GND AT35 PE3A_RX_DN 1 PCIEX3 AR40 PE3B_TX_DP 7 PCIEX3 AT36 PE3A_RX_DP 0 PCIEX3 41 VSA PWR AT37 PE1A_RX_DN 3 PCIEX3 42 PE3D_TX_DN 13 PCIEX3 8 PE1A_RX_DP 2 PCIEX3 AR43 PE3D_TX_DP 13 PCIEX3 AT39 RSVD ARS 1 2 Inte QPl DRXDNIO 1 Intel Xeon Processor 5 2400 v2 Product Family 181 Datasheet Volume One Processor Land Listing intel Table 8 2 Land Number Sheet 15 of 37 Table 8 2 Land Number Sheet 16 of 37 Mod utm Land Name 7 Direction Ms Land Name jc Direction AT40 VSA PWR AU36 PE3A RX DNIO PCIEX3 41 141 PCIEX3 AU37 VS
126. DC 149 7 8 3 2 DMI2 PCI Express DC Specifications 149 7 8 3 3 Intel QuickPath Interconnect DC Specifications 149 7 8 3 4 Reset and Miscellaneous Signal DC Specifications 149 7 8 3 5 PCI Express AC 5 2 7 0 2012 149 7 8 3 6 DMI2 PCI Express AC Specifications 150 7 8 3 7 Intel QuickPath Interconnect AC Specifications 150 7 8 3 8 SMBus Signal AC 150 7 8 3 9 Reset and Miscellaneous Signal AC Specifications 150 T9 Signal Qu allty ICM 152 7 9 1 DDR3 Signal Quality 153 7 9 2 Signal Quality 153 7 9 3 Intel QuickPath Interconnect Signal Quality Specifications 153 7 9 4 Input Reference Clock Signal Quality 153 7 9 5 Overshoot Undershoot 153 7 9 5 1 Overshoot Undershoot Magnitude 154 7 9 5 2 Overshoot Undershoot Pulse Duration 154 74953
127. DDR1 DQS DN 08 H29 SSTL 1 0 DDR1 DQ 35 L5 SSTL 1 0 DDR1_DQS_DN 09 AB35 SSTL 1 0 DDR1 DQ 36 K10 SSTL 1 0 DDR1_DQS_DN 10 R36 SSTL 1 0 DDR1 DQ 37 L10 SSTL 1 0 DDR1_DQS_DN 11 K34 SSTL 1 0 DDR1 DQ 38 K6 SSTL 1 0 DDR1_DQS_DN 12 K30 SSTL 1 0 DDR1_DQ 39 L6 SSTL 1 0 DDR1_DQS_DN 13 L8 SSTL 1 0 DDR1 DQ 40 N8 SSTL 1 0 DDR1_DQS_DN 14 R8 SSTL 1 0 DDR1 DQ 41 P8 SSTL DDR1 005 0 151 SSTL 1 0 DDR1 DQ 42 v9 SSTL 1 0 DDR1_DQS_DN 16 AC3 SSTL 1 0 DDR1 DQ 43 V8 SSTL 1 0 DDR1 DQS DN 17 G30 SSTL 1 0 DDR1 DQ 44 N9 SSTL 1 0 DDR1 005 DP 00 AA36 SSTL DDR1 DQ 45 P9 SSTL DDR1_DQS_DP 01 P36 SSTL 1 0 DDR1 DQ 46 U9 SSTL 1 0 DDR1_DQS_DP 02 H34 SSTL 1 0 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 158 Processor Land Listing tel Table 8 1 Land Name Sheet 5 of 37 Table 8 1 Land Name Sheet 6 of 37 Land Name Buffer Direction Land Name un Buffer Type Direction DDR1 DQS DP 03 K29 SSTL 1 0 DDR1 MA 15 K24 SSTL DDR1_DQS_DP 04 L7 SSTL 1 0 DDR1_MA_PAR 19 SSTL DDR1_DQS_DP 05 T8 SSTL 1 0 DDR1_ODT 0 G15 SSTL DDR1_DQS_DP 06 AC8 SSTL 1 0 DDR1_ODT 1 H13 SSTL DDR1_DQS_DP 07
128. DDR2_CS_N 4 E15 SSTL 0 DDR1_MA 10 M18 SSTL 0 DDR2_CS_N 5 E14 SSTL 0 DDR1_MA 11 M24 SSTL 0 DDR2_CS_N 6 G11 SSTL 0 DDR1 MA 12 120 SSTL DDR2_CS_N 7 H11 SSTL DDR1 MA 13 L13 SSTL DDR2 001001 AC39 SSTL 1 0 DDR1 MA 14 122 SSTL DDR2 DQ 01 AC38 SSTL 1 0 Intel Xeon Processor E5 2400 v2 Product Family 159 Datasheet Volume One intel Processor Land Listing Table 8 1 Land Name Sheet 7 of 37 Table 8 1 Land Name Sheet 8 of 37 Land Name 6 Buffer Direction Land Name un Buffer Type Direction DDR2 001021 W39 SSTL 1 0 DDR2 DQ 40 G9 SSTL 1 0 DDR2_DQ 03 W38 SSTL 1 0 DDR2_DQ 41 H9 SSTL 1 0 DDR2 001041 AD37 SSTL 1 0 DDR2_DQ 42 G5 SSTL 1 0 DDR2 001051 AC37 SSTL DDR2 DQ 43 H5 SSTL 1 0 DDR2 001061 Y39 SSTL 1 0 DDR2 DQ 44 G10 SSTL 1 0 DDR2 001071 Y38 SSTL 1 0 DDR2 DQ 45 H10 SSTL 1 0 DDR2_DQ 08 T39 SSTL 1 0 DDR2 DQ 46 G6 SSTL 1 0 DDR2 001091 T38 SSTL 1 0 DDR2_DQ 47 H6 SSTL 1 0 DDR2 DQ 10 M38 SSTL 1 0 DDR2_DQ 48 P6 SSTL 1 0 DDR2 DQ 11 M39 SSTL 1 0 DDR2_DQ 49 P5 SSTL 1 0 DDR2_DQ 12 U39 SSTL 1 0 DDR2 DQ 50 V6 SSTL 1 0 DDR2_DQ 13 U38 SSTL 1 0 DDR2 DQ 51 V5 SSTL 1 0 DDR2 DQ 14 N39 SSTL 1 0 DDR2 DQ 52 N6 SSTL 1 0 DDR2 DQ 15 N38 SSTL 1 0 DDR2 DQ 53 N5
129. DMI_TX_DP 2 AK36 PCIEX Intel Xeon Processor 5 2400 v2 Product Family 163 Datasheet Volume One Processor Land Listing tel Table 8 1 Land Name Sheet 15 of 37 Table 8 1 Land Name Sheet 16 of 37 Land Name Land Buffer Type Direction Land Name Buffer Type Direction Number Number DMI_TX_DP 3 AJ 37 PCIEX PE1B_RX_DP 6 AW38 PCIEX3 TXT PLTEN AN8 CMOS PE1B_RX_DP 7 AV37 PCIEX3 DRAM PWR OK C1 Y10 CMOS 1 5V PE1B_TX_DN 4 AF41 PCIEX3 PWR OK C2 AD40 CMOS_1 5V PE1B_TX_DN 5 AG42 PCIEX3 1 TX DN 6 41 PCIEX3 _ ODCMOS 1 0 PE1B_TX_DN 7 AJ 42 PCIEX3 ERROR_N O AL34 ODCMOS PE1B_TX_DP 4 AF42 PCIEX3 ERROR_N 1 AM34 ODCMOS PE1B_TX_DP 5 AG43 PCIEX3 ERROR_N 2 AL33 ODCMOS PE1B_TX_DP 6 AH42 PCIEX3 5 PE1B_TX_DP 7 AJ 43 PCIEX3 IVT ID N V34 PE3A_RX_DN 0 AU36 PCIEX3 _ 4 5 _ PE3A_RX_DN 1 AT35 PCI EX3 _ _ 1_ 10 ODCMOS 1 0 PE3A_RX_DN 2 AU34 PCIEX3 23 N41 ODCMOS 1 0 0 31 PCIEX3 RBIAS AL31 1 0 PE3A_RX_DP 0 AT36 PCIEX3 PE RBIAS SENSE AL32 PCI EX3 PE3
130. Data Link Data Link Physical Physical Logical Sub Block Logical Sub Block Electrical Sub Block Electrical Sub Block PCI Express uses packets to communicate information between components Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component As the transmitted packets flow through the other layers they are extended with additional information necessary to handle packets at those layers At the receiving side the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally for Transaction Layer Packets to the form that can be processed by the Transaction Layer of the receiving device Intel Xeon Processor E5 2400 v2 Product Family 25 Datasheet Volume One Interfaces Figure 2 2 2 2 1 1 2 2 1 2 2 2 1 3 intel Packet Flow through the Layers umber T ayer ransaction L Data Link Layer Physical Layer Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is the assembly and disassembly of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs Data Link Layer The middle layer in the Express stack
131. Duty Cycle Differential Differential BCLK Figure 7 8 BCLK 0 1 Differential Clock Measurement Points for Edge Rate 150 mV BCLK Figure 7 9 BCLK 0 1 Differential Clock Measurement Point for Ringback Vng Ditterential 5 Va H50 ex 00 ______ NM ______ ______ jf CE ee 100 22 222 _ REFCLK stase VB Differential Intel Xeon Processor E5 2400 v2 Product Family 151 Datasheet Volume One intel Figure 7 10 BCLK 0 1 Single Ended Clock Measurement Points for Absolute Cross Point and Swing BCLK DP 7 9 Signal Quality Data transfer requires the clean reception of data signals and clock signals Ringing below receiver thresholds non monotonic signal edges and excessive voltage swings will adversely affect system timings Ringback and signal non monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines Excessive signal swings overshoot and undershoot are detrimental to silicon gate oxide integrity and can cause device failure if absolute voltage limits are exceeded Overshoot and undershoot can also cause timing degradation due to the build up of inter symbol interference ISI effects For these reasons it is crucial that the designer work towards a solution that prov
132. ECI Specification revision 3 0 interface operates at a nominal voltage set by The set of DC electrical specifications shown in Table 7 16 is used with devices normally operating from a Vrrp interface supply Input Device Hysteresis The PECI client and host input buffers must use a Schmitt triggered input design for improved noise immunity Please refer to Figure 7 1 and Table 7 16 Input Device Hysteresis as Maximum Ve Mnimum Vg gt Valid Inout Signal Range Maximum Mnimum Ground System Reference Clocks BCLK 0 1 DP BCLK 0 1 DN The processor core processor uncore Intel QuickPath Interconnect link PCI Express and DDR3 memory interface frequencies are generated from BCLK 0 1 DP and BCLK 0 1 DN signals There is no direct link between core frequency and Intel QuickPath Interconnect link frequency 9 no core frequency to Intel QuickPath Interconnect multiplier The processor maximum core frequency Intel QuickPath Interconnect link frequency and DDR memory frequency are set during manufacturing It is possible to override the processor core frequency setting using software see the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers This permits operation at lower core frequencies than the factory set maximum core frequency Intel Xeon Processor E5 2400 v2 Product Family 125 Datas
133. EMPERATURE TARGET temperature and processor TconTROL Package 20 0x0000 Thermal Status N A Read the thermal MSR 1B1h Thermal Status Register status register and 1A32_PACKAGE_THERM_STATUS Read Clear optionally clear any log bits The register includes status and log bits for TCC activation PROCHOT_N assertion and Critical Temperature Thermal 21 0x0000 Thermal N A Reads the Thermal N A Averaging Averaging Averaging Constant Constant Write Constant Read Thermal 21 0x0000 N A Thermal Writes the Thermal N A Averaging Averaging Averaging Constant Constant Write Constant Read Intel Xeon Processor E5 2400 v2 Product Family 46 Datasheet Volume One intel Table 2 8 RdPkgConfig 6 WrPkgConfig CPU Thermal and Power Optimization Services Summary Sheet 3 of 4 T Parameter RdPkgConfig wrPkgConfig Alternate T Value Data 0 Inband STIRE aue word dword Data Description MSR or CSR decimal dword Access Thermally 32 0x0000 Thermally N A Read the time for N A Constrained Constrained which the processor Time Read Time has been operating in a lowered power state due to internal TCC activation Current Limit 17 0x0000 Current Limit N A Reads the current CSR Read per power plane limit on the VCC PRIMARY_PLANE_CURRENT_ power plane CONFIG_CONTROL Accumulated 03 0x0000 Accumulated N A Returns the value of MSR 639h PPO_ENERGY_ Energy Status
134. EX3 QPI1_DRX_DN 02 AR5 Intel QPI PE3C_TX_DP 10 AM42 PCIEX3 QPI1_DRX_DN 03 AR2 Intel QPI PE3C_TX_DP 11 AN43 PCIEX3 QPI1_DRX_DN 04 AP4 Intel QPI PE3C_TX_DP 8 AK42 PCIEX3 QPI1 DRX 051 AP1 Intel PE3C_TX_DP 9 AL43 PCIEX3 QPI1_DRX_DN 06 AP8 Intel QPI PE3D_RX_DN 12 AY32 PCIEX3 QPI1_DRX_DN 07 AN2 Intel QPI PE3D_RX_DN 13 BA31 PCIEX3 1 081 AN6 Intel QPI DN 14 AY30 PCIEX3 QPI1 DRX DN O09 AM1 Intel QPI PE3D_RX_DN 15 BA29 PCIEX3 QPI1_DRX_DN 10 AM5 Intel QPI DP 12 AW32 PCIEX3 1 DN 11 12 Intel DP 13 1 PCI EX3 1 DN 12 5 Intel DP 14 AW30 PCIEX3 QPI1_DRX_DN 13 AK1 Intel DP 15 29 PCIEX3 QPI1_DRX_DN 14 6 Intel PE3D_TX_DN 12 AP41 PCIEX3 1 15 2 Intel PE3D_TX_DN 13 AR42 PCIEX3 QPI1_DRX_DN 16 AH5 Intel QPI PE3D_TX_DN 14 AT41 PCIEX3 1 0 171 Intel PE3D_TX_DN 15 AU42 PCIEX3 0 QPI1_DRX_DN 18 AG6 Intel QPI PE3D_TX_DP 12 AP42 PCIEX3 QPI1_DRX_DN 19 AG2 Intel QPI PE3D_TX_DP 13 AR43 PCIEX3 1 DRX DP O00 AT5 Intel PE3D_TX_DP 14 AT42 PCIEX3 QPI1_DRX_DP 01 AT2 Intel QPI PE3D_TX_DP 15 AU43 PCIEX3 0 QPI1_DRX_DP 02 AR6 Intel QPI AN37 1 0 1 DRX DP O03 AR3 Intel OPI PEHPSC
135. Express Memory transactions received from PCI Express that go above the top of physical address space when Intel VT d is enabled the check would be against the translated HPA Host Physical Address address are reported as errors by the processor Outbound access to PCI Express will always have address bits 63 to 46 cleared Re issues Configuration cycles that have been previously completed with the Configuration Retry status Power Management Event PME functions Message Signaled Interrupt MSI and MSI X messages Degraded Mode support and Lane Reversal support Static lane numbering reversal and polarity inversion support Figure 1 2 Express Lane Partitioning and Direct Media I nterface Gen 2 DMI2 Port 1 Port 3 Port 0 10U2 10U1 Oke PCle PCle Transaction Transaction Transaction Physical 1 1 4 4 4 4 4 ae 5 sts 2 Port 3c X16 Port 3a 1 2 3 Direct Media nterface Gen 2 DMI 2 Chip to chip interface to the Intel C600 Chipset Intel Xeon Processor E5 2400 v2 Product Family 17 Datasheet Volume One Overview intel Supports only x4 link width when in DMI2 mode Operates at PCI Express 1 0 or 2 0 speeds Transparent to software Processor and peer to peer writes and reads with 64 bit address support APIC and Message Signaled Interrupt MSI support Will send Intel defined End of Interrupt broadcast message when initiate
136. I originator determine the exact suite of available PECI client services by issuing each of the PECI commands The processor will issue timeout responses for those services that may not be available f the PECI client continues to return the 0x81 completion code in response to multiple retries of the RdPkgConfig command no PECI services with the exception of the Ping GetTemp and GetDIB will be guaranteed The RdIAMSR command may be serviced during a CAT ERR assertion though it cannot be guaranteed 2 5 3 9 Originator Retry and Timeout Policy The PECI originator may need to retry a command if the processor PECI client responds with a response timeout completion code or a bad Read FCS In each instance the processor PECI client may have started the operation but not completed it yet When the retry bit is set the PECI client will ignore a new request if it exactly matches a previous valid request Intel Xeon Processor E5 2400 v2 Product Family 72 Datasheet Volume One intel The processor PECI client will not clear the semaphore that was acquired to service the request until the originator sends the retry request in a timely fashion to successfully retrieve the response data In the absence of any automatic timeouts this could tie up shared resources and result in artificial bandwidth conflicts 2 5 3 10 Enumerating PECI Client Capabilities The host originator should be designed to suppo
137. Indicator 57 2 39 ACPI Notify ERR M ELEME 58 2 40 Caching Agent TOR Read teeter 59 2 41 DTS Thermal Margin 59 2 42 Processor ID Construction 0 60 2 43 ete tix REL E DIR eerie 61 2 44 PCI Configuration Address eene Ra REX dayne eer 63 2 45 RaPClConfig 3 rmm RI MR Qr ened 64 2 46 PCI Configuration Address for local ACCESSES mmn 65 2 47 RdPGliConfigLocal rccte ext xr e e OUR ER ER PER RE Y IRA RAE RC CHER ER KERN ER TER CE x 65 2 48 WrPCIConfigLocal 0 2 2 1 2 444 6 nnne nnns 67 2 49 The Processor Power up Timeline 4 6 69 2 50 Temperature Sensor Data nennen ne nnn 75 4 1 Idle Power Management Breakdown of the Processor 89 4 2 Thread and Core C State Entry and 89 4 3 Package C State Entry and 93 5 1 Case Temperature Thermal
138. Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One January 2014 Reference Number 329819 002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS LICENSE EXPRESS IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJ URY OR DEATH MAY OCCUR A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT
139. Intel SpeedStep Technology transitions signal Please refer to the Intel Xeon Processor E5 v2 Intel Xeon Processor E5 2400 v2 Product Family 136 Datasheet Volume One m 9 Electrical Specifications tel Product Family Datasheet Volume Two Registers for details on the FLEX_RATIO MSR and setting the processor core frequency Not all operating systems can support dual processors with mixed frequencies Mixing processors of different steppings but the same model as per CPUID instruction is supported provided there is no more than one stepping delta between the processors for example S and S 1 S and S 1 is defined as mixing of two CPU steppings in the same platform where one CPU is S stepping CPUID EAX 01h EAX 3 0 and the other is 5 1 CPUID EAX 01h EAX 3 0 1 The stepping ID is found in EAX 3 0 after executing the CPUID instruction with Function O1h Details regarding the CPUID instruction are provided in the AP 485 Intel Processor Identification and the CPUID Instruction application note also refer to the Intel Xeon Processor E5 v2 Product Family NDA Sightings Report 7 6 Flexible Motherboard Guidelines FMB The Flexible Motherboard FMB guidelines are estimates of the maximum values the processor will have over certain time periods The values are only estimates and actual specifications for future processors may differ Processors may or may not ha
140. L AR30 ODCMOS 1 0 QPI1_DRX_DP 04 AP5 Intel QPI Intel Xeon Processor 5 2400 v2 Product Family Datasheet Volume One 165 Processor Land Listing intel Table 8 1 Land Name Sheet 19 of 37 Table 8 1 Land Name Sheet 20 of 37 Land Name Land Buffer Type Direction Land Name Buffer Type Direction Number Number QPI1 DRX DP 05 AP2 Intel QPI1_DTX_DP 03 AY12 Intel QPI QPI1 DRX DP 06 AP7 Intel QPI1 DTX DP 04 AU12 Intel OPI QPI1 DP O07 AN3 Intel QPI1_DTX_DP 05 11 Intel QPI1 DP O08 AN5 Intel QPI1_DTX_DP 06 AV11 Intel 1 DRX DP 09 AM2 Intel QPI1 DTX DP O07 AY10 Intel 1 DP 10 AMA Intel QPI1 DTX DP O08 AU10 Intel OPI QPI1 DRX DP 11 AL3 Intel QPI1_DTX_DP 09 AY8 Intel QPI QPI1 DRX DP 12 Intel 1 DTX DP 10 AV9 Intel 1 DRX DP 13 AK2 Intel QPI QPI1_DTX_DP 11 BA7 Intel QPI QPI1 DP 14 AJ5 Intel QPI1 DTX DP 12 AU8 Intel QPI 1 DRX DP 15 Intel 1 DTX DP 13 BA5 Intel 1
141. LIABILITY PERSONAL I NJ OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNI NG OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The Intel Xeon processor E5 2400 v2 product family Intel C600 Chipset and the Intel Xeon processor E5 2400 v2 product family based platform described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com US 01 Hyper Threading Technology requires a computer system with a pr
142. Land Buter Direction Number Type Number Type 91 DDR3_DQ 62 SSTL V43 VSS GND 010 VSS GND v5 DDR2_DQ 51 SSTL 1 0 911 VCC PWR V6 DDR2 DQ 50 SSTL 1 0 U2 vss GND 7 vss GND U3 DDR3_DQS_DP 07 SSTL 1 0 V8 DDR1 DQ 43 SSTL 1 0 U33 VCC PWR V9 DDR1 DQ 42 SSTL 1 0 034 VSS GND VSS GND 935 DDR1 001121 SSTL 1 0 10 1 ODCMOS 1 0 U36 DDR1_DQ 13 SSTL 1 0 W11 VCC PWR 937 VSS GND 2 vss GND U38 DDR2_DQ 13 SSTL 1 0 w3 VSS GND 039 DDR2_DQ 12 SSTL 1 0 W33 VCC PWR U4 VSS GND 34 vss GND 40 VSS GND w35 DDR1_DQ 02 SSTL 1 0 U41 DDR3_DQ 12 SSTL 1 0 W36 DDR1_DQ 03 SSTL 1 0 042 DDR3_DQ 08 SSTL 1 0 W37 VSS GND U43 DDR3_DQ 13 SSTL 1 0 W38 DDR2_DQ 03 SSTL 1 0 U5 DDR2_DQ 55 SSTL 1 0 W39 DDR2_DQ 02 SSTL 1 0 U6 DDR2_DQ 54 SSTL 1 0 w4 DDR VREFDQTX C1 DC U7 vss GND W40 VSS GND U8 DDR1_DQ 47 SSTL 1 0 W41 DDR3_DQ 07 SSTL 1 0 U9 DDR1 001461 SSTL 1 0 W42 DDR3_DQ 02 SSTL 1 0 1 DDR3_DQ 58 SSTL 1 0 W43 DDR3_DQ 03 SSTL 1 0 V10 VSS GND w5 VSS GND V11 VCC PWR W6 VSS GND 2 DDR3_DQ 63 SSTL 1 0 W7 DDR_SCL_C1 ODCMOS 1 0 V3 DDR3 DQI 59 SSTL 1 0 w8 DDR_SDA_C1 ODCMOS 1 0 VCC PWR w9 VSS GND V34 IVT_ID_N 1 DDR1_DQ 56 SSTL 1 0 V35 vss GND Y10 DRAM PWR OK C1 CMOS 1 5 V 6 VSS GND Y11 VCC PWR v37 DDR_VREFDQTX_C23 DC Y2 DDR1_DQ 61 SSTL 1 0 38 vss GND DDR1_DQ 60 SSTL 1 0 v39 VSS GND Y33 VCC PWR vss GND Y34 vss GND 40 DDR_SCL_C23 ODCMOS 1 0 Y35 DDR1 DQ 06 SSTL 1 0 41 DDR_SDA_C
143. O Package 1 additional power reduction actions are taken in the package 1 state However if the C1E substate is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage Autonomous power reduction actions which are based on idle timers can trigger depending on the activity in the system The package enters the 1 low power state when At least one core is in the C1 state The other cores are in a C1 or lower power state The package enters the state when All cores have directly requested via MWAIT C1 with sub state hint All cores are in a power state lower that 1 but the package low power state is limited to C1 C1E via the CST CONFIG CONTROL MSR All cores have requested C1 using HLT or MWAIT C1 and auto promotion is enabled in POWER CTL No notification to the system occurs upon entry to 1 Intel Xeon Processor E5 2400 v2 Product Family 93 Datasheet Volume One intel 4 2 5 3 Package C2 State Package C2 state is an intermediate state which represents the point at which the system level coordination is in progress The package cannot reach this state unless all cores are in at least C3 The package will remain in C2 when itis awaiting for a coordinated response the coordinated exit latency requirements are too stringent for the package to take any po
144. OV Intel Xeon processor E5 2400 v2 product family does not retain any end user data when powered down and or the processor is physically removed from the socket State of Data The data contained within this document is subject to change It is the most accurate information available by the publication date of this document The information in this revision of the document is based on final silicon characterization Intel Xeon Processor E5 2400 v2 Product Family 23 Datasheet Volume One intel 2 nterfaces This chapter describes the interfaces supported by the processor For functional descriptions and additional details of these interfaces see Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers 2 1 System Memory Interface 2 1 1 System Memory Technology Support The Integrated Memory Controller IMC supports DDR3 protocols with threeindependent 64 bit memory channels with 8 bits of ECC for each channel total of 72 bits and supports 2 DIMMs per channel The type of memory supported by the processor is dependent on the target platform Intel Xeon processor E5 2400 v2 product family based platforms support ECC registered DIMMs with a maximum of two DIMMs per channel allowing up to eight device ranks per channel ECC and non ECC unbuffered DIMMs with a maximum of two DIMMs per channel thus allowing up to four device ranks per channel Support for mixed non ECC
145. One intel The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following f a core break event is received the target core is activated and the break event message is forwarded to the target core f the break event is not masked the target core enters the core CO state and the processor enters package CO f the break event is masked the processor attempts to re enter its previous package state f the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package remains in the higher power C state The package C states fall into two categories independent and coordinated 1 are independent while C2 C3 C6 are coordinated Package C states are based on exit latency requirements which are accumulated from the devices PCH and software sources The level of power savings that can be achieved is a function of the exit latency requirement from the platform As a result there is no fixed relationship between the coordinated C state of a package and the power savings that will be obtained from the state Coordinated package C states offer a range of power savings which is a
146. PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling the target voltage on the SVID Bus All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested amongst all active cores is selected Software requested transitions are accepted at any time The processor has a new capability from the previous processor generation it can preempt the previous transition and complete the new request without waiting for this request to complete The processor controls voltage ramp rates internally to ensure glitch free transitions Because there is low transition latency between P states a significant number of transitions per second are possible Low Power Idle States When the processor is idle low power idle states C states are used to save power More power savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Resolution of C states occurs at the thread processor core and processor package level Thread level C states are available if Intel Hyper Threading Technology is enabled Entry and exit of the C States at the thread and core level are shown in Figure 4 2 Intel Xeon Processor E5 2400 v2 Product Family 88 Datasheet Volume One
147. Processor E5 2400 v2 Product Family 55 Datasheet Volume One intel Figure 2 35 Power Limit Data for VCC Power Plane 31 24 23 17 16 14 0 15 Control Time Clamp Power Limit VCC Power Plane Power Limit Data 2 5 2 6 26 Package Power Limits For Multiple Turbo Modes This feature allows the PECI host to program two power limit values to support multiple turbo modes The operating systems and drivers can balance the power budget using these two limits Two separate PECI requests are available to program the lower and upper 32 bits of the power limit data shown in Figure 2 36 The units for the Power Limit and Control Time Window are determined as per the Package Power SKU Unit settings described in Section 2 5 2 6 13 while the valid range for power limit values are determined by the Package Power SKU settings described in Section 2 5 2 6 14 Setting the Clamp Mode bits is required to allow the cores to go into power states below what the operating system originally requested The Power Limit Enable bits should be set to enable the power limiting function Power limit values enable and clamp mode bits can all be set in the same command cycle All RAPL parameter values including the power limit value control time window clamp mode and enable bit will have to be specified correctly even if the intent is to change just one parameter value when programming over PECI Intel recommends exclusive use of just one entity or interf
148. Q 42 SSTL G5 DDR2 DQ 42 SSTL G10 DDR2_DQ 44 SSTL G6 DDR2 DQ 46 SSTL 611 DDR2 CS N 6 SSTL G7 DDR2 DQS DN 05 SSTL 1 0 G12 VCCD PWR G8 DDR2 005 DP 14 SSTL 1 0 Intel Xeon Processor E5 2400 v2 Product Family 187 Datasheet Volume One Processor Land Listing tel Table 8 2 Land Number Sheet 27 of 37 Table 8 2 Land Number Sheet 28 of 37 Meu Land Name T Direction ab Land Name pi Direction G9 DDR2 DQ 40 SSTL 43 DDR3 DQ 18 SSTL Hl VSS GND H5 DDR2 DQ 43 SSTL H10 DDR2_DQ 45 SSTL H6 DDR2 DQ 47 SSTL H11 DDR2_CS_N 7 SSTL H7 DDR2_DQS_DP 05 SSTL 1 0 H12 DDR2_ODT 2 SSTL H8 DDR2_DQS_DN 14 SSTL H13 DDR1_ODT 1 SSTL H9 DDR2 DQ 41 SSTL H14 DDR1_CS_N 5 SSTL 1 DDR3_DQ 53 SSTL 15 VCCD PWR 10 VSS GND H16 DDR1 DN 2 SSTL J11 DDR2_CS_N 3 SSTL H17 DDR1_CLK_DN 0 SSTL 12 DDR1 CS N 7 SSTL H18 DDR1 DN 3 SSTL 13 VCCD PWR H19 DDR1 CLK DP 1 SSTL 14 DDR1_ODT 2 SSTL H2 VSS GND J15 DDR1_CS_N 0 SSTL H20 VCCD PWR 16 DDR1_CLK_DP 2 SSTL 0 H21 DDR2 CLK DN 1 SSTL Ji7 DDR1 DP 0 SSTL H22 DDR2_MA 02 SSTL 18 DDR1_CLK_DP 3 SSTL H23 DDR2_MA 05 SSTL 19 DDR1_MA_PAR SSTL 0 H24 DDR2_MA 09 SSTL 0 12 DDR3_DQ 48 SSTL 25 VCCD PWR 120 DDR1 MA 12
149. QPI1 DRX DN 04 Intel QPI AN6 QPI1_DRX_DN 08 Intel 40 VSS GND 7 VTTD PWR AP41 PE3D_TX_DN 12 PCIEX3 8 5 42 PE3D TX DP 12 PCIEX3 AN9 BPM N 2 ODCMOS 1 0 AP43 VSS GND QPI1 DN 05 Intel QPI 5 QPI1 DRX DP 04 Intel QPI 10 _ 4 ODCMOS 1 0 AP6 VSS GND AP11 BPM_N 5 ODCMOS 1 0 AP7 QPI1_DRX_DP 06 Intel QPI 12 5 5 AP8 QPI1 DRX DN 06 Intel QPI AP13 BCLKO_DN CMOS 9 vss GND 14 vss GND 1 vss GND Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 180 Processor Land Listing tel Table 8 2 Land Number Sheet 13 of 37 Table 8 2 Land Number Sheet 14 of 37 Land 7 Direction abs Land Name pei Direction AR10 PREQ N CMOS 1 0 AR6 QPI1 DP 02 Intel AR11 PRDY N CMOS 7 RSVD AR12 TCK CMOS 8 RSVD AR13 BCLKO DP CMOS 9 RSVD AR14 vss GND AT1 QPI1_DRX_DN 01 Intel AR15 VCC PWR AT10 QPI1_DTX_DN 08 Intel QPI AR16 VCC PWR AT11 VSS GND AR17 VSS GND AT12 QPI1 DTX DN 04 Intel AR18 VCC PWR AT13 VSS GND AR19 VCC PWR AT14 RSVD AR2 QPI1_DRX_DN 03 Intel QPI 15 VCC PWR AR20 VSS GND AT16 VCC PWR AR21 VCC PWR AT17 VSS GND AR22 VCC PWR AT18 VCC PWR AR23 VSS GN
150. R Limit package CPU throttle for which the PACKAGE_RAPL_PERF_STATUS Performance time processor package Status Read was throttled due to power limiting Efficient 06 0x0000 Number of N A Read number of N A Performance productive productive cycles for Indicator Read processor cycles power budgeting purposes ACPI P T Notify 33 0x0000 N A New p state Notify the processor N A Write amp Read Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One equivalent of P1 used in conjunction with package power limiting 47 PCU of the new p state that is one state below the turbo frequency as specified through the last ACPI Notify intel Table 2 8 RdPkgConfig amp WrPkgConfig CPU Thermal and Power Optimization Services Summary Sheet 4 of 4 Parameter RdPkgConfig wrPkgConfig Alternate Value Data 0 EE Inband vane word dword Data Description MSR or CSR decimal dword Access ACPI Notify 33 0x0000 New p state N A Read the processor N A Write amp Read equivalent of P1 PCU to determine used in the p state that is conjunction with one state below the package power turbo frequency as limiting specified through the last ACPI Notify Caching Agent 39 Cbo Index Caching Agent N A Read the Cbo TOR N A TOR Read TOR Index Cbo Table of data for all enabled Bank Requests TOR cores in the event of Read Mode data a 3 strike timeout C
151. R3 MA 03 SSTL 018 vss GND C23 DDR3 MA 06 SSTL 019 DDR2 MA 00 SSTL 24 DDR3_MA 05 SSTL 2 DDR3 DQ 41 SSTL 25 VSS GND D20 vss GND C26 DDR3 MA 14 SSTL 0 D21 DDR3_MA 01 SSTL 27 DDR3_BA 2 SSTL 022 DDR3 MA 02 SSTL 28 DDR3_CKE 3 SSTL 023 DDR3_MA 04 SSTL 29 DDR RESET C23 CMOS 1 5 24 DDR2 MA 08 SSTL 025 DDR3 MA 07 SSTL 0 DDR3_DQ 44 SSTL 026 DDR2_MA 14 SSTL C30 VSS GND Intel Xeon Processor E5 2400 v2 Product Family 185 Datasheet Volume One Processor Land Listing tel Table 8 2 Land Number Sheet 23 of 37 Table 8 2 Land Number Sheet 24 of 37 Land T Direction Mal Land Name hey Direction D27 DDR2_CKE 0 SSTL 22 DDR2_MA 01 SSTL 028 DDR2_CKE 3 SSTL 2 VSS GND D29 DDR2_ECC 3 SSTL 1 0 E24 DDR2_MA 06 SSTL DDR3 DQ 45 SSTL 25 DDR2 111 SSTL D30 DDR2_ECC 7 SSTL 26 VCCD PWR D31 DDR2 005 DP 08 SSTL 27 DDR2 CKE 2 SSTL 032 DDR2_DQS_DN 17 SSTL 28 DDR2 CKE 1 SSTL 033 vss GND E29 DDR2_ECC 2 SSTL 1 0 D34 VSS GND E3 DDR3 DQ 40 SSTL 035 vss GND E30 DDR2_ECC 6 SSTL 1 0 D36 vss GND E31 DDR2_DQS_DN 08 SSTL 1 0 D37 DDR2_DQ 30 SSTL 2 DDR2 005 DP 17 SSTL 038 vss GND E33 DDR2_ECC 0 SSTL 1 0 D39 DDR2_DQ 24 SSTL
152. RX_DP 14 Intel QPI QPI1 DRX DP 12 Intel 6 QPI1_DRX_DN 14 Intel QPI AK40 VSS GND AJ7 VTTD PWR AK41 PE3C_TX_DN 8 PCIEX3 8 RSVD AK42 PE3C_TX_DP 8 PCIEX3 9 VSS GND AK43 VSS GND AK1 QPI1 DN 13 Intel 5 QPI1 DRX DN 12 Intel AK10 RSVD AK6 PWRGOOD CMOS 11 RSVD AK7 SVIDDATA ODCMOS 1 0 AK12 TDO ODCMOS 8 RSVD AK13 QPI_RBIAS Analog 9 RSVD AK14 VSS GND AL1 VSS GND AK15 VCC PWR AL10 _ 0 5 16 VCC PWR AL11 BPM_N 1 ODCMOS 17 VSS GND AL12 TRST_N CMOS 18 PWR AL13 QPI_RBIAS_ SENSE Analog 19 VCC PWR AL14 VSS GND AK2 QPI1_DRX_DP 13 Intel QPI AL15 VCC PWR AK20 VSS GND AL16 VCC PWR AK21 VCC PWR AL17 VSS GND AK22 VCC PWR AL18 VCC PWR AK23 VSS GND AL19 VCC PWR AK24 VCC PWR AL2 QPI1_DRX_DN 11 Intel QPI 25 VCC PWR AL20 VSS GND AK26 VSS GND AL21 VCC PWR AK27 VCC PWR AL22 VCC PWR AK28 VCC PWR AL23 VSS GND AK29 VSS GND AL24 VCC PWR AK3 VTTD PWR AL25 VCC PWR AK30 VTTD PWR AL26 VSS GND AK31 VSS GND AL27 VCC PWR AK32 TEST4 128 VCC PWR Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 178 Processor Land Listing tel Table 8 2 Land Number Sheet 9 of 37 Table 8 2 Land Number Sheet 10 of 37
153. Registers MEM HOT C1 N MEM HOT C23 N PMSYNC Memory throttle control MEM HOT C1 N and MEM HOT C23 N signals have two modes of operation input and output mode Input mode is externally asserted and is used to detect external events such as VR HOT from the memory voltage regulator and causes the processor to throttle the appropriate memory channels Output mode is asserted by the processor known as level mode In level mode the output indicates that a particular branch of memory subsystem is hot MEM HOT 1 is used for memory channel 1 while MEM HOT C23 N is used for memory channels 2 amp 3 Power Management Sync A sideband signal to communicate power management status from the Platform Controller Hub PCH to the processor Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 120 Signal Descriptions intel Table 6 13 Processor Asynchronous Sideband Signals Sheet 3 of 4 Signal Name Description PROCHOT_N PROCHOT_N will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled This signal can also be driven to the processor to activate the Thermal Control Circuit This signal is sampled after PWRGOOD assertion If PROCHOT_N is asserted at the deassertion of RESET_N the processor will tr
154. S GND AT42 PE3D_TX_DP 14 PCIEX3 AU38 21 PCIEX3 AT43 VSS GND AU39 PE1A_RX_DP 1 PCIEX3 5 QPI1 DRX DP 00 Intel QPI AU4 RSVD AT6 CAT_ERR_N ODCMOS 1 0 AU40 SAFE_MODE_BOOT CMOS 7 PWR AU41 VSS GND AT8 QPI1 DTX DN 12 Intel QPI AU42 PE3D_TX_DN 15 PCIEX3 9 VSS GND AU43 151 PCIEX3 AU1 VSS GND AU5 VSS GND AU10 QPI1_DTX_DP 08 Intel QPI AUG RSVD AU11 QPI1 DTX DN 06 Intel QPI 07 QPI1 DTX DN 14 Intel QPI 012 QPI1 DTX DP 04 Intel QPI AU8 QPI1 DTX DP 12 Intel QPI AU13 QPI1 DTX DN 02 Intel QPI AU9 QPI1 DTX DN 10 Intel QPI 14 RSVD QPI1 DTX DN 19 Intel QPI 15 PWR AV10 VSS GND AU16 PWR 11 QPI1 DTX DP 06 Intel QPI 17 VSS GND AV12 VSS GND AU18 VCC PWR AV13 QPI1 DTX DP 02 Intel QPI 19 PWR AV14 VSS GND AU2 RESET_N CMOS AV15 PWR AU20 VSS GND AV16 VCC PWR AU21 VCC PWR AV17 VSS GND AU22 PWR AV18 VCC PWR AU23 vss GND AV19 PWR AU24 PWR AV2 QPI1 DTX DP 19 Intel QPI 25 PWR 20 VSS GND AU26 vss GND AV21 VCC PWR AU27 PWR AV22 PWR AU28 PWR AV23 VSS GND AU29 PE3B RX DP 7 PCIEX3 24 VCC PWR AU3 RSVD AV25 VCC PWR AU30 PE3B DN 6 PCIEX3 26 vss GND AU31 PE3B RX DP 5 PCIEX3 27 PWR AU32 4 PCIEX3 28 VCC PWR AU33 vss GND AV29 DN 7 PCIEX3 AU34 PE3
155. S M32 GND VSS 110 GND vss M33 GND vss 123 GND vss M34 GND VSS 127 GND VSS M35 GND VSS 128 GND VSS M37 GND VSS 129 GND VSS M40 GND VSS 130 GND vss M42 GND VSS 131 GND VSS M43 GND VSS 132 GND VSS M5 GND VSS 35 GND VSS M6 GND VSS 36 GND VSS M7 GND VSS 137 GND VSS M8 GND VSS J40 GND VSS M9 GND VSS 142 GND VSS 1 GND VSS 15 GND VSS N2 GND VSS 16 GND VSS N37 GND VSS 17 GND VSS N40 GND lvss js vss N42 GND Intel Xeon Processor E5 2400 v2 Product Family 173 Datasheet Volume One Processor Land Listing tel Table 8 1 Land Name Sheet 35 of 37 Table 8 1 Land Name Sheet 36 of 37 Land Name Buffer Direction Land Name Buffer Type Direction Number Number VSS P10 GND VSS 2 GND VSS P2 GND vss w3 GND VSS P3 GND VSS W34 GND VSS P33 GND VSS w37 GND VSS P37 GND VSS W40 GND VSS P4 GND VSS w5 GND VSS P40 GND VSS W6 GND VSS P7 GND VSS w9 GND VSS R10 GND VSS Y34 GND VSS R34 GND VSS Y37 GND VSS R37 GND VSS Y4 GND VSS R4 GND VSS Y40 GND vss R40 GND VSS Y7 GND VSS R7 GND VSS_VCC_SENSE N11 VSS T10 GND VSS_VSA_SENSE AE34 VSS T34 GND VSS VITD SENSE AK33 VSS T37 GND VTTA AT7 PWR VSS T4 GND VTTA AW7 PWR VSS T40 GND VTTA AW9 PWR VSS
156. SS D38 GND VSS B3 GND VSS D4 GND VSS B36 GND VSS D40 GND VSS B40 GND VSS E11 GND VSS B42 GND VSS E16 GND VSS BA10 GND VSS E23 GND VSS BA12 GND VSS E4 GND VSS BA14 GND VSS E40 GND VSS BA17 GND VSS F10 GND VSS BA20 GND VSS F27 GND VSS BA26 GND VSS F28 GND vss BA3 GND vss F29 GND vss BA32 GND 55 GND VSS BA40 GND VSS F31 GND VSS BA8 GND VSS F32 GND VSS C10 GND VSS F33 GND VSS C15 GND VSS F35 GND Iss Toe cn vss F36 GND Intel Xeon Processor E5 2400 v2 Product Family 172 Datasheet Volume One Processor Land Listing tel Table 8 1 Land Name Sheet 33 of 37 Table 8 1 Land Name Sheet 34 of 37 Land Name Buffer Direction Land Name Aaa Buffer Type Direction VSS F37 GND VSS J9 GND VSS F38 GND VSS K2 GND VSS F39 GND VSS K21 GND VSS F4 GND VSS K37 GND VSS F40 GND VSS K4 GND VSS F5 GND VSS K40 GND VSS F6 GND VSS L14 GND VSS F7 GND VSS L19 GND VSS F8 GND VSS L24 GND VSS F9 GND VSS L37 GND VSS G33 GND VSS L39 GND VSS G34 GND VSS L4 GND VSS G35 GND VSS L40 GND VSS G4 GND VSS M10 GND VSS G41 GND VSS M11 GND VSS G42 GND VSS M13 GND VSS G43 GND VSS M16 GND VSS H1 GND VSS M23 GND VSS H2 GND VSS M27 GND VSS H3 GND VSS M28 GND VSS H40 GND VS
157. SSTL 15 VSS GND K4 VSS GND 16 VSS GND K40 VSS GND 17 55 GND K41 DDR3_DQS_DN 02 SSTL 18 VSS GND K42 DDR3_DQS_DP 11 SSTL 19 VSS GND K43 DDR3_DQS_DN 11 SSTL K1 DDR3 001491 SSTL 5 DDR1 0091341 5511 K10 DDR1_DQ 36 SSTL DDR1_DQ 38 SSTL K11 VCCD PWR K7 DDR1 005 DN 04 SSTL K12 DDR1 CS N 3 SSTL DDR1 DQS DP 13 SSTL 1 0 K13 DDR1_CAS_N SSTL K9 DDR1 DQ 32 SSTL K14 DDR1_WE_N SSTL L1 DDR3_DQS_DN 06 SSTL 1 0 K15 DDR1_CS_N 4 SSTL 110 DDR1_DQ 37 SSTL K16 VCCD PWR L11 DDR1 CS N 2 SSTL K17 DDR1 RAS SSTL 112 DDR1 CS N 6 SSTL K18 VCCD PWR L13 DDR1 MA 13 SSTL K19 DDR1 SSTL 114 VSS GND K2 VSS GND L15 DDR1_CS_N 1 SSTL 0 K20 DDR1_MA 02 SSTL 0 L16 RSVD K21 VSS GND L17 DDR1_BA 0 SSTL K22 DDR1_MA 05 SSTL 0 L18 DDR1 BA 1 SSTL K23 DDR1 MA 08 SSTL 119 VSS GND K24 DDR1_MA 15 SSTL 0 L2 DDR3 005 DP 06 SSTL 25 DDR1 SSTL 0 L20 DDR1_MA 01 SSTL 0 K26 VCCD PWR L21 DDR1 MA 03 SSTL 0 K27 DDR1_DQ 27 SSTL 122 DDR1 MA 06 SSTL K28 DDR1_DQ 31 SSTL 123 DDR1 71 SSTL 0 K29 DDR1 DQS DP 03 SSTL 124 55 GND K3 DDR3 DQS DP 15 SSTL 125 DDR1 MA 09 SSTL K30 DDR1 005 DN 12 SSTL 1 0 L26 DDR RESET C1 N CMOS 1 5 K31 DDR1 DQ 25 SSTL 127 DDR1_DQ 26 SSTL 1 0 K32 DDR1_DQ 29 SSTL 128 DDR1_DQ 30 SSTL DDR1_DQ 18 SSTL 1 0 L29 DDR1 DQS DN 03 SSTL 1 0 Int
158. SSTL H26 DDR1_CKE 3 SSTL 21 DDR1_PAR_ERR_N SSTL 27 DDR1_ECC 2 SSTL 122 DDR1 MA 14 SSTL 0 H28 DDR1_ECC 6 SSTL 1 0 123 vss GND H29 DDR1 DQS DN 08 SSTL 124 DDR1 BA 2 SSTL H3 VSS GND 125 DDR1_CKE 2 SSTL H30 DDR1 DQS DP 17 SSTL 126 DDR1_CKE 1 SSTL H31 DDR1_ECC 4 SSTL 127 55 GND H32 DDR1_ECC 5 SSTL 128 55 GND H33 DDR1_DQS_DN 02 SSTL 1 0 129 vss GND H34 DDR1_DQS_DP 02 SSTL J3 DDR3_DQ 52 SSTL H35 DDR23_RCOMP 0 Analog 130 vss GND H36 DDR2_DQ 18 SSTL 131 VSS GND H37 DDR2_DQ 22 SSTL 1 0 132 VSS GND H38 DDR2_DQS_DN 11 SSTL 133 DDR1_DQ 23 SSTL H39 DDR2 DQS DP 11 SSTL 134 DDR1_DQ 22 SSTL H4 TESTO 135 VSS GND H40 VSS GND 136 vss GND H41 DDR3_DQ 19 SSTL 137 55 GND H42 0083 0923 ssm 138 DDR2 DQ 16 SSTL 1 0 Intel Xeon Processor E5 2400 v2 Product Family 188 Datasheet Volume One Processor Land Listing intel Table 8 2 Land Number Sheet 29 of 37 Table 8 2 Land Number Sheet 30 of 37 Ted Land Name T Direction Land cpi Direction 139 DDR2_DQ 17 SSTL 1 0 K34 DDR1_DQS_DN 11 SSTL DDR1_RCOMP 0 Analog K35 DDR1 DQ 16 SSTL 7140 55 GND K36 DDR1_DQ 17 SSTL 141 DDR3 DQS DP 02 SSTL K37 VSS GND 142 VSS GND K38 DDR2 DQ 20 SSTL 143 DDR3_DQ 22 SSTL K39 DDR2_DQ 21
159. ST Enable Strap Input which allows the platform to enable or disable built in self test BIST on the processor This signal is pulled up on the die refer to Table 7 6 for details Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 119 Signal Descriptions intel Table 6 13 Processor Asynchronous Sideband Signals Sheet 2 of 4 Signal Name Description BMCINIT BMC Initialization Strap Indicates whether Service Processor Boot Mode should be used Used in combination with FRMAGENT and SOCKET 10 inputs 0 Service Processor Boot Mode Disabled Example boot modes Local PCH this processor hosts a legacy PCH with firmware behind it Intel QPI Link Boot for processors one hop away from the FW agent or Intel QPI Link Init for processors more than one hop away from the firmware agent 1 Service Processor Boot Mode Enabled In this mode of operation the processor performs the absolute minimum internal configuration and then waits for the Service Processor to complete its initialization The socket boots after receiving a GO handshake signal via a firmware scratchpad register This signal is pulled down on the die refer to Table 7 6 for details For further details see Intel Xeon Processor 5 v2 Product Family Datasheet Volume Two Registers CAT ERR N Indicates that the system has experienced a fatal or catastrophic error and cannot continue to operate The processor will a
160. Sensor DTS thermal profiles 105 5 1 5 Thermal Metrology ierit E E 107 5 2 Processor Core Thermal lt 109 5 2 1 Processor Temperature iioc cenare terere ened onde ARR RES 109 5 2 2 Adaptive Thermal Monitor ies sa eee e Lin ense ta sa de P deed ld 109 5 2 2 1 Frequency SVID Control sss 110 5 2 2 2 Clock Modulation iei beret erroe i 111 5 2 3 On Demand sees ed 111 5 2 4 PROCHOT N Signal oiii rrr temet ea enia rece terrse Ea eed 112 5 2 5 THERMTRIP Signal eb RANK RR Edi 112 5 2 6 Integrated Memory Controller IMC Thermal Features 113 5 2 6 1 DRAM Throttling 11 113 5 2 6 2 Hybrid Closed Loop Thermal Throttling CLTT Hybrid 113 5 2 6 3 MEM HOT C1 MEM HOT C23 113 5 2 6 4 Integrated SMBus Master Controllers for Memory Interface 114 6 Signal Descriptions oe RA xD 115 6 1 System Memory Interface 5 0 115 6 2 PCI Express Based Interface 5 116 6 3 2 Express Port 0 Signals 117 6 4 Intel QuickPath Interconnect Signals
161. T ID 0 AW11 CMOS 124 PWR Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 167 Processor Land Listing tel Table 8 1 Land Name Sheet 23 of 37 Table 8 1 Land Name Sheet 24 of 37 Land Name Land Buffer Type Direction Land Name Buffer Type Direction Number Number VCC AL25 PWR VCC AR22 PWR VCC AL27 PWR VCC AR24 PWR VCC AL28 PWR VCC AR25 PWR VCC AM15 PWR VCC AR27 PWR VCC AM16 PWR VCC AR28 PWR VCC AM18 PWR VCC AT15 PWR VCC AM19 PWR VCC AT16 PWR VCC AM21 PWR VCC AT18 PWR VCC AM22 PWR VCC AT19 PWR VCC AM24 PWR VCC AT21 PWR VCC AM25 PWR VCC AT22 PWR VCC AM27 PWR VCC AT24 PWR VCC AM28 PWR VCC AT25 PWR VCC AN15 PWR VCC AT27 PWR VCC AN16 PWR VCC AT28 PWR VCC AN18 PWR VCC AU15 PWR VCC AN19 PWR VCC AU16 PWR VCC AN21 PWR VCC AU18 PWR VCC AN22 PWR VCC AU19 PWR VCC AN24 PWR VCC AU21 PWR VCC AN25 PWR VCC AU22 PWR VCC AN27 PWR VCC AU24 PWR VCC AN28 PWR VCC AU25 PWR VCC AP15 PWR VCC AU27 PWR VCC AP16 PWR VCC AU28 PWR VCC AP18 PWR VCC AV15 PWR VCC AP19 PWR VCC AV16 PWR VCC AP21 PWR VCC AV18 PWR VCC AP22 PWR VCC AV19 PWR VCC AP24 PWR VCC AV21 PWR VCC AP25 PWR VCC AV22 PWR VCC AP27 PWR VCC AV
162. TAG and TAP Signals DC Specifications 147 7 20 Serial VID Interface SVID DC 5 2 0 4 0 440 447 4 24 147 7 21 Processor Asynchronous Sideband DC Specifications 148 7 22 Miscellaneous Signals DC 5 mm 148 7 23 Processor I O Overshoot Undershoot Specifications 154 7 24 Processor Sideband Signal Group Overshoot Undershoot Tolerance 155 3 1 i rep 157 9 2 175 9 1 Processor Loading Specifications 198 9 2 Package Handling 2 4 0 0 44 1 memes 198 9 3 Processor Materials ee VER EXE ERE EXE EIE CDM 199 10 1 PWM Fan Frequency Specifications For 4 Pin Active Thermal Solution 212 10 2 PWM Fan Characteristics for Active Thermal 212 10 3 PWM Fan Connector Pin and Wire 213 10 4 Processor Thermal Solution Boundary 214 Intel Xeon Processor E5 2400 v2 Product Family 10 Datasheet Volume One Revision History
163. Test Access Port TAP Signals 4 4 1 1 2 0 126 7 1 8 Processor Sideband Signals 126 7 1 9 Power Ground and Sense 5 126 7 1 9 1 Power and Ground mns 126 7 1 9 2 Decoupling Guidelines essem 127 7 1 9 3 Voltage Identification 127 7 1 10 Reserved or Unused Signals sss 131 7 2 Signal Group 132 7 3 Power On Configuration 5 135 7 4 Fault Resilient Booting 136 738 MIXING 550 rmm 136 7 6 Flexible Motherboard Guidelines 2 4 3 137 7 7 Absolute Maximum and Minimum 065 137 7 7 1 Storage Condition 138 7 8 138 7 8 1 Voltage and Current 5 5 139 7 8 2 Die Voltage 1 143 7 8 2 1 VCC Overshoot Specifications 1000 2 143 7 8 3 Signal DC 5 144 7 8 3 1 PCI Express
164. The Thermal Status Read provides information on package level thermal status Data includes Thermal Control Circuit TCC activation Bidirectional PROCHOT N signal assertion Critical Temperature Both status and sticky log bits are managed in this status word All sticky log bits are set upon a rising edge of the associated status bit and the log bits are cleared only by Thermal Status reads or a processor reset A read of the Thermal Status word always includes a log bit clear mask that allows the host to clear any or all of the log bits that it is interested in tracking A bit set to 0 in the log bit clear mask will result in clearing the associated log bit If a mask bit is set to 0 and that bit is not a legal mask a failing completion code will be returned A bit set to 1 is ignored and results in no change to any sticky log bits For example to clear the TCC Activation Log bit and retain all other log bits the Thermal Status Read should send a mask of OxFFFFFFFD Figure 2 31 Thermal Status Word 31 6543210 Reserved a Critical Temperature Log Critical Temperature Status Bidirectional PROCHOT Log Bidirectional PROCHOT Status TCC Activation Log TCC Activation Status 2 5 2 6 21 Thermal Averaging Constant Write Read This feature allows the PECI host to control the window over which the estimated processor PECI temperature is filtered The hos
165. The VR should ramp to the new VID setting with a slow slew rate as defined in the slow slew rate data register The SetVID Slow is 1 4 slower than the SetVID fast slew rate The SetVID slow command is preemptive the VR interrupts its current processes and moves to the new VID This is the instruction used for normal P state voltage change This command is used in the processor for the Intel Enhanced SpeedStep Technology transitions 7 1 9 3 4 SetVI D Decay Command The SetVI D Decay command is the slowest of the DVID transitions It is only used for VID down transitions The VR does not control the slew rate the output voltage declines with the output load current only Intel Xeon Processor E5 2400 v2 Product Family 128 Datasheet Volume One The SetVID Decay command is preemptive i e the VR interrupts its current processes and moves to the new VID 7 1 9 3 5 SVID Power State Functions SetPS The processor has three power state functions and these will be set seamlessly via the SVID bus using the SetPS command Based on the power state command the SetPS commands sends information to VR controller to configure the VR to improve efficiency especially at light loads For example typical power states are PS 00h Represents full power or active mode PS 01h Represents a light load 5A to 20A PS 02h Represents a very light load 5A The VR may change its configuration to meet the processor s power needs with greater efficien
166. Thermal N A Read the DRAM CSR Thermal Estimation Thermal ESTIMATION _ Estimation 15 0x0000 Configuration Data Estimation CONFIG Configuration configuration Data parameters Read Write DRAM N A DRAM Thermal Configure the CSR Thermal Estimation DRAM Thermal MEM TRML ESTIMATION Estimation Configuration Estimation CONFIG Configuration 15 0x0000 Data parameters Data Read Write DRAM Rank N A Absolute Write N A Temperature Channel temperature in temperature Write 18 Index amp Degrees Celsius for each rank DIMM Index for ranks 0 1 2 within a single amp 3 DIMM DIMM Absolute N A Read CSR DIMMTEMPSTAT 0 2 Temperature Ch temperature temperature of Read 14 M ek Degrees Celsius for each DIMM DIMMs 0 1 amp 2 within a channel DIMM N A Absolute Write ambient N A Ambient temperature in temperature Temperature Degrees C to be reference for Write Read 19 0x0000 used as ambient activity based temperature rank reference temperature estimation DIMM Absolute N A Read ambient N A Ambient temperature in temperature Temperature Degrees C to be reference for Write Read 19 0x0000 used as ambient activity based temperature rank reference temperature estimation DRAM Maximum of all N A Read the N A Channel rank temperatures maximum Temperature 22 for each channel in DRAM channel Read Degrees Celsius temperature Accumulated DRAM energy N A Read the DRAM MSR 619h DRAM Energy consumed by the energy DRAM_ENERGY_ST
167. VTTD PWR N10 DDR VREFDQRX C1 DC M16 VSS GND N11 VSS_VCC_SENSE 17 VTTD PWR N2 VSS GND M18 DDR1 MA 10 SSTL N3 DDR3_DQ 51 SSTL 19 RSVD N33 TEST2 2 DDR3_DQ 54 SSTL N34 DDR1_DQ 15 SSTL M20 RSVD N35 DDR1_DQ 11 SSTL 21 RSVD N36 DDR1_DQ 10 SSTL 22 DDR1_MA 04 SSTL N37 vss GND M23 VSS GND N38 DDR2_DQ 15 SSTL m24 _ sse o 39 DDR2 DQ 14 SSTL 1 0 Intel Xeon Processor E5 2400 v2 Product Family 190 Datasheet Volume One Processor Land Listing intel Table 8 2 Land Number Sheet 33 of 37 Table 8 2 Land Number Sheet 34 of 37 Land pated Direction b Land Name Direction N4 RSVD R34 VSS GND N40 VSS GND R35 DDR1 DQS DP 10 SSTL N41 MEM_HOT_C23_N ODCMOS 1 0 R36 DDR1 DQS DN 10 SSTL 1 0 N42 VSS GND R37 VSS GND N43 DDR3 DQ 11 SSTL R38 DDR2_DQS_DN 10 SSTL 5 DDR2_DQ 53 SSTL R39 DDR2 DQS DP 10 SSTL 6 DDR2_DQ 52 SSTL 4 VSS GND N7 DDR1_RCOMP 1 Analog R40 VSS GND N8 DDR1_DQ 40 SSTL R41 DDR3_DQS_DN 10 SSTL DDR1_DQ 44 SSTL 42 DDR3_DQS_DP 01 SSTL DDR3_DQ 60 SSTL R43 DDR3_DQS_DN 01 SSTL 10 VSS GND R5 DDR2 DQS DN 15 SSTL 11 SENSE 0 R6 DDR2_DQS_DP 15 SSTL 2 55 GND R7 VSS GND P3 VSS GND R8 DDR1_DQS_DN 14 SSTL
168. _DP 6 PCIEX3 AG1 55 GND AH43 vss GND AG10 RSVD 5 QPI1_DRX_DN 16 Intel 11 RSVD AH6 vss GND AG2 QPI1_DRX_DN 19 Intel 7 PROCHOT ODCMOS 1 0 AG3 QPI1_DRX_DP 19 Intel 8 RSVD AG33 DMI_RX_DP 2 PCIEX 9 RSVD AG34 DMI_RX_DN 2 PCIEX 1 vss GND AG35 vss GND 10 RSVD AG36 PE1A_TX_DP 1 PCIEX3 11 55 GND AG37 PE1A_TX_DN 1 PCIEX3 2 QPI1 DRX DN 15 Intel QPI AG38 VSS GND QPI1 DRX DP 15 Intel QPI AG39 PE1A_TX_DN 3 PCIEX3 AJ33 DMI_RX_DP 0 PCIEX AG4 vss GND 34 DN 0 PCIEX AG40 1 TX DP 3 PCIEX3 AJ35 VSS GND AG41 VSA PWR 36 DMI_TX_DN 3 PCIEX AG42 PE1B TX DN 5 PCIEX3 AJ37 TX DP 3 PCIEX Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 177 Processor Land Listing intel Table 8 2 Land Number Sheet 7 of 37 Table 8 2 Land Number Sheet 8 of 37 Land 7 Direction Penton Land Name ghey Direction 38 VSS GND AK33 VSS_VTTD_SENSE 39 TX DNI 1 PCIEX3 0 AK34 VTTD_SENSE 0 4 VSS GND AK35 DMI TX DNI 2 PCIEX 0 40 PE3A_TX_DP 1 PCIEX3 AK36 DMI_TX_DP 2 PCIEX 41 VSA PWR AK37 VSS GND 42 PE1B_TX_DN 7 PCIEX3 AK38 PE3A_TX_DN 2 PCIEX3 43 PE1B_TX_DP 7 PCIEX3 AK39 PE3A_TX_DP 2 PCIEX3 5 QPI1_D
169. _DQS_DN 09 SSTL 1 0 AB39 DDR2 DQS DP 09 SSTL 1 0 Table 8 1 Land Name Sheet 37 of 37 Land Name Buffer Direction VTTD M26 PWR VTTD M29 PWR VTTD M30 PWR VTTD M31 PWR VTTD_SENSE AK34 8 2 Listing by Land Number Table 8 2 Land Number Sheet 1 of 37 Land pus Direction A10 DDR3 DQ 36 SSTL 14 55 GND 15 DDR3_CS_N 4 SSTL A16 DDR3 RAS N SSTL 17 DDR3 MA 10 SSTL 18 DDR3_CLK_DN 2 SSTL 19 VSS GND A20 DDR3 DN 1 SSTL 24 VSS GND A25 DDR3 MA 11 SSTL 26 DDR3 ERR SSTL 27 DDR3 MA 15 SSTL A28 DDR3 CKE 2 SSTL A29 VSS GND A30 DDR3 ECC 3 SSTL A31 DDR3_ECC 7 SSTL 2 DDR3 DQS DP 08 SSTL 1 0 A39 DDR2 DQS DN 12 SSTL 1 0 A4 VSS GND A40 VSS GND A41 VSS GND A5 VSS GND A6 DDR3_DQ 38 SSTL 7 DDR3 DQS DN 04 SSTL A8 DDR3 DQS DP 13 SSTL 1 0 A9 DDR3_DQ 32 SSTL AA10 VSS GND Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One Processor Land Listing intel Table 8 2 Land Number Sheet 3 of 37 Table 8 2 Land Number Sheet 4 of 37 Land Land Name Buffer Direction Land Land Name Sutter Direction Number Type Number Type AB4 VSS GND AD34 DDR1 DQ 04 SSTL 1 0 AB40
170. a 31 24 23 16 15 8 7 0 2 5 2 6 4 Rank 0 Absolute Temp in Degrees C Rank 1 Absolute Temp in Degrees C Rank 2 Absolute Temp in Degrees C Rank 3 Absolute Temp in Degrees C Rank Temperature Data 15 6 5 3 2 0 DIMM Index Channel Index Parameter format DIMM Temperature Read This feature allows the PECI host to read the temperature of all the DIMMs within a channel up to a maximum of three DIMMs This read is not limited to platforms using a particular memory temperature source or temperature estimation method For platforms using DRAM thermal estimation the PCU will provide the estimated temperatures Otherwise the data represents the latest DIMM temperature provided by the TSOD or on board DIMM sensor and requires that CLTT closed loop throttling mode be enabled and OLTT open loop throttling mode be disabled Refer to Table 2 7 for channel index encodings Intel Xeon Processor E5 2400 v2 Product Family 40 Datasheet Volume One Figure 2 14 2 5 2 6 5 Figure 2 15 2 5 2 6 6 DIMM Temperature Read Write DIMM 1 DIMM 0 Reserved Reserved Absolute Temp Absolute Temp In Degrees C In Degrees C DIMM Temperature Data 15 3 2 0 Parameter Format DIMM Ambient Temperature Write Read This feature allows the PECI host to provide an ambient temperature reference to be used by the processor for activity based DRAM temperature estimation This write
171. ace PECI for instance to manage all processor package power limiting and budgeting needs If PECI is being used to manage package power limiting activities BIOS should lock out all subsequent inband package power limiting accesses by setting bit 31 of the PACKAGE POWER LIMIT MSR and CSR to 1 The power limit 1 is intended to limit processor power consumption to any reasonable value below TDP and defaults to TDP Power Limit 1 values may be impacted by the processor heat sinks and system air flow Processor power limit 2 can be used as appropriate to limit the current drawn by the processor to prevent any external power supply unit issues The Power Limit 2 should always be programmed to a value typically 2096 higher than Power Limit 1 and has no default value associated with it Though this feature is disabled by default and external programming is required to enable initialize and control package power limit values and time windows the processor package will still turbo to if Limit 1 is not enabled or initialized Control Time Window 1 Power Limit 1 Time also known as Tau values may be programmed to be within a range of 250 mS 40 seconds Control Time Window 2 Power Limit 2 Time values should be in the range 3 mS 10 mS The same conversion formula used for the DRAM Power Limiting feature see Section 2 5 2 6 9 should be applied when programming the Control Time Window bits 23 17 fo
172. actions If THERMTRIP_N is asserted all processor supplies VCC VSA VCCD must removed The temperature at which THERMTRIP_N asserts is not user configurable and is not software visible Intel Xeon Processor E5 2400 v2 Product Family 112 Datasheet Volume One 5 2 6 5 2 6 1 5 2 6 1 1 5 2 6 1 2 5 2 6 1 3 5 2 6 2 5 2 6 Integrated Memory Controller Thermal Features DRAM Throttling Options The Integrated Memory Controller IMC has two independent mechanisms that cause system memory throttling Open Loop Thermal Throttling OLTT and Hybrid OLTT OLTT Hybrid Closed Loop Thermal Throttling CLTT and Hybrid CLTT CLTT Hybrid Please refer to Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers section 8 11 for further details Open Loop Thermal Throttling OLTT Pure energy based estimation for systems with no BMC or Intel Management Engine Intel ME No memory temperature information is provided by the platform or DIMMs The CPU is informed of the ambient temperature estimate by the BIOS or by a device via the PECI interface DIMM temperature estimates and bandwidth control are monitored and managed by the PCU on a per rank basis Hybrid Open Loop Thermal Throttling OLTT Hybrid Temperature information is provided by the platform for example BMC or Intel ME through PECI and the PCU interpolates gaps with energy based estimati
173. age to allow most reads to occur without VM exits 3 1 3 Intel VT d Objectives The key Intel VT d objectives are domain based isolation and hardware based virtualization A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated Virtualization allows for the creation of one or more partitions on a single system This could be multiple Intel Xeon Processor E5 2400 v2 Product Family 78 Datasheet Volume One partitions in the same operating system or there be multiple operating system instances running on the same system offering benefits such as system consolidation legacy migration activity partitioning or security 3 1 3 1 Intel VT d Features Supported The processor supports the following Intel VT d features Root entry context entry and default context Support for 4 K page sizes only Support for register based fault recording only for single entry only and support for MSI interrupts for faults Support for fault collapsing based on Requester ID Support for both leaf and non leaf caching Support for boot protection of default page table Support for non caching of invalid page table entries Support for hardware based flushing of translated but pending writes and pending reads upon IOTLB invalidation Support for page selective OTLB invalidation Support for ARI Alternative Requester ID a PCI SIG ECR for increas
174. al PROCHOT_N processor hot is asserted when the processor core temperature has reached its maximum operating temperature If Adaptive Thermal Monitor is enabled note it must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT_N is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers for specific register and programming details The PROCHOT_N signal is bi directional in that it can either signal when the processor any core has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT_N can provide a means for thermal protection of system components As an output PROCHOT_N will go active when the processor temperature monitoring sensor detects that one or more cores has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT_N by the system will activate the TCC if enabled for all cores TCC activation due to PROCHOT_N assertion by the system will result in the processor immediately transitioning to the minimum frequency and corresponding voltage using Freq SVID control Clock modulation is not activated in this case The TCC will rema
175. all Passive Heat Sink Solution The STS100Pis available for use with boxed processors that have TDP s of 95W and lower The 25 5 mm Tall passive solution is designed to be used in SSI Blades 1U and 2U chassis where ducting is present The use of a 25 5 mm Tall heatsink in a 2U chassis is recommended to achieve a lower heatsink T and more flexibility in system design optimization Figure 10 4 is a representation of the heat sink solution The retention solution used for these products is called Unified Retention System URS Figure 10 4 STS100P 25 5 mm Tall Passive Heat Sink Intel Xeon Processor E5 2400 v2 Product Family 202 Datasheet Volume One Boxed Processor Specifications tel 10 2 10 2 1 Mechanical Specifications This section documents the mechanical specifications of the boxed processor solution Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones The boxed processor and boxed thermal solutions will be sold separately Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling Baseboard keepout zones are Figure 10 5 Figure 10 8 Physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in Figure 10 9 and Figure 10 10 Mechanical drawings for the 4 pin fan header and 4 pin connector used for the active fan heat sink solution are represented in Figure 10 11 and Figure 10 12 None of th
176. alue Units Notes DDR 1 _PAR_ERR_N Pull Up VCCD 100 Q DDR 2 3 PAR ERR Pull Up VCCD 100 Q BMCINIT Pull Down VSS 2K Q 1 FRMAGENT Pull Down vss 2K Q 1 _ Pull Down vss 2K Q 1 SAFE_MODE_BOOT Pull Down vss 2K Q 1 SOCKET ID 1 0 Pull Down vss 2K Q 1 BIST_ENABLE Pull Up VIT 2K Q 1 Pull Up VIT 2K Q 1 EAR N Pull Up VTT 2K Q 2 Notes 1 Please refer to the Platform Design Guide PDG to change the default states of these signals 2 Refer to Table 7 19 for details on the Roy Buffer on Resistance value for this signal 7 3 Power On Configuration POC Options Several configuration options can be configured by hardware The processor samples its hardware configuration at reset on the active to inactive transition of RESET_N or upon assertion of PWRGOOD inactive to active transition For specifics on these options please refer to Table 7 7 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset transition of the latching signal RESET_N or PWRGOOD Table 7 7 Power On Configuration Option Lands Configuration Option Land Name Notes Output tri state PROCHOT_N 1 Execute BIST Built In Self Test BIST_ENABLE 2 Enable Service Processor Boot Mode BMCINIT 3 Enable Intel Trusted Execution Technology Intel TXT_PLTEN 3 TXT Platform Power up Sequence Halt for I TP configurat
177. as measured across the VCC SENSE and VSS VCC SENSE lands Table 7 14 Vcc Overshoot Specifications Sheet 1 of 2 Symbol Parameter Min Max Units Figure Notes Vos MAX Magnitude of Vcc overshoot above VID 65 mV 7 5 Intel Xeon Processor E5 2400 v2 Product Family 143 Datasheet Volume One Table 7 14 Vcc Overshoot Specifications Sheet 2 of 2 intel Symbol Parameter Min Max Units Figure Notes Tos MAX Time duration of Vcc overshoot above VccMAX 25 us 7 5 E value at the new lighter load Figure 7 5 Vcc Overshoot Example Waveform V VID Vos VccMAX I1 8 o 2 Tos wax 0 10 15 20 25 Time us Notes 1 Vos max is the measured overshoot voltage Tos max is the measured time duration above VccMAX I1 3 Load Release Current Step for example 12 to I1 where 12 gt 11 4 VccMAX I1 VID 11 RLL 15mV 7 8 3 Signal DC Specifications DC specifications are defined at the processor pads unless otherwise noted DC specifications are only valid while meeting specifications for case temperature Tcase specified in Section 5 Thermal Management Specifications clock frequency and input voltages Care should be taken to read all notes associated with each specification Table 7 15 DDR3 and DDR3L Signal DC Specifications Sheet 1 of 2 Symbol Parameter Min Typ
178. assing completion code if it successfully submits the request to the appropriate location and gets a response Exactly what the receiving agent does with the data or how it responds is up to that agent and is outside the scope of PECI 3 0 Table 2 14 WrPCI ConfigLocal Response Definition Response Meaning Bad FCS Electrical error or AW FCS failure Abort FCS Illegal command formatting mismatched RL WL Command Code CC 0x40 Command passed data is valid CC 0x80 Response timeout The processor was not able to generate the required response in a timely fashion Retry is appropriate CC 0x81 Response timeout The processor is not able to allocate resources for servicing this command at this time Retry is appropriate Intel Xeon Processor E5 2400 v2 Product Family 67 Datasheet Volume One Table 2 14 2 5 2 10 3 Table 2 15 intel WrPCI ConfigLocal Response Definition Response Meaning CC 0x82 The processor hardware resources required to service this command are in a low power state Retry may be appropriate after modification of PECI wake mode behavior if appropriate CC 0x90 Unknown Invalid Illegal Request CC 0x91 PECI control hardware firmware or associated logic error The processor is unable to process the request WrPCI ConfigLocal Capabilities On the processor PECI clients the PECI WrPCIConfigLocal command provides a method for programming certa
179. ature specification is the responsibility of the system integrator Note This thermal solution is for use with processor SKUs no higher than 95W 8 and 10 Core 80W 4 6 Core Please refer to the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG for detailed mechanical drawings of the STS100P Table 10 4 Processor Thermal Solution Boundary Conditions Form Thermal Heatsink A Core Solution Volumetric inch of Delta P TDP W Count et mm H50 2 95 10 0 316 50 0 95 8 0 320 49 6 1U STS100P 90 x 90 x 25 5 9 7 0 196 80 6 4 0 333 49 4 60 10 0 313 49 2 60 6 0 334 49 0 95 10 0 311 50 5 95 8 0 315 50 1 STS100A without fan 0 070 80 6 4 0 328 49 8 60 10 0 308 49 5 60 6 0 329 49 3 2U 90 x 90 x 64 26 95 10 0 186 62 3 95 8 0 190 62 0 STS100C without fan 0 140 80 6 4 0 203 59 8 60 10 0 183 57 0 60 6 0 204 56 8 Intel Xeon Processor E5 2400 v2 Product Family 214 Datasheet Volume One m e oxed Processor Specifications n tel Table 10 4 Processor Thermal Solution Boundary Conditions Form Thermal Heatsink A Core Peca Tra 1 1 4 Solution Volumetric inch of Delta P TDP W Count C W et 20 95 10 0 281 53 3 95 8 0 285 52 9 STS100A with fan 80 6 4 0 298 52 2 60 10 0 278 51 3
180. b Absolute C ing Point 7 6 cross abs Single Ended 0 250 0 550 Jao 247 Veross rel Relative Crossing Point Single Ended 0 250 0 550 0 5 VHayg 0 5 VHayg V 7 6 3 4 5 0 700 0 700 AV cross Range of Crossing Points Single Ended N A 0 140 7 11 6 Threshold Voltage Single Ended Vcross 0 1 Vcross 0 1 V Input Leakage Current N A 1 50 uA 8 Cpad Pad Capacitance N A 0 9 1 2 pF Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies These specifications are specified at the processor pad m edge of BCLK 0 1 DP is the statistical average of the VH measured by the oscilloscope The crossing point must meet the absolute and relative crossing point specifications simultaneously Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK 0 1 DN is equal to the falling Intel Xeon Processor 5 2400 v2 Product Family Vuavg Can be measured directly using Vtop on Agilent and High on Tektronix oscilloscopes Veross is defined as the total variation of all crossing voltages as defined in Note 3 The rising edge of BCLK 0 1 _DN is equal to the falling edge of BCLK 0 1 DP 146 Datasheet Volume One 8 For Vin between 0 and Vih Table 7 18 SMBus DC Specifications
181. ble 8 2 Land Number Sheet 26 of 37 Land T Direction Meal Land Name ri Direction F18 DDR2 MA 10 SSTL 1 DDR1 ODT 3 SSTL 19 VCCD PWR G14 DDR2 CS N 1 SSTL 2 DDR3_DQS_DN 05 SSTL 15 DDR1_ODT 0 SSTL 0 F20 DDR2_CLK_DP 2 SSTL G16 DDR2 CS SSTL 21 DDR2_CLK_DN 3 SSTL G17 VCCD PWR F22 DDR2 CLK DP 3 SSTL G18 DDR2 BA 1 SSTL 23 DDR2 MA 04 SSTL 19 DDR1 SSTL 0 F24 VCCD PWR G2 DDR3 DQ 43 SSTL 25 DDR2_MA 12 SSTL G20 DDR2 CLK DNI 2 SSTL 26 DDR2 BA 2 SSTL G21 DDR2 CLK DP 1 SSTL 27 VSS GND G22 VCCD PWR F28 VSS GND G23 DDR2 MA 03 SSTL F29 VSS GND G24 DDR2 71 SSTL F3 DDR3 001461 SSTL 1 0 G25 DDR2_PAR_ERR_N SSTL VSS GND G26 DDR2 MA 15 SSTL 1 VSS GND G27 DDR1 ECC 3 SSTL 2 VSS GND G28 DDR1_ECC 7 SSTL F33 VSS GND G29 DDR1 DQS DP 08 SSTL 4 DDR2_ECC 1 SSTL G3 DDR3 DQ 47 SSTL F35 VSS GND G30 DDR1 DQS DN 17 SSTL F36 VSS GND G31 DDR1 ECC 1 SSTL 7 VSS GND G32 DDR1 ECC 0 SSTL 8 VSS GND G33 VSS GND F39 VSS GND G34 VSS GND F4 VSS GND G35 VSS GND F40 VSS GND G36 DDR2_DQ 19 SSTL 41 DDR3_DQ 24 SSTL G37 DDR2_DQ 23 SSTL 42 DDR3_DQ 28 SSTL G38 DDR2 DQS DP 02 SSTL F43 DDR3_DQ 29 SSTL G39 DDR2 DQS DN 02 SSTL 5 55 GND G4 VSS GND F6 VSS GND G40 TEST3 7 VSS GND G41 VSS GND F8 VSS GND G42 VSS GND F9 VSS GND G43 VSS GND G1 DDR3_D
182. cal WrPCI ConfigLocal 4 Ping GetDIB GetTemp WrPkgConfig RdPkgConfig RdIAMSR RdPCI ConfigLocal WrPCI ConfigLocal RdPCI Config Intel Xeon Processor E5 2400 v2 Product Family 32 Datasheet Volume One Table 2 2 2 5 2 3 2 5 2 3 1 Figure 2 8 intel Minor Revision Number Meaning Minor Revision Supported Command Suite 5 Ping GetDIB GetTemp WrPkgConfig RdPkgConfig AMSR RdPCI ConfigLocal WrPCI ConfigLocal RdPCIConfig WrPCIConfig 6 Ping GetDIB GetTemp WrPkgConfig RdPkgConfig AMSR RdPCI ConfigLocal WrPCI ConfigLocal RdPCIConfig WrPCIConfig Wrl AMSR For the processor PECI client that is designed to meet the RS Platform Environment Control Interface PECI Specification Rev 3 0 the Revision Number it returns will be 0011 0100b GetTemp The GetTemp command is used to retrieve the die temperature from a target address The temperature is used by the external thermal management system to regulate the temperature on the die The data is returned as a negative value representing the number of degrees Celsius below the processor DTS temperature Tprochot at which PROCHOT_N asserts The PECI temperature value of zero corresponds to This also represents the minimum temperature at which the processor Thermal Control Circuit activates The actual value that the thermal
183. ce In general for the purposes of DRAM RAPL the DRAM power management entity should use PECI accesses to DRAM energy and performance status in conjunction with the power limiting feature to budget power between the various memory sub systems in the server system Intel Xeon Processor E5 2400 v2 Product Family 44 Datasheet Volume One Figure 2 20 DRAM Power Limit Performance Data Accumulated DRAM Throttle Time DRAM Power Limit Performance 2 5 2 6 11 CPU Thermal and Power Optimization Capabilities Table 2 8 provides a summary of the processor power and thermal optimization capabilities that can be accessed over PECI Note The I ndex values referenced in Table 2 8 are in decimal format Table 2 8 also provides information on alternate inband mechanisms to access similar or equivalent information for register reads and writes where applicable The user should consult the appropriate Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers for exact details on MSR or CSR register content Table 2 8 RdPkgConfig amp WrPkgConfig CPU Thermal and Power Optimization Services Summary Sheet 1 of 4 Parameter RdPkgConfig wrPkgConfig Alternate Index Value Data 0 Service Value word dword Data Description MSR or CSR decimal dword Access Package 00 0
184. cessor 1 Signal Quality Specifications Signal Quality specifications for PCle Signals are included as part of the PCIe DC specifications and PCle AC specifications Various scenarios have been simulated to generate a set of layout guidelines which are available in the Platform Design Guide PDG Intel QuickPath nterconnect Signal Quality Specifications Signal Quality specifications for Differential Intel QuickPath Interconnect Signals are included as part of the Intel QuickPath Interconnect defined in the Intel QuickPath Interconnect V1 1 Base Electrical Specification and Validation Methodologies Various scenarios have been simulated to generate a set of layout guidelines which are available in the Platform Design Guide PDG Input Reference Clock Signal Quality Specifications Overshoot Undershoot and Ringback specifications for BCLK 0 1 D N P found in Table 7 23 Overshoot Undershoot and Ringback specifications for the DDR3 Reference Clocks are specified by the DIMM Overshoot Undershoot Tolerance Overshoot or undershoot is the absolute value of the maximum voltage above or below Vss see Figure 7 12 The overshoot undershoot specifications limit transitions beyond Vss due to the fast signal edge rates The processor can be damaged by single and or repeated overshoot or undershoot events any input output buffer if the charge is large enough that is if the over undershoot is
185. characteristics The units for the DRAM Power Limit and Control Time Window are determined as per the Package Power SKU Unit settings described in Section 2 5 2 6 11 The DRAM Power Limit Enable bit in Figure 2 19 should be set to activate this feature Exact DRAM power limit values are largely determined by platform memory configuration As such this feature is disabled by default and there are no defaults associated with the DRAM power limit values The PECI host may be used to enable and initialize the power limit fields for the purposes of DRAM power budgeting Alternatively this can also be accomplished through inband writes to the appropriate registers Both power limit enabling and initialization of power limit values can be done Intel Xeon Processor E5 2400 v2 Product Family 43 Datasheet Volume One intel in the same command cycle All RAPL parameter values including the power limit value control time window and enable bit will have to be specified correctly even if the intent is to change just one parameter value when programming over PECI The following conversion formula should be used for encoding or programming the Control Time Window in bits 23 17 Control Time Window in seconds 1 0 25 x 2Y z where integer value of bits 23 22 y integer value of bits 21 17 7 Package Power SKU Time Unit 19 16 see Section 2 5 2 6 13 for details on Package Power SKU Unit For exampl
186. cy For example it may reduce the number of active phases transition from CCM Continuous Conduction Mode to DCM Discontinuous Conduction Mode mode reduce the switching frequency or pulse skip or change to asynchronous regulation For example typical power states are 00h run in normal mode a command of O1h shed phases mode and an 02h pulse skip The VR may reduce the number of active phases from PS 00h to PS O1h or PS 00h to PS 02h for example There are multiple VR design schemes that can be used to maintain a greater efficiency in these different power states please work with your VR controller suppliers for optimizations The SetPS command sends a byte that is encoded as to what power state the VR should transition to If a power state is not supported by the controller the slave should acknowledge with command rejected 11b Note the mapping of power states 0 will be detailed in the VR12 IMVP7 Pulse Width Modulation Specification If the VR is in a low power state and receives a SetVID command moving the VID up then the VR exits the low power state to normal mode 50 to move the voltage up as fast as possible The processor must re issue low power state PS1 or 52 command if it is in a low current condition at the new higher voltage See Figure 7 2 for VR power state transitions Intel Xeon Processor E5 2400 v2 Product Family 129 Datasheet Volume One Electrical Specifications Figure 7 2 VR Power Stat
187. d by the processor Downstream System Management Interrupt SMI SCI and SERR error indication Static lane numbering reversal support Supports DMI2 virtual channels VCO VC1 VCm and VCp 1 2 4 I ntel QuickPath nterconnect ntel Compliant with Intel QuickPath Interconnect v1 1 standard packet formats Implements a full width Intel QuickPath Interconnect port Full width port includes 20 data lanes and 1 clock lane 64 byte cache lines Isochronous access support for Quality of Service QoS native 2 socket platforms only Home snoop based coherency 4 bit Node ID 46 bit physical addressing support No Intel QuickPath Interconnect bifurcation support Differential signaling Forwarded clocking Up to 8 0 GT s data rate up to 16 GB s direction peak bandwidth per port All ports run at same operational frequency Reference Clock is 100 MHz Slow boot speed initialization at 50 MT s Common reference clocking same clock generator for both sender and receiver Intel Interconnect Built In Self Test Intel IBIST for high speed testability Polarity Inversion and Lane reversal Rx side only 1 2 5 Platform Environment Control nterface The PECI is a one wire interface that provides a communication channel between a PECI client the processor and a PECI master the PCH The PECI interface is based on revision 3 0 of the RS Platform Environment Control Interface PECI Specification Ref
188. definition is generic and more advanced response policies may be employed at the discretion of the originator developer Originator Response Guidelines Response After 1 Attempt After 3 Attempts Bad FCS Retry Fail with PECI client device error Abort FCS Retry Fail with PECI client device error if command was not illegal or malformed CC 0x8x Retry The PECI client has failed in its attempts to generate a response Notify application layer CC 0x9x Abandon any further n a attempts and notify application layer None all 05 Force bus idle drive Fail with PECI client device error Client may not be alive or may be low for 1mS and retry otherwise unresponsive for example it could be in RESET CC Ox4x Pass n a Good FCS Pass n a DTS Temperature Data Format The temperature is formatted in a 16 bit 2 5 complement value representing a number of 1 64 degrees Celsius This format allows temperatures in a range of 512 C to be reported to approximately a 0 016 C resolution Figure 2 50 Temperature Sensor Data Format MSB MSB LSB LSB Upper nibble Lower nibble Upper nibble Lower nibble S x x 5 Integer Value 0 511 Fractional Value 0 016 Intel Xeon Processor E5 2400 v2 Product Family 75 Datasheet Volume One intel The resolution of the processor s Digital Th
189. details on sensor errors GetTemp Response Definition Response Meaning General Sensor Error GSE Thermal scan did not complete in time Retry is appropriate Bad Write FCS Electrical error Abort FCS Illegal command formatting mismatched RL WL Command Code 0 00001 Processor is running at its maximum temperature or is currently being reset All other data Valid temperature reading reported as a negative offset from Tprochot Notes 1 This response will be reflected in Bytes 5 amp 6 in Figure 2 9 RdPkgConfig The RdPkgConfig command provides read access to the package configuration space PCS within the processor including various power and thermal management functions Typical PCS read services supported by the processor may include access to temperature data energy status run time information DIMM temperatures and so on Refer to Section 2 5 2 6 for more details on processor specific services supported through this command Command Format The RdPkgConfig format is as follows Write Length 0x05 Read Length 0x05 dword Command 1 Description Returns the data maintained in the processor package configuration space for the PCS entry as specified by the index and parameter fields The index field contains the encoding for the requested service and is used in conjunction with the parameter field to specify the exact data being requested The Read Length dicta
190. e that is processor voltage remains within specification Please see the applicable platform design guide for implementation details VSA SENSE VSS VSA SENSE VSA SENSE and VSS VSA SENSE provide an isolated low impedance connection to the processor system agent VSA power plane These signals must be connected to the voltage regulator feedback circuit which insures the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details SENSE VSS SENSE SENSE and VSS VITD SENSE provide an isolated low impedance connection to the processor 1 power plane These signals must be connected to the voltage regulator feedback circuit which insures the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details VCCD Variable power supply for the processor system memory interface Provided by two VRM EVRD 12 0 compliant regulators per CPU Socket VCCD is used for memory channels 1 2 amp 3 The valid voltage of this supply 1 50V or 1 35V is configured by BIOS after determining the operating voltages of the installed memory Note The processor must be provided VCCD for proper operation even in configurations where no memory is populated A VRM EVRD 12 0 controller is recommended but not required VCCPLL Fixed power s
191. e using this formula a control time value of will correspond to a 1 second time window A valid range for the value of the Control Time Window in Figure 2 19 that can be programmed into bits 23 17 is 250 mS 40 seconds From a DRAM power management standpoint all post boot DRAM power management activities also referred to as DRAM RAPL or DRAM Running Average Power Limit should be managed exclusively through a single interface like PECI or alternatively an inband mechanism If PECI is being used to manage DRAM power budgeting activities BIOS should lock out all subsequent inband DRAM power limiting accesses by setting bit 31 of the DRAM POWER LIMIT MSR or DRAM PLANE POWER LIMIT CSR to 1 Figure 2 19 DRAM Power Limit Data 31 16 15 14 Control Time PRAN RESERVED RESERVED Power Limit DRAM Power Limit Window Enable 24 23 17 0 DRAM_POWER_LIMIT Data 2 5 2 6 10 DRAM Power Limit Performance Status Read This service allows the PECI host to assess the performance impact of the currently active DRAM power limiting modes The read return data contains the sum of all the time durations for which each of the DIMMs has been operating in a low power state This information is tracked by a 32 bit counter that wraps around The unit for time is determined as per the Package Power SKU Unit settings described in Section 2 5 2 6 11 The DRAM performance data does not account for stalls on the memory interfa
192. e 7 5 for further details 7 1 4 Intel QuickPath Interconnect Intel The processor provides one Intel port for high speed serial transfer between other processors The port consists of two uni directional links for transmit and receive A differential signaling scheme is utilized which consists of opposite polarity DP DN signal pairs Intel Xeon Processor E5 2400 v2 Product Family 124 Datasheet Volume One 7 1 5 7 1 5 1 Figure 7 1 7 1 6 Platform Environmental Control I nterface PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices The processor contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read processor temperature perform processor manageability functions and manage processor interface tuning and diagnostics Please refer to Section 2 5 Platform Environment Control Interface PECI for processor specific implementation details for PECI Generic PECI specification details are out of the scope of this document and can be found in RS Platform Environment Control Interface P
193. e Transitions PS1 PS2 7 1 9 3 6 SVID Voltage Rail Addressing The processor addresses 4 different voltage rail control segments within VR12 VCC VCCD and VSA The SVID data packet contains a 4 bit addressing code Table 7 2 SVID Address Usage PWM Address HEX Processor 00 01 02 Vccp 03 N A 04 N A 05 N A Notes 1 Check with VR vendors for determining the physical address assignment method for their controllers 2 addressing is assigned on a per voltage rail basis 3 Dual VR controllers will have two addresses with the lowest order address always being the higher phase count 4 For future platform flexibility the VR controller should include an address offset as shown with 1 not used Table 7 3 VR12 0 Reference Code Voltage dentification VI D Table Sheet 1 of 2 VCC VSA VCC VSA VCC VSA VCC VSA VSA VCC VSA wecp wecp HEX HEX veco 00 0 00000 55 0 67000 78 0 84500 9B 1 02000 BE 1 19500 1 1 37000 33 0 50000 56 0 67500 79 0 85000 9c 1 02500 BF 1 20000 E2 1 37500 34 0 50500 57 0 68000 7A 0 85500 9D 1 03000 CO 1 20500 E3 1 38000 35 0 51000 58 0 68500 7B 0 86000 9E 1 03500 C1 1 21000 E4 1 38500 36 0 51500 59 0 69000 7 0 86500 9F 1 04000 C2 1 21500 E5 1 39000 37 0 52000 5A 0 69500 7D 0 87000 1 04500 1 22000 1 39500
194. e Unified Backplate Assembly The URS spring captive in the heatsink provides the necessary compressive load for the thermal interface material For specific design details on the URS and the Unified Backplate please refer to the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG All components of the URS heat sink solution will be captive to the heat sink and will only require a Phillips screwdriver to attach to the Unified Backplate Assembly When installing the URS the screws should be tightened until they will no longer turn easily This should represent approximately 8 inch pounds of torque More than that may damage the retention mechanism components Fan Power Supply STS100C and STS1OOA The 4 pin PWM controlled thermal solution is being offered to help provide better control over pedestal chassis acoustics This is achieved through more accurate measurement of processor die temperature through the processor s Digital Thermal Sensors Fan RPM is modulated through the use of an ASIC located on the baseboard that sends out a PWM control signal to the 4th pin of the connector labeled as Control This thermal solution requires a constant 12 V supplied to pin 2 of the active thermal solution and does not support variable voltage control or 3 pin PWM control See Figure 10 13 and Table 10 1 for details on the 4 pin active heat sink solution connectors The fan power header on the baseboard must be positio
195. e between the processor and DIMMs must be connected The SMBus controllers for the system memory interface support the following SMBus protocols commands Random byte Read Byte Write C Write to Pointer Register C Present Pointer Register Word Read C Pointer Write Register Read Refer to the System Management Bus SMBus Specification Revision 2 0 for standing timing protocols and specific command structure details 8 Intel Xeon Processor E5 2400 v2 Product Family 114 Datasheet Volume One Signal Descriptions 6 6 1 Table 6 1 Intel Xeon Processor E5 2400 v2 Product Family Signal Descriptions This chapter describes the processor signals They are arranged in functional groups according to their associated interface or category System Memory Interface Signals Memory Channel DDR1 DDR2 DDR3 Signal Name Description DDR 1 2 3 _BA 2 0 Bank Address Defines the bank which is the destination for the current Activate Read Write or Precharge command DDR 1 2 3 _CAS_N Column Address Strobe DDR 1 2 3 _CKE 3 0 DDR 1 2 3 CLK DN 3 0 DDR 1 2 3 CLK DP 3 0 Clock Enable Differential clocks to the DI MM command and control signals are valid on the rising edge of clock DDR 1 2 3 CS 7 01 Chip Select Each signal selects one rank as the target of the command and address DDR 1 2 3 _DQ 63 00 Data Bus DDR3 Data bits DDR 1 2
196. e dedicated interface to the serial presence DDR SCL C23 detect SPD and thermal sensors TSoD on the DIMMs DDR SCL C1 is used for memory channel 1 while DDR SCL C23 is used for memory channels 2 and 3 DDR SDA C1 SMBus data for the dedicated interface to the serial presence DDR SDA C23 detect SPD and thermal sensors TSoD on the DIMMs DDR SDA is used for memory channel 1 while DDR SDA C23 is used for memory channels 2 and 3 DDR VREFDQRX DDR VREFDQRX C23 Voltage reference for system memory reads DDR VREFDQRX C1 is used for memory channel 1 while DDR VREFDQRX C23 is used for memory channels 2 and 3 DDR VREFDQTX C1 DDR VREFDQTX C23 Voltage reference for system memory writes DDR VREFDQTX C1 is used for memory channel 1 while DDR VREFDQTX C23 is used for memory channels 2 and 3 These signals are not connected and there is no functionality provided on these two signals They are unused by the processor DDR 1 23 _RCOMP 2 0 System memory impedance compensation Impedance compensation must be terminated on the system board using a precision resistor See the Platform Design Guide PDG for implementation details DRAM PWR OK DRAM PWR OK C23 Power good input signal used to indicate that the VCCD power supply is stable for memory channel 1 and channels 2 amp 3 PCI Express Based nterface Signals PCI Express Ports 1 and 3 Signals are receive and transmit differential pai
197. e heat sink solutions exceed a mass of 550 grams Note that this is per processor a dual processor system will have up to 1100 grams total mass in the heat sinks See Section 9 6 for details on the processor mass test Intel Xeon Processor E5 2400 v2 Product Family 203 Datasheet Volume One Boxed Processor Specifications Figure 10 5 Boxed Processor Motherboard Keepout Zones 1 of 4 zm cee s XN LVI LM S amavi ON 2 1 1 30 3015 O33 Q3M3lA SV 72 AN e ANNY 21 RAY SS Wa ID AN oo St SSN NOLLYYOdYOO TELNI 30 1N3SNOO 3063 3H1 145 0390008438 03501050 38 LON S1N31NOO 3943013400 NI 03901050 SI NOU VWHOJNI TILNI SNIVINCO SHL 204 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One Boxed Processor Specifications Figure 10 6 Boxed Processor Motherboard Keepout Zones 2 of 4 SS SS 3H1 JO AsiVWiHd SV Y 2 2 LAA SS SSIS 2 HUNI JO 1N3SNOO 3H1 LDIOHLIA 103131000
198. ed MCERR bit 30 is set if the Intel Xeon Processor E5 2400 v2 Product Family 49 Datasheet Volume One package asserted ERR and bit 31 is set if the package asserted CAT ERR The CAT ERR N may be used to signal the occurrence of a MCERR or IERR Figure 2 26 Machine Check Status 31 30 29 28 0 MCA Error Source Log 2 5 2 6 13 Package Power SKU Unit Read This feature enables the PECI host to read the units of time energy and power used in the processor and DRAM power control registers for calculating power and timing parameters In Figure 2 27 the default value of the power unit field 3 0 is 0011b energy unit 12 8 is 100006 and the time unit 19 16 is 1010b Actual unit values are calculated as shown in Table 2 9 Figure 2 27 Package Power SKU Unit Data 31 20 19 16 15 13 12 8 7 4 3 0 Reserved Time Unit Reserved Energy Unit Reserved Power Unit Table 2 9 Power Control Register Unit Calculations Unit Field Value Calculation Default Value Time 15 2 UNIT 1s 210 976 us Energy 1 2ENERGY UNIT 1J 216 15 3 y Power 1W 2POWER UNIT 1 23 1 8 2 5 2 6 14 Package Power SKU Read This read allows the PECI host to access the minimum Thermal Design Power and maximum power settings for the processor package SKU It also returns the maximum time interval or window over which the power can be sustained If the power limiting entity specifies a
199. eeded Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and 32 Architectures Software Developer s Manuals for more detailed information Flit Flow Control Unit The Intel Link layer s unit of transfer 1 Flit 80 bits Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied IMC Integrated Memory Controller System memory controller that is integrated in the processor die The Integrated I O Controller An 1 controller that is integrated the processor die Intel ME Intel Management Engine Intel ME Intel QuickData Technology Intel QuickData Technology is a platform solution designed to maximize the throughput of server data traffic across a broader range of configurations and server environments to achieve faster scalable and more reliable 1 0 Intel QuickPath Interconnect Intel A cache coherent link based Interconnect specification for In
200. el Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 189 Processor Land Listing tel Table 8 2 Land Number Sheet 31 of 37 Table 8 2 Land Number Sheet 32 of 37 Med ut Land Name T Direction mb Land Name ri Direction L3 DDR3 DQS DN 15 SSTL 25 VTTD PWR L30 DDR1 DQS DP 12 SSTL M26 VTTD PWR L31 DDR1_DQ 24 SSTL 27 55 GND L32 DDR1_DQ 28 SSTL 1 0 M28 VSS GND L33 DDR1_DQ 19 SSTL 29 VTTD PWR L34 DDR1 DQS DP 11 SSTL M3 DDR3_DQ 50 SSTL 135 DDR1_DQ 21 SSTL VTTD PWR L36 DDR1_DQ 20 SSTL 31 VTTD PWR L37 VSS GND M32 VSS GND L38 DDR23_RCOMP 2 Analog M33 vss GND L39 VSS GND M34 VSS GND L4 VSS GND M35 VSS GND L40 VSS GND M36 DDR_VREFDQRX_C23 DC 141 DDR3_DQ 21 SSTL 37 VSS GND L42 DDR3_DQ 17 SSTL M38 DDR2_DQ 10 SSTL 143 DDR3_DQ 16 SSTL 9 DDR2_DQ 11 SSTL 15 DDR1_DQ 35 SSTL M4 DDR1_RCOMP 2 Analog L6 DDR1 DQ 39 SSTL 40 VSS GND L7 DDR1 DQS DP 04 SSTL M41 DDR3_DQ 20 SSTL 18 DDR1 005 DN 13 SSTL 42 55 GND 19 DDR1_DQ 33 SSTL M43 VSS GND M1 DDR3_DQ 55 SSTL 5 55 GND M10 VSS GND M6 VSS GND M11 VSS GND M7 VSS GND M12 RSVD M8 VSS GND M13 VSS GND M9 VSS GND M14 VTTD PWR 1 VSS GND M15
201. el Xeon Processor E5 2400 v2 Product Family 26 Datasheet Volume One Interfaces 2 2 2 2 3 Note 2 3 1 2 3 2 2 3 3 intel PCI Express Configuration Mechanism The PCI Express link is mapped through a PCI to PCI bridge structure PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the Conventional PCI Specification PCI Express configuration space is divided into a PCI compatible region which consists of the first 256 bytes of a logical device s configuration space and an extended PCI Express region which consists of the remaining configuration space The PCI compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section The PCI Express Host Bridge is required to translate the memory mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles To maintain compatibility with PCI configuration addressing mechanisms it is recommended that system software access the enhanced configuration space using 32 bit operations 32 bit aligned only See the PCI Express Base Specification for details of both the PCI compatible and PCI Express Enhanced configuration mechanisms and transaction rules DMI 2 PCI Express Interface Direct Media In
202. el 55 4 Existing Intel amp SSE applications library can Run unmodified and benefit from processor enhancements Recompile existing Intel amp SSE intrinsic using compilers that generate Intel AVX code nter operate with library ported to Intel AVX Applications compiled with Intel AVX can inter operate with existing Intel SSE libraries 3 10 I ntel Dynamic Power Technology Intel amp Dynamic Power technology Memory Power Management is a platform feature with the ability to transition memory components into various low power states based on workload requirements The Intel Xeon processor E5 2400 v2 product family based platform supports Dynamic CKE hardware assisted and Memory Self Refresh software assisted For further details refer to the ACPI Specifications for Memory Power Management document Intel Xeon Processor E5 2400 v2 Product Family 84 Datasheet Volume One intel 4 This chapter provides information on the following power management topics e ACPI States System States Processor Core Package States Integrated Memory Controller and System Memory States Direct Media Interface Gen 2 DMI2 PCI Express Link States Intel QuickPath Interconnect States 4 1 ACPI States Supported The ACPI states supported by the processor are described in this section 4 1 1 System States Table 4 1 Syst
203. em States State Description G0 S0 Full On G1 S3 Cold Suspend to RAM STR Context saved to memory 1 54 Suspend to Disk STD All power lost except wakeup PCH G2 S5 Soft off All power lost except wakeup on PCH Total reboot G3 Mechanical off All power removed from system 4 1 2 Processor Package and Core States Table 4 2 lists the package C state support as 1 the shallowest core C state that allows entry into the package C state 2 the additional factors that will restrict the state from going any deeper and 3 the actions taken with respect to the Ring Vcc PLL state and LLC Table 4 3 lists the processor core C states support Table 4 2 Package C State Support Sheet 1 of 2 Package Core Limiting Fact Retention and Len N i C State States PLL Off t otas Flushed PCO 2 2 CC3 CC6 PCle PCH and Remote Socket VccMin No 2 Snoopable Snoops Freq MinFreq Idle PCle PCH and Remote Socket PLL ON Accesses Interrupt response time requirement DMI Sidebands Configuration Constraints Intel Xeon Processor E5 2400 v2 Product Family 85 Datasheet Volume One Table 4 2 Package C State Support Sheet 2 of 2 Package Core Limiting Factors bod Notes C State States PLL Off Flushed PC3 Light at least Core C state reten
204. eon Processor E5 2400 v2 Product Family 200 Datasheet Volume One Boxed Processor Specifications n tel Figure 10 1 STS100C Passive Active Combination Heat Sink with Removable Fan 10 1 3 Intel Thermal Solution STS100A Active Heat Sink Solution The STS100A in the active fan configuration is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present see Figure 10 3 The STS100A with the fan removed as with any passive thermal solution will require the use of chassis ducting and is targeted for use in rack mount or ducted pedestal servers The retention solution used for these products is called Unified Retention System URS The STS100C and STS100A utilize a fan capable of 4 pin pulse width modulated PWM control Use of a 4 pin PWM controlled active thermal solution helps customers meet acoustic targets in pedestal platforms through the baseboard s ability to directly control the RPM of the processor heat sink fan See Section 10 3 for more details on fan speed control Also see Section 2 5 Platform Environment Control Interface PECI for more Intel Xeon Processor E5 2400 v2 Product Family 201 Datasheet Volume One Boxed Processor Specifications tel on the PWM and interface along with Digital Thermal Sensors DTS Figure 10 3 STS100A Active Heat Sink 10 1 4 Intel Thermal Solution STS100P Boxed 25 5 mm T
205. eon processor Intel 22 nm processor design follow on to the 32 nm design Intel Xeon E5 2400 v2 product family processor E5 2400 product family Integrated Heat Spreader A component of the processor package used to enhance the thermal IHS performance of the package Component thermal solutions interface with the processor at the IHS surface Jitter Any timing variation of a transition edge or edges from the defined Unit I nterval UI Virtualization LGA1356 Socket The 1356 land FCLGA package mates with the system board through this surface mount 1356 contact socket LLC Last Level Cache LRDIMM Load Reduced Dual In line Memory Module NCTF Non Critical to Function NCTF locations are typically redundant ground or non critical reserved so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality NEBS Network Equipment Building System NEBS is the most common set of environmental design guidelines applied to telecommunications equipment in the United States PCH Platform Controller Hub The next generation chipset with centralized platform capabilities including the main 1 0 interfaces along with display connectivity audio features power management manageability security and storage features PCU Power Control Unit PCI Express 3 0 PCI Express Generation 3 0 The third generation PCI Express specification that operates at twice the speed of Expre
206. er dissipation Table 5 1 provides the PSIcA and T parameters that define thermal profile for each TDP Core count combination Figure 5 1 illustrates the general form of the resulting linear graph resulting from Tcase PSlca P Tja Table 5 1 Case Temperature Thermal Specifications Core 8 E Minimum Maximum Count Tra COD C Tease C 95 10 8 52 6 0 289 5 0 80 0 80 6 4 51 7 0 303 5 0 76 0 80 1S 4 2 50 5 0 268 5 0 72 0 60 10 51 0 0 283 5 0 68 0 Intel Xeon Processor E5 2400 v2 Product Family 101 Datasheet Volume One 5 1 Figure 5 1 5 1 3 3 Case Temperature Thermal Specifications Core Minimum Maximum TOP W Count C 5 C W Tcase C Tease C 60 6 51 0 0 301 5 0 69 0 Case Temperature Thermal Profile T CaseMax Tcase T case PSI Power W Digital Thermal Sensor DTS thermal profiles Each DTS thermal profile is unique to each TDP and core count combination These Tpts profiles are fully defined by the simple linear equation PSlpA P Where PSI pa is the Processor to Ambient thermal resistance of the processor thermal solution is the Local Ambient temperature P is the processor power dissipation Table 5 2 provides the 51 parameters that define Tprs thermal profile for each TDP Core c
207. er is unimplemented even with a passing completion code Alternatively reads to unimplemented registers may return a completion code of 0x90 indicating an invalid request Responses will follow normal PCI protocol PCI configuration addresses are constructed as shown in Figure 2 44 Under normal in band procedures the Bus number would be used to direct a read or write to the proper device Actual PCI bus numbers for all PCI devices including the PCH are programmable by BIOS The bus number for PCH devices may be obtained by reading the CPUBUSNO CSR Refer to the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers document for details on this register Figure 2 44 PCI Configuration Address 31 28 27 20 19 15 14 12 11 0 Reserved Bus Device Function Register PCI configuration reads may be issued in byte word or dword granularities 2 5 2 8 1 Command Format The RdPCI Config format is as follows Write Length 0x06 Read Length 0x05 dword Command 0x61 Description Returns the data maintained in the PCI configuration space at the requested PCI configuration address The Read Length dictates the desired data return size This command supports only dword responses with a completion code on the Intel Xeon Processor E5 2400 v2 Product Family 63 Datasheet Volume One intel processor PECI clients All command responses are prepended with a completion code
208. er to Section 2 5 Platform Environment Control Interface PECI for additional details on PECI services available in the processor Supports operation at up to 2 Mbps data transfers Link layer improvements to support additional services and higher efficiency over PECI 2 0 generation Services include CPU thermal and estimated power information control functions for power limiting P state and T state control and access for Machine Check Intel Xeon Processor E5 2400 v2 Product Family 18 Datasheet Volume One M intel Architecture registers and PCI configuration space both within the processor package and downstream devices PECI address determined by SOCKET ID configuration Single domain Domain 0 is supported 1 3 Power Management Support 1 3 1 Processor Package and Core States ACPI C states as implemented by the following processor C states Package PC2 PC6 Package C7 is not supported Core CC1 CC3 CC6 Processor Core C7 is not supported Enhanced Intel SpeedStep Technology 1 3 2 System States Support 50 S1 53 S4 55 1 3 3 Memory Controller Multiple CKE power down modes Multiple self refresh modes Memory thermal monitoring via MEM HOT C1 N and MEM HOT C23 N Signals 1 3 4 PCI Express 105 is not supported L1 ASPM power management capability 1 3 5 Intel 105 is not supported 10 and L1 power manage
209. ermal Sensor DTS is approximately 1 C which be confirmed by RDMSR from the 2 STATUS MSR where it is architecturally defined The MSR read will return only bits 13 6 of the temperature sensor data defined in Figure 2 50 temperatures are sent through a configurable low pass filter prior to delivery in the GetTemp response data The output of this filter produces temperatures at the full 1 64 C resolution even though the DTS itself is not this accurate 2 5 7 2 Interpretation Temperature readings from the processor are always negative in a 2 s complement format and imply an offset from the processor Tprochot PECI 0 For example if the processor Tprochot 5 100 C thermal reading of 10 implies that the processor is running at approximately 10 C below Tprochot or 90 C temperature readings are not reliable at temperatures above Tprochot since the processor is outside its operating range and hence PECI temperature readings are never positive The changes in PECI data counts are approximately linear in relation to changes in temperature in degrees Celsius A change of 1 in the PECI count represents roughly a temperature change of 1 degree Celsius This linearity is approximate and cannot be guaranteed over the entire range of PECI temperatures especially as the offset from the maximum PECI temperature zero increases 2 5 7 3 Temperature Filtering The process
210. espect to 0 3 1 4 Vss Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied Intel Xeon Processor E5 2400 v2 Product Family 137 Datasheet Volume One Electrical Specifications tel 7 7 1 2 Overshoot undershoot voltage guidelines for input output I O signals are outlined in Section 7 9 5 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor Storage Condition Specifications Environmental storage condition limits define the temperature and relative humidity limits to which the device is exposed to while being stored in a Moisture Barrier Bag The specified storage conditions are for component level prior to board attach see notes in Table 7 10 for post board attach limits Table 7 10 specifies absolute maximum and minimum storage temperature limits which represent the maximum or minimum device condition beyond which damage latent or otherwise may occur The table also specifies sustained storage temperature relative humidity and time duration limits These limits specify the maximum or minimum device storage conditions for a sustained period of time At conditions outside sustained limits but within absolute maximum and minimum ratings quality amp reliability may be affected Table 7 10 Storage Condition Ratings 7 8 Symbol Parameter Min Max Unit
211. essor E5 2400 v2 Product Family Datasheet Volume One Signal Descriptions 6 4 Table 6 7 Table 6 8 6 5 Table 6 9 6 6 Intel QuickPath Interconnect Signals Intel QPI Port Signals Signal Name Description Reference Clock Differential Input These pins provide the PLL reference clock differential input The Intel forward clock frequency is half the Intel data rate Reference Clock Differential Output These pins provide the PLL reference clock differential input The Intel QPI forward clock frequency is half the Intel data rate QPI_DRX_DN DP 19 00 Intel Receive data input QPI_DTX_DN DP 19 001 Intel QPI Transmit data output Intel QPI Miscellaneous Signals Signal Name QPI_RBIAS Description This input is used to control Intel bias currents QPI_RBIAS is required to be connected as if the link is being used even when QPI is not used Refer to the Platform Design Guide PDG for further details RBIAS SENSE Provides dedicated bias resistor sensing to minimize the voltage drop caused by packaging and platform effects RBIAS SENSE is required to be connected as if the link is being used even when Intel QPI is not used Refer to the Platform Design Guide PDG for further details VREF CAP Intel voltage reference used to measu
212. evices or determine if a device has been removed been powered off etc A Ping sent to a device address always returns a non zero Write FCS if the device at the targeted address is able to respond Command Format The Ping format is as follows Write Length 0x00 Read Length 0x00 Intel amp Xeon Processor E5 2400 v2 Product Family 30 Datasheet Volume One Figure 2 3 Ping Byte 0 1 2 3 Write Length Read Length 0x00 0x00 pes Byte Client Address Definition An example Ping command to PECI device address 0x30 is shown below Figure 2 4 Ping Example Byte 0 1 2 3 Definition 2 5 2 2 GetDI B The processor PECI client implementation of GetDIB includes an 8 byte response and provides information regarding client revision number and the number of supported domains All processor clients support the GetDIB command 2 5 2 2 1 Command Format The B format is as follows Write Length 0x01 Read Length 0x08 Command 7 Figure 2 5 GetDIB Byte Write Length Read Length Cmd Code Definition Revision 10 11 12 13 Intel Xeon Processor E5 2400 v2 Product Family 31 Datasheet Volume 2 5 2 2 2 Figure 2 6 2 5 2 2 3 Figure 2 7 Table 2 2 intel The Device Info byte gives details regarding the PECI client configuration At a minimum all clients supporting GetDIB will return the number of domains inside the package via
213. for PO or turbo The PCU will use the 2 ENERGY PERFORMANCE BIAS register settings to determine the exact extent of turbo Any OS p state request that is equal to or below what is specified in the PECI ACPI P T Notify will be granted as long as the RAPL power limit does not impose a lower p state However turbo will not be enabled in this instance even if there is headroom between the processor energy consumption and the RAPL power limit This feature does not affect the Thermal Monitor behavior of the processor nor is it impacted by the setting of the power limit clamp mode bit Figure 2 39 ACPI P T Notify Data 31 8 7 0 Reserved New state ACPI P T Notify Data 2 5 2 6 30 Caching Agent TOR Read This feature allows the PECI host to read the Caching Agent Cbo Table of Requests TOR This information is useful for debug in the event of a 3 strike timeout that results in a processor IERR assertion The 16 bit parameter field is used to specify the Cbo index TOR array index and bank number according to the following bit assignments Bits 1 0 Bank Number legal values from 0 to 2 Bits 6 2 TOR Array Index legal values from 0 to 19 Bits 10 7 Cbo Index legal values from 0 to 7 Bit 11 Read Mode should be set to 0 for TOR reads 1 for Core ID reads Bits 15 12 Reserved Intel Xeon Processor E5 2400 v2 Product Family 58 Datasheet Volume One Figure 2 40 2 5 2 6 31
214. fresh state Power may be removed from the memory controller core at this point But Vccp supply 1 5 V or 1 35 V to the DDR IO must be maintained 4 3 2 2 Self Refresh Exit Self refresh exit can be either a message from an external unit PCU in most cases but also possibly from any message channel master or as reaction for an incoming transaction Here are the proper actions on self refresh exit CK is enabled and four CK cycles driven When proper skew between Address Command and CK are established assert CKE e Issue NOPs for tXSRD cycles ssue ZQCL to each rank The global scheduler will be enabled to issue commands 4 3 2 3 DLL and PLL Shutdown Self refresh according to configuration may be a trigger for master DLL shut down and PLL shut down The master DLL shut down is issued by the memory controller after the DRAMs have entered self refresh The PLL shut down and wake up is issued by the PCU The memory controller gets a signal from PLL indicating that the memory controller can start working again 4 3 3 DRAM 1 Power Management Unused signals are tristated to save power This includes all signals associated with an unused memory channel The 1 buffer for an unused signal should be tristated output driver disabled the input receiver differential sense amp should be disabled The input path must be gated to prevent spurious results due to noise on the unused signals typically handled automatically when input receive
215. fy the processor power control unit PCU device when combined with the Vendor Identification register content and remains constant across all SKUs Refer to the appropriate register description for the exact processor PCU Device ID value Figure 2 23 PCU Device ID 31 16 15 0 RESERVED PCU Device ID PCU Device ID Data Max Thread ID The maximum Thread ID data provides the number of supported processor threads This value is dependent on the number of cores within the processor as determined by the processor SKU and is independent of whether certain cores or corresponding threads are enabled or disabled Figure 2 24 Maximum Thread ID 31 4 3 0 Max Thread ID Reserved Maximum Thread ID Data CPU Microcode Update Revision Reflects the revision number for the microcode update and power control unit firmware updates on the processor sample The revision data is a unique 32 bit identifier that reflects a combination of specific versions of the processor microcode and PCU control firmware Figure 2 25 Processor Microcode Revision 31 0 CPU microcode and PCU firmware revision CPU code patch revision Machine Check Status Returns error information as logged by the MCA Error Source Log register See Figure 2 26 for details The power control unit will assert the relevant bit when the error condition represented by the bit occurs For example bit 29 will be set if the package assert
216. g back any of their contents Note some PLL Intel QuickPath Interconnect and error states are not effected by reset and only PWRGOOD forces them to a known state RSVD RESERVED All signals that are RSVD must be left unconnected on the board Refer to Section 7 1 10 Reserved or Unused Signals for details SAFE MODE BOOT Safe mode boot Strap SAFE MODE BOOT allows the processor to wake up safely by disabling all clock gating this allows BIOS to load registers or patches if required This signal is sampled after PWRGOOD assertion The signal is pulled down on the die refer to Table 7 6 for details SOCKET 1011 01 Socket ID Strap Socket identification configuration straps for establishing the PECI address Intel amp QPI Node ID and other settings This signal is used in combination with FRMAGENT to determine whether the socket is a legacy socket bootable firmware agent is present and DMI links are used PCle mode instead of DMI2 mode Each processor socket consumes one Node ID and there are 128 Home Agent tracker entries This signal is pulled down on the die refer to Table 7 6 for details For further details see Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers TEST 4 0 Test 4 0 must be individually connected to an appropriate power Source or ground through a resistor for proper processor operation Refer to the Platform Design Guide PDG for additional impleme
217. ge Drawing Sheet 2 of 2 tats 555556 5 555056555555 555555556 5 555555555556 WOO 50 QUO WOOO 5 tate 555555959 5952529 wi NON 55555996 555255555555 tat 55555555555 e 9090909 959090909 5555 555555556 5995595006 555555555 555559 SIGHS SCS Rs C 9590909 5555555 ese oe 552 OOOOOOOOOOQO Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 197 Package Mechanical Specifications l n tel 9 2 Processor Component Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Do not contact the Test Pad Area with conductive material Decoupling capacitors are typically mounted to either the topside or land side of the package substrate See Figure 9 2 through Figure 9 3 for keep out zones The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep in 9 3 Package Loading Specifications Table 9 1 provides load specifications for the processor package These maximum limits should not be exceeded during heatsink assembly shipping conditions or standard use condition E
218. great enough Determining the impact of an overshoot undershoot condition requires knowledge of the magnitude the pulse direction and the activity factor AF Permanent damage to the processor is the likely result of excessive overshoot undershoot Baseboard designs which meet signal integrity and timing requirements and which do not exceed the maximum overshoot or undershoot limits listed in Table 7 23 will insure reliable IO performance for the lifetime of the processor Intel Xeon Processor E5 2400 v2 Product Family 153 Datasheet Volume One Table 7 23 Processor 1 Overshoot Undershoot Specifications intel Signal Group Minimum Maximum Overshoot Undershoot Notes Undershoot Overshoot Duration Duration Intel QuickPath Interconnect 0 2 VIT 1 2 VIT 39 ps 15 ps 1 2 DDR3 0 2 Vccp 1 2 Vccp 0 25 Tcu 0 1 1 2 3 System Reference Clock BCLK 0 1 0 3V 1 15V N A N A 1 2 PWRGOOD Signal 0 420V VTT 0 28 N A N A 4 Notes 1 These specifications are measured at the processor pad 2 Refer to Figure 7 12 for description of allowable Overshoot Undershoot magnitude and duration 3 is the minimum high pulse width duration 4 For PWRGOOD DC specifications see Table 7 21 7 9 5 1 7 9 5 2 Note 7 9 5 3 Overshoot Undershoot Magnitude Overshoot Undershoot magnitude describes the maximum potential difference between a signal and its voltage reference level F
219. gure 2 18 provides a maximum value for the time window typically a few seconds the minimum value may be assumed to be 100 mS The PCU programs the DRAM power settings described in Figure 2 18 when DRAM characterization has been completed by the memory reference code MRC during boot as indicated by the setting of the RST_CPL bit of the BIOS RESET register The DRAM power settings will be programmed during boot independent of the DRAM Power Limit Enable bit setting Please refer to the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers and Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers for information on memory energy estimation methods and energy tuning options used by BIOS and other utilities for determining the range specified in the DRAM power settings In general any tuning of the power settings is done by polling the voltage regulators supplying the DI MMs Figure 2 18 DRAM Power I nfo Read Data 63 55 54 48 47 46 32 Maximum Time DRAM POWER INFO upper bits 31 30 16 15 14 0 m TDP DRAM Power Minimum DRAM Power Typical Value DRAM POWER INFO lower bits 2 5 2 6 9 DRAM Power Limit Data Write Read This feature allows the PECI host to program the power limit over a specified time or control window for the entire DRAM domain covering all the DIMMs within all the memory channels Actual values are chosen based on DRAM power consumption
220. he processor is a software readable field in the TEMPERATURE_TARGET MSR register that contains the minimum temperature at which the TCC will be activated and PROCHOT_N will be asserted The TCC activation temperature is calibrated on a part by part basis and normal factory variation may result in the actual TCC activation temperature being higher than the value listed in the register TCC activation temperatures may change based on processor stepping frequency or manufacturing efficiencies Adaptive Thermal Monitor The Adaptive Thermal Monitor feature provides an enhanced method for controlling the processor temperature when the processor silicon reaches its maximum operating temperature Adaptive Thermal Monitor uses Thermal Control Circuit TCC activation to reduce processor power via a combination of methods The first method Frequency SVID control involves the processor adjusting its operating frequency via the core ratio multiplier and input voltage via the SVID signals This combination of reduced frequency and voltage results in a reduction to the processor power consumption The second method clock modulation reduces power consumption by modulating starting and stopping the internal processor core clocks The processor intelligently selects the appropriate TCC method to use on a dynamic basis BIOS is not required to select a specific method The Adaptive Thermal Monitor feature must be enabled for the processor to be operating wi
221. heet Volume One The processor core frequency is configured during reset by using values stored within the device during manufacturing The stored value sets the lowest core multiplier at which the particular processor can operate If higher speeds are desired the appropriate ratio can be configured the IA32 MSR MSR 1995 Bits 15 0 For details of operation at core frequencies lower than the maximum rated processor speed refer to the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK 0 1 _DP BCLK 0 1 _DN input with exceptions for spread spectrum clocking DC specifications for the BCLK 0 1 _ DP BCLK 0 1 _DN inputs are provided in Table 7 17 These specifications must met while also meeting the associated signal quality specifications outlined in Section 7 9 Details regarding BCLK 0 1 DP BCLK 0 1 _DN driver specifications are provided in the CK420BQ Clock Synthesizer Driver Specification 7 1 6 1 PLL Power Supply An on die PLL filter solution is implemented on the processor Refer to Table 7 12for DC specifications and to the Platform Design Guide PDG for decoupling and routing guidelines 7 1 7 and Test Access Port TAP Signals Due to the voltage levels supported by other components the TAG and Test Access Port TAP logic Intel
222. ications tel temperature reported over is always a negative value and represents delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT_N see Section 7 Electrical Specifications Systems that implement fan speed control must be designed to use this data Systems that do not alter the fan speed need to guarantee the case temperature meets the thermal profile specifications The processor thermal profiles for planned SKUs are summarized in Section 5 1 3 Thermal profiles ensure adherence to Intel reliability requirements With adherence to the thermal profile it is expected that the Thermal Control Circuit TCC would be activated for very brief periods of time when running the most power intensive applications Additionally utilization of a thermal solution that does not meet this Thermal Profile will violate the thermal specifications and may result in permanent damage to the processor Refer to the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG for details on system thermal solution design thermal profiles and environmental considerations For Embedded Servers Communications and storage markets Intel has plan SKU s that support Thermal Profiles with nominal and short term conditions for products intended for NEBS level 3 thermal excursions For these SKU s operation at either the nominal or short term thermal profiles should result in
223. ides acceptable signal quality across all systematic variations encountered in volume manufacturing This section documents signal quality metrics used to derive topology and routing guidelines through simulation All specifications are specified at the processor die pad measurements Specifications for signal quality are for measurements at the processor core only and are only observable through simulation Therefore proper simulation is the only way to verify proper timing and signal quality Intel Xeon Processor E5 2400 v2 Product Family 152 Datasheet Volume One 7 9 1 7 9 2 7 9 3 7 9 4 7 9 5 DDR3 Signal Quality Specifications Various scenarios for the DDR3 Signals have been simulated to generate a set of layout guidelines which are available in the Platform Design Guide PDG Overshoot or undershoot is the absolute value of the maximum voltage above or below Vss The overshoot undershoot specifications limit transitions beyond specified maximum voltages or due to the fast signal edge rates The processor be damaged by single and or repeated overshoot or undershoot events on any input output or I O buffer if the charge is large enough i e if the over undershoot is great enough Baseboard designs which meet signal integrity and timing requirements and which do not exceed the maximum overshoot or undershoot limits listed in Table 7 23 will insure reliable performance for the lifetime of the pro
224. ifferential SSTL Input Output DDR 1 2 3 _DQS_D N P 17 00 Single ended SSTL Input Output DDR 1 2 3 _DQ 63 00 DDR 1 2 3 _ECC 7 0 SSTL Input DDR 1 2 3 PAR ERR DDR3 Miscellaneous Signals Single ended CMOS1 5v Input DRAM PWR OK 1 23 PCI Express Port 1 amp 3Signals Differential PCI Express Input DI N P 3 0 PE1B D N P 7 4 D N P 3 0 PE3B_RX_D N P 7 4 PE3C RX D N P 11 8 PE3D DIN P 15 12 Differential PCI Express Output 1 TX D N P 3 0 1 TX D N P 7 4 PE3A TX D N P 3 0 PE3B TX D N P 7 4 PE3C TX D N P 11 8 PE3D TX D N P 15 12 PCI Express Miscellaneous Signals Single ended Analog Input PE RBIAS SENSE Reference Input Output PE RBIAS PE VREF CAP DMI 2 PCI Express Signals Differential DMI2 Input DI N P 3 0 2 Output DMI_TX_D N P 3 0 Intel QuickPath Interconnect Intel Signals Differential Intel QPI Input QPI 1 DRX D N P 19 00 QPI1 CLKRX D N P Intel amp QPI Output QPI1 DTX D N P 19 00 QPI1 CLKTX D N P Single ended Analog Input QPI RBIAS SENSE Analog Input Output QPI RBIAS Platform Environmental Control I nterface Single ended PECI PECI System Reference Clock BCLK 0 1 Differential CMOS1 0v Input BCLK 0 1 D N P Intel Xeon Processor E5 2400 v2 Product Family 133 Datasheet Volume One Electrical Specifications Table 7 5 Signa
225. ification for details on this option 9 COMP resistance must be provided on the system board with 1 resistors See the Platform Design Guide PDG for implementation details DDR1_RCOMP 2 0 and DDR23_RCOMP 2 0 resistors are terminated to VSS 10 Input leakage current is specified for all DDR3 signals Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 145 tage of all DIMMs connected to the intel 11 DRAM PWR OK 1 23 must have a maximum of 30 ns rise or fall time over VCCD 0 55 300 mV and 200 mV and the edge must be monotonic 12 The DDR1 23 RCOMP error tolerance is 1596 from the compensated value 13 DRAM PWR OK 1 23 Data Scrambling must be enabled for production environments Disabling Data scrambling can be used for debug and testing purposes only Running systems with Data Scrambling off will make the configuration out of specification For details please reference these documents Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers and the Platform Design Guide PDG Table 7 16 PECI DC Specifications Symbol Definition and Conditions Min Max Units Figure Notes Vin Input Voltage Range 0 150 V Vuysteresis Hysteresis 0 100 V VN Negative edge threshold voltage 0 275 0 500 V V 7 1 2 Vp Positive edge threshold voltage 0 550 0 725 V 7 1 2 l SOURCE High
226. iles Temperature values are specified at VCC MAX for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds MAX at specified CC Please refer to the electrical loadline specifications in Chapter 7 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at specified maximum Tease Power specifications are defined at all VID values found in Table 7 3 The Intel Xeon processor E5 2400 v2 product family may be delivered under multiple VI Ds for each frequency Implementation of a specified thermal profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet the specified thermal profile will result in increased probability of TCC activation and may incur measurable performance loss Refer to the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG for system and environmental implementation details Each case temperature thermal profile is unique to each TDP and core count combination These profiles are fully defined by the simple linear equation TCASE PSI TLA Where 51 is the Case to Ambient thermal resistance of the processor thermal solution is the Local Ambient temperature P is the processor pow
227. in active until the system de asserts PROCHOT_N PROCHOT_N can allow voltage regulator VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on PROCHOT_N as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized thermal solution it is anticipated that PROCHOT_N will be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT_N in the anticipated ambient environment may cause a noticeable performance loss Refer to the appropriate platform design guide and for details on implementing the bi directional PROCHOT_N feature Signal Regardless of whether Adaptive Thermal Monitor is enabled the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP_N definition in Section 6 Signal Descriptions At this point the THERMTRIP_N signal will go active and stay active THERMTRIP_N activation is independent of processor activity and does not generate any Intel QuickPath Interconnect trans
228. in integrated memory controller and functions as described in Table 2 15 Refer to the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers for more details on specific register definitions It also enables writing to processor REUT Robust Electrical Unified Test registers associated with the Intel PCle and DDR3 functions WrPCI ConfigLocal Memory Controller and 110 Device Function Support Bus Device Function Offset Range Description 0000 0 5 0 7 000 FFFh Integrated 1 0 Configuration Registers 0001 15 0 104h 127h Integrated Memory Controller MemHot Registers 0001 15 0 180h 1AFh Integrated Memory Controller SMBus Registers 0001 15 1 080h OCFh Integrated Memory Controller RAS Registers Scrub Spare 0001 104h 18Bh 1F4h 1FFh 16 0 1 4 5 Integrated Memory Controller Thermal Control Registers 0001 16 2 3 6 7 104h 147h Integrated Memory Controller Error Registers 2 5 3 2 5 3 1 Client Management Power up Sequencing The PECI client will not be available when the PWRGOOD signal is de asserted Any transactions on the bus during this time will be completely ignored and the host will read the response from the client as all zeroes client initialization is completed approximately 100 5 after the PWRGOOD assertion This is represented by the start of the Client Data Not Ready DNR phase in Figure 2
229. ine check banks 0 through 19 Information on the exact number of accessible banks for the processor device may be obtained by reading the 2 CAP 7 0 MSR 0x0179 This register may be alternatively read using a RDMSR RBIOS instruction Please consult the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers for more information on the exact number of Intel amp Xeon Processor E5 2400 v2 Product Family 61 Datasheet Volume One Table 2 11 AMSR Services Summary intel cores supported by a particular processor SKU Any attempt to read processor MSRs that are not accessible over PECI or simply not implemented will result in a completion code of 0x90 PECI access to these registers is expected only when in band access mechanisms are not available Processor MSR 5 Processor MSR Processor MSR 10 byte 10 byte gradiens Meaning 10 byte quies Meaning 0x0 OxF 0x0400 2 MCO 0 0 0x041B 1A32_MC6_MISC 0 0 0 0436 1A32_MC13_ADDR 0 0 0 0280 1 32 2 0x0 OxF Ox041C 2 MC7 0x0 OxF 0x0437 2 MC13 MISC 0 0 0 0401 1A32_MCO_STATUS 0x0287 1A32_MC7_CTL2 0 0 0 0438 2 14 0 0 0 0402 2 ADDR 0x0 OxF 0 0410 1 2 MC7 STATUS 0x0 OxF 0x028E 1A
230. ing the function number count in PCle device to support OV devices Improved invalidation architecture End point caching support ATS Interrupt remapping 3 1 4 Intel Virtualization Technology Processor Extensions The processor supports the following Intel VT Processor Extensions features Large Intel VT d Pages Adds 2 MB and 1 GB page sizes to Intel VT d implementations Matches current support for Extended Page Tables EPT Ability to share CPU s EPT page table with super pages with Intel VT d Benefits Less memory foot print for I O page tables when using super pages Potential for improved performance Due to shorter page walks allows hardware optimization for Transition latency reductions expected to improve virtualization performance without the need for VMM enabling This reduces the VMM overheads further and increase virtualization performance 3 2 Security Technologies 3 2 1 Intel Trusted Execution Technology Intel TXT defines platform level enhancements that provide the building blocks for creating trusted platforms Intel Xeon Processor E5 2400 v2 Product Family 79 Datasheet Volume One Technologies 3 2 2 3 2 3 intel The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision The Intel TXT platform determines the identity of the controlli
231. ints for Delta Cross Point 152 7 12 Maximum Acceptable Overshoot Undershoot 156 9 1 Processor Package Assembly Sketch 4 2 194 9 2 Processor Package Drawing Sheet 1 of 2 sss 196 9 3 Processor Package Drawing Sheet 2 Of 2 sssssssssssssssseseme mme 197 9 4 Processor Top Side Markings sse 199 10 1 STS100C Passive Active Combination Heat Sink with Removable Fan 201 10 2 STS100C Passive Active Combination Heat Sink with Fan Removed 201 10 3 STS100A Active Heat 202 10 4 STS100P 25 5 mm Tall Passive Heat SINK 202 Intel Xeon Processor E5 2400 v2 Product Family 8 Datasheet Volume One 10 5 Boxed Processor Motherboard Keepout Zones 1 of 4 204 10 6 Boxed Processor Motherboard Keepout Zones 2 of 4 205 10 7 Boxed Processor Motherboard Keepout Zones 3 of 4 206 10 8 Boxed Processor Motherboard Keepout Zones 4 of 4 207 10 9 Boxed Processor Heat Sink Volumetric 1 of 2 208 10 10 Boxed Processor Heat Sink Volumetric 2 of 2 209 10 11 4 Pin Fan Cable Connector For Active Heat Sink
232. ion EAR N 3 Enable Bootable Firmware Agent FRMAGENT 3 Enable Intel Trusted Execution Technology TXT AGENT 3 Intel TXT Agent Enable Safe Mode Boot SAFE MODE BOOT 3 Configure Socket ID SOCKET ID 1 0 3 Notes 1 Output tri state option enables Fault Resilient Booting FRB for FRB details see Section 7 4 The signal used to latch PROCHOT N for enabling FRB mode is RESET N 2 BIST ENABLE is sampled at RESET N de assertion 3 This signal is sampled after PNRGOOD assertion Intel Xeon Processor E5 2400 v2 Product Family 135 Datasheet Volume One Electrical Specifications intel 7 4 Fault Resilient Booting FRB The processor supports both socket and core level Fault Resilient Booting FRB which provides the ability to boot the system as long as there is one processor functional in the system One limitation to socket level FRB is that the system cannot boot if the legacy socket that connects to an active PCH becomes unavailable since this is the path to the system BIOS See Table 7 8 for a list of output tri state FRB signals Socket level FRB will tri state processor outputs via the PROCHOT_N signal Assertion of the PROCHOT_N signal through RESET_N de assertion will tri state processor outputs Note that individual core disabling is also supported for those cases where disabling the entire package is not desired For Core FRB support refer to the Intel Xeon Processor E5 v2 Product Family Datasheet
233. ion and Validation Methodologies 7 8 3 8 SMBus Signal AC Specifications The processor AC specifications for the SMBus are available in the System Management Bus SMBus Specification Revision 2 0 This document will provide only the processor exceptions to the System Management Bus SMBus Specification Revision 2 0 7 8 3 9 Reset and Miscellaneous Signal AC Specifications a power on Reset RESET_N must stay active for at least 3 5 millisecond after Vcc and BCLK 0 1 have reached their proper specifications RESET_N must not be kept asserted for more than 100 ms while PWRGOOD is asserted RESET_N must be held asserted for at least 3 5 millisecond before it is deasserted again RESET_N must be held asserted before PWRGOOD is asserted This signal does not have on die termination and must be terminated on the system board Figure 7 6 BCLK 0 1 Differential Clock Crosspoint Specification 650 600 500 550 0 5 VHavg 700 450 400 250 0 5 VHavg 700 350 300 250 mV 250 5 Crossing Point mV 200 T T T T T T T T T T T T T T T T T T 1 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg mV Intel Xeon Processor E5 2400 v2 Product Family 150 Datasheet Volume One Figure 7 7 BCLK 0 1 Differential Clock Measurement Points for Duty Cycle and Period Clock Period Differential Positive Duty Negative
234. is entered if there are open pages when CKE is de asserted In this mode the open pages are retained Existing this mode is 3 5 DCLK cycles Precharge power down fast exit This mode is entered if all banks in DDR are precharged when de asserting CKE Existing this mode is 3 5 DCLK cycles Difference from the active power down mode is that when waking up all page buffers are empty Precharge power down slow exit 1 this mode the data in DLL s on DDR are off Existing this mode is 3 5 DCLK cycles until the first command is allowed but about 16 cycles until first data is allowed 4 3 2 Self Refresh The Power Control Unit PCU may request the memory controller to place the DRAMs in self refresh state Self refresh per channel is supported The BIOS can put the channel in self refresh if software remaps memory to use a subset of all channels Also processor channels can enter self refresh autonomously without PCU instruction when the package is in a package CO state Intel amp Xeon Processor E5 2400 v2 Product Family 96 Datasheet Volume One 4 3 2 1 Self Refresh Entry Self refresh entrance can be either disabled or triggered by an idle counter Idle counter always clears with any access to the memory controller and remains clear as long as the memory controller is not drained As soon as the memory controller is drained the counter starts counting and when it reaches the idle count the memory controller will place the DRAMs in self re
235. istate its outputs PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that BCLK VITA VTTD VSA VCCPLL and VCCD supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD PWRGOOD transitions from inactive to active when all supplies except VCC are stable VCC has a VBOOT of zero volts and is not included in PWRGOOD indication in this phase However for the active to inactive transition if any CPU power supply VCC VTTA VTTD VSA VCCD or VCCPLL is about to fail or is out of regulation the PWRGOOD is to be negated The signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation Note VCC has a Vboot setting of 0 0V and is not included in the PWRGOOD indication and VSA has a Vboot setting of 0 9V Refer to the VR12 IMVP7 Pulse Width Modulation Specification RESET N Asserting the RESET N signal resets the processor to a known state and invalidates its internal caches without writin
236. k layer is responsible for reliable transmission and flow control The Link layer s unit of transfer is 80 bits which is called a Flit for Flow control unit The Routing layer provides the framework for directing packets through the fabric The Transport layer is an architecturally defined layer not implemented in the initial products providing advanced routing capability for reliable end to end transmission The Protocol layer is the high level set of rules for exchanging packets of data between devices A packet is comprised of an integral number of Flits The Intel QuickPath Interconnect includes a cache coherency protocol to keep the distributed memory and caching structures coherent during system operation It supports both low latency source snooping and a scalable home snoop behavior The coherency protocol provides for direct cache to cache transfers for optimal latency Intel Xeon Processor E5 2400 v2 Product Family 28 Datasheet Volume One 2 5 Note Table 2 1 2 5 1 intel Platform Environment Control I nterface The Platform Environment Control Interface PECI uses a single wire for self clocking and data transfer The bus requires no additional control lines The physical layer is a self clocked one wire bus that begins each bit with a driven rising edge from an idle level near zero volts The duration of the signal driven high depends on whether the bit value is a logic 0 or logic
237. l Groups Sheet 3 of 3 Differential Single 1 Ended Buffer Type Signals SMBus Single ended Open Drain CMOS DDR_SCL_C 1 23 Input Output DDR_SDA_C 1 23 PEHPSCL PEHPSDA JTAG amp TAP Signals Single ended CMOS1 0v Input TCK TDI TMS TRST_N CMOS1 0v Input Output PREQ_N CMOS1 0v Output PRDY_N Open Drain CMOS BPM N 7 0 Input Output EAR N Open Drain CMOS Output TDO Serial VID Interface SVI D Signals Single ended CMOS1 0v Input SVIDALERT N Open Drain CMOS SVIDDATA Input Output Open Drain CMOS Output SVIDCLK Processor Asynchronous Sideband Signals Single ended CMOS1 0v Input BIST_ENABLE BMCI NIT FRMAGENT PWRGOOD PMSYNC RESET_N SAFE_MODE_BOOT SOCKET ID 1 0 TXT AGENT TXT PLTEN Open Drain CMOS CAT ERR N Input Output MEM HOT 41 23 PROCHOT N Open Drain CMOS Output ERROR N 2 0 THERMTRIP N Miscellaneous Signals N A Output IVT ID N SKTOCC N Power Other Signals Power Ground Vsa and Vss Sense Points VCC SENSE VSS VCC SENSE VSS VITD SENSE SENSEVSA SENSE VSS VSA SENSE Notes 1 Refer to Section 6 Signal Descriptions for signal description details 2 DDR 1 2 3 refers to DDR3 Channel 1 DDR3 Channel 2 and DDR3 Channel 3 Intel Xeon Processor E5 2400 v2 Product Family 134 Datasheet Volume One Electrical Specifications tel Table 7 6 Signals with On Die Termination Signal Name Rail V
238. l MSR 614h SKU Read SKU 31 0 Design Power and PACKAGE_POWER_SKU minimum package CSR PACKAGE_POWER_SKU power values for the processor SKU Package Power 29 0x0000 Package Power N A Returns the MSR 614h SKU Read SKU 64 32 maximum package PACKAGE_POWER_SKU power value for the CSR PACKAGE_POWER_SKU processor SKU and B the maximum time interval for which it can be sustained Wake on 05 0x0001 Set N A Wake Enables package N A Mode bit Write 0x0000 mode bit pop up to C2 to Read Reset service PECI PCI Config accesses if appropriate Wake 05 0 0000 Wake Read status N A Mode bit Write mode bit Wake on PECI Read mode bit Accumulated 31 0x0000 Total reference N A Returns the total run MSR 10h Run Time Read time time 1A32 TIME STAMP COUNTER Package 02 OxOOFF Processor N A Returns the MSR 1B1h Temperature package maximum processor 2 PACKAGE THERM STATUS Read Temperature die temperature in PECI format Per Core DTS 09 0x0000 Per core DTS N A Read the maximum MSR 19Ch 2 THERM STATUS Temperature 0x0007 maximum DTS temperature of Read cores 0 7 temperature a particular core or the System Agent System within the processor Agent die in relative PECI temperature format Temperature 16 0x0000 Processor N A Returns the MSR 1A2h Target Read TProchot PROCHOT N TEMPERATURE TARGET TCONTROL assertion CSR T
239. l Mechanical Design Guide TMDG for system and environmental implementation details Each case temperature thermal profile is unique to each TDP and core count combination These profiles are fully defined by the simple linear equation TcAsE 51 P Tia Where 5 is the Case to Ambient thermal resistance of the processor thermal solution is the Local Ambient nominal temperature P is the processor power dissipation The Short Term thermal profile provides for a 15 C rise of temperature above the nominal profile due to scenarios such as fan failure or A C failure Short term excursions to higher ambient operating temperatures are strictly limited 96 hours per instance 360 hours per year and a maximum of 15 instances per year as intended by NEBS Level 3 designates the Local Ambient temperature for Short Term operation Intel Xeon Processor E5 2400 v2 Product Family 104 Datasheet Volume One Table 5 3 Figure 5 3 5 1 4 2 Intel Xeon Processor E5 2400 v2 Product Family intel Table 5 3 provides the PSIcA and T parameters that define thermal profile for each TDP Core count combination Figure 5 3 illustrates the general form of the resulting linear graph resulting from Tcase 5 P Tia Embedded Case Temperature Thermal Specifications Short Term TDP W Core
240. le 8 2 Land Number Sheet 21 of 37 Table 8 2 Land Number Sheet 22 of 37 Land 7 Direction Land Direction BA28 VCC PWR C31 VSS GND BA29 PE3D_RX_DN 15 PCI EX3 C32 VSS GND BA3 VSS GND C33 DDR3_ECC 1 SSTL 1 0 BA30 VTTD PWR C34 DDR3 ECC 0 SSTL 1 PE3D_RX_DN 13 PCIEX3 5 DDR3_ECC 4 SSTL 2 VSS GND C36 vss GND BA38 RSVD C37 DDR2_DQ 26 SSTL 1 0 BA39 PE1B_RX_DN 5 PCIEX3 C38 DDR2 DQS DN 03 SSTL 4 QPI1 DTX DN 13 Intel C39 DDR2 DQ 25 SSTL 40 VSS GND C4 TEST1 5 QPI1_DTX_DP 13 Intel QPI 0 C40 VSS GND BA6 RSVD C41 DDR3 001261 SSTL 7 QPI1_DTX_DP 11 Intel QPI 42 DDR3_DQ 30 SSTL vss GND C43 VSS GND BA9 QPI1_CLKTX_DP Intel QPI 5 VSS GND C10 VSS GND C6 vss GND C11 DDR3 CS NI6 SSTL C7 vss GND C12 DDR3_ODT 1 SSTL C8 vss GND C13 DDR3_ODT 3 SSTL C9 vss GND C14 DDR3 ODT 2 SSTL 01 VSS GND C15 VSS GND D10 DDR2 DQ 36 SSTL C16 DDR3_WE_N SSTL 011 DDR3 CS N 3 SSTL 17 DDR3 MA 00 SSTL 012 DDR3_CS_N 7 SSTL C18 DDR3 MA PAR SSTL 013 55 GND C19 DDR3 CLK DP 0 SSTL 14 DDR3 MA 13 SSTL C2 VSS GND D15 DDR3_ODT 0 SSTL 20 DDR3_CLK_DP 3 SSTL 016 DDR3 CS 01 SSTL 21 DDR3_CLK_DN 3 SSTL 017 DDR3 11 5511 22 DD
241. les when the processor is engaged in any activity to retire instructions and as a result consuming energy Any power management entity monitoring this indicator should sample it at least once every 4 seconds to enable detection wraparounds Refer to the processor Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers for details on programming the 2 ENERGY PERFORMANCE BIAS register to set the Energy Efficiency policy of the processor Figure 2 38 Efficient Performance Indicator Read 31 0 Efficient Performance Cycles Efficient Performance Indicator Data Intel Xeon Processor E5 2400 v2 Product Family 57 Datasheet Volume One intel 2 5 2 6 29 ACPI P T Notify Write amp Read This feature enables the processor turbo capability when used in conjunction with the package or power limit When the BMC sets the package power limit to a value below TDP it also determines a new corresponding turbo frequency and notifies the OS using the ACPI Notify mechanism as supported by the _PPC or performance present capabilities object The BMC then notifies the processor PCU using the ACPI P T Notify service by programming a new state that is one p state below the turbo frequency sent to the OS via the _PPC method When the OS requests a p state higher than what is specified in bits 7 0 of the PECI ACPI P T Notify data field the CPU will treat it as request
242. level output source 6 0 mA 0 75 Vr impedance state leakage to 50 200 uA 3 OL Ron Buffer On Resistance 20 36 Q lt 10 pF 4 5 VNoise Signal noise immunity above 300 MHz 0 100 N A Vp p Output Edge Rate 50 ohm to VSS between Vj 1 5 4 V ns and Notes 1 supplies the interface behavior does not affect Min max specification 2 is expected that the driver will take into account the variance in the receiver input thresholds and consequently be able to drive its output within safe limits 0 150 V to 0 275 for the low level and 0 725 to Vrrp4 0 150 for the high level 3 The leakage specification applies to powered devices on the PECI bus 4 One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes 5 Excessive capacitive loading on the PECI line may slow down the signal rise fall times and consequently limit the maximum bit rate at which the interface can operate Table 7 17 System Reference Clock BCLK 0 1 DC Specifications Symbol Parameter Signal Min Max Unit Figure Notes dit Differential Input High Voltage Differential 0 150 N A V 7 9 aiff Differential Input Low Voltage Differential 0 150 V 7 9 V
243. location of all Reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional 131 Electrical Specifications intel signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the baseboard trace unless otherwise noted in the appropriate platform design guidelines 7 2 Signal Group Summary Signals are grouped by buffer type and similar characteristics as listed in Table 7 5 The buffer type indicates which signaling technology and specifications apply to the signals Table 7 4 Signal Description Buffer Types Signal Description Analog Analog reference or output May be used as a threshold voltage or for buffer compensation Asynchronous Signal has no timing relationship with any system reference clock CMOS CMOS buffers 1 0 V or 1 5 V tolerant DDR3 DDR3 buffers 1 5 V and 1 35 V tolerant DMI2 Direct Media Interface 2 signals These signals are compatible with Express 2 0 and 1 0 Signaling En
244. low through the 2 2 2 2 42 26 2535 31 2 4 Example 2 ER PY 31 2 5 REND URINE 31 2 6 Device Info Field 1 1 4 42 2 2 24 4 4 1 441 ener 32 2 7 Revision Number menn nne nne 32 2 8 33 2 9 GetTemp 4 4 eme eere nan re ne nnne nnn 34 2 10 RadPkgCohflg E ETE PH aa erben Iud 35 2 11 WrPkgConfig nne nnne nnn nne rne nnn anseres nna nnns 36 2 12 DRAM Thermal Estimation Configuration Data 39 2 13 DRAM Rank Temperature Write menm memes 40 2 14 DIMM Temperature Read Write 41 2 15 Ambient Temperature Reference 41 2 16 DRAM Channel Temperature 1 42 2 17 Accumulated DRAM Energy Data 42 2 18 DRAM Power I
245. meet the imposed power limits Programming too large a time window runs the risk of the PCU not being able to monitor and take timely action on package energy excursions On the other hand programming too small a time window may not give the PCU enough time to sample energy information and enforce the limit The minimum value of the time window can be obtained by reading bits 21 15 of the PWR_LIMIT_MISC_INFO CSR using the RdPCI ConfigLocal command Figure 2 28 Package Power SKU Data 63 55 54 48 47 46 32 Maximum Time Package Power SKU upper bits 31 30 16 15 14 0 Minimum Package Power TDP Package Power Package Power SKU lower bits 2 5 2 6 15 Wake on Mode bit Write Read Setting the Wake on PECI mode bit enables successful completion of the WrPCI ConfigLocal RdPCI ConfigLocal WrPCIConfig and RdPCI Config commands by forcing a package pop up to the C2 state to service these commands if the processor is in a low power state The exact power impact of such a pop up is determined by the product SKU the C state from which the pop up is initiated and the negotiated PECI bit rate A reset or clear of this bit or simply not setting the Wake on PECI mode bit could result in a timeout response completion code of 0x82 from the processor indicating that the resources required to service the command are in a low power state Alternatively this mode bit ca
246. ment capabilities 1 4 Thermal Management Support Digital Thermal Sensor with multiple on die temperature zones Adaptive Thermal Monitor THERMTRIP N and PROCHOT N signal support On Demand mode clock modulation Open and Closed Loop Thermal Throttling OLTT CLTT support for system memory in addition to Hybrid OLTT CLTT mode Fan speed control with DTS Two integrated SMBus masters for accessing thermal data from DI MMs e New Memory Thermal Throttling features via MEM HOT C 1 23 signals Intel Xeon Processor E5 2400 v2 Product Family 19 Datasheet Volume One Overview 1 5 1 6 intel Running Average Power Limit RAPL Processor and DRAM Thermal and Power Optimization Capabilities Package Summary package LGA1356 2 Terminology The Processor socket type is noted as Socket B2 It is a 45 mm x 42 5 mm FCLGA12 Term Description ASPM Active State Power Management BMC Baseboard Management Controllers Cbo Cache and Core Box It is a term used for internal logic providing ring interface to LLC and Core DDR3 Third generation Double Data Rate SDRAM memory technology that is the successor to DDR2 SDRAM DMA Direct Memory Access DMI Direct Media Interface DMI2 Direct Media Interface Gen 2 DTS Digital Thermal Sensor ECC Error Correction Code Enhanced Intel SpeedStep Technology Allows the operating system to reduce power consumption when performance is not n
247. n CKE de asserted In this mode no transactions are executed and the system memory consumes the minimum possible power Self refresh modes apply to all memory channels for the processor O MDLL Off Option that sets the IO master DLL off when self refresh occurs PLL Off Option that sets the PLL off when self refresh occurs In addition the register component found on registered DIMMs RDIMMs is complemented with the following power down states Clock Stopped Power Down with IBT On Clock Stopped Power Down with BT Off DMI 2 PCI Express Link States DMI 2 PCI Express Link States State Description LO Full on Active transfer state 11 Lowest Active State Power Management ASPM Longer exit latency Note 11 is only supported when the 2 Express port is operating as a PCI Express port Intel QuickPath Interconnect States Intel QPI States State Description LO Link on This is the power on active working state 10 lower power state from LO that reduces the link from full width to half width L1 A low power state with longer latency and lower power than 105 and is activated in conjunction with package C states below G S and C State Combinations G S and C State Combinations Processor e e es uem Description GO 50 CO Full On On Full On GO SO 1 Auto Halt On Auto Halt GO SO C
248. n also be read to determine PECI behavior in package states C3 or deeper 2 5 2 6 16 Accumulated Run Time Read This read returns the total time for which the processor has been executing with a resolution of 1mS per count This is tracked by a 32 bit counter that rolls over on reaching the maximum value This counter activates and starts counting for the first time at RESET N de assertion Intel Xeon Processor E5 2400 v2 Product Family 51 Datasheet Volume 2 5 2 6 17 intel This read returns the maximum processor die temperature in 16 bit PECI format The upper 16 bits of the response data are reserved The PECI temperature data returned by this read is an exponential moving average of the maximum sensor temperature max core and uncore sensors updated once every ms The equation for the update is Package Temperature Read 255 T x el n 1 256 25 Where Tj is the current average value 1 is the last average value t is the current maximum sensor temperature Figure 2 29 Package Temperature Read Data 31 16 15 14 6 5 0 Sign PECI Temperature PECI Temperature RESERVED Bit Integer Value Fractional Value Note 2 5 2 6 18 2 5 2 6 19 This value is not the value as returned by the PECI GetTemp described in Section 2 5 2 3 Per Core DTS Temperature Read This feature enables the PECI host to read the maximum value of the DTS temperature for any specific core withi
249. n the processor Alternatively this service can be used to read the System Agent temperature Temperature is returned in the same format as the Package Temperature Read described in Section 2 5 2 6 17 Data is returned in relative PECI temperature format Reads to a parameter value outside the supported range will return an error as indicated by a completion code of 0x90 The supported range of parameter values can vary depending on the number of cores within the processor The temperature data returned through this feature is the instantaneous value and not an averaged value It is updated once every 1 mS Temperature Target Read The Temperature Target Read allows the PECI host to obtain the target DTS temperature Tprochot for assertion in degrees Celsius This is the minimum temperature at which the processor thermal control circuit TCC activates The actual temperature of TCC activation may vary slightly between processor units due to manufacturing process variations The Temperature Target read also returns the processor Value 15 returned in standard temperature format and represents the threshold temperature used by the thermal management system for fan speed control Intel Xeon Processor E5 2400 v2 Product Family 52 Datasheet Volume One intel Figure 2 30 Temperature Target Read 31 24 23 16 15 8 7 0 2 5 2 6 20 Package Thermal Status Read Clear
250. nal Alignment of Reset used to bring the processor up into a deterministic state This signal is pulled up on the die refer to Table 7 6 for details PRDY N Probe Mode Ready is a processor output used by debug tools to determine processor debug readiness PREQ N Probe Mode Request is used by debug tools to request debug operation of the processor TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TMS TMS Test Mode Select is a J TAG specification support signal used by debug tools TRST N TRST Test Reset resets the Test Access Port TAP logic TRST_N must be driven low during power on Reset Note Refer to the Platform Design Guide PDG for Debug Port implementation details 6 8 Serial VI D I nterface SVI D Signals Table 6 12 SVID Signals SVIDALERT N Serial VID alert SVIDCLK Serial VID clock SVIDDATA Serial VID data out 6 9 Processor Asynchronous Sideband and Miscellaneous Signals Table 6 13 Processor Asynchronous Sideband Signals Sheet 1 of 4 Signal Name Description BIST ENABLE BI
251. nd other countries Other names and brands may be claimed as the property of others Copyright 2009 2014 Intel Corporation All rights reserved Intel Xeon Processor E5 2400 v2 Product Family 2 Datasheet Volume One Table of Contents 1 OVErVICW m Medina ries eee ape 13 T sss huoc inet 13 1 1 1 Processor Feature Details 14 1 1 2 Supported 5 14 ns cT wmm 15 1 2 1 System Memory Support kr RR RACER ss 15 1 2 2 55 tette RKEEFRFBURRRAERFERRERRAREERRERAR ANERRCRURFNRERERKRAUES 16 1 2 3 Direct Media Interface Gen 2 2 1 4 20 4 4 4 17 1 2 4 Intel QuickPath Interconnect Intel 18 1 2 5 Platform Environment Control Interface 18 1 3 Power Management se mese nennen nnns 19 1 3 1 Processor Package and Core 19 1 3 2 System States SuppOLFt iiec ences pa Ee i ROSE ERO EORR IURE FUE 19 133 Memory Controller nier rr ient redeo erp cta ORE Ad tame 19 1 3 4
252. ned to allow the fan heat sink power cable to reach it The fan power header identification and location must be documented in the suppliers platform documentation or on the baseboard itself The baseboard fan power header should be positioned within 177 8 mm 7 in from the center of the processor socket Table 10 1 PWM Fan Frequency Specifications For 4 Pin Active Thermal Solution Description Min Frequency Nominal Frequency Max Frequency Unit PWM Control Frequency Range 21 000 25 000 28 000 Hz Table 10 2 PWM Fan Characteristics for Active Thermal Solution 4 Description Min Typical Steady Startup Unit 12V 12 Volt Supply 10 8 12 12 13 2 V IC Fan Current Draw N A 1 25 1 5 2 2 Pulses fan Sense Pulse Frequency 2 revolution Intel Xeon Processor E5 2400 v2 Product Family 212 Datasheet Volume One Boxed Processor Specifications n tel Figure 10 13 Fan Cable Connector Pin Out For 4 Pin Active Thermal Solution PIN 3 PIN4 PIN 2 Table 10 3 PWM Fan Connector Pin and Wire Description 10 3 1 10 3 1 1 10 3 1 2 Pin Number Signal Wire Color 1 Ground Black 2 Power 12V Yellow 3 Sense 2 pulse per revolution Green 4 Control 21KHz 28KHz Blue Boxed Processor Cooling Requirements As previously stated the boxed processor will have three thermal solutions available Each configu
253. nfo Read 7 eene 43 2 19 DRAM Power Limit 44 2 20 DRAM Power Limit Performance Data 45 2 21 CHER 48 2 22 Platform ID Data ecc XR E PRX i E TR CER TAREA ER es es 49 25239 PCU DEVICE ID 49 2 24 Maximum Thread 10 RR ERE 49 2 25 Processor Microcode 1 49 2 26 Machine Check Status 50 2 27 Package Power SKU Unit 50 2 28 Package Power SKU Data 51 Intel Xeon Processor E5 2400 v2 Product Family 7 Datasheet Volume One 2 29 Package Temperature Read 52 2 30 Temperature Target 53 2 31 Thermal Status WOrd rr RARE TEX VAR RR EY GRO ERA ERAN ER ARR GUAE PER CER AU x 53 2 32 Thermal Averaging Constant Write Read 54 2 33 Current Config Limit Read 54 2 34 Accumulated Energy Read 55 2 35 Power Limit Data for VCC Power Plane 1 enne 56 2 36 Package Turbo Power Limit Data 57 2 37 Package Power Limit Performance 57 2 38 Efficient Performance
254. ng environment by accurately measuring and verifying the controlling software Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute These extensions enhance two areas The launching of the Measured Launched Environment MLE The protection of the MLE from potential corruption The enhanced platform provides these launch and control interfaces using Safer Mode Extensions SMX The SMX interface includes the following functions e Measured Verified launch of the MLE Mechanisms to ensure the above measurement is protected and stored in a secure location Protection mechanisms that allow the MLE to control attempts to modify itself For more information refer to the RS Intel amp Trusted Execution Technology BIOS Specification and Intel amp Trusted Execution Technology Software Development Guide For more information on Intel Trusted Execution Technology see http www intel com technology security Intel Trusted Execution Technology Server Extensions Software binary compatible
255. ntation details Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 121 Signal Descriptions intel Table 6 13 Processor Asynchronous Sideband Signals Sheet 4 of 4 Signal Name Description THERMTRIP_N Assertion of THERMTRIP_N Thermal Trip indicates one of two possible critical over temperature conditions One the processor junction temperature has reached a level beyond which permanent silicon damage may occur and Two the system memory interface has exceeded a critical temperature limit set by BIOS Measurement of the processor junction temperature is accomplished through multiple internal thermal sensors that are monitored by the Digital Thermal Sensor DTS Simultaneously the Power Control Unit PCU monitors external memory temperatures via the dedicated SMBus interface to the DIMMs If any of the DIMMs exceed the BIOS defined limits the PCU will signal THERMTRIP_N to prevent damage to the DIMMs Once activated the processor will stop all execution and shut down all PLLs To further protect the processor its core voltage VCC VTTA VTTD VSA VCCPLL VCCD supplies must be removed following the assertion of THERMTRIP_N Once activated THERMTRIP_N remains latched until RESET_N is asserted While the assertion of the RESET_N signal may de assert THERMTRIP_N if the processor s junction temperature remains at or above the trip level THERMTRIP_N will again be asserted after RESET_N i
256. o a negative result from the subtraction will accomplish the same goal Accumulated Energy Read Data 31 0 Accumulated CPU Energy Accumulated Energy Status Power Limit for the VCC Power Plane Write Read This feature allows the PECI host to program the power limit over a specified time or control window for the processor logic supplied by the VCC power plane This typically includes all the cores home agent and last level cache The processor does not support power limiting on a per core basis Actual power limit values are chosen based on the external VR voltage regulator capabilities The units for the Power Limit and Control Time Window are determined as per the Package Power SKU Unit settings described in Section 2 5 2 6 13 Since the exact VCC plane power limit value is a function of the platform VR this feature is not enabled by default and there are no default values associated with the power limit value or the control time window The Power Limit Enable bit in Figure 2 35 should be set to activate this feature The Clamp Mode bit is also required to be set to allow the cores to go into power states below what the operating system originally requested In general this feature provides an improved mechanism for VR protection compared to the input PROCHOT N signal assertion method Both power limit enabling and initialization of power limit values can be done in the same command cycle Setting a power limit for the VCC
257. ocessor client a high degree of confidence that the data it received from the host is correct This is especially critical where the consumption of bad data might result in improper or non recoverable operation Please refer to the RS Platform Environment Control Interface Specification Rev 3 0 for more details Figure 2 11 WrPkgConfig Byte 0 1 2 3 Write Length Read Length Cmd Code Definition 4 5 6 7 Host ID 7 1 amp Retry 0 LSB Parameter MSB 8 9 10 11 LSB Data 4 bytes MSB 12 13 14 15 Completion Note The 2 byte parameter field and 4 byte write data field defined in Figure 2 11 are sent in standard PECI ordering with LSB first and MSB last Intel Xeon Processor E5 2400 v2 Product Family 36 Datasheet Volume One 2 5 2 5 2 2 5 2 5 2 6 2 5 2 6 1 Note intel Supported Responses The typical client response is a passing FCS a passing Completion Code and valid data Under some conditions the client s response will indicate a failure WrPkgConfig Response Definition Response Meaning Bad Write FCS Electrical error or AW FCS failure Abort FCS Illegal command formatting mismatched RL WL Command Code CC 0x40 Command passed data is valid CC 0x80 Response timeout The processor was not able to generate the required response in a timely fashion Retry is appropriate CC 0x81 Response timeout The processor is not able to allocate re
258. ocessor package configuration space provides a means for Baseboard Management Controllers BMCs or other platform management devices to actively manage the processor and memory power and thermal features Details on the list of available power and thermal optimization services can be found in Section 2 5 2 6 Platform Manageability PECI allows read access to certain error registers in the processor MSR space and status monitoring registers in the PCI configuration space within the processor and downstream devices Details are covered in subsequent sections PECI permits writes to certain Memory Controller RAS related registers in the processor PCI configuration space Details are covered in Section 2 5 2 10 Client Command Suite PECI command requires at least one frame check sequence FCS byte to ensure reliable data exchange between originator and client The PECI message protocol defines two FCS bytes that are returned by the client to the message originator The first FCS byte covers the client address byte the Read and Write Length bytes and all bytes in the write data block The second FCS byte covers the read response data returned by the PECI client The FCS byte is the result of a cyclic redundancy check CRC of each data block More details can be found in the RS Platform Environment Control Interface PECI Specification Rev 3 0 Ping Ping is a required message for all PECI devices This message is used to enumerate d
259. ocessor supporting HT Technology and an HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see http www intel com products ht hyperthreading more htm Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel amp Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see http www intel com technology turboboost No computer system can provide absolute security under all conditi
260. of 0 9V Vss 353 Ground Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Large electrolytic bulk capacitors help maintain the output voltage during current transients for example coming out of an idle condition Care must be taken in the baseboard design to ensure that the voltages provided to the processor remain within the specifications listed in Table 7 11 Failure to do so can result in timing violations or reduced lifetime of the processor For further information refer to the Platform Design Guide PDG Voltage Identification VID The Voltage Identification VID specification for the Vcc Vsa Vccp voltage are defined by the VR12 IMVP7 Pulse Width Modulation Specification The reference voltage or the VID setting is set via the SVID communication bus between the processor and the voltage regulator controller chip The VID settings are the nominal voltages to be delivered to the processor s Vcc Vsa Vccp lands Table 7 3 specifies the reference voltage level corresponding to the VID value transmitted over serial VID The VID codes will change due to temperature and or current load changes in order to minimize the power and to maximize the performance of the pa
261. of 2 State Description Power Up Normal Operation asserted Active Mode highest power consumption CKE Power Down Opportunistic per rank control after idle time Active Power Down APD default mode de asserted Power savings in this mode relative to active idle state is about 5596 of the memory power Exiting this mode takes 3 5 DCLK cycles Pre charge Power Down Fast Exit PPDF de asserted DLL On Also known as Fast Power savings in this mode relative to active idle state is about 6096 of the memory power Exiting this mode takes 3 5 DCLK cycles Pre charge Power Down Slow Exit PPDS de asserted DLL Off Also known as Slow Power savings in this mode relative to active idle state is about 8796 of the memory power Exiting this mode takes 3 5 DCLK cycles until the first command is allowed and 16 cycles until first data is allowed Register CKE Power Down BT ON mode Both CKE s are de asserted the Input Buffer Terminators IBTs are left on mode Both are de asserted the Input Buffer Terminators IBTs are turned off Intel Xeon Processor E5 2400 v2 Product Family 86 Datasheet Volume One Table 4 4 4 1 4 4 5 4 1 5 4 6 4 1 6 Table 4 7 intel System Memory Power States Sheet 2 of 2 State Self Refresh Descriptio
262. off the shelf OS s and applications without any special steps Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on 1 x86 processors More reliable Due to the hardware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system Intel Xeon Processor E5 2400 v2 Product Family 71 Datasheet Volume One Technologies l n tel 3 1 2 Intel VT x Features The processor core supports the following Intel VT x features Extended Page Tables hardware assisted page table virtualization eliminates VM exits from guest OS to the VMM for shadow page table maintenance Virtual Processor IDs VPID Ability to assign a VM ID to tag processor core hardware structures e g TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS guarantees Descriptor Table Exiting
263. ons Closed Loop Thermal Throttling CLTT The processor periodically samples temperatures from the DIMM TSoD devices over a programmable interval The PCU determines the hottest DI MM rank from TSoD data and informs the integrated memory controller for use in bandwidth throttling decisions Hybrid Closed Loop Thermal Throttling CLTT Hybrid The processor periodically samples temperature from the DIMM TSoD devices over a programmable interval and interpolates gaps or the BMC or Intel ME samples a motherboard thermal sensor in the memory subsection and provides this data to the PCU via the PECI interface This data is combined with an energy based estimations calculated by the PCU When needed system memory is then throttled using CAS bandwidth control The processor supports dynamic reprogramming of the memory thermal limits based on system thermal state by the BMC or Intel ME MEM HOT C1 MEM HOT C23 Signal The processor includes new bi directional memory thermal status signals useful for manageability schemes Each signal presents and receives thermal status for a pair of memory channels channel 1 and channels 2 amp 3 e Input Function The processor can periodically sense the MEM HOT 1 23 signals to detect if the platform is requesting a memory throttling event Manageability hardware could drive this signal due to a memory voltage regulator thermal or electrical issue or because of a detected system thermal event
264. ons Intel Trusted Execution Technology Intel TXT requires a computer with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment Intel TXT also requires the system to contain a TPM 1 5 For more information visit http www intel com technology security The Processor Spec Finder at http ark intel com or contact your Intel representative for more information 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information A Intel processor numbers are a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details 12C is a two wire communications bus protocol developed by Philips SMBus is a subset of the 2 bus protocol and was developed by Intel Implementations of the 12 bus protocol may require licenses from various entities including Philips Electronics and North American Philips Corporation Intel Xeon Enhanced Intel SpeedStep Technology Core and the Intel logo are trademarks of Intel Corporation in the U S a
265. or digital thermal sensor DTS provides an improved capability to monitor device hot spots which inherently leads to more varying temperature readings over short time intervals Coupled with the fact that typical fan speed controllers may only read temperatures at 4Hz it is necessary for the thermal readings to reflect thermal trends and not instantaneous readings Therefore supports a configurable low pass temperature filtering function that is expressed by the equation 1 0 0 where Ty and 1 are the current and previous averaged temperature values respectively Tsamp te is the current temperature sample value and the variable a 1 2 where X is the Thermal Averaging Constant that is programmable as described in Section 2 5 2 6 21 2 5 7 4 Reserved Values Several values well out of the operational range are reserved to signal temperature sensor errors These are summarized in Table 2 24 Table 2 24 Error Codes and Descriptions Error Code Description 0x8000 General Sensor Error GSE 0x8001 Reserved 0x8002 Sensor is operational but has detected a temperature below its operational range underflow 0x8003 0x81ff Reserved Intel Xeon Processor E5 2400 v2 Product Family 76 Datasheet Volume One Technologies 3 3 1 3 1 1 intel Technologies Intel Virtualization Technology Intel VT Intel Virt
266. or the processor both overshoot and undershoot magnitude are referenced to Vss It is important to note that the overshoot and undershoot conditions are separate and their impact must be determined independently The pulse magnitude and duration and activity factor must be used to determine if the overshoot undershoot pulse is within specifications Overshoot Undershoot Pulse Duration Overshoot undershoot pulse duration describes the total amount of time that an overshoot undershoot event exceeds the overshoot undershoot reference voltage The total time could encompass several oscillations above the reference voltage Multiple overshoot undershoot pulses within a single overshoot undershoot event may need to be measured to determine the total pulse duration Oscillations below the reference voltage cannot be subtracted from the total overshoot undershoot pulse duration Activity Factor Activity factor AF describes the frequency of overshoot or undershoot occurrence relative to a clock Since the highest frequency of assertion of any common clock signal is every other clock an AF 0 1 indicates that the specific overshoot or undershoot waveform occurs every other clock cycle The specification provided in the table shows the maximum pulse duration allowed for a given overshoot undershoot magnitude at a specific activity factor Each table entry is independent of all others meaning that the pulse duration reflects the existence of
267. ore ID amp Can alternatively be associated valid used to read Core bit ID data to confirm that IERR was caused by a core timeout Thermal Margin 10 0x0000 Thermal margin N A Read margin to N A Read to processor thermal profile or load line processor thermal load line 2 5 2 6 12 Package Identifier Read This feature enables the PECI host to uniquely identify the PECI client processor The parameter field encodings shown in Table 2 8 allow the PECI host to access the relevant processor information as described below CPUID data This is the equivalent of data that can be accessed through the CPUID instruction execution It contains processor type stepping model and family ID information as shown in Figure 2 21 Figure 2 21 CPUI D Data 28 27 20 19 16 15 14 13 12 11 Extended Extended Processor CPU ID Data Platform ID data The Platform ID data can be used to ensure processor microcode updates are compatible with the processor The value of the Platform ID or Processor Flag 2 0 as shown in Figure 2 22 is typically unique to the platform Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 48 type and processor stepping Refer to the processor BIOS Writer s Guide for information Figure 2 22 Platform I D Data 31 2 0 Processor Platform 10 Data PCU Device ID This information can be used to uniquely identi
268. orm Design Guide PDG for decoupling voltage plane and routing guidelines for each power supply voltage Intel Xeon Processor E5 2400 v2 Product Family 126 Datasheet Volume One Electrical Specifications tel Table 7 1 7 1 9 2 7 1 9 3 For clean on chip power distribution processors include lands for all required voltage supplies These are listed in Table 7 1 Power and Ground Lands Power and Number of Ground Lands Lands Comments Vcc 135 Each land must be supplied with the voltage determined by the SVID Bus signals Table 7 3 Defines the voltage level associated with each core SVID pattern Table 7 12 Figure 7 2represent Vcc static and transient limits VCC has a VBOOT setting of 0 0V VccPLL 2 Each land is connected to 1 0 V supply power the Phase Lock Loop PLL clock generation circuitry An on die PLL filter solution is implemented within the processor Vccp 16 Each land is connected to a switchable 1 50 V and 1 35 V supply provide power to the processor DDR3 interface These supplies also power the DDR3 memory subsystem Vccp is also controlled by the SVID Bus 9 Vtta lands must be supplied by a fixed 1 0V supply 18 Vrp lands must supplied by a fixed 1 0V supply 23 Each land must be supplied with the voltage determined by the SVID Bus signals typically set at 0 940V VSA has a VBOOT setting
269. ot supported The processor supports the following VR commands e SetVID fast 20mV us for 10mV us for VsA Vccp e SetVID slow SmV us for Vcc 2 5mV ys for VsA Vccp and Slew Rate Decay downward voltage only and it s a function of the output capacitance s time constant commands Table 7 3 includes SVID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 7 11 The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID The VR12 IMVP7 Pulse Width Modulation Specification contains further details Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable 7 1 9 3 2 SetVI D Fast Command The SetVI D fast command contains the target VID in the payload byte The range of voltage is defined in the VID table The VR should ramp to the new VID setting with a fast slew rate as defined in the slew rate data register Typically 10 to 20 mV us depending on platform voltage rail and the amount of decoupling capacitance The SetVI D fast command is preemptive the VR interrupts its current processes and moves to the new VID The SetVI D fast command operates on 1 VR address at a time This command is used in the processor for package C6 fast exit and entry 7 1 9 3 3 SetVI D Slow Command The SetVI D slow command contains the target VID in the payload byte The range voltage is defined in the VID table
270. ount combination Figure 5 2 illustrates the general form of the resulting linear graph resulting from Tprs 51 P Intel Xeon Processor E5 2400 v2 Product Family 102 Datasheet Volume One intel 5 1 3 4 Processor Digital Thermal Sensor DTS Specifications Table 5 2 Digital Thermal Sensor Specification Summary T CO PSlpaC Cr w 95 10 52 6 0 398 90 4 95 8 52 6 0 431 93 5 80 6 51 7 0 473 89 6 80 4 51 7 0 542 95 1 80 15 4 50 5 0 505 90 9 80 15 2 50 5 0 624 100 4 60 10 51 0 0 381 73 9 60 6 51 0 0 456 78 3 Figure 5 2 Digital Thermal Sensor DTS Thermal Profile DTS Absolute Cj T DTS Max T ois PSl pa TDP Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 103 5 1 4 5 1 4 1 intel Embedded Server Thermal Profiles Network Equipment Building System NEBS is the most common set of environmental design guidelines applied to telecommunications equipment in the United States Embedded server SKU s target operation at higher case temperatures and or NEBS thermal profiles for embedded communications server and storage form factors The term Embedded is used to refer to those segments collectively Thermal profiles in this section pertain only to those specific Embedded SKU s The Nominal Thermal Profile must be used for standard operating conditions or for produc
271. p pedestal chassis users to meet the thermal processor requirements without the use of processor chassis ducting It is strongly recommended to implement some form of air duct to meet memory cooling and processor T temperature requirements Use of the active configuration in a 2U rackmount chassis is not recommended Intel Xeon Processor E5 2400 v2 Product Family 213 Datasheet Volume One Boxed Processor Specifications tel In the passive configuration it is assumed that a chassis duct will be implemented For a list processor and thermal solution boundary conditions such as T A airflow flow impedance etc Table 10 4 It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 Meeting the processor s temperature specification is the responsibility of the system integrator This thermal solution is for use with processor SKUs no higher than 95W 8 and 10 Core 80W 4 and 6 Core 10 3 1 3 STS100P 25 5mm Passive Heat Sink Blade 1U 2U Rack This passive solution is intended for use in SSI Blade 1U or 2U rack configurations It is assumed that a chassis duct will be implemented in all configurations For a list processor and thermal solution boundary conditions such as T A airflow flow impedance etc see Table 10 4 It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 Meeting the processor s temper
272. pplication board are not specified Intel does not conduct component level certification assessments post board attach given the multitude of attach methods socket types and board types used by customers Provided as general guidance only Intel board products are specified and certified to meet the following temperature and humidity limits Non Operating Temperature Limit 40C to 70C amp Humidity 5096 to 9096 non condensing with a maximum wet bulb of 28C 5 Device storage temperature qualification methods follow J EDEC High and Low Temperature Storage Life Standards JESD22 A119 low temperature and ESD22 A103 high temperature TU DC Specifications DC specifications are defined at the processor pads unless otherwise noted DC specifications are only valid while meeting specifications for case temperature Specified in Section 5 clock frequency and input voltages Care should be taken to read all notes associated with each specification Intel Xeon Processor E5 2400 v2 Product Family 138 Datasheet Volume One 7 8 1 Voltage and Current Specifications Table 7 11 Voltage Specification Symbol Parameter Voltage Min Typ Max Unit Notes Plane Vcc VID Vcc VID Range 0 6 1 35 V 2 3 VhRetention Retention Voltage 0 65 V 2 3 VID VID in Package C3 and C6 states Vcc Core Voltage Vcc See Table 7 13 and Figure 7 3 V 3 4 7 8 Launch FMB 12 14 18 STEP VID
273. pports Enhanced Intel SpeedStep Technology as an advanced means of enabling very high performance while also meeting the power conservation needs of the platform Enhanced Intel SpeedStep Technology builds upon that architecture using design strategies that include the following Separation between Voltage and Frequency Changes By stepping voltage up and down in small increments separately from frequency changes the processor is able to reduce periods of system unavailability which occur during frequency change Thus the system is able to transition between voltage and frequency states more often providing improved power performance balance Intel Xeon Processor E5 2400 v2 Product Family 82 Datasheet Volume One Technologies 3 8 3 9 intel Clock Partitioning and Recovery The bus clock continues running during state transition even when the core clock and Phase Locked Loop are stopped which allows logic to remain active The core clock is also able to restart more quickly under Enhanced Intel SpeedStep Technology For additional information on Enhanced Intel SpeedStep Technology see Section 4 2 1 Intel Intelligent Power Technology Intel Intelligent Power Technology conserves power while delivering advanced power management capabilities at the rack group and data center level Providing the highest system level performance per watt with Automated Low Power States and Integrated Power Gates Impro
274. ption IVT ID This output can be used by the platform to determine if the installed processor is a future processor planned for Romley platforms This is pulled to ground on the processor package This signal is also used by the VCCPLL and VTT rails to switch their output voltage to support future processors SKTOCC N SKTOCC N Socket occupied is used to indicate that a processor is present This is pulled to ground on the processor package there is no connection to the processor silicon for this signal Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 122 Signal Descriptions tel 6 10 Processor Power and Ground Supplies Table 6 15 Power and Ground Signals Signal Name Description VCC Variable power supply for the processor cores lowest level caches LLC ring interface and home agent It is provided by a VRM EVRD 12 0 compliant regulator for each CPU socket The output voltage of this supply is selected by the processor using the serial voltage ID SVID bus Note VCC has Vboot setting 0 0 is not included in the PWRGOOD indication Refer to the VR12 I MVP7 Pulse Width Modulation Specification SENSE VSS VCC SENSE VCC SENSE and VSS VCC SENSE provide an isolated low impedance connection to the processor core power and ground These signals must be connected to the voltage regulator feedback circuit which insures the output voltag
275. r power limit 1 in Figure 2 36 The Control Time Window for power limit 2 can be directly programmed into bits 55 49 in units of mS without the aid of any conversion formulas Intel Xeon Processor E5 2400 v2 Product Family 56 Datasheet Volume One Figure 2 36 Package Turbo Power Limit Data 63 56 55 49 48 4 46 32 7 Control Time Clamp Power Limit ae RESERVED Window 2 Mode 2 Enable 2 POW el ME SE Package Power Limit 2 14 0 31 24 23 17 16 15 Control Time Clamp Power Limit Window 1 Mode 1 Enable 1 Package Power Limit 1 2 5 2 6 27 Package Power Limit Performance Status Read This service allows the PECI host to assess the performance impact of the currently active power limiting modes The read return data contains the total amount of time for which the entire processor package has been operating in a power state that is lower than what the operating system originally requested This information is tracked by a 32 bit counter that wraps around The unit for time is determined as per the Package Power SKU Unit settings described in Section 2 5 2 6 13 Figure 2 37 Package Power Limit Performance Data 31 0 Accumulated CPU Throttle Time Accumulated CPU Throttle Time 2 5 2 6 28 Efficient Performance Indicator Read The Efficient Performance Indicator EPI Read provides an indication of the total number of productive cycles Specifically these are the cyc
276. r temperature and current limits The result is increased performance in multi threaded and single threaded workloads It should be enabled the BIOS for the processor to operate with maximum performance Refer to the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers for enabling details Intel Turbo Boost Operating Frequency The processor s rated frequency assumes that all execution cores are running an application at the thermal design power TDP However under typical operation not all cores are active Therefore most applications are consuming less than the TDP at the rated frequency To take advantage of the available TDP headroom the active cores can increase their operating frequency To determine the highest performance frequency amongst active cores the processor takes the following into consideration The number of cores operating in the CO state The estimated current consumption The estimated power consumption The die temperature Any of these factors can affect the maximum frequency for a given workload If the power current or thermal limit is reached the processor will automatically reduce the frequency to stay with its TDP limit Intel Turbo Boost Technology is only active if the operating system is requesting the PO state For more information on P states and C states refer to Section 4 Power Management Enhanced Intel SpeedStep Technology The processor su
277. r is disabled 4 4 DMI 2 PCI Express Power Management Active State Power Management ASPM support using L1 state LOs is not supported Intel Xeon Processor E5 2400 v2 Product Family 97 Datasheet Volume One Thermal Management Specifications tel 5 Thermal Management Specifications 5 1 Package Thermal Specifications The processor requires a thermal solution to maintain temperatures within operating limits Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system see section Section 7 7 1 Storage Condition Specifications Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting This section provides data necessary for developing a complete thermal solution For more information on designing a component level thermal solution refer to the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG 5 1 1 Thermal Specifications To allow optimal operation and long term reliability of Intel processor based systems the processor mu
278. r servicing this command at this time Retry is appropriate CC 0x82 The processor hardware resources required to service this command are in a low power state Retry may be appropriate after modification of PECI wake mode behavior if appropriate CC 0x90 Unknown Invalid lllegal Request CC 0x91 PECI control hardware firmware or associated logic error The processor is unable to process the request 2 5 2 9 RdPCI ConfigLocal The RdPCI ConfigLocal command provides sideband read access to the PCI configuration space that resides within the processor This includes all processor and uncore registers within the PCI configuration space as described in the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers document Intel Xeon Processor E5 2400 v2 Product Family 64 Datasheet Volume One intel originators may conduct a device function enumeration sweep of this space by issuing reads in the same manner that the BIOS would A response of all 1 s may indicate that the device function register is unimplemented even with a passing completion code Alternatively reads to unimplemented or hidden registers may return a completion code of 0x90 indicating an invalid request It is also possible that reads to function 0 of non existent devices issued prior to BIOS POST may return all 05 with a passing completion code PECI originators can access this space even prior
279. ration will require unique design considerations Meeting the processor s temperature specifications is also the function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specifications are found in Section 5 Thermal Management Specifications of this document STS100C Passive Active Combination Heat Sink Solution The active configuration of the combination solution is designed to help pedestal chassis users to meet the thermal processor requirements without the use of processor chassis ducting However it is strongly recommended to implement some form of air duct to meet memory cooling and processor T temperature requirements Use of the active configuration in a 2U rackmount chassis is not recommended In the passive configuration it is assumed that a chassis duct will be implemented For a list processor and thermal solution boundary conditions such as airflow flow impedance etc see Table 10 4 It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 Meeting the processor s temperature specification is the responsibility of the system integrator This thermal solution is for use with processor SKUs no higher than 95W 8 and 10 Core or 80W 4 and 6 core STS100A Active Heat Sink Solution Pedestal only The active configuration of the combination solution is designed to hel
280. re is in C1 CIE state it processes bus snoops and snoops from other threads For more information on see Section 4 2 5 2 Package C1 C1E To operate within specification BIOS must enable the feature for all installed processors Core C3 State Individual threads of a core can enter the state by initiating a P LVL2 1 0 read to the P BLK or an MWAIT C3 instruction A core in C3 state flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core s caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory Core C6 State Individual threads of a core can enter the state by initiating a P LVL3 1 0 read or an MWAIT C6 instruction Before entering core C6 the core will save its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts In addition to flushing core caches core architecture state is saved to the uncore Once the core state save is completed core voltage is reduced to zero During exit the core is powered on and its architectural state is restored Delayed Deep C States The Delayed Deep C states DDCst feature on this processor replaces the C state auto demotion scheme used in the previous processor generation
281. re the actual output voltage and comparing it to the assumed voltage Refer to the Platform Design Guide PDG for further details Note Refer to the Platform Design Guide for additional implementation details PECI Signal PECI Signals Signal Name Description PECI Platform Environment Control Interface is the serial sideband interface to the processor and is used primarily for thermal power and error management Details regarding the PECI electrical specifications protocols and functions can be found in the Platform Environment Control Interface Specification System Reference Clock Signals Table 6 10 System Reference Clock BCLK Signals Signal Name Description BCLK 0 1 D N P Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One Reference Clock Differential input These pins provide the PLL reference clock differential input into the processor 100 MHz typical BCLKO is the Intel QPI reference clock system clock and is the PCI Express reference clock 118 Signal Descriptions 6 7 J TAG and TAP Signals Table 6 11 JTAG and TAP Signals Signal Name Description BPM N 7 0 Breakpoint and Performance Monitor Signals 1 0 signals from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance These are 100 MHz signals EAR N Exter
282. recommends the processor be first in the TAP chain followed by any other components within the system Please refer to the Intel Xeon Processor E5 2400 v2 Product Family Boundary Scan Description Language BSDL File for more details A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level 7 1 8 Processor Sideband Signals The processor include asynchronous sideband signals that provide asynchronous input output 1 0 signals between the processor and the platform or Platform Controller Hub Details can be found in Table 7 5 and the applicable platform design guide Processor Asynchronous Sideband input signals are required to be asserted deasserted for a defined number of BCLKs in order for the processor to recognize the proper signal state Refer to Section 7 9 for applicable signal integrity specifications 7 1 9 Power Ground and Sense Signals Processors also include various other signals including power ground and sense points Details can be found in Table 7 5 and the applicable platform design guide 7 1 9 1 Power and Ground Lands All Vcc VccPLL VTD lands must be connected to their respective processor power planes while all Vss lands must be connected to the system ground plane Refer to the Platf
283. resis 0 05 Vir V 1 Buffer On Resistance 4 14 2 Signals SVIDCLK SVIDDATA lu Input Leakage Current 50 200 uA 3 4 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 147 Table 7 20 Serial VID Interface SVID DC Specifications Sheet 2 of 2 Symbol Parameter Min Typ Max Units Notes Input Edge Rate 0 05 V ns 5 6 Signal SVIDALERT_N Output Edge Rate 50 ohm to Vm 0 20 1 5 V ns 5 Notes 1 Vr refers to instantaneous Vr 2 Measured at 0 31 3 Vin between and 4 Refer to the Platform Design Guide PDG for routing design guidelines 5 These are measured between VIL and VIH 6 The signal edge rate must be met or the signal must transition monotonically to the asserted state Table 7 21 Processor Asynchronous Sideband DC Specifications Symbol Parameter Min Max Units Notes CMOS1 0v Signals 51 0 Input Low Voltage 0 3 Vir V 12 CMOS1 0v Input High Voltage 0 7 V M 12 Viysteresis Hysteresis 0 1 V T liL 51 0 Input Leakage Current 50 200 1 2 Open Drain CMOS ODCMOS Signals 5 Input Low Voltage 0 3 Vi V 1 2 Signals MEM HOT 01 23 5 Input Low Voltage 0 4 V 12 Signals ERR 5 Input High Voltage 0 7 Vt 1 2 VoL
284. rocessor to adjust its operating frequency via the core ratio multiplier and VCC input voltage via the SVID signals This combination of reduced frequency and voltage results in a reduction to the processor power consumption 5 2 2 1 Frequency SVID Control This method includes multiple operating points each consisting of a specific operating frequency and voltage The first operating point represents the normal operating condition for the processor The remaining points consist of both lower operating frequencies and voltages When the TCC is activated the processor automatically transitions to the new lower operating frequency This transition occurs very rapidly on the order of microseconds Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new SVID code to the VCC voltage regulator The voltage regulator must support dynamic SVID steps to support this method During the voltage change it will be necessary to transition through multiple SVID codes to reach the target operating voltage Each step will be one SVID table entry see Table 7 3 12 0 Reference Code Voltage Identification VID Table The processor continues to execute instructions during the voltage transition Operation at the lower voltages reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the
285. rs PCI Express Port 1 Signals Signal Name Description DN 3 0 DP 3 0 Receive Data Input DN 7 4 DP 7 4 PCle Receive Data Input TX DN 3 0 TX DP 3 0 PCle Transmit Data Output TX DN 7 4 PElB TX DP 7 4 PCle Transmit Data Output PCI Express Port 3 Signals Sheet 1 of 2 Signal Name Description PE3A RX DN 3 0 PE3A RX DP 3 0 PCIe Receive Data Input PE3B RX DN 7 4 PE3B RX DP 7 4 Receive Data Input PE3C RX DN 11 8 PE3C RX DP 11 8 PCle Receive Data Input Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 116 Signal Descriptions Table 6 4 Express Port 3 Signals Sheet 2 of 2 Signal Name Description PE3D RX DN 15 12 PE3D DP 15 12 PCI e Receive Data Input PE3A TX DN 3 0 PE3A TX DP 3 0 Transmit Data Output PE3B TX DN 7 4 PE3B TX DP 7 4 Transmit Data Output PE3C TX DN 11 8 PE3C TX DP 11 8 PCIe Transmit Data Output PE3D TX DN 15 12 PE3D TX DP 15 12 Transmit Data Output Table 6 5 PCI Express Miscellaneous Signals Signal Name Description PE RBIAS This input is used to control PCI Express bias currents A 50 ohm 196 tolerance resistor must be connected from this land to VSS by the pla
286. rs a wakeup on an interrupt even if interrupts are masked by EFLAGS IF Core C states The following are general rules for all core C states unless specified otherwise A core C State is determined by the lowest numerical thread state e g Thread 0 requests 1 while Thread 1 requests resulting in a core CIE state See Table 4 7 core transitions to CO state when an interrupt occurs there is an access to the monitored address if the state was entered via an MWAIT instruction For core C1 C1E and core C3 an interrupt directed toward a single thread wakes only that thread However since both threads are no longer at the same core C state the core resolves to CO An interrupt only wakes the target thread for both C3 and C6 states Any interrupt coming into the processor package may wake any core Core CO State The normal operating state of a core where code is being executed Core C1 State 1 is a low power state entered when all threads within a core execute HLT or MWAI T C1 CIE instruction A System Management Interrupt SMI handler returns execution to either Normal state or the 1 state See the Intel 64 and 32 Architecture Software Developer s Manual Volume 3A 3B System Programmer s Guide for more information Intel Xeon Processor E5 2400 v2 Product Family 90 Datasheet Volume One intel 4 2 4 3 4 2 4 4 4 2 4 5 4 2 5 While a co
287. rt The specifications are set so that a voltage regulator can operate with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two processor units with the same core frequency may have different default VID settings The processor uses voltage identification signals to support automatic selection of and Vccp power supply voltages If the processor socket is empty SKTOCC high or a not supported response is received from the SVID bus then the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself or not power on Vout MAX register 30h is programmed by the Intel Xeon Processor E5 2400 v2 Product Family 127 Datasheet Volume One processor to set the maximum supported VID code if the programmed VID code is higher than the VID supported by the VR then VR will respond with a not supported acknowledgement See the VR12 IMVP7 Pulse Width Modulation Specification for further details 7 1 9 3 1 SVI D Commands The processor provides the ability to operate while transitioning to a new VID setting and its associated processor voltage rails Vcc and This is represented by a DC shift It should be noted that low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target voltage Transitions above the maximum specified VID are n
288. rt all optional but desirable features from all processors of interest Each feature has a discovery method and response code that indicates availability on the destination PECI client The first step in the enumeration process would be for the host to confirm the Revision Number through the use of the GetDIB command The revision number returned by the PECI client processor always maps to the revision number of the PECI specification that it is designed to The Minor Revision Number as described in Table 2 2 may be used to identify the subset of commands that the processor in question supports for any major PECI revision The next step in the enumeration process is to utilize the desired command suite in a real execution context If the Write FCS response is an Abort FCS or if the data returned includes Unknown Invalid lllegal Request completion code 0x90 then the command is unsupported Enumerating known commands without real execution context data or attempting undefined commands is dangerous because a write command could result in unexpected behavior if the data is not properly formatted Methods for enumerating write commands using carefully constructed and innocuous data are possible but are not guaranteed by the PECI client definition This enumeration procedure is not robust enough to detect differences in bit definitions or data interpretation in the message payload or client response Instead it is only
289. s de asserted This signal can also be asserted if the system memory interface has exceeded a critical temperature limit set by BIOS This signal is sampled after PWRGOOD assertion TXT_AGENT Intel Trusted Execution Technology Intel TXT Agent Strap 0 Default The socket is not the Intel TXT Agent 1 The socket is the Intel TXT Agent In non Scalable DP platforms the legacy socket identified by SOCKET 1011 01 00b with Intel TXT Agent should always set the TXT_AGENT to 1b On Scalable DP platforms the TXT AGENT is at the Node Controller Refer to the Platform Design Guide PDG for more details This signal is pulled down on the die refer to Table 7 6 for details TXT_PLTEN Intel Trusted Execution Technology Intel TXT Platform Enable Strap 0 The platform is not Intel TXT enabled All sockets should be set to zero Scalable DP sDP platforms should choose this setting if the Node Controller does not support Intel TXT 1 Default The platform is Intel TXT enabled All sockets should be set to one In a non Scalable DP platform this is the default When this is set Intel TXT functionality requires user to explicitly enable Intel TXT via BIOS setup This signal is pulled up on the die refer to Table 7 6 for details For further details see Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers Table 6 14 Miscellaneous Signals Signal Name Descri
290. s and may be derived from actual platform characterization data The Scaling Factor is used to convert memory transaction information to energy units in Joules and can be derived from system memory configuration information Refer to the processor BIOS Writer s Guide for methods to program and access Scaling Factor information Figure 2 12 DRAM Thermal Estimation Configuration Data 31 20 19 10 9 RESERVED THETA VARIABLE BETA VARIABLE Memory Thermal Estimation Configuration Data 0 Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 39 intel 2 5 2 6 3 DRAM Rank Temperature Write This feature allows the PECI host to program into the processor the temperature for all the ranks within a DIMM up to a maximum of four ranks as shown in Figure 2 13 The DIMM index and Channel index are specified through the parameter field as shown in Table 2 7 This write is relevant in platforms that do not have on die or on board DIMM thermal sensors to provide memory temperature information or if the processor does not have direct access to the DIMM thermal sensors This temperature information is used by the processor in conjunction with the activity based DRAM temperature estimations Table 2 7 Channel amp DIMM Index Decoding Index Encoding Physical Channel Physical DIMM 000 Reserved 0 001 1 1 010 2 Reserved 011 3 Reserved Figure 2 13 DRAM Rank Temperature Write Dat
291. so less memory and bandwidth is required The key advantages of Intel AVX are Performance Intel AVX can accelerate application performance via data parallelism and scalable hardware infrastructure across existing and new application domains 256 bit vector data sets can be processed up to twice the throughput of 128 bit data sets Application performance can scale up with number of hardware threads and number of cores Intel Xeon Processor E5 2400 v2 Product Family 83 Datasheet Volume One Technologies intel Application domain can scale out with advanced platform interconnect fabrics such as Intel Power Efficiency Intel AVX is extremely power efficient Incremental power is insignificant when the instructions are unused or scarcely used Combined with the high performance that it can deliver applications that lend themselves heavily to using Intel AVX can be much more energy efficient and realize a higher performance per watt Extensibility AVX has built in extensibility for the future vector extensions OS context management for vector widths beyond 256 bits is streamlined Efficient instruction encoding allows unlimited functional enhancements Vector width support beyond 256 bits 256 bit Vector Integer processing Additional computational and or data manipulation primitives Compatibility Intel AVX is backward compatible with previous ISA extensions including Int
292. sor must meet the specifications in Table 7 14 when measured across the VCC_SENSE and VSS_VCC_SENSE lands Overshoot events that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope Figure 7 4 Load Current Versus Time 7 8 2 1 Load Current vs Time 1 0s 5 05 100 05 IccTDC 20 0s v v v 1 0s 5 0s 10 0s 20 0s 100 0s Notes 1 peak current for any 5 second sample does not exceed max 2 The average current for any 10 second sample does not exceed the Y value at 10 seconds 3 The average current for any 20 second period or greater does not exceed tdc 4 Turbo performance may be impacted by failing to meet durations specified in this graph Ensure that the platform design can handle peak and average current based on the specification Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than 6 Not 100 tested Specified by design characterization m Vcc Overshoot Specifications The processor can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot above VID These specifications apply to the processor die voltage
293. sources for servicing this command at this time Retry is appropriate CC 0x90 Unknown Invalid Illegal Request CC 0x91 PECI control hardware firmware or associated logic error The processor is unable to process the request Package Configuration Capabilities Table 2 6 combines both read and write services Any service listed as a read would use the RdPkgConfig command and a service listed as a write would use the WrPkgConfig command PECI requests for memory temperature or other data generated outside the processor package do not trigger special polling cycles on the processor memory or SMBus interfaces to procure the required information DRAM Thermal and Power Optimization Capabilities DRAM thermal and power optimization also known as RAPL or Running Average Power Limit services provide a way for platform thermal management solutions to program and access DRAM power energy and temperature parameters Memory temperature information is typically used to regulate fan speeds tune refresh rates and throttle the memory subsystem as appropriate Memory temperature data may be derived from a variety of sources including on die or on board DIMM sensors DRAM activity information or a combination of the two Though memory temperature data is a byte long range of actual temperature values are determined by the DIMM specifications and operating range DRAM related PECI services described in this section apply only to
294. ss 2 0 8 Gb s Express 3 0 is backward compatible with Express 1 0 and 2 0 PCI Express 2 0 PCI Express Generation 2 0 PCI Express PCI Express Generation 2 0 3 0 PECI Platform Environment Control Interface Phit Physical Unit An Intel QPI terminology defining units of transfer at the physical layer 1 Phit is equal to 20 bits in full width mode and 10 bits in half width mode Processor The 64 bit single core or multi core component package Processor Core The term processor core refers to silicon die itself which can contain multiple execution cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the L3 cache All DC and AC timing and signal integrity specifications are measured at the processor die pads unless otherwise noted Protected Processor A solution for inventory management available on Intel Xeon processor E5 Inventory Number PPIN product families for use in server platforms PPIN defaults to disabled and follows an opt in model to enable it Once is enabled a reboot is necessary to make it available to privileged software such as the OS or VMM and other ring 0 applications RDIMM Registered Dual In line Module Intel Xeon Processor E5 2400 v2 Product Family 21 Datasheet Volume One Overview 1 7 intel Term Description Rank A unit of DRAM corresponding four to eight devices in parallel
295. ssert CAT ERR N for nonrecoverable machine check errors and other internal unrecoverable errors It is expected that every processor in the system will wire OR CAT ERR N for all processors Since this is an 1 land external agents are allowed to assert this land which will cause the processor to take a machine check exception This signal is sampled after PWRGOOD assertion On the processor CAT ERR N is used for signaling the following types of errors Legacy MCERRS CAT ERR N is asserted for 16 BCLKs Legacy IERR s CAT ERR N remains asserted until warm or cold reset CPU ONLY RESET Reserved not used ERROR N 2 0 FRMAGENT Error status signals for integrated I O unit 0 Hardware correctable error no operating system or firmware action necessary e 1 Non fatal error operating system or firmware action required to contain and recover 2 Fatal error system reset likely required to recover Bootable Firmware Agent Strap This input configuration strap used in combination with SOCKET ID to determine whether the Socket is a legacy socket bootable firmware agent is present and DMI links are used in PCI e mode instead of DMI2 mode The firmware flash ROM is located behind the local PCH attached to the processor via the DMI2 interface This signal is pulled down on the die refer to Table 7 6 for details For further details see Intel Xeon Processor 5 v2 Product Family Datasheet Volume Two
296. sserted for more than 100 ms while PWRGOOD is asserted RESET N must be held asserted for at least 3 5 millisecond before it is deasserted again RESET N must be held asserted before PWRGOOD is asserted This signal does not have on die termination and must be terminated on the system board PCI Express AC Specifications The processor AC specifications for the PCI Express are available in the PCI Express Base Specification Revision 3 0 This document will provide only the processor exceptions to the PCI Express Base Specification Revision 3 0 Intel Xeon Processor E5 2400 v2 Product Family 149 Datasheet Volume One intel The processor AC specifications for the Express are available in the Express Base Specification 2 0 and 1 0 This document will provide only the processor exceptions to the PCI Express Base Specification 2 0 and 1 0 7 8 3 6 DMI 2 PCI Express AC Specifications 7 8 3 7 Intel QuickPath I nterconnect AC Specifications Intel QuickPath Interconnect specifications are defined at the processor lands Please refer to the appropriate platform design guidelines for specific implementation details The processor AC specifications for the Intel interface are available in the Intel QuickPath Interconnect V1 1 Base Electrical Specification and Validation Methodologies This document will provide only the processor exceptions to the Intel QuickPath Interconnect V1 1 Base Electrical Specificat
297. sss nn 118 6 5 SIONAL TC EO MEE 118 6 6 System Reference Clock 5 118 67 JTAG and WAP 59 deter dada ade ne een T 119 6 8 Serial VID Interface SVID 5 4 1 0 22 4 6 119 6 9 Processor Asynchronous Sideband and Miscellaneous 5 119 6 10 Processor Power and Ground ens 123 7 Electrical 5 1111 124 Intel Xeon Processor E5 2400 v2 Product Family 5 Datasheet Volume One 71 55 Signaling RDUM E EE EIER 124 7 1 1 System Memory Interface Signal 124 141 2 PCI Express Signals roi pops Dee A 124 7 1 3 2 Express 5 124 7 1 4 Intel QuickPath Interconnect Intel 124 7 1 5 Platform Environmental Control Interface 125 7 1 5 1 Input Device 125 7 1 6 System Reference Clocks BCLK 0 1 DP 1 125 7 1 6 1 Power S pply eei eeepc eet asda ier eet e vede aed 126 7 1 7 JTAG and
298. st remain within the minimum and maximum case temperature Tease specifications as defined by the applicable thermal profile Thermal solutions not designed to provide sufficient thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG The processors implement a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI as described in Section 2 5 Platform Environment Control Interface PECI If the DTS value is less than then the case temperature is permitted to exceed the Thermal Profile but the DTS value must remain at or below TCONTROL For Tcase implementations if DTS is greater than TCONTROL then the case temperature must meet the based Thermal Profiles For DTS implementations e Tcase thermal profile can be ignored during processor run time f DTS is greater than Tcontrol then follow DTS thermal profile specifications for fan speed optimization Intel Xeon Processor E5 2400 v2 Product Family 98 Datasheet Volume One Thermal Management Specif
299. step size during 5 0 mV 10 Vcc Vsa transition Vccd VccPLL PLL Voltage VccPLL 0 955 Vccpi 1 70 1 045 V 11 12 13 7 B 17 Vccp Voltage for Vccp 0 95 Vccp TYP 1 50 1 05 Vccp TYP V 11 13 14 DDR3 Standard 16 17 Voltage Vccp Voltage for Vccp 0 95 Vccp TYP 1 35 1 075 TYP V 11 13 14 DDR3L Low 16 17 Voltage Vra Uncore Voltage 0 957 Vir TYP 1 00 1 043 V41 TYP V 3 5 9 12 VTD Launch FMB T 13 VsA VID Range 0 60 0 940 1 25 V 2 3 14 15 System Agent Vsa Vsa 0 057 VID Vsa vip 0 057 V 3 6 12 Voltage E 14 19 Launch Notes 1 Unless otherwise noted all specifications in this table apply to all processors These specifications are based on final silicon characterization 2 Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different settings 3 Voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required 4 The voltage specification requirements are measured across the remote sense pin pairs SENSE and VSS VCC SENSE on the processor package Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit or DC to 20 MHz for older model oscilloscopes using a 1 5 pF maximum probe
300. stic Random Bit Generator NRBG Intel OS Guard This was formerly known as Supervisor Mode Execution Protection SMEP Supervisor Mode Execution Protection Bit SMEP prevents execution and calls to the operating system by compromised application in the user mode or code pages This also allows additional malware protection over existing Intel XD bit technology Intel Hyper Threading Technology The processor supports Intel Hyper Threading Technology Intel HT Technology which allows an execution core to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled via the BIOS and requires operating system support For enabling details please refer to the Intel Xeon Intel Xeon Processor E5 2400 v2 Product Family 81 Datasheet Volume One Technologies 3 6 3 6 1 Note 3 7 intel Processor E5 v2 Product Family Datasheet Volume Two Registers for enabling details For more information on Intel Hyper Threading Technology see http www intel com products ht hyperthreading_more htm Intel Turbo Boost Technology Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below powe
301. t 1 82 3 6 1 Intel Turbo Boost Operating 1 2 82 3 7 Enhanced Intel SpeedStep Technology 82 3 8 Intel Intelligent Power Technology 83 3 9 Intel Advanced Vector Extensions Intel 1 1 1 83 3 10 Intel Dynamic Power Technology 84 4 Power Managemo ant rentrer rend nace ene fas acc n ha a da ia 85 4 1 States 5 esee eene nennen nnn 85 4 1 1 System States s E RERO ETE 85 4 1 2 Processor Package and Core 85 4 1 3 Integrated Memory Controller States 86 4 1 4 DMI2 PCI Express Link States 87 4 1 5 Intel QuickPath Interconnect States 87 4 1 6 S and C State Combinations 87 4 2 Processor Core Package Power 88 4 2 1 Enhanced Intel SpeedStep Technology 88 4 2 2 Low Power Idle States 88 4 2 3 Requesting Low Power Idle
302. t may configure this window as a power of two For example programming a value of 5 results in a filtering window of 2 or 32 samples The maximum programmable value is 8 or 256 samples Programming a value of zero would disable the PECI temperature averaging feature The default value of the thermal averaging constant is 4 which translates to an averaging window size of 24 16 samples More details on the temperature filtering function can be found in Section 2 5 7 3 Intel Xeon Processor E5 2400 v2 Product Family 53 Datasheet Volume One intel Figure 2 32 Thermal Averaging Constant Write Read 5 4 3 0 Temperature RESERVED Averaging Constant Thermal Averaging Constant 2 5 2 6 22 Thermally Constrained Time Read This features allows the host to access the total time for which the processor has been operating in a lowered power state due to TCC activation The returned data includes the time required to ramp back up to the original P state target after TCC activation expires This timer does not include TCC activation as a result of an external assertion of PROCHOT_N This is tracked by a 32 bit counter with a resolution 1mS per count that rolls over or wraps around On the processor PECI clients the only logic that can be thermally constrained is that supplied by VCC 2 5 2 6 23 Current Limit Read This read returns the current limit for the processor VCC power plane in 1 8A increments
303. t this time Retry is appropriate CC 0x82 The processor hardware resources required to service this command are in a low power state Retry may be appropriate after modification of PECI wake mode behavior if appropriate CC 0x90 Unknown Invalid lllegal Request CC 0x91 PECI control hardware firmware or associated logic error The processor is unable to process the request WrPCI ConfigLocal The WrPCI ConfigLocal command provides sideband write access to the PCI configuration space that resides within the processor PECI originators can access this space even before BIOS enumeration of the system buses The exact listing of supported devices and functions for writes using this command on the processor is defined in Table 2 19 The write accesses to registers that are locked will not take effect but will still return a completion code of 0x40 However write accesses to registers that are hidden will return a completion code of 0x90 Because a WrPCI ConfigLocal command results in an update to potentially critical registers inside the processor it includes an Assured Write FCS AW FCS byte as part of the write data payload Refer to the RS Platform Environment Control Interface PECI Specification Rev 3 0 for the definition of the AW FCS protocol In the event that the AW FCS mismatches with the client calculated FCS the client will abort the write and will always respond with a bad write FCS PCI Configura
304. tel processors chipsets and 1 bridge components Intel 64 Technology 64 bit memory extensions to the 32 architecture Further details on Intel 64 architecture and programming model can be found at http developer intel com technology intel64 Intel Turbo Boost Intel Turbo Boost Technology is a way to automatically run the processor core Technology faster than the marked frequency if the part is operating under power temperature and current specifications limits of the Thermal Design Power TDP This results in increased performance of both single and multi threaded applications Intel Xeon Processor E5 2400 v2 Product Family 20 Datasheet Volume One intel Overview Term Description Intel TXT Intel Trusted Execution Technology Intel Virtualization Processor virtualization which when used in conjunction with Virtual Machine Technology Intel VT Monitor software enables multiple robust independent software environments inside a single platform Intel VT d Intel Virtualization Technology Intel VT for Directed I O Intel VT d is hardware assist under system software Virtual Machine Manager or OS control for enabling 1 device virtualization Intel VT d also brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d Intel X
305. terface 2 DMI2 connects the processor to the Platform Controller Hub PCH DMI2 is similar to a four lane PCI Express supporting a speed of 5 GT s per lane This interface can be configured at power on to serve as a x4 PCI Express link based the setting of the SOCKET 10 1 0 and FRMAGENT signal for processors not connected to a PCH Refer to the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers for additional details Only DMI2 x4 configuration is supported DMI 2 Error Flow DMI2 can only generate SERR in response to errors never SCI SMI MSI PCI INT or GPE Any DMI2 related SERR activity is associated with Device 0 Processor PCH Compatibility Assumptions The processor is compatible with the PCH and is not compatible with any previous MCH or ICH products DMI 2 Link Down The DMI2 link going down is a fatal unrecoverable error If the DMI2 data link goes to data link down after the link was up then the DMI2 link hangs the system by not allowing the link to retrain to prevent data corruption This is controlled by the PCH Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal No completions from downstream non posted transactions are returned upstream over the DMI2 link after a link down event Intel Xeon Processor E5 2400 v2 Product Family 27 Datasheet Volume One Interfaces 2 4 intel Intel
306. tes the desired data return size This command supports only dword responses on the processor clients All command responses are prepended with a completion code that contains additional pass fail status information Refer to Section 2 5 5 2 for details Intel Xeon Processor E5 2400 v2 Product Family 34 Datasheet Volume One regarding completion codes Figure 2 10 RdPkgConfig 0 1 2 3 Write Length Read Length Cmd Code Byte Client Address 0x05 gt 0 05 9 Definition 4 5 6 7 8 Host ID 7 1 amp 10 11 12 13 14 9 Completion LSB Data 4 bytes MSB FCS Note 2 byte parameter field 4 byte read data field defined in Figure 2 10 are sent in standard ordering with LSB first and MSB last 2 5 2 4 2 Supported Responses The typical client response is a passing FCS a passing Completion Code and valid data Under some conditions the client s response will indicate a failure Table 2 4 RdPkgConfig Response Definition Response Meaning Bad Write FCS Electrical error Abort FCS Illegal command formatting mismatched RL WL Command Code CC 0x40 Command passed data is valid CC 0x80 Response timeout The processor is not able to generate the required response in a timely fashion Retry is appropriate CC 0x81 Response timeout The processor is not able to allocate resources for servicing this command at this time Retry is appropriate CC 0x90
307. tform PE RBIAS is required to be connected as if the link is being used even when PCle is not used Refer to the Platform Design Guide PDG for further details PE RBIAS SENSE Provides dedicated bias resistor sensing to minimize the voltage drop caused by packaging and platform effects PE RBIAS SENSE is required to be connected as if the link is being used even when PCle is not used Refer to the Platform Design Guide PDG for further details PE VREF CAP PCI Express voltage reference used to measure the actual output voltage and comparing it to the assumed voltage A 0 01uF capacitor must be connected from this land to VSS PEHPSCL PCI Express Hot Plug SMBus Clock Provides PCI Express hot plug support via a dedicated SMBus interface Requires an external general purpose input output GPIO expansion device on the platform PEHPSDA PCI Express Hot Plug SMBus Data Provides PCI Express hot plug support via a dedicated SMBus interface Requires an external general purpose input output GPIO expansion device on the platform Note Refer to the Platform Design Guide for additional implementation details 6 3 DMI 2 PCI Express Port Signals Table 6 6 DMI2 and PCI Express Port 0 Signals Signal Name Description DN 3 0 DP 3 0 DMI2 Receive Data Input DMI_TX_DP 3 0 DMI_TX_DN 3 0 DMI2 Transmit Data Output Intel Xeon Proc
308. the memory connected to the specific processor PECI client in question and not the overall platform memory in general For estimating DRAM thermal information in closed loop throttling mode a dedicated SMBus is required between the CPU and the DIMMs The processor PCU requires access to the VR12 voltage regulator for reading average output current information through the SVID bus for initial DRAM RAPL related power tuning Table 2 6 provides a summary of the DRAM power and thermal optimization capabilities that can be accessed over PECI on the processor The I ndex values referenced in Table 2 6 are in decimal format Table 2 6 also provides information on alternate inband mechanisms to access similar or equivalent information through register reads and writes where applicable The user should consult the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers or the Intel Xeon Processor E5 v2 Product Family Datasheet Volume Two Registers for exact details on MSR or CSR register content Intel Xeon Processor E5 2400 v2 Product Family 37 Datasheet Volume One intel Table 2 6 RdPkgConfig amp WrPkgConfig DRAM Thermal and Power Optimization Services Summary Sheet 1 of 2 Parameter RdPkgConfig WrPkgConfig Alternate Value Data Data Inband Service Value d d d d d Description MSR or CSR i wor decimal ACCESS DRAM DRAM
309. thin specifications Snooping and interrupt processing are performed in the normal manner while the TCC is active With a properly designed and characterized thermal solution it is anticipated that the TCC would be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result in a that exceeds the specified maximum temperature which may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG for information on designing a compliant thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Intel Xeon Processor E5 2400 v2 Product Family 109 Datasheet Volume One intel The processor uses Frequency SVID control whereby TCC activation causes the p
310. tiating down to narrower widths there are caveats as to how lane reversal is supported Non Transparent Bridge is supported by PCle Port3a l OU1 For more details on NTB mode operation refer to PCI Express Base Specification Revision 3 0 x4 or x8widths and at PCle 1 0 2 0 3 0 speeds Two usage models NTB attached to a Root Port or NTB attached to another NTB Supports three 64 bit BARs Supports posted writes and non posted memory read transactions across the NTB Supports INTx MSI and MSI X mechanisms for interrupts on both side of NTB in upstream direction only Address Translation Services ATS 1 0 support Hierarchical PCl compliant configuration mechanism for downstream devices Traditional PCI style traffic asynchronous snooped PCI ordering Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI compatibility configuration space The remaining Intel Xeon Processor E5 2400 v2 Product Family 16 Datasheet Volume One intel Overview portion of the fixed 4 KB block of memory mapped space above that starting at 100h is known as extended configuration space PCI Express Enhanced Access Mechanism Accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Supports receiving and decoding 64 bits of address from PCI
311. tion No 2 3 4 5 Retention Snoop Response Time OFF in C3 e Interrupt Response Time Non Snoop Response Time PC6 6 LLC ways open Vcc retention No 2 3 4 5 Deeper Snoop Response Time PLL OFF Retention Non Snoop Response Time nterrupt Response Time Notes 1 Package C7 is not supported 2 All package states are defined to be E states such that they always exit back into the LFM point upon execution resume 3 The mapping of actions for PC3 and PC6 are suggestions microcode will dynamically determine which actions should be taken based on the desired exit latency parameters 4 CC3 CC6 will all use a voltage below the VccMin operational point The exact voltage selected will be a function of the snoop and interrupt response time requirements made by the devices PCle and DMI and the operating system 5 The processor supports retention voltage during package C3 and package C6 See Section 7 8 1 Voltage and Current Specifications for retention voltage details Table 4 3 Core C State Support Core C State Global Clock PLL L1 L2 Cache Core VCC Context CCO Running On Coherent Active Maintained 1 Stopped On Coherent Active Maintained CC1E Stopped On Coherent Request LFM Maintained Stopped On Flushed to LLC Request Retention Maintained CCb Stopped Off Flushed to LLC Power Gate Flushed to LLC 4 1 3 I ntegrated Memory Controller States Table 4 4 System Memory Power States Sheet 1
312. tion addresses are constructed as shown in Figure 2 46 The write command is subject to the same address configuration rules as defined in Section 2 5 2 9 PCI configuration writes may be issued in byte word or dword granularity Command Format The WrPCI ConfigLocal format is as follows Write Length 0x07 byte 0x08 word dword Intel Xeon Processor E5 2400 v2 Product Family 66 Datasheet Volume One Read Length 0x01 Command 5 AW FCS Support Yes Description Writes the data sent to the requested register address Write Length dictates the desired write granularity The command always returns a completion code indicating pass fail status Refer to Section 2 5 5 2 for details on completion codes Figure 2 48 WrPCI ConfigLocal Byte 0 1 2 3 Write Length Read Length Cmd Code i mie Dis id 19x95 008 Oxoa Definition 4 5 6 7 Host ID 7 1 amp Retry 0 PCI Configuration Address MSB 8 9 10 11 LSB Data 1 2 or 4 bytes MSB Completion Code Note The 3 byte PCI configuration address and write data field defined in Figure 2 48 are sent in standard PECI ordering with LSB first and MSB last 2 5 2 10 2 Supported Responses The typical client response is a passing FCS a passing Completion Code and valid data Under some conditions the client s response will indicate a failure The PECI client response can also vary depending on the address and data It will respond with a p
313. tivity labeling MSL as indicated on the packaging material TAC Thermal Averaging Constant TDP Thermal Design Power TSOD Thermal Sensor on DIMM UDIMM Unbuffered Dual In line Module Uncore The portion of the processor comprising the shared cache IMC HA PCU UBox and Intel QPI link interface Unit Interval Signaling convention that is binary and unidirectional In this binary signaling one bit is sent for every edge of the forwarded clock whether it be a rising edge a falling edge If a number of edges are collected at instances t t t t then the UI at instance n is defined as Ul t t 1 Processor core power supply Vss Processor ground Vccp Variable power supply for the processor system memory interface x1 Refers to a Link or Port with one Physical Lane x4 Refers to a Link or Port with four Physical Lanes x8 Refers to a Link or Port with eight Physical Lanes x16 Refers to a Link or Port with sixteen Physical Lanes Related Documents Refer to the following documents for additional information Datasheet Volume One Table 1 3 Related Documents and Specifications Sheet 1 of 2 Document Document Number Location Intel Xeon Processor E5 v2 Product Family Datasheet Volume www intel com Two Registers Advanced Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 h
314. to BIOS enumeration of the system buses There is no read restriction on accesses to locked registers PCI configuration addresses are constructed as shown in Figure 2 46 Under normal in band procedures the Bus number would be used to direct a read or write to the proper device PECI reads to the processor IIO devices should specify a bus number of 0000 and reads to the rest of the processor uncore should specify a bus number of 0001 for bits 23 20 in Figure 2 46 Any request made with a bad Bus number is ignored and the client will respond with all 0 s and a passing completion code Figure 2 46 PCI Configuration Address for local accesses 23 20 19 15 14 12 11 0 Bus Device Function Register 2 5 2 9 1 Command Format The RdPCI ConfigLocal format is as follows Write Length 0x05 Read Length 0x02 byte 0x03 word 0x05 dword Command 1 Description Returns the data maintained in the PCI configuration space within the processor at the requested PCI configuration address The Read Length dictates the desired data return size This command supports byte word and dword responses as well as a completion code All command responses are prepended with a completion code that includes additional pass fail status information Refer to Section 2 5 5 2 for details regarding completion codes Figure 2 47 RdPCI ConfigLocal Byte 0 1 2 3 Write Length Read Length Cmd
315. ts that do not require NEBS Level 3 compliance The Short Term Thermal Profile may only be used for short term excursions to higher ambient operating temperatures not to exceed 96 hours per instance 360 hours per year and a maximum of 15 instances per year as intended by NEBS Level 3 Operation at the Short Term Thermal Profile for durations exceeding 360 hours per year violate the processor thermal specifications and may result in permanent damage to the processor Implementation of the defined thermal profile should result in virtually no TCC activation Refer to the Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG for system and environmental implementation details Embedded operating case temperature thermal profiles Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at specified maximum Tease Power specifications are defined at all VID values found in Table 7 3 The Intel Xeon processor E5 2400 v2 product family may be delivered under multiple VI Ds for each frequency Implementation of a specified thermal profile should result in virtually no TCC activation Failure to comply with the specified thermal profile will result in increased probability of TCC activation and may incur measurable performance loss Refer to the Intel Xeon Processor E5 2400 v2 Product Family Therma
316. ttp www pcisig com specifications Intel Xeon Processor E5 2400 v2 Product Family 22 Overview Table 1 3 1 8 1 9 intel Related Documents and Specifications Sheet 2 of 2 Document Document Number Location PCI Express Base Specification Revision 2 1 and 1 1 PCI Express Base Specification Revision 3 0 http www pcisig com System Management Bus SMBus Specification http smbus org DDR3 SDRAM Specification http www jedec org Low J ESD22 A119 and High J ESD A103 Temperature Storage Life Specifications http www jedec org Intel 64 and IA 32 Architectures Software Developer s Manuals Volume 1 Basic Architecture Volume 2A Instruction Set Reference A M Volume 2B Instruction Set Reference N Z Volume 3A System Programming Guide Volume 3B System Programming Guide Intel 64 IA 32 Architectures Optimization Reference Manual http www intel com products proce ssor manuals index htm Intel amp Virtualization Technology Specification for Directed 1 Architecture Specification http download intel com technolog y computing vptech Intel r VT for Direct Intel amp Trusted Execution Technology Software Development Guide http www intel com technology sec urity National Institute of Standards and Technology NIST SP800 90 http csrc nist gov publications Pubs SPs html Statement of Volatility S
317. ualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single system Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets Intel Virtualization Technology Intel VT for Intel 64 and 32 Intel Architecture Intel VT x adds hardware support in the processor to improve the virtualization performance and robustness Intel VT x specifications and functional descriptions are included in the Intel 64 and 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals index htm Intel Virtualization Technology Intel VT for Directed 1 Intel VT d adds processor and uncore implementations to support and improve I O virtualization performance and robustness The Intel VI d spec and other Intel VT documents can be referenced at http www intel com technology virtualization index htm Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of 1 platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved reliable virtualized platform By using Intel VT x a VMM is Robust VMMs no longer need to use para virtualization or binary translation This means that they will be able to run
318. uency SVID targets are at their minimum settings It may also be initiated by software at a configurable duty cycle 5 2 3 On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode is distinct from the Adaptive Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the A32 CLOCK MODULATION MSR is set to 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 0 of the same IA32 CLOCK MODULATION MSR In On Demand mode the duty cycle can be programmed from 6 25 93 75 off to 93 75 6 25 off in 6 25 Intel Xeon Processor E5 2400 v2 Product Family 111 Datasheet Volume One 5 2 4 5 2 5 intel increments On Demand mode may be used in conjunction with the Adaptive Thermal Monitor however if the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT_N Signal An external sign
319. ult address of 0x30 The PECI client address for the processor is configured through the settings of the SOCKET_ID 1 0 signals Each processor socket in the system requires that the two SOCKET_ID signals be configured Intel Xeon Processor E5 2400 v2 Product Family 69 Datasheet Volume One Table 2 17 2 5 3 4 intel to a different addresses Strapping the SOCKET_ID 1 0 pins results the client addresses shown in Table 2 17 These package strap s are evaluated at the assertion of PWRGOOD as depicted in Figure 2 49 Refer to the Romley Platform Design Guide for recommended resistor values for establishing non default SOCKET 10 settings The client address may not be changed after PWRGOOD assertion until the next power cycle on the processor Removal of a processor from its socket or tri stating a processor will have no impact to the remaining non tri stated PECI client addresses Since each socket in the system should have a unique PECI address the SOCKET ID strapping is required to be unique for each socket SOCKET ID Strapping C states SOCKET 10111 Strap SOCKET ID O Strap PECI Client Address Ground Ground 0x30 Ground Vir 0x31 Vit Ground 0x32 Va Vu 0x33 The processor PECI client may be fully functional in most core and package C states The Ping GetDIB GetTemp RdPkgConfig and WrPkgConfig commands have no measurable impact on CPU power in any of the core or package C states
320. upply 1 V for the processor phased lock loop PLL VSA Variable power supply for the processor system agent units These include logic non 1 O for the integrated 1 controller the integrated memory controller iMC the Intel agent and the Power Control Unit PCU The output voltage of this supply is selected by the processor using the serial voltage ID SVID bus Note VSA has a Vboot setting of 0 9V Refer to the VR12 I 7 Pulse Width Modulation Specification 55 Processor ground node VITA VTTD Combined fixed analog and digital power supply for I O sections of the processor Intel interface Direct Media Interface Gen 2 DMI 2 interface and PCI Express interface These signals will also be referred to as VTT Please see the Platform Design Guide PDG for implementation details Intel Xeon Processor E5 2400 v2 Product Family Datasheet Volume One 8 123 Electrical Specifications n tel 7 Electrical Specifications 7 1 Processor Signaling The processor includes 1356 lands which utilize various signaling technologies Signals are grouped by electrical characteristics and buffer type into various signal groups These include DDR3 Reference Clock Command Control and Data PCI Express DMI2 Intel QuickPath Interconnect Platform Environmental Control Interface PECI System Reference Clock SMBus JTAG and Test Access Port TAP SVID Interface
321. ve specifications equal to the FMB value in the foreseeable future System designers should meet the FMB values to ensure their systems will be compatible with future processors 7 7 Absolute Maximum and Minimum Ratings Table 7 9 specifies absolute maximum and minimum ratings At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits Although the processor contains protective circuitry to resist damage from Electro Static Discharge ESD precautions should always be taken to avoid high static voltages or electric fields Table 7 9 Processor Absolute Minimum and Maximum Ratings Symbol Parameter Min Max Unit Vcc Processor core voltage with respect to Vss 0 3 1 4 V VccPLL Processor PLL voltage with respect to Vss 0 3 2 0 V Vccp Processor IO supply voltage for DDR3 0 3 1 85 V standard voltage with respect to Vss Vccp Processor IO supply voltage for DDR3L low 0 3 1 7 V Voltage with respect to Vss Processor SA voltage with respect to Vss 0 3 1 4 Processor analog 10 voltage with r
322. vements to this processor generation are Intel Network Power Management Technology Intel Power Tuning Technology For more information on Intel Intelligent Power Technology see this link http www intel com technology intelligentpower Intel Advanced Vector Extensions Intel AVX Intel Advanced Vector Extensions Intel AVX is a 256 bit vector SIMD extension of Intel Architecture that continues with the processor Intel AVX accelerates the trend of parallel computation in general purpose applications like image video and audio processing engineering applications such as 3D modeling and analysis scientific simulation and financial analysts Intel AVX is a comprehensive ISA extension of the Intel 64 Architecture The main elements of Intel AVX are Support for wider vector data up to 256 bit for floating point computation Efficient instruction encoding scheme that supports operand syntax and headroom for future extensions Flexibility in programming environment ranging from branch handling to relaxed memory alignment requirements New data manipulation and arithmetic compute primitives including broadcast permute fused multiply add etc Floating point bit depth conversion Float 16 A group of 4 instructions that accelerate data conversion between 16 bit floating point format to 32 bit and vice versa This benefits image processing and graphical applications allowing compression of data
323. vironment AC Specifications Intel Current mode 6 4 GT s and 8 0 GT s forwarded clock Intel QuickPath Interconnect signaling Open Drain CMOS Open Drain CMOS ODCMOS buffers 1 0V tolerant PCI Express PCI Express interface signals These signals are compatible with PCI Express 3 0 Signalling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Refer to the PCle specification Reference Voltage reference signal SSTL Source Series Terminated Logic J EDEC SSTL_15 Notes 1 Qualifier for a buffer type Table 7 5 Signal Groups Sheet 1 of 3 Differential Single Ended 9 Buffer Type Signals DDR3 Reference Clocks Differential SSTL Output DDR 1 2 3 D N P 3 0 DDR3 Command Signals Single ended SSTL Output DDR 1 2 3 _BA 2 0 DDR 1 2 3 _CAS_N DDR 1 2 3 _MA 15 00 DDR 1 2 3 _MA_PAR DDR 1 2 3 _RAS_N DDR 1 2 3 _WE_N CMOS1 5v Output DDR_RESET_C 1 23 _N DDR3 Control Signals Intel Xeon Processor E5 2400 v2 Product Family 132 Datasheet Volume One Electrical Specifications Table 7 5 Signal Groups Sheet 2 of 3 Diff tial Singl ae ial Single Buffer Type Signals Single ended CMOS1 5v Output DDR 1 2 3 CS 7 01 DDR 1 2 3 _ODT 3 0 DDR 1 2 3 _CKE 3 0 Reference Output DDR_VREFDQTX_C 1 23 Reference Input DDR_VREFDQRX_C 1 23 DDR 1 23 _RCOMP 2 0 DDR3 Data Signals D
324. virtually no TCC activation Thermal Profiles for these SKU s are found in Section 5 1 4 Intel recommends that complete thermal solution designs target the Thermal Design Power TDP The Adaptive Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period To ensure maximum flexibility for future requirements systems should be designed to the Flexible Motherboard FMB guidelines even if a processor with lower power dissipation is currently planned The Adaptive Thermal Monitor feature must be enabled for the processor to remain within its specifications Intel Xeon Processor E5 2400 v2 Product Family 99 Datasheet Volume One Thermal Management Specifications tel 5 1 2 Tcase and DTS Based Thermal Specifications To simplify compliance to thermal specifications at processor run time the processor has added a Digital Thermal Sensor DTS based thermal specification Digital Thermal Sensor reports a relative die temperature as an offset from TCC activation temperature Tcase thermal based specifications are used for heat sink sizing and DTS based specs are used for acoustic and fan speed optimizations For the processor family firmware for example BMC or other platform management devices will have DTS based specifications for all SKUs programmed by the customer Some SKUs at sharing the same TDP may share a common
325. wer Technology Memory Power Management 1 2 I nterfaces 1 2 1 System Memory Support Processor supports three DDR3 channels Unbuffered DDR3 and registered DDR3 DIMMs LR DIMM Load Reduced DIMM for buffered memory solutions demanding higher capacity memory subsystems Independent channel mode or lockstep mode Data burst length of eight cycles for all memory organization modes Memory DDR3 data transfer rates of 800 1066 1333 and 1600 MT s 64 bit wide channels plus 8 bits of ECC support for each channel DDR3 standard 1 Voltage of 1 5 V and DDR3 Low Voltage of 1 35 V 1 Gb 2 Gb 4 Gb DDR3 DRAM technologies supported for these devices UDIMMs x8 x16 RDIMMs x4 x8 LRDIMM x4 x8 2 Gb and 4 Gb only Up to 8 ranks supported per memory channel 1 2 or 4 ranks per DIMM Open with adaptive idle page close timer or closed page policy Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC with or without data scrambler or a predefined test pattern Minimum memory configuration independent channel support with 1 DIMM populated Integrated dual SMBus master controllers Command launch modes of 1n 2n RAS Support including and not limited to Rank Level Sparing and Device Tagging Demand and Patrol Scrubbing Intel Xeon Processor E5 2400 v2 Product Family 15 Datasheet Volume One Overview intel DRAM Single Device Data Correction SDDC for any single x
326. wer saving actions If the exit latency requirements are high enough the package will transition to C3 or C6 depending on the state of the cores 4 2 5 4 Package C3 State A processor enters the package C3 low power state when At least one core is in the C3 state The other cores are in a C3 or lower power state and the processor has been granted permission by the platform L3 shared cache retains context and becomes inaccessible in this state Additional power savings actions as allowed by the exit latency requirements include putting Intel and links in L1 the uncore is not available further voltage reduction can be taken In package C3 the ring will be off and as a result no accesses to the LLC are possible The content of the LLC is preserved 4 2 5 5 Package C6 State A processor enters the package C6 low power state when At least one core is in the C6 state The other cores are in a C6 or lower power state and the processor has been granted permission by the platform L3 shared cache retains context and becomes inaccessible in this state Additional power savings actions as allowed by the exit latency requirements include putting Intel and PCle links in L1 the uncore is not available further voltage reduction can be taken In package C6 state all cores have saved their architectural state and have had their core voltages reduced to zero volts The LLC retains context but no accesses
327. with Intel Trusted Execution Technology for Servers Provides measurement of runtime firmware including SMM Enables run time firmware in trusted session BIOS and SSP Covers support for existing and expected future Server RAS features Only requires portions of BIOS to be trusted for example Option ROMs need not be trusted Supports S3 State without teardown Since BIOS is part of the trust chain For more information on Intel TXT Server Extensions refer to the Intel Trusted Execution Technology Intel amp TXT Server BIOS Specification AES Instructions These instructions enable fast and secure data encryption and decryption using the Advanced Encryption Standard AES which is defined by FIPS Publication number 197 Since AES is the dominant block cipher and it is deployed in various protocols the new instructions will be valuable for a wide range of applications Intel Xeon Processor E5 2400 v2 Product Family 80 Datasheet Volume One Technologies 3 2 4 3 3 3 4 3 5 intel The architecture consists of six instructions that offer full hardware support for AES Four instructions support the AES encryption and decryption and the other two instructions support the AES key expansion Together they offer a significant increase in performance compared to pure software implementations The AES instructions have the flexibility to support all three standard AES key lengths all standard modes of operation
328. with a TDP of 95W or lower in pedestal chassis Boxed Intel Thermal Solution STS100P Order Code BXSTS100P A 25 5 mm Tall Passive Heat Sink Solution that is intended for processors with a TDP of 95W or lower in 1U or 2U chassis with appropriate ducting Check with Blade manufacturer for compatibility 10 1 2 Intel Thermal Solution STS100C Passive Active Combination Heat Sink Solution The STS100C based on a 2U passive heat sink with a removable fan is intended for use with Intel Xeon processor E5 2400 v2 product family processors with TDP s up to 95W This heat pipe based solution is intended to be used as either a passive heat sink in a 2U or larger chassis or as an active heat sink for pedestal chassis and will provide improved acoustic performance when compared to the STS100A Figure 10 1 and Figure 10 2 are representations of the heat sink solution Although the active combination solution with the removable fan installed mechanically fits into a 2U keepout its use has not been validated in that configuration The STS100C in the active fan configuration is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present The STS100C with the fan removed as with any passive thermal solution will require the use of chassis ducting and are targeted for use in rack mount or ducted pedestal servers The retention solution used for these products is called Unified Retention System URS Intel X
329. x0000 CPUID Returns processor Execute CPUID instruction to get Identifier Read Information specific information processor signature including CPU family model and stepping information 0x0001 Platform ID Used to ensure MSR 17h 2 PLATFORM ID microcode update compatibility with processor 0x0002 PCU Device ID Returns the Device CSR DID information for the processor Power Control Unit 0x0003 Max Thread ID Returns the MSR RESOLVED CORES MASK maximum Thread RESOLVED CORES MASK 10 value supported by the processor 0x0004 CPU Microcode Returns processor MSR 8Bh 2 BIOS SIGN ID Update Revision microcode and PCU firmware revision information 0x0005 MCA Error Returns the MCA CSR MCA ERR SRC LOG Source Log Error Source Log Package Power 30 0x0000 Time Energy N A Read units for power MSR 606h SKU Unit Read and Power Units energy and time PACKAGE POWER SKU UNIT used in power CSR control registers PACKAGE POWER SKU UNIT Intel Xeon Processor E5 2400 v2 Product Family 45 Datasheet Volume One intel Table 2 8 RdPkgConfig amp WrPkgConfig CPU Thermal and Power Optimization Services Summary Sheet 2 of 4 T Parameter RdPkgConfig wrPkgConfig Alt rnate ee Value Data Inband dword Data Description MSR or CSR decimal dword Access Package Power 28 0x0000 Package Power N A Returns Therma
330. xceeding these limits during test may result in component failure The processor substrate should not be used as a mechanical reference or load bearing surface for thermal solutions Table 9 1 Processor Loading Specifications Parameter Maximum Notes Static Compressive Load 890 N 200 Ibf 1 2 3 5 Dynamic Load 1779 400Ibf max static compressive dynamic load 1 3 4 5 Notes 1 These specifications apply to uniform compressive loading in a direction normal to the processor IHS 2 This is the maximum static force that can be applied by the heatsink and Independent Loading Mechanism ILM 3 These specifications are based on limited testing for design characterization Loading limits are for the package constrained by the limits of the processor socket 4 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement 5 See Intel Xeon Processor E5 2400 v2 Product Family Thermal Mechanical Design Guide TMDG for minimum socket load to engage processor within socket 9 4 Package Handling Guidelines Table 9 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Table 9 2 Package Handling Guidelines Parameter Maximum Recommended Notes Shear 70 Ibs Tensile 25 165 Torque 35 in
331. ximum Temperature RESERVED in Degrees C in Degrees C in Degrees C Channel Temperature Data Accumulated DRAM Energy Read This feature allows the PECI host to read the DRAM energy consumed by all the DIMMs within all the channels or all the DIMMs within just a specified channel The parameter field is used to specify the channel index Units used are defined as per the Package Power SKU Unit read described in Section 2 5 2 6 11 This information is tracked by a 32 bit counter that wraps around The channel index in Figure 2 17 is specified as per the index encoding described in Table 2 7 A channel index of OxOOFF is used to specify the all channels case While Intel requires reading the accumulated energy data at least once every 16 seconds to ensure functional correctness a more realistic polling rate recommendation is once every 100 mS for better accuracy This feature assumes a 200W memory capacity In general as the power capability decreases so will the minimum polling rate requirement When determining energy changes by subtracting energy values between successive reads Intel advocates using the 2 s complement method to account for counter wrap arounds Alternatively adding all F s OxFFFFFFFF to a negative result from the subtraction will accomplish the same goal Accumulated DRAM Energy Data 31 0 Accumulated DRAM Energy Accumulated DRAM Energy Data 15 3 2 0 Parameter format

NEC Xeon E5-2420 v2

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