Dataram 8GB DDR3-1600
Contents
1. PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tcecp 4 tok Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 25 1 875 ns Clock Low Level Width tcL avg 0 47 0 53 tox Data Input Hold Time after DQS Strobe tou 45 ps DQ Input Pulse Width toipw 360 ps DOS Output Access Time from Clock tpasck 225 225 ps Write DOS High Level Width toasH 0 45 0 55 tck avg Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 100 ps Data Input Setup Time Before DQS Strobe tos 10 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tup minimum of tc or ter ns Address and Command Hold Time after Clock tin 120 ps Address and Command Setup Time before Clock tis 45 ps Load Mode Command Cycle Time tmRD 4 tck DQ to DQS Hold Lou 0 38 tck avg Active to Precharge Time tras 35 O tREFI ns Active to Active Auto Refresh Time tre 48 125 ns RAS to CAS Delay trep 13 125 ns Average Periodic Refresh Interval 0 C lt Tease lt 85 C Leen 7 8 us Average Periodic Refresh Interval 0 C lt Tease lt 95 C tREFI 3 9 us Auto Refresh Row Cycle Time treo 260 ns Row Precharge Time tre 13 125 ns Read DQS Preamble Time tRPRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK2. 6ns ns Internal Read to Precharge Command Delay tRTP Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twpst 0 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06250 Revision A 29 May 13 Dataram Corporation 2013 Page 7 eco DTM64396C ZE d WW Optimizing Value and Performance 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM YPDATARAM Med RW Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06250 Revision A 29 May 13 Dataram Corporation 2013 Page 8
3. D QS DOS CBR 7 0 O V O 7 0 O 7 0 All 15 OHMS DQ 63 0 O VW O DQRI63 0 CBI7 0 O VW O CBRI7 0 DQS 8 0 O VA O _ DASRIB 0 IDQS 8 0 OVWW O _ DASRIB 0 DM 8 0 O VWA O DMRIB 0 GLOBAL SDRAM CONNECTS All 39 OHMS BA 2 0 An SO IRAS ICAS MWE VTT All 39 OHMS CKE 1 0 ODT 1 0 ow S 1 0 VTT All 240 OHMS R Vss DQSR4 O _ IDQSR4 rT S DQS DQS CS DM DQS Dos CS DM DQR 39 32 O 1 017 0 VO 7 0 DMR5 O DQSR5 O DQSR5 O DOS DOS CS DM DQS DOS CS DM DQR 47 40 O 1 017 0 VO 7 0 DMR6 DQSR6 en CS DM Fe DOS DQR 55 48 O V O 7 0 DMR7 O DQSR7 DQSR7 O DQS DQS m ps SC DQR 63 56 O 1 017 0 VO 7 0 2 2 pF CK 1 0 Ob CK 1 0 VDD All 36 OHMS 100 nf CKO CKO 100 nf CK1 v DECOUPLING DDSPD _ Serial PD VDD All Devices VREF_DQ All SDRAMs Vss All Devices VREF_CA All SDRAMs Mrt A F Al SDRAMs EVENT TEMPERATURE MONITOR SCL SERIAL PD SDA SAO SA1 SA2 Document 06250 Revision A 29 May 13 Dataram Corporation 2013 Page 3 DR Optimizing Value and Performance DTM64396C 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperat
4. 5CB7 195ODTO 225DQ55 SCL SPD Clock Input 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226Vss SDA SPD Data Input Output 17 Ven MI Vss 77 ODT1 107 Vss 137 DQ14 167 NC TEST 197 Voo 227 DQ60 EVENT Temperature Sensing 18 DQ10 48 Vr NC 78 Voo 108 DQ56 138 DQ15 168 RESET 198 S3 NC 228 DQ61 RESET Reset for register and DRAMs 19 DQ11 49 Vr NC 79 S2 NC 109 DQ57 f139Vss 169 CKE1 199 Vss 229Vss PAR_IN Parity bit for Addr Ctrl 20Vsg 50 CKEO 80 Vss 110Vsg 140 DQ20 170 Voo 200DQ36 230DM7 ERR_OUT Error bit for Parity Error 21 DQ16 51 Ven 81 DQ32 111 DQS7f141 DQ21 171 A15 201DQ37 231NC A12 BC Combination input Addr12 Burst Chop 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172 A14 202 Vss 232 Vss A10 AP Combination input Addr10 Auto precharge 23 Vss 53 Err Our NC 83 Vss 113Vss 143 DM2 173 Voo 203DM4 233DQ62 Vss Ground 24 IDQS2 54 Vpn 84 DQS4 114 DQ58 HAAN 174A12 BC 204 NC 234DQ63 Von Power 25 DQS2 55 A11 85 DQS4 115 DQ59 f145Vss 175 AQ 205 Vss 235Vss VbopsPo SPD EEPROM Power 26Vss 56 A7 86 Vss 116 Vss 146 DQ22 176 Voo 206 DQ38 236 Vbosro Vrerva Reference Voltage for DQ s 27 DQ18 57 Ven 87 DQ34 117 SA0 147 DQ23 177 A8 207 DQ39 237 SA1 VRreFcA Reference Voltage for CA 28 DQ19 58 A5 88 DQ35 118 SCL f148Vss 178 A6 208 Vss 238SDA Vr Termination Voltage 29Vss 59 Ad 89 Vss 119SA2 149 DQ28 179 Voo 209DQ44 239Vss NC No Connection 30 DQ24 60 Voo 90 DQ40 120 ven 150 DQ29 180 A3 210DQ45 240 Vr _ Not used D
5. II PATARA d WW Optimizing Value and Performance m DTM64396C 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5 V 0 075 V I O Type SSTL_15 On board I C temperature sensor with integrated Serial Presence Detect SPD EEPROM Data Transfer Rate 12 8 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 9 10 and 11 Differential Data Strobe signals SDRAM Addressing Row Col Bank 16 10 3 Fully ROHS Compliant Pin Configuration Identification DTM64396C 1Gx72 8GB 2Rx8 PC3 12800E 11 11 E2 Performance range Clock Module Speed CL trep Ze 800 MHz PC3 12800 11 11 11 667 MHz PC3 10600 10 10 10 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64396C is an Unbuffered 1Gx72 memory module which conforms to JEDEC s DDR3 PC3 12800 standard The assembly is Dual Rank Each Rank is comprised of nine 512Mx8 DDR3 1600 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Both output driver strength and input termi
6. nation impedance are programmable to maintain signal integrity on the I O signals Pin Description Front Side Back Side Name Function 1 Veerpa 31 DQ25 61 A2 ei DQ41121Vsg_ 151 Vg 181 A 211Vss CBI7 0 Data Check Bits 2 Vss DI Vss 62 Voo 92 Vss 122DQ4 152 DM3 182 Voo 212DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 93 DQS5 123 DAS 153 NC 183 Voo 213NC DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34 DQS3 64 CK1 94 DQAS5 124Vss 154 Vss 184CKO 214Vss DM 8 0 Data Mask 5 Vss 35 Vss 65 Voo 95 Vss 125 DMO 155 DQ30 185 CKO 215DQ46 CK 1 0 CK 1 0 Differential Clock Inputs 6 DQS0 36 DQ26 66 Voo ee DQ42f126NC 156 DQ31 186 Voo 216 DQ47 CKE 1 0 Clock Enables 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 Event 217Vss CAS Column Address Strobe 8 Vss 38 Vss 68 Parin NC 98 Vss f128DQ6 158 CB4 188 A0 218 DQ52 RAS Row Address Strobe 9 DQ2 39CB0 69 VDD eo DQ48 129 DQ7 159 CBS 189 Voo 219DQ53 S 3 0 Chip Selects 10DQ3 40 CB1 70 A10 AP 100 DQ49 M30 Vss 160 Vss 190 BA1 220Vss WE Write Enable 11Vss MI Vss 71 BAO 101Vss 131 DQ12 161 DM8 191 Voo 221DM6 A 15 0 Address Inputs 12DQ8 42 DQS8 72 Voo 102 DQS6 132 DQ13 162 NC 192 RAS 222NC BA 2 0 Bank Addresses 13DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 163 Vss 193 SO 223Vss ODT 1 0 On Die Termination Inputs 14Vss MA Vg 74 ICAS 104Vss_ 134DM1 164 CBG 194 Von 224 DQ54 SA 2 0 SPD Address 15 DQS1 45 CB2 75 Voo 105 DQ50 135NC 16
7. ocument 06250 Revision A 29 May 13 Dataram Corporation 2013 Page 1 D SpGatapgan DTM64396C EE o GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM Front view 133 35 M 5 250 9 50 0 374 1 181 C 17 30 0 681 O mmm N m y 5 00 0 197 250 5 175 47 00 le TE 0 098 0 204 1 850 2 795 123 00 4 843 Back view Side view 4 00 Max 7 GER Max 4 00 Min 0 157 Min LO mmm WURR mmm DU O 1 27 10 P S 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches ee SEENEN Document 06250 Revision A 29 May 13 Dataram Corporation 2013 Page 2 DATARA Optimizing Value and Performance D m DTM64396C 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM 1810 S0 O Lt DMRO O DMR4 O Byes PI C BEE DQS DOS CS DM DOS DAS JC DQR 7 0 O 1 0 7 0 VO 7 0 DMR1 O Ge DQSR1 O IDASR1 O rT DQS DOS CS DM DQS DQS CS DM DQR 15 8 O MOO V O 7 0 ICS an DQS DAS CS DM me F f f YT Dos DOS CS DM DOS DAS ee Eih ane DMR2 DQSR2 DQR 23 16 0 DMR3 DQSR3 O DQSR3 O DQR 31 24 O 1 O 7 0 DQS DAS CS
8. rrent One bank ACTIVATE to PRECHARGE 765 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read lee PRECHARGE 855 mA Precharge Current Precharge Power An Precharge power down current Slow exit Down Current ooch EC Precharge Power An Precharge power down current Fast exit Down Current ooch SE MA Precharge Quiet Precharge quiet standby current Standby Current mec 540 mA Precharge Standby xx Precharge standby current Current Ipp2N 540 mA Active Power Down x Active power down current Current Ipp3P 450 mA Active Standby An Active standby current Current Ipp3N 630 mA Operating Burst Burst write operating current Write Current oi 1485 MA Operating Burst Burst read operating current Read Current oi 1440 MA Burst Refresh Si Refresh current Current Ipp5 1620 mA Self Refresh ee Self refresh temperature current MAX Tc 85 C Current Ipp6 360 mA Operating Bank i Interleave Read E All bank interleaved read current 1935 mA Current One module rank in this operation rest in IDD2P slow exit All module ranks in this operation Subject to change Document 06250 Revision A 29 May 13 Dataram Corporation 2013 Page 6 DTM64396C De Optimizing Value and Performance AC Operating Conditions 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM
9. s T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High VIH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low Vu per DC Vss AC Vgs 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix ern 0 150 Z Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO CK1 CK1 Cox 7 2 13 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE C 13 5 27 pF Input Capacitance Control SO S1 CKEO CKE1 ODTO ODT1 Ci 6 8 13 5 pF Input Output Capacitance Gr CB 7 0 DQSI8 0 DQSIB 0 Cio 3 5 pF DC Characteristics T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 18 18 pA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current lo 10 10 yA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ s DQS DQS and ODT are disabled eee Document 06250 Revision A 29 May 13 Dataram Corporation 2013 Page 5 EE 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V en Max F PARAMETER Symbol Test Condition Value Unit Operating One 8 Bank Active kaft Operating cu
10. ure non Operating TsTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tcase 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V UO Reference Voltage VREFDQ 0 49 Vop 0 50 Von 0 51 Voo V 1 UO Reference Voltage VREFCA 0 49 Voo 0 50 Von 0 51 Voo V 1 Notes The value of Vrer is expected to equal one half Voo and to track variations in the Voo DC level Peak to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin oc Vrer 0 1 Von V Logical Low Logic 0 Vioc Vss Vrer 0 1 V AC Input Logic Levels Single Ended CT 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 175 V Logical Low Logic 0 Viac Vrer 0 175 V be a bg Document 06250 Revision A 29 May 13 Dataram Corporation 2013 Page 4 EE 8 GB 240 Pin 2Rx8 Unbuffered ECC DDR3 DIMM Differential Input Logic Level
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