Dataram 4GB DDR3-1333
Contents
1. PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High VIH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low Vu per DC Vss AC Vgs 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix ern 0 150 2 Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CK 1 0 CK 1 0 Cox 8 6 13 4 pF Input Capacitance i Address BA 2 0 A 14 0 RAS CAS WE Ci 12 20 8 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 C 6 10 4 pF Input Output Capacitance DQ 63 0 DQS 7 0 DQS 7 0 DM 7 0 Cpio 3 5 pF DC Characteristics T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 16 32 yA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current lot 10 10 yA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled a TF E Document 06203 Revision A 2 Apr 13 Dataram Corporation 2013 Page 5 Ger DTM64329D SE 4GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V e Max g PARAMETER Symbol Test Condition Value Unit Operating One 8 Bank Active kaft Operating current One bank ACTIVATE to PRECHARGE 320 mA Precharge2. 9 50 0 374 30 00 1 181 H 17 30 0 681 O mmm f 5 00 0 19 PF 2 50 5 175 EN 47 00 ot E TE 0 098 0 204 1 850 2 795 123 00 G 4 843 ai Back view Side view 4 00 Max 7 GER Max 4 00 Min 0 157 Min O NNNMNNN mmm N mmm mmm O i 1 27 10 P S 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches a ene Page 2 Document 06203 Revision A 2 Apr 13 Dataram Corporation 2013 Ger DTM64329D Optimizing Value and Performance 4GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM S1O DQSRO O DQSRO O DQS DOS CS DM DQR 7 0 O O 7 0 O 7 0 CK CKE ODT CK CKE ODT DMR1 O DQSR1 O DQSR1 O DQS DOS CS DM DQR 15 8 O 1 0 7 0 VO 7 0 CK CKE ODT CK CKE ODT BRO TT TT DQSR2 O T pil IDQSR2 O 2m Een SCH DQS DOS CS om Te DOG CS DM DQR 23 16 O V O 7 0 V O 7 0 CK CKE ODT CK CKE ODT me DQSR3 O d Cen DQS DOS CS DM DQS DOS CS DM DQR 31 24 O V O 7 0 V O 7 0 CK CKE ODT CK CKE ODT CKO CKO CK1 CK1 CKEO CKE1 ODTO ODT1 All 15 OHMS DQ 63 0 O VW O DQRI 63 0 DQS 7 0 O VW O_DQRSI7 0 DQS 7 0 O WW O _ DQRS 7 0 DM 7 0 O VW O _DMRI7 0 GLOBAL SDRAM CONN
3. Addr12 Burst Chop 19 DQ11 49 Vrr 79 82 NC 109 DQ57 139Vsg 169 CKE1 199 Vss 229 Vss A10 AP Combination input Addr10 Auto precharge 20Vss 50 CKEO 80 Vss 110 Vss 140 DQ20 170 Voo 200 DQ36 230 DM7 Vss Ground 21 DQ16 51 Vbo 81 DQ32 111 DQS7141 DQ21 171 A15 201 DQ37 231 NC Mon Power 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172 A14 202 Vss 232 Vss Vppspp SPD EEPROM Power 23Vsg 53NC 83 Vss 113Vss 143 DM2 173 Voo 203 DM4 233 DQ62 VReFpa Reference Voltage for DQ s 24 DQS2 54 Von 84 DQS4 114 DQ58 144NC 174A12 BC 204 NC 234 DQ63 VRrefca Reference Voltage for CA 25 DQS2 55 A11 85 DQS4 115 DQ59 f145Vss 175 AQ 205 Vss 235 Vss Vit Termination Voltage 26Vsg 56 A7 86 Vss 116Vss 146 DQ22 176 ven 206 DQ38 236 Vopspp NC No Connection 27 DQ18 57 Vop 87 DQ34 117 SA0 147 DQ23 177 A8 207 DQ39 237 SA1 28 DQ19 58 A5 88 DQ35 118 SCL f148Vss 178 A6 208 Vss 238 SDA 29Vss 59A4 89 Vss 119SA2 bag DQ28 179 Vop 209 DQ44 239 Vss 30 DQ24 60 Von 90 DQ40 120 Maer 150 DQ29 180 A3 210 DQ45 240 Mr Not used n Document 06203 Revision A 2 Apr 13 Dataram Corporation 2013 Page 1 ye DTM64329D ttt 4GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM Front view 133 35 5 250
4. Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read lee PRECHARGE 360 mA Precharge Current Precharge Power x Precharge power down current Slow exit Down Current ooch 160 mes Precharge Power x Precharge power down current Fast exit Down Current ooch 208 mA Precharge Quiet Precharge quiet standby current Standby Current mec 240 mA Precharge Standby xx Precharge standby current Current Ipp2N 240 mA Active Power Down x Active power down current Current Ipp3P 192 mA Active Standby An Active standby current Current Ipp3N 288 mA Operating Burst Burst write operating current Write Current G ng 640 MA Operating Burst Burst read operating current Read Current oi 600 MA Burst Refresh Si Refresh current Current Ipp5 1440 mA Self Refresh lon6 Self refresh temperature current MAX Tc 85 C 160 mA Current G Operating Bank i Interleave Read E All bank interleaved read current 1920 mA Current One module rank in this operation the other in IDD2P Slow exit All module ranks in this operation Document 06203 Revision A 2 Apr 13 Dataram Corporation 2013 Page 6 DYPDATARAM Optimizing Value and Performance AC Operating Conditions DTM64329D 4GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM PARAMETER Symbol Min Max Unit Internal read command t
5. 5123 DQ5 153 NC 183 Vbo 213 NC DQSJ 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34DQS3 64 CK1 94 DQS5f124Vss 154 Vsg 184 CKO 214 Vss DM 8 0 Data Mask 5 Vss Das 65 Vor 95 Vss 125DMO 155 DQ30 185 CKO 215 DQ46 CK 1 0 CK 1 0 Differential Clock Inputs 6 DQS0 36 DQ26 66 Vop 96 DQ42 126NC 156DQ31 186 Von 216 DQ47 CKE 1 0 Clock Enables 7 DQSO 37 DQ27 67 VReFca 97 DQ43 127 Vss 157 Vss 187 NC 217 Vss ICAS Column Address Strobe 8 Vss 38 Vss 68 NC 98 Vss 128 DQ6 158 CB4 NC 188 AO 218 DQ52 RAS Row Address Strobe 9 DQ2 39CBO NC 69 VDD 99 DQ48 129 DQ7 159 CB5 NC 189 Vpp 219 DQ53 S 3 0 Chip Selects 10DQ3 40 CB1 NC 70 A10 AP 100 DQ49 f130 Vss 160 Vss 190 BA1 220 Vss IWE Write Enable 11Vss 141 Vss 71BA0 101 Vss 131 DQ12 161 DM8 NC 191 Von 221 DM6 A 15 0 Address Inputs 12 DQ8 42 DQS8 72 Vpop 102 DQS6f132 DQ13 162 NC 192 RAS 222 NC BA 2 0 Bank Addresses 13DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 1163 Vss 193 S0 223 Vss ODT 1 0 On Die Termination Inputs 14Vss d Vas 174 CAS 104 Vss 134DM1 164 CB6 NC 194 Von 224 DQ54 SA 2 0 SPD Address 15 DQS1 45 CB2 NC 175 Vpop 105 DQ50 135NC_ 165 CB7 NC 195 ODTO 225 DQ55 SCL SPD Clock Input 16 DQS1 46 CB3 NC 76 S1 106 DQ51 f136 Vss 166 Vss 196 A13 226 Vss SDA SPD Data Input Output 17 Vss 47 Vss 77 ODT1 107 Vss 137 DQ14 167 NC TEST 197 Mon 227 DQ60 RESET Reset for register and DRAMs 18 DQ10 48 Vrr 78 Vop 108 DQ56 138 DQ15 168 RESET 198 S3 NC 228 DQ61 A12 BC Combination input
6. ECTS All 39 OHMS BA 2 0 A 15 0 IRAS ICAS MWE VTT All 39 OHMS CKE 1 0 ODT 1 0 owe S 1 0 VTT All 240 OHMS Ee Vss DQR 39 32 O 1 017 0 DQR 55 48 O V O 7 0 DMR7 DQSR7 DQSR7 DQS DOS CS DM DQS DOS CS DM DQR 63 56 V O 7 0 HOI CO DQSR4 O L IDOSR4 H gt DQS DOS CS DM DQS DOS CS DM 180 m ee DMRO O DMR4 O rT O 7 0 CK KE ODT CK CKE ODT E TTI DASRS O eH c IDQSR5 O Te DOS CS DM O 7 0 CK CKE ODT BRE O T DQSR6 O SA IDQSR6 O IDAS DAS CS DM IDAS DOS CS DM rn I O 7 0 CK CKE ODT CK CKE ODT CK CKE ODT CK CKE ODT 2 2 pF CK 1 0 O 4j CK 1 0 VDD All 36 OHMS 100 nf CKO CKO 100 nf SS eae Chi DECOUPLING Vppsep _ Serial PD VoD All SDRAMs VREF_DQ All SDRAMs Vss All SDRAMs VREF_CA All SDRAMs Mer a A SDRAM SCL SERIAL PD SDA SAO SA1 SA2 Document 06203 Revision A 2 Apr 13 Dataram Corporation 2013 Page 3 DYeDATARAM Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability DTM64329D 4GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsToRAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperatur
7. Kmin UNUSED 0x00 CAS Latencies Supported Least Significant Byte Bit 0 CL 4 Bit 1 CL 5 Bit 2 CL 6 Bit 3 CL 7 Bit 4 CL 8 Bit 5 CL 9 Bit 6 CL 10 Bit 7 CL 11 Document 06203 Revision A 2 Apr 13 Dataram Corporation 2013 Page 8 Ger DTM64329D es 4GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 13 125ns Ox Minimum Write Recovery Time tWRmin x Minimum RAS to CAS Delay Time tRCDmin 13 125ns 0x6 f ime O CH N Minimum Row Active to Row Active Delay Time tRRDmin Minimum Row Precharge Delay Time tRPmin 13 125ns Ox Upper Nibbles for tRAS and tRC Bit 3 Bit 0 tRAS Most Significant Nibble 1 0x11 Bit 7 Bit 4 tRC Most Significant Nibble 1 Minimum Active to Precharge Delay Time tRASmin Least 36 0ns Ee 0x20 Significant Byte Minimum Active to Active Refresh Delay Time tRCmin Least 49 125ns ze 0x89 Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least 160 0ns nee 0x00 Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Most 160 0ns eer 0x05 Significant Byte Minimum Internal Write to Read Command Delay
8. Time 7 5ns 0x3C tWTRmin Minimum Internal Read to Precharge Command Delay Time 7 5ns 0x3C tRTPmin Upper Nibble for tFAW Bit 3 Bit 0 tFAW Most Significant Nibble 0x00 Bit 7 Bit 4 Reserved Minimum Four Activate Window Delay Time tFAWmin Least 30 0ns A OxFO Significant Byte SDRAM Optional Features x CH CA ojo O Bit 0 RZQ 6 Bit 1 RZQ 7 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Reserved Document 06203 Revision A 2 Apr 13 Dataram Corporation 2013 Page 9 Ger DTM64329D es 4GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM 32 59 UNUSED 1 2 3 4 64 112 Bytes 122 Module Nominal Height Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 Bit 7 Bits Reserved 0 Module Maximum Thickness Bit 3 Bit 0 Front in mm baseline thickness 1 mm 1 lt th lt 2 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 Reference Raw Card Used Bit 4 Bit 0 Reference Raw Card R C B Bit 6 Bit 5 Reference Raw Card Revision Rev 1 Bit 7 Reserved Address Mapping from Edge Connector to DRAM Bit 0 Rank 1 Mapping Registered DIMM Reserved Mirrored it 7 Bit 1 Re
9. ck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twtr Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZ2DQS min 2 The maximum postamble is bound by tHZDQS max Document 06203 Revision A 2 Apr 13 Dataram Corporation 2013 Page 7 Ger DTM64329D es 4GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Function Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 Bit 3 Bit 0 Module Type Bit 7 Bit 4 Reserved SDRAM Density and Banks Bit 3 Bit 0 Total SDRAM capacity in megabits 2GB Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved SDRAM Addressing Bit 2 Bit 0 Column Address Bits Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved REECH Module Organization Bit 2 Bit 0 SDRAM Device Width 8 Bits 0x09 Bit 5 Bit 3 Number of Ranks 2 Rank Bit 7 6 Reserved 0 Module Memory Bus Width Bit 2 Bit 0 Primary bus width in bits 64 Bits 0x03 Bit 4 Bit 3 Bus width extension in bits 0 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Dividend Divisor Bit 3 Bit 0 Fine Timebase FTB Divisor 0x52 Bit 7 Bit 4 Fine Timebase FTB Dividend Medium Timebase MTB Dividend 1 MTB 0 125ns 2x01 11 Medium Timebase MTB Divisor 8 MTB 0x08 0 125ns 12 SDRAM Minimum Cycle Time tC
10. e Operating Tcase 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V UO Reference Voltage VREFDQ 0 49 Von 0 50 Von 0 51 Voo V 1 UO Reference Voltage VREFCA 0 49 Voo 0 50 Von 0 51 Voo V 1 Notes The value of Vrer is expected to equal one half Voo and to track variations in the Voo DC level Peak to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin oc Vrer 0 1 Von V Logical Low Logic 0 Vioc Vss Vrer 0 1 V AC Input Logic Levels Single Ended CT 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH ac Vrer 0 175 V Logical Low Logic 0 Vit ac Vrer 0 175 V D E a EE SEENEN Document 06203 Revision A 2 Apr 13 Dataram Corporation 2013 Page 4 Ger DTM64329D es 4GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V
11. ed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06203 Revision A 2 Apr 13 Dataram Corporation 2013 Page 11
12. o first data taa 13 125 20 ns CAS to CAS Command Delay tcecp 4 tok Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 3 3 ns Clock Low Level Width tcL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe toH 65 ps DQ Input Pulse Width toipw 400 ps DOS Output Access Time from Clock toasck 255 255 ps Write DOS High Level Width toasH 0 45 0 55 tcx ava Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tup minimum of tcx or ter ns Address and Command Hold Time after Clock tin 140 ps Address and Command Setup Time before Clock tis 190 ps Load Mode Command Cycle Time tmRD 4 tck DQ to DQS Hold Lou 0 38 tek avg Active to Precharge Time tras 36 O tREFI ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trep 13 125 ns Average Periodic Refresh Interval tREFI 7 8 US Auto Refresh Row Cycle Time trFc 160 ns Row Precharge Time tre 13 125 ns Read DQS Preamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay trrD Max 4nCK 6ns ns Internal Read to Precharge Command Delay tRTP Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twest 0 4 t
13. served UNUSED UNUSED UNUSED Module Specific Section Module Specific Section Module Specific Section Module Manufacturer ID Code Least Significant Byte Module Manufacturer ID Code Most Significant Byte Module Manufacturing Location Module Manufacturing Date Module Serial Number Cyclical Redundancy Code CRC Cyclical Redundancy Code CRC Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Revision Code DRAM Manufacturer ID Code Least Significant Byte DRAM Manufacturer ID Code Most Significant Byte Manufacturer s Specific Data Open for customer use UNUSED ES ES OCH COOC a CH x lt N CH UNUSED Ox wW N W 2 125 change per DIMM Document 06203 Revision A 2 Apr 13 Dataram Corporation 2013 0 UNUSED UNUSED UNUSED OxFF ye DTM64329D itt 4GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM Ve DATARAM Med WW Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believ
14. yee DTM64329D EE 4GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM Identification DTM64329D 512Mx64 4GB 2Rx8 PC3 10600U 9 11 B1 Performance range Clock Module Speed CL trep Ze 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high DTM64329D is an Unbuffered 512Mx64 z memory module which conforms to Operating Voltage 1 5 V 0 075 V JEDEC s DDR3 PC3 10600 standard The I O Type SSTL_15 assembly is Dual Rank Each Rank consists of eight 256Mx8 DDR3 Hynix SDRAMs Data Transfer Rate 10 6 Gigabytes sec One 2K bit EEPROM is used for Serial Data Bursts 8 and burst chop 4 mode Presence Detect ZQ Calibration for Output Driver and On Die Termination ODT Both output driver strength and input termination impedance are programmable to Programmable ODT Dynamic ODT during Wie maintain signal integrity on the I O signals Programmable CAS Latency 6 7 8 and 9 Differential Data Strobe signals SDRAM Addressing Row Col Bank 15 10 3 Fully ROHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 Vererpa 31 DQ25 61 A2 91 DQ41 f121Vss 151 Vss 181 A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32Vss 62 Vpop 92 Vss 122 DQ4 152 DM3 182 Vbo 212 DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 93 DQS
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