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Super Talent Technology W1066UB2GM memory module

1. SRE tCKSRE max 5tCK 10ns max 5tCK 10ns Valid Clock Requirement before Self Refresh Exit SRX tCKSRX max 5tCK 10ns max 5tCK 10ns Power Down Timing Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL tXP max 8tCK 7 5ns max 3tCK 6ns Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL tXPDLL max 10tCK 24ns max 10tCK 24ns CKE minimum pulse width tCKE max 3tCK 5 625ns max 3tCK 5 625ns Command pass disable delay tCPDED 1 1 Power Down Entry to Exit Timing tPD tCKE min 9 tREFI tCKE min 9 tREFI Timing of ACT command to Power Down entry tACTPDEN 1 1 Timing of PRE command to Power Down entry tPRPDEN 1 1 Timing of RD RDA command to Power Down entry tRDPDEN RL 4 1 RL 4 1 Timing of WR command to Power Down entry BL8OTF BL8MRS BL4OTF Timing of WRA command to Power Down entry BL8OTF BL8MRS BL4OTF tWRPDEN tWRAPDEN WL 4 tWR tCk WL 4 WR 1 WL 4 tWR tCk WL 4 WR 1 Timing of WR command to Power Down entry BL4MRS tWRPDEN WL 2 tWR tCK avg WL 2 tWR tCK avg http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 8 2006 Super Ta
2. 12 cycles tERR 12per 242 242 ps tERR nper min Cumulative error across n 13 14 49 50 cycles tERR nper max tERR nper q 0 68 Nn E Tipar 1 0 68In n tulT per Ps 0 43 Absolute clock HIGH pulse width tCH abs 0 43 tCK avg Absolute clock Low pulse width tCL abs 0 43 0 43 tCK avg Data Timing tDQSQ tQH tLZ DQ tHZ DQ DQS DQS to DQ skew per group per access DQ output hold time from DQS DQS DQ low impedance time from CK CK 13 14 f DQ high impedance time from CK CK 13 14 f Data setup time to DQS DQS referenced to Vih ac Vil ac levels Data hold time to DQS DQS referenced to Vih ac Vil ac levels DQ and DM Input pulse width for each input tDS base d 17 tDH base tDIPW Data Strobe Timing DQS DQS READ Preamble tRPRE Note 19 0 9 Note 19 tCK 13 19 g tRPST Note 11 tCK tQSH 0 4 tQSL 0 4 tWPRE 0 9 0 9 tCK DQS DQS differential READ Postamble Note 11 0 3 11 13 g DQS DQS output high time tCK avg DQS DQS output low time tCK avg DQS DQS WRITE Preamble DQS DQS WRITE Postamble tWPST 0 3 0 3 tCK DQS DQS rising edge output access time from rising CK CK DQS DQS low impedance time Referenced from RL 1 DQS DQS high impedance time Referenced from RL BL 2 DQS DQS differential input low pulse width tDQSCK 300 255 ps tLZ DQS 600 500 ps tHZ DQS 300 250 ps tDQSL 0 45
3. avg tCK avg Clock Period tCK abs min tJIT max tJIT min tJIT max tJIT ps per min per max per min per max Average high pulse width tCH avg 0 47 0 53 0 47 0 53 tCK avg Average low pulse width tCL avg 0 47 0 53 0 47 0 53 tCK avg Clock Period Jitter tUIT per 90 90 80 80 ps Clock Period Jitter during DLL locking period tJIT per Ick 90 90 80 80 ps Cycle to Cycle Period Jitter tUIT cc 180 160 ps Cycle to Cycle Period Jitter during DLL locking period tJIT cc Ick ps Cumulative error across 2 cycles tERR 2per ps Cumulative error across 3 cycles tERR 3per ps Cumulative error across 4 cycles tERR 4per ps Cumulative error across 5 cycles tERR 5per ps Cumulative error across 6 cycles tERR 6per ps Cumulative error across 7 cycles tERR 7per ps Cumulative error across 8 cycles tERR 8per ps Cumulative error across 9 cycles tERR 9per ps Cumulative error across 10 cycles tERR 10per ps http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 6 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 11 2 AC Timing Parameters amp Specifications con t DDR3 1066 m n Parameter DDR3 1333 Symbol max 237 237 ps Cumulative error across 11 cycles tERR 11per Cumulative error across
4. tCK tDQSH tDQSS tDSS 0 2 0 2 0 45 DQS DQS differential input high pulse width 0 45 0 45 tCK DQS DQS rising edge to CK CK rising edge 0 25 0 25 tCK avg DQS DQS faling edge setup time to CK CK rising edge tCK avg DQS DQS faling edge hold time to CK CK rising edge tDSH 0 2 0 2 tCK avg tDLLK 512 512 nCK max DLL locking time internal READ Command to PRECHARGE Command max delay tRTP 4tCK 7 5ns 4tCK 7 5ns Delay from start of internal write transaction to internal read command tWTR 4tCK 7 5ns max max 4tCK 7 5ns WRITE recovery time tWR 15 15 Mode Register Set command cycle time tMRD 4 4 Mode Register Set command update delay tMOD 12tCK 15ns max max 12tCK 15ns CAS to CAS command delay tCCD 4 4 Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK AVG Products and Specifications discussed herein are subject to change without notice 7 2006 Super Talent Tech Corporation http www supertalent com oem THE POWER OF MEMORY 240 Pin Unbuffered DIMM SUPER TALENT DDR3 SDRAM 11 3 AC Timing Parameters amp Specifications con t Parameter Symbol DDR3 1066 m n DDR3 1333 m n Multi Purpose Register Recovery Time tMPRR 1 1 ACTIVE to PRECHARGE command period tRAS
5. 37 5 36 ACTIVE to ACTIVE command period for 1KB page size tRRD max 4tCK 7 5ns max 4tCK 6ns ACTIVE to ACTIVE command period for 2KB page size tRRD max 4tCK 10ns max 4tCK 7 5ns Four activate window for 1KB page size tFAW 37 5 30 Four activate window for 2KB page size tFAW 50 45 Command and Address setup time to CK CK referenced to Vih ac Vil ac levels tlS base 65 Command and Address hold time from CK CK referenced to Vih ac Vil ac levels tlH base 140 Command and Address setup time to CK CK referenced to Vih ac Vil ac levels tlS base AC150 65 125 Control amp Address Input pulse width for each input tIPW 620 Calibration Timing Power up and RESET calibration time tZQinitl Normal operation Full calibration time tZQoper 25 Normal operation short calibration time tZQCS 64 64 Reset Timing Exit Reset from CKE HIGH to a valid command max 5tCkK tRFC 10ns max 5tCK tRFC 10ns Self Refresh Timing Exit Self Refresh to commands not requiring a locked DLL tXS max 5tCK tRF C 10ns max 5tCK tRF C 10ns Exit Self Refresh to commands requiring a locked DLL Minimum CKE low width for Self refresh entry to exit timing tXSDLL tCKESR tDLLK min CKE min 1tCK tDLLK min iCKE min 1tCK Valid Clock Requirement after Self Refresh Entry
6. 56Mx64 128Mx8 16 TFBGA 2 PC3 8500U 2GB 2Rx8 W1333UB2Gx 2GB 256Mx64 128Mx8 16 TFBGA 2 PC3 10600U 4GB Kit r 2GB 2Rx8 W1333UX4Gx 2x 2GB 2x 256Mx64 128Mx8 16 TFBGA 2 PC3 10600U Last digit of part number indicates DRAM chip brand E Elpida M Micron Q Qimonda S Samsung W1066UB2Gx 2GB 256Mx64 128Mx8 16 TFBGA 2 3 0 Key Timing Parameters DDR3 1333 DD3 1066 CL tRCD tRP 9 9 9 7 7 7 CAS Latency 9 7 tCK min 1 5 1 875 tRCD min 13 5 13 125 tRP min 13 5 13 125 tRAS min 36 37 5 tRC min 49 5 50 625 4 0 Absolute Maximum DC Rating Symbol Parameter Rating Vin Vout Voltage on any pin relative to Vss 0 4 1 975 Vpp Voltage on Vpp amp Vppg supply relative to Vss 0 4 1 975 Vppe Short circuit current 0 4 1 975 VoppL Power dissipation 0 4 1 975 http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 2 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM TstG Storage Temperature 55 100 C 5 0 DIMM Pin Configurations Front side Back side Pin Front Pin Back Pin Front Pin Back i i Back VrerDQ 121 Vss 41 Vss 161 DM8 DQS17_P DQ37 Vss 122 DQ4 42 NC 162 DQS1I7_N Vss DQO 123 DQ5 43 NC 163 Vss S DM4 DQS13_P DQ 124 Vss 44 Vss 164 N
7. C DQS1I3_N Vss 125 DM0 DQS9_P 45 NC 165 NC Vss DQSO_N 126 NC DQS9_N 46 NC 166 Vss s DQ38 DQSO_P 127 Vss 47 Vss 167 NC TEST DQ39 Vss 128 DQ6 48 NC 168 RESET_N Vss DQ2 129 DQ7 KEY s DQ44 DQ3 130 Vss 49 NC 169 CKE1 DQ45 Vss 131 DQ12 50 CKE0 170 Vss DQ8 132 DQ13 51 VDD 171 A15 s DM5 DQS14_P DQ9 133 Vss 52 BA2 172 DQS14_N Vss 134 DMI DQS10_P 53 NC Err Out 173 Vss DQSI_N DQSIO_N 54 VDD 174 A12 s DQ46 DQS2_P 136 Vss 55 All 175 A9 DQ47 Vss 137 DQ14 56 A7 176 Vss DQ10 138 DQ15 57 VDD 177 A8 s DQ52 DQ11 Vss 58 A5 178 A6 DQ53 Vss DQ20 59 A4 179 Vss DQ16 DQ21 60 VDD 180 A3 DM6_DQS15_P DQ17 Vss 61 A2 181 Al DQSI5_N Vss DQS11_P 62 VDD 182 VDD Vss DQS2_N DQSI1_N 63 CKI_P NC 183 VDD S DQ54 DQS2_P Vss 64 CKI_N NC 184 CKO_P DQS55 Vss DQ22 65 VDD 185 CKO_N Vss DQ18 DQ23 66 VDD 186 VDD s DQ60 DQ19 Vss 67 VrerCA 187 NC EVENT DQ61 Vss DQ28 68 NC Par_In 188 AO Vss DQ24 DQ29 69 VDD 189 VDD s DM7 DQS16_P DQ25 Vss 70 A10 AP 190 BAI DQSI6_N Vss DM3 DQS12_P 71 BAO 191 VDD Vss DQ3_N DQS12_N 72 VDD 192 RAS_N s DQ62 DQ3_P Vss 73 WE 193 SO_N DQ63 Vss DQ30 74 CAS 194 VDD Vss DQ26 DQ31 75 VDD 195 ODTO VppSPD DQ27 Vss 76 S1 196 A13 SA1 Vss NC 77 ODT1 197 VDD NC NC 78 VDD 198 NC NC Vss 79 S2 NC 199 Vss 80 Vss 200 DQ36 O oo NoU RA UNM Se o http www supertalent com oem Products and Specifications discussed herein are subject to c
8. HE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 12 0 Physical Dimensions 128Mbx8 Based 256Mx64 2 ranks FRONT VIEW 40 0 157 MAX 132 5005 290 133 2005240 2 40 006 D 2 2 20 0 091 TY j O76 pox R 1 77 posa ETS 1 177 pog 2 20 0 089 TYP 1 0 0 039 020 pan 5 0 374 TY 1 45 0 067 TYP Ww Tr i PN 120 1339 430 Te BACK VIEW l PIN 121 _ _ D D G e TP TP Tolerances 0 005 13 unless otherwise specified Products and Specifications discussed herein are subject to change without notice http www supertalent com oem 10 2006 Super Talent Tech Corporation
9. KE S relationships must be maintained as shown DQ DM DQSIDOS resistors Refer to associ ate topology diagram BAx Ax RAS CAS WE resistors Refer to associate topology diagram Refer to the appro priate clock wiring topology under the DIMM wiring details section of this document http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 5 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 9 0 AC amp DC Operating Conditions Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Symbol Parameter Min Vpop Supply Voltage 1 425 Vppe Supply Voltage for Output 1 425 VrerDQic I O Reference Voltage DQ 0 49 Vppo VrerCA po T O Reference Voltage CMD Add 0 49 Vppo Ver Termination Voltage 0 49 Vppo 10 0 Capacitance Max Symbol Parameter Condition CCK Input capacitance CK and CK Ci Input capacitance CKE and cs CI2 Input capacitance Addr RAS CAS WE CIO Input capacitance DQ DM DQS DOS 11 1 AC Timing Parameters amp Specifications AC operating conditions unless otherwise noted DDR3 1066 DDR3 1333 min max min max Minimum Clock Cycle Time DLL off mode tCK DLL_OFF 8 8 ns Parameter Symbol Average Clock Period tCK avg See Speed Bins Table ps tCK avg tCK avg tCK
10. SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM DDR3 Unbuffered DIMM Module 2GB based on 1Gbit component TFBGA with Pb Free RoHS 2002 95 EC Revision 1 01 June 2009 http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 1 0 Features JEDEC standard VDD VDDQ 1 5V 0 075V Power Supply 1 5V centered terminated push pull I O Programmable CAS latencies 5 6 7 8 9 10 Burst Length 4 amp 8 and Burst Type Auto Refresh CRB and Self Refresh Bi directional Differential Data Strobe Off Chip Driver OCD impedance adjustment On Die termination using ODT pin 8 independent internal bank Average Refresh Period 7 8us at lower than a TCASE 85 C 3 9us at 85 C lt TCASE lt 95 C support High Temperature Self Refresh rate enable feature Serial presence detect with EEPROM DIMM Dimension Nominal 30 00 mm high 133 35 mm wide Based on JEDEC standard reference Raw Cards Lay out RoHS compliant Gold plated contacts 2 0 Ordering Information These products can be ordered as individual 2GB DIMMs or as 4GB kits 2x 2GB Module Component Component Module Fart mumabex Density Organization composition PKG Rank Description 2GB 2Rx8 PC3 8500U 4GB Kit 2GB 2Rx8 W1066UX4Gx 2x 2GB 2x 2
11. ank Address BAO BA2 Column Address A0 A9 Organization 128Mx8 1Gb base Auto Pre charge A10 AP http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 4 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 8 0 Functional Block Diagram 2GB 256Mx64 Module Populated as 2 ranks of x8 31 Pp re lt a m 1a A N DM TS DQ Bos LOO ro Ds 202 4203 104 ros Hios 107 we D v 1 D DQ10 M DQ mM DQ w DQI3 v DQ M DOIS M W N AN DQi6 wW D10 DQ w Dili D26 m DN mv DQ w D29 wN DQ m DQ m DQ32 vi DQ33 M D34 W DQ35 M DQ36 m DQ37 M D33 WV A DQ48 v DQs9 v DQ50 mv DQ51 v Den W D53 Mv Dos nisi An A ma a DM TS Dos Dos o0 DM tS Loo oo rol D4 D12 ro2 ro3 o4 ros o os TS pgs DE vol D6 r02 103 o4 ros Vpp SPD SPD Voo Voog D0 D15 Vas D0 D15 BA0 BA2 gt AQ Al5S v gt CKEL CKE gt Ta veo ODTO gt ODT _ BA0 BA2 SDRAMs D0 D A0 A15 SDRAMs D0 D15 CKE SDRAMs D8 D15 CKE SDRAMs DO D7 FAS SDRAMs D0 D15 TAS SDRAMs D0 D15 WE SDRAMs D0 D15 ODT SDRAMs D0 D7 ODT SDRAMs D8 D15 DQ to 1 O wiring is shown as recommended but may be changed DODOSDOS ODT DM C
12. hange without notice 3 2006 Super Talent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM NC No Connect RFU Reserved for Future Use 1 Par_in and Err_out pins are intended for register control functions 6 0 DIMM Pin Description Pin Name Function Pin Name Function AO A15 Address input Multiplexed ODT0 ODT1 On Die Termination A10 AP Address Input Auto pre charge CB0 CB7 ECC Data check bits Input Output BAO BA2 Bank Select DQ0 DQ63 Data Input Output CKO CK2 CKO CK2 Clock input DQSO DQS8 Data strobes negative line CKEO CKE1 Clock enable input DM 0 8 Data Masks Data strobes Read 0 S1 Chip select input DQS0 DQS8 Data Strobes RAS Row address strobe RFU Reserved for future used CAS Column address strobe SDRAM I O termination power supply WE Write Enable Memory bus test tool SCL SPD Clock Input Core Power SDA SA0 SA2 SPD Data Input Output SPD Address T O Power Ground Par_In Parity bit for address amp Control bus SDRAM Input Output Reference Supply Err_Out Parity error found in the Address and Control bus Serial EEPROM Power Supply RESET Register and PLL control pin Command Address Reference Supply 7 0 Address Configuration Row Address AO0 A13 B
13. lent Tech Corporation SUPER TALENT THE POWER OF MEMORY 240 Pin Unbuffered DIMM DDR3 SDRAM 11 4 AC Timing Parameters amp Specifications con t DDR3 1066 DDR3 1333 mm max min max Timing of WRA command to Power Down entry WL 2 WL 2 BL4MRS IWRAPDEN WR 1 4WR j Timing of REF command to Power Down entry tREFPDEN 1 1 Parameter Symbol Timing of MRS command to Power Down entry tMRSPDEN tMOD min tMOD min ODT Timing ODT high time without write command or with wirte commandand BC4 ODT high time with Write command and BL8 ODTH8 Asynchronous RTT tum on delay Power Down with DLL frozen Asynchronous RTT tum off delay Power Down with DLL frozen ODT turn on tAON ps RTT_NOM and RTT_WR turn off time from ODTL off reference RTT dynamic change skew tADC 5 A tCK avg ODTH4 tAONPD ns tAOFPD ns tAOF 3 tCK avg Write Leveling Timing First DQS pulse rising edge after tDQSS margining mode is programmed DQS DQS delay after tDQS margining mode is programmed Setup time for tDQSS latch tWLS tWLMRD tWLDQSEN Hold time of tDQSS latch tWLH Write leveling output delay tWLO Write leveling output error tWLOE http www supertalent com oem Products and Specifications discussed herein are subject to change without notice 9 2006 Super Talent Tech Corporation SUPER TALENT T

Super Talent Technology W1066UB2GM memory module

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