Goodram 2GB DDR2 SO-DIMM
Contents
1. Factor tQHS Ox1E 30 46 Reserved for future use 0x00 0 47 SDRAM Device Attributes DDR SDRAM DIMM Height 0x51 81 48 Reserved for future use 0x00 0 49 Reserved for future use 0x00 0 50 Reserved for future use 0x00 0 51 Reserved for future use 0x00 0 52 Reserved for future use 0x00 0 53 Reserved for future use 0x00 0 54 Reserved for future use 0x00 0 55 Reserved for future use 0x00 0 56 Reserved for future use 0x00 0 57 Reserved for future use 0x00 0 58 Reserved for future use 0x00 0 59 Reserved for future use 0x00 0 60 Reserved for future use 0x00 0 61 Reserved for future use 0x00 0 62 SPD Revision 0x11 17 63 Checksum for Bytes 0 62 0x0C 12 64 255 Manufacturer s specific data GOODRAM logo and GOODDRIVE logo are registered trademarks of Wilk Elektronik S A Wilk Elektronik S A All other trademarks and logos are the property of their respective owners Poland 43 174 aziska G rne ul Mikotowska 42 WILK All products and specifications are subject to change without notice tel 0 32 736 90 00 fax 0 32 736 90 01 ELEKTRONIK sA www wilk com p www goodram com L Rev 10 07 2008 Wilk Elektronik S A 20082. MEMORY MODULE SPECIFICATION www goodram com GR 800 S2 64 L5 2 GOODRAM R A MI SPEED DATA TRANSFER 800MHz PC2 6400 professional memory for everyone MODULETYPE DDR2 SO DIMM DDR II MODULE MODULE DATAWIDTH 64 PART NUMBERING CAS LATENCY 5 SYSTEM MODULE DENSITY 2GB FEATURES 3 y 2z PART NUMBER GR8005264L5 2G o MODULE TYPE DDR2 SDRAM SODIMM E MODULE DENSITY 2GB E E MODULE DATA WIDTH 64 E DRAM CHIP ORAGNIZATION 128Mx8 E NUMBER OF DRAM CHIPS 16 2 6 NUMBER OF MODULE RANKS 2 es sf amp NUMBER OF MODULE SIDES 2 z REGISTERED NO Z ECC SUPPORT NO z PIN COUNT 200 PIN SUPPLY VOLTAGE 1 8V SSTL_18 COMPATIBLE YES Le PROGRAMMED SPD MEMORY 128 BYTES a MAX AVG PERIODIC REFRESH INTERVAL 7 8 us TE OPERATING FREQUENCY CAS Latency 800MHz 2x400MHz PC2 6400 6 533MHz 2x266MHz PC2 3200 4 DYNAMIC PARAMETERS FOR 800MHz 0791 RAS TO CAS DELAY tRCD 12 5 ns ROW PRECHARGE TIME tRP 12 5 ns ROW ACTIVE TO ROW ACTIVE DELAY tRRD 7 5 Ns ACTIVE TO PRECHARGE TIME tRAS 45 ns ACTIVE TO ACTIVE AUTO REFRESH TIME tRC 57 ns 3 AUTO REFRESH TO ACTIVE AUTO REFRESH tRFC 127 ns DEVICE CYCLE TIME tCK MAX 8 PCB DETAILS PCB TYPE DDR2 SDRAM SODIMM BOARD DIMENSIONS 67 56 x 30mm 0 1mm BOARD THICKNESS 1 27mm 0 13mm DRAM PACKAGE INFORMATION FBGA x8bit CONTACT PADS PIN GOLD PLATED Wilk Elektronik S A Poland 43 174 aziska G rne ul Mikotow
3. ska 42 tel 0 32 736 90 00 fax 0 32 736 90 01 www wilk com pl www goodram com Wilk Elektronik S A 2008 GOODRAM logo and GOODDRIVE logo are registered trademarks of Wilk Elektronik S A All other trademarks and logos are the property of their respective owners WILK ELEKTRONIK SA at A All products and specifications are subject to change without notice Rev 10 07 2008 Wwww goodram com MEMORY MODULE SPECIFICATION SPD CONFIGURATION GOOD i BYTE DESCRIPTION HEX DEC y aN IVI professional memory for everyone 0 Number of Serial PD Bytes written during module production 0x80 128 1 Total number of Bytes in Serial PD device 0x08 8 2 Fundamental Memory Type FPM EDO SDRAM 0x08 8 3 Number of Row Addresses on this assembly Ox0E 14 4 Number of Column Addresses on this assembly Ox0A 10 5 Number of DIMM Banks 0x61 97 6 Data Width of this assembly 0x40 64 7 Data Width of this assembly 0x00 0 8 Voltage Interface Level of this assembly 0x05 5 9 SDRAM Cycle time at Maximum Supported CAS Latency CL CL X 0x25 37 10 SDRAM Access from Clock 0x40 64 11 DIMM configuration type Non parity Parity or ECC 0x00 0 12 Refresh Rate Type 0x82 130 13 Primary SDRAM Width 0x08 8 14 Error Checking SDRAM Width 0x00 0 15 SDRAM Device Attributes Minimum Clock Delay Back to Back RCA 0x00 0 16 SDRAM Device Attributes Burst Lengths Supported 0x0 12 17 SDRAM Device Attributes Number of Banks on SDRAM Device 0x08 8 18 SDRAM De
4. vice Attributes CAS Latency 0x70 112 19 SDRAM Device Attributes CS Latency 0x01 1 20 SDRAM Device Attributes Write Latency DIMM Type Information 0x04 4 21 SDRAM Module Attributes 0x00 0 22 SDRAM Device Attributes General 0x07 7 23 Minimum Clock Cycle at CL X 0 5 0x25 37 24 Maximum Data Access Time tAC from Clock at CL X 0 5 0x40 64 25 Minimum Clock Cycle at CL X 1 0x3D 61 26 Maximum Data Access Time tAC from Clock at CL X 1 0x50 80 27 Minimum Row Precharge Time tRP 0x32 50 28 Minimum Row Active to Row Active delay tRRD Ox1E 30 29 Minimum RAS to CAS delay tRCD 0x32 50 30 Minimum Active to Precharge Time tRAS 0x2D 45 31 Module Bank Density 0x01 1 32 Address and Command Input Setup Time Before Clock 0x17 23 33 Address and Command Input Hold Time After Clock 0x25 37 34 Data Input Setup Time Before Clock 0x05 5 35 Data Input Hold Time After Clock 0x12 18 36 Write recovery time tWR 0x3C 60 37 Internal write to read command delay tWTR Ox1E 30 38 Internal read to precharge command delay tRTP Ox1E 30 39 Memory Analysis Probe Characteristics 0x00 0 40 Extension of Byte 41 tRC and Byte 42 tRFC 0x06 6 41 SDRAM Device Minimum Active to Active Auto Refresh Time tRC 0x39 57 42 SDRAM Device Minimum Auto Refresh to Active Auto Refresh tRFC 0x7F 127 43 SDRAM Device Maximum device cycle time tCKmax 0x80 128 44 SDRAM Device Maximum skew between DQS and DQ signals tDQSQ 0x14 20 45 DDR SDRAM Device Maximum Read Data Hold Skew
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