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Intel Celeron 1020M

1. gt mI epo 8 E _ Ei FL S 2 ES NDERF ILL B IE z EMT TTT TPA TT VT TTT FRONT VIE o o E 7 ti u 5 E a E 164 Datasheet Volume 1 Processor Pin Signal and Package I nformation intel Figure 8 11 Processor rPGA988B 4C GT2 E95127 Mechanical Package Sheet 2 of 2 1 EENEG Hs 5586859888 99000000000060 6600000000 Er EE 99990999900 6606066000 iiit N a o 90600006 VIEW BOTTO TEST POINT SRO S Datasheet Volume 1 165 Processor Pin Signal and Package Information intel Figure 8 12
2. Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type bir Pin Name Pin Buffer Type bir vss B15 GND vss G17 GND vss B17 GND vss G20 GND vss B19 GND vss G23 GND vss B2 GND vss G26 GND vss B22 GND vss G29 GND vss B3 GND vss G32 GND vss B5 GND vss G35 GND vss B7 GND vss H1 GND vss B8 GND vss H10 GND vss B9 GND vss H13 GND vss C1 GND vss H15 GND vss C10 GND vss H18 GND vss C23 GND vss H2 GND vss C25 GND vss H21 GND vss C27 GND vss H24 GND vss C28 GND vss H27 GND vss C31 GND vss H3 GND vss C34 GND vss H30 GND vss D17 GND vss H33 GND vss D20 GND vss H4 GND vss D26 GND vss H5 GND vss D29 GND vss H6 GND vss D32 GND vss H7 GND vss D35 GND vss H8 GND vss E1 GND vss H9 GND vss E10 GND vss J31 GND vss E13 GND vss J34 GND vss E15 GND vss K26 GND vss E18 GND vss K29 GND vss E2 GND vss K32 GND vss E21 GND vss K35 GND vss E24 GND vss L1 GND vss E27 GND vss L2 GND vss E3 GND vss L27 GND vss E30 GND vss L3 GND vss E4 GND vss L30 GND vss E5 GND vss L33 GND vss E6 GND vss L4 GND vss E7 GND vss L5 GND vss E8 GND vss L6 GND vss E9 GND vss L8 GND vss F19 GND vss L9 GND vss F22 GND vss M34 GND vss F29 GND vss N26 GND vss F31 GND vss N27 GND vss F34 GND vss N28 GND vss G11 GND
3. 5 us mi e m E E o ES z ojo lt lt E Si 4 a m lt d ER 2458 2 s e ESL gt 5 E kE lei lt ale 8 3 gt x e 2 d BE EAR E 3 a m E EN E 43 p gt s L M 8 c N Pepe yn Ol E 1 Pe i H E m P I o L 5 pad EN n 160 Datasheet Volume 1 Processor Pin Signal and Package I nformation intel Figure 8 7 Processor rPGA988B 2C GT1 G24406 Mechanical Package Sheet 2 of 2 TWO 980800 rou WENT JE a ARRANIN Datasheet Volume 1 161 Processor Pin Signal and Package Information intel Processor rPGA988B 2C GT2 G23867 Mechanical Package Sheet 1 of 2 Figure 8 8 EIER BCEE DDR AN3
4. 168 Datasheet Volume 1 DDR Data Swizzling intel 9 DDR Data Swizzling To achieve better memory performance and timing Intel Design performed DDR Data pin swizzling that allows a better use of the product across different platforms Swizzling has no effect on functional operation and is invisible to the operating system software However during debug swizzling needs to be taken into consideration Therefore this swizzling information is presented When placing a DIMM logic analyzer the design engineer must pay attention to the swizzling table to be able to debug memory efficiently Datasheet Volume 1 169 intel 170 Table 9 1 DDR Data Swizzling Table Channel A Pin Pin Pin e Pin Number Number Number ee rPGA BGA1023 BGA1224 SA_DQ 0 C5 AG AL6 DO06 SA 2 6 soar SA DQ 3 SA DQ 5 D3 AP11 D2 AL6 SA DQ 4 D6 AJ10 AK7 DO04 SA DQ 6 SA DQ 8 C6 AJ8 C2 AL8 rer RR SA DQ 9 F10 AR11 F8 AP6 st Dari vc ooo SA DQ 11 G9 AV9 SA DQ 12 F9 AR6 re me Dar SA_DQ 14 G8 AT13 5 151 G7 AU13 reg TS SA DQ 17 K5 BB7 SA DQ 18 BA13 SA DQ 19 BB11 AY9 DQ18 SA DQI 23 SA DQ 20 25 BA7 SA DQ 21 14 BA9 re sz bum K2 AY13 SA DQ 24 M8 AV14 SA DQ 25 14 avii DO30 SA DQ 26 AY17 SA DO 27 7 AR19 st ba
5. y w U T R P N M L K J H G F E D 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 126 Datasheet Volume 1 Processor Pin Signal and Package I nformation intel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball Buffer Type Dir BCLK D5 Diff Clk I DC TEST B65 B65 N A BCLK Diff Clk I DC TEST BF1 N A BCLK ITP Diff Clk I DC_TEST_BF65 N A BCLK_ITP Diff Clk I DC_TEST_BG2 N A BPM 0 Asynch CMOS 1 0 DC_TEST_BG64 N A Asynch CMOS I O DC_TEST_BH1 N A Asynch CMOS 1 0 DC_TEST_BH3 N A Asynch CMOS 1 0 DC_TEST_BH63 N A Asynch CMOS 1 0 DC_TEST_BH65 N A Asynch CMOS 1 0 DC_TEST_BJ2 N A Asynch CMOS 1 0 DC TEST BJ4 N A BPM 7 Asynch CMOS 1 0 DC_TEST_BJ62 N A CATERR Asynch CMOS DC TEST BJ64 N A CFG 0 CMOS I DC TEST C2 N A CFG 1 CMOS I DC TEST C64 N A CFG 2 CMOS I DC TEST D1 N A CFG 3 CMOS I DC TEST D65 N A CFG 4 CMOS I DMI_RX 0 DMI I CFG 5 CMOS I DMI_RX 1 DMI I CFG 6 CMOS I DMI_RX 2 DMI I CFG 7 CMOS I DMI_RX 3 DMI I CFG 8 CMOS I DMI_RX 0 DMI I CFG 9 CMOS I DMI RX 1 DMI I CFG 10 CMOS I DMI RX 2 DMI I CFG 11 CMOS I DMI RX 3 DMI I CFG 12 CMOS I DMI_TX 0 DMI 13 CMOS I DMI_TX 1 DMI 14 CMOS I DMI_TX
6. 13 Eu se 3 V ONIMVYC TVOINVH33W 39V39vd m l dlos E 119137 d S A im 1 H 110 ANINI uw H 1 i313 7199 YOR 1NS 38e G0 OT d d KREE o 4 STE 804 OJ ld NIA d aly 3903 390107 ig 3135 167 Figure 8 13 Processor BGA1023 2C GT2 G23866 Mechanical Package Processor Pin Signal and Package I nformation 4 1540 E i z g g Nolioas i ei 7 mol lt o 2 MT c i S 1123810 136440 804 i Td J v eu N 0 2 A YIN Sosy i Ze CALDO T 4 120138 J Ai138035 131113 TIL EON TE a J 8 NAIA 401 101 1 108 18138 1N3NOdA02 ke BEER siehe VA 0 ani Fal k l 4 1 N 1 D 3 3 9990950 950 950 0000000000000 050 050 O909 000000000000 0 0000 0 0090000000 q p 8 EC oooogooo 0900 o o 99909 88004089 o 99 9 9 o 05 99999 o oo 9 o 990 000 99 COE 0900 o ki 2 BUN a a 0050000 o SN o E J 700050000 0000000000000 50 8 909 00000000 coooo 2000000 990 T 909 00000000 00000 1 900 00000000 I 0000000000000 996 M 990 000000000 99900 990 990 999900000 e 3099000000000 800 o d 0000000 9 x 3 IB j E BOE a 1 990 000000000 LL 8809092200000 Sao 0000000 0 0 o o o o o o o b o o oD 090000000 1 Pea 900000
7. 130 Datasheet Volume 1 8 Processor Pin Signal and Package I nformation n tel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball Buffer Type Dir SA DQ 13 AR6 DDR3 yo SA DQ 50 BA60 DDR3 yo DDR3 yo DDR3 DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo DDR3 yo SA 63 DDR3 yo DDR3 yo SA_DQS 0 DDR3 yo DDR3 yo SA_DQS 1 DDR3 yo DDR3 yo SA_DQS 2 DDR3 yo DDR3 yo SA_DQS 3 DDR3 yo DDR3 yo SA_DQS 4 DDR3 yo DDR3 yo SA_DQS 5 DDR3 yo DDR3 yo SA_DQS 6 DDR3 yo DDR3 I O SA_DQS 7 DDR3 I O DDR3 yo SA_DOS 0 DDR3 yo DDR3 yo SA_DOS 1 DDR3 yo DDR3 yo SA_DOS 2 DDR3 yo DDR3 I O SA_DQS 3 DDR3 yo DDR3 yo SA_DOS 4 DDR3 yo DDR3 yo SA_DOS 5 DDR3 yo DDR3 yo SA_DOS 6 DDR3 yo DDR3 yo SA_DOS 7 DDR3 yo DDR3 yo SA_MA DDR3 DDR3 yo DDR3 DDR3 yo DDR3 DDR3 yo DDR3 DDR3 yo DDR3 DDR3 yo DDR3 DDR3 yo DDR3 Datasheet Volume 1 131 m 8 n tel Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Na
8. 65 4 6 7 Automatic Display Brightness ADR 65 4 6 8 Intel Seamless Display Refresh Rate Switching Technology Intel SDRRS Technologie 65 4 7 Graphics Thermal Power Management 66 5 Thermal Managemenit u u tete there nete ER REA ATE HAN RAE EEN Vra eR FCR RR KENE 67 5 1 Thermal Considerations retur ONR EWC esa eine Deer aed er RR xg ecu sas Y GA e 67 5 2 Intel Turbo Boost Technology Power Monitoring 68 5 3 Intel Turbo Boost Technology Power Control nnne nna 68 5 3 1 Package Power Control onn AEN cad eden n de tte RAA wawa 68 5 3 2 Power Plane iei ua A asa sa dada XO PA de d 70 5 3 3 Turbo Time Parameter ceded En ee XE EAR AR E NEXU Non 70 5 4 Configurable Thermal Design Power cTDP and Low Power Mode LPM rennen DWRN RAA LUW HERE RR ER RW RW Rad RIDE ER RWAN a 70 5 4 1 Configurable TOP CDP iecit seed ber ace tes SEN Y dE Saat data sextet 70 5 4 2 Low POWer MOde geet sage See sa FER Tf Seene 71 5 5 Thermal and Power Gpechfications LLY LARA ense eee nen 72 5 6 Thermal Management Features uuu aula piqaspaqqwqasqaqasqaqapawaq qawa 75 5 6 1 Adaptive Thermal Monitor 75 5 6 1 1 TCC Activation Offset L FL GL ea Yy Urea 76 5 6 1 2 Frequency Voltage Control 76 5 6 1 3 Clock Modulation sederet ehe teg a
9. DDR3 Control Buffer pull up Resistance 15 20 25 12 pN CTL DDR3 Control Buffer pull down Resistance 15 20 25 o 12 Datasheet Volume 1 107 intel Electrical Specifications Table 7 11 DDR3 DDR3L DDR3L RS Signal Group DC Specifications Sheet 2 of 2 Symbol Units Notes meme wm Input Leakage Current DQ CK DV lr mA 0 8 Vppo VDDQ Input Leakage Current CMD CTL 0 2 Vppq VDDQ Ii mA SM RCOMPO SM Command COMP Resistance Data COMP Resistance 25 245 25 5 25 755 SM RCOMP2 ODT COMP Resistance 198 200 202 Notes 1 2 Table 7 12 Unless otherwise noted all specifications in this table apply to all processor frequencies Vi is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value Vip is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value Vin and Voy may experience excursions above Vppo However input signal drivers must comply with the signal quality specifications This is the pull up pull down driver resistance is the termination on the DIMM and in not controlled by the processor The minimum and maximum values for these signals are programmable by BIOS to one of the two sets SM RCOMPx resistance must be provided on the system b
10. Datasheet Volume 1 DDR3 DDR3L DDR3L RS at 1 5 V Data Transfer Rates 1333 MT s PC3 10600 1600 MT s PC3 12800 DDR3L DDR3L RS at 1 35 V Data Transfer Rates 1333 MT s PC3 10600 1600 MT s PC3 12800 DDR3 DDR3L DDR3L RS DRAM Device Technology Standard 1 Gb 2 Gb and 4 Gb technologies and addressing are supported for x16 and x8 devices There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module If one side of a memory module is populated the other side is either identical or empty 25 intel I nterfaces Table 2 2 Supported DDR3 DDR3L DDR3L RS SO DI MM Module Configurations of of of Raw DRAM DRAM T or Physical Row Col Banks Page Deet Capacity Organization irl Device Address Inside Size 9y Ranks Bits DRAM e 128 M x 16 8 14 10 8 8K 4 Gb 256 Mx 16 8 15 10 8 8K 1Gb 128 M x 8 8 14 10 8 8K B 256 Mx 8 8 8K 512M x8 8 8K 128 M x 16 8 8K 256M x 16 8 8K 1Gb 128M x8 16 14 10 8 8K F 2 Gb 256 Mx 8 16 15 10 8 8K 512 16 8 8K Note 1 System memory configurations are based on availability and are subject to change Table 2 3 Supported Maximum Memory Size Per DI MM Max Size Max Size Per Configuration GB Platform Package Memory per DI MM GB 2 Ch 2 DPC SODIMM RC A 4 4 8 8 16 SODIMM RC B 4 4 8 8 16 Mobile rPGA SODIMM RC C 2 2 4 4 8 SODIMM RC F
11. 104 7 10 Processor Graphics Vaxc Supply DC Voltage and Current Specifications 104 7 11 DDR3 DDR3L DDR3L RS Signal Group DC Specifications sess 105 7 12 Control Sideband and TAP Signal Group DC Specifications YY Y YY 106 7513 PCI Express tcs scan RR DDR RD AD EN A dee SEN FA BO SC 107 7 14 Embedded DisplayPort DC Specifications LARA RAA ELE Y Y En 107 7515 PECI DC Electrical Limits erre groe aW RAOR SEA WYR TH se Ein na YRR NYRS GWER Ra 109 8 1 rPGA988B Processor Pin List by Pin Name Y LLYRY RY ALL LARA LLE 112 8 2 BGA1224 Processor Ball List by Ball Name 125 8 3 BGA1023 Processor Ball List by Ball Name 144 9 1 DDR Data Swizzling Table Channel A 168 9 2 DDR Data Swizzling Table for Package Channel 169 Datasheet Volume 1 Revision History Revision e Initial release e Added Mobile 3rd Generation Intel Core i7 3520M i5 3360M i5 3320M 002 i7 3667U i5 3427U processors Updated Table 7 10 Processor Graphics Vayg Supply DC Voltage and Current Specifications Updated Section 1 5 Package 003 Removed DDR 1066 MHz support Updated Table 2 5 DDR3L DDR3L RS System Memory Timing Support Added support for DDR3L RS Minor edits throughout for clarity Added Mobile 3rd Generation Intel Core i7 3940XM i7 3840QM i7 004 3740QM processors
12. deine DR 15 1 3 5 Direct Media Interface DMI YY aaa aaia 15 1 3 6 Processor Graphics Controller GT esses nene 16 1 3 7 Thermal Management Support 16 1 4 Processor Family SKU Definition E 16 1 5 Package TM 17 1 6 Processor Compatibility asnon ee Ee 17 1 7 P rmin o0 6gV RR wg 19 1 Related dE EEN ER E YAR 22 2 interface eS u EC 23 2 1 System Memory Interface us us u u a pa u aaa GER UNE 23 2 1 1 System Memory Technology Supported r 23 2 1 2 System Memory Timing Support 24 2 1 3 System Memory Organization Modes r 25 2 1 3 1 Single Channel Mode nitent DEENEN canes aspa qasa AGA AR Rad 25 2 1 3 2 Dual Channel Mode Intel Flex Memory Technology Mode 25 2 1 4 Rules for Populating Memory Slots memes 26 2 1 5 Technology Enhancements of Intel Fast Memory Access Intel FMA 27 2 1 5 1 Just in Time Command SGchedulmg eee ee eens ee 27 2 1 5 2 Command Overlap re certae st ae HERE WN Ddu SEE Rae aA ERE MEA AIR 27 2 1 5 3 Out of Order 2 nennen nni 27 2 1 6 Data Scrambling au a s a EE 27 2 1 7 DRAM Clock Generation noi reserare
13. Processor Pin Signal and Package I nformation intel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir vss AF5 GND vss R57 GND GND VSS R50 GND GND VSS R44 GND GND VSS R38 GND GND VSS R31 GND vss AD3 GND VSS R25 GND vss AD1 GND VSS R19 GND GND VSS R17 GND GND VSS R15 GND GND VSS R12 GND GND VSS P65 GND GND VSS P63 GND GND VSS P61 GND GND VSS P11 GND GND VSS P9 GND GND VSS P5 GND GND VSS N54 GND VSS AA12 GND VSS N47 GND VSS Y65 GND VSS N41 GND vss Y63 GND vss N35 GND vss Y7 GND vss N22 GND vss Y1 GND vss M50 GND vss V16 GND VSS M38 GND vss V11 GND vss M25 GND vss V5 GND VSS M7 GND vss U62 GND VSS M1 GND vss U57 GND VSS L62 GND vss T3 GND vss L58 GND Datasheet Volume 1 141 intel Processor Pin Signal and Package I nformation Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VSS L50 GND VSS G46 GND VSS L46 GND VSS G42 GND VSS L42 GND VSS G36 GND VSS L36 GND VSS G30 GND VSS L30 GND VSS G24 GND VSS L24 GND VSS G20 GND VSS L20 GND VSS G16 GND VSS L16 GND VSS G12 GND VSS L12 GND VSS G8
14. Table 8 3 1023 Processor Ball List Table 8 3 1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball Buffer Type Dir SA DQI 63 SB 5 0 SA_DQS 0 SB_BS 1 SA_DQS 1 SB_BS 2 SA_DQS 2 SB_CAS SA_DQS 3 SB CKE 0 SA_DQS 4 SB_CKE 1 SA_DQS 5 SB_CLK 0 SA_DQS 6 SB_CLK 1 SA_DQS 7 SB CK 0 SA_DOS 0 SB CK 1 SA_DOS 1 SB_CS 0 SA_DQS 2 SB_CS 1 SA_DQS 3 SB DQ 0 SA_DOS 4 SB DQ 1 SA DQS 5 SB DQ 2 SA_DOS 6 SB DQ 3 SA 7 SB DQ 4 SA SB DQ 5 SA MA 1 SB DQ 6 SA MA 2 SB DQ 7 SA MA 3 SB DQ 8 SA MA 4 SB DQ 9 SA MA 5 SB DQ 10 SA MA 6 SB DQ 11 SA MA 7 SB DQ 12 SA MA 8 SB DQ 13 SA MA 9 SB DQ 14 SA MA 10 SB DQ 15 SA MA 11 SB DQ 16 SA MA 12 SB DQ 17 SA MA 13 SB DQ 18 SA MA 14 SB DQ 19 SA MA 15 SB DQ 20 SA ODT 0 SB DQ 21 SA ODT 1 SB DQ 22 SA_RAS SB DQ 23 SA WEZ AT41 DDR3 SB DQ 24 BF16 DDR3 yo 150 Datasheet Volume 1 m Processor Pin Signal and Package I nformation n tel Table 8 3 1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type bir Ball Name Ball Buffer Type Dir SB DQ 25 BE17 DDR3 SB DQ 62 AF61 DDR3 I O 1 DDR3 I DDR3 I O epe DDR3 DDR3 DDR3 DDR3 DDR3
15. _ 2 K21 I FDIO TX 0 W6 FDI PEG RX 3 F19 PCIe I FDIO TX 1 W10 FDI PEG RX 4 K19 I FDIO TX 2 Y9 FDI PEG RX 5 H17 PCIe I FDIO TX 3 AA10 FDI _ 6 K15 I FDI1 FSYNC AA2 CMOS I PEG RX 7 G14 PCIe I FDI1_LSYNC AB3 I PEG_RX 8 J16 I FDI1_TX 0 U4 FDI _ 9 K13 PCIe I FDI1 TXH 1 w2 FDI _ 10 11 1 FDI1 TX 2 V1 FDI _ 11 K11 PCIe I FDI1 TX 3 Y5 FDI _ 12 F9 I FDI1 TX 0 U2 FDI _ 13 H9 PCIe I FDI1 TX 1 wa FDI _ 14 H7 I FDI1 TX 2 v3 FDI _ 15 G6 PCIe I FDI1 TX 3 AA6 FDI _ 0 22 PECI F53 Asynch I O PEG TXF 1 B23 PCIe PEG ICOMPI G2 I PEG TX 2 C18 _1 H1 Analog I PEG_TX 3 D21 PCIe PEG RCOMPO F3 I PEG TX 4 B19 PEG_RX 0 F23 PCIe I PEG TX 5 E20 PCIe 128 Datasheet Volume 1 Processor Pin Signal and Package I nformation intel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball Buffer Type Dir PEG 6 A14 PCIe RSVD BH43 PEG TX 7 PCIe _ 8 PEG_TX 9 PCIe _ PEG PEG PEG 4 PEG PE
16. enr e waa nr ane s ena YR 27 2 1 8 DDR3 Reference Voltage Generation 28 2 2 PCLExpress InterfaCe sss gere es na a tius SEN dT TRW UE FER IDE FR EFIE ARE 28 2 2 1 PCI Express Architecture tae a ana DE ax 28 22 1 1 Transaction deg 29 2 2 1 2 Data LINK Layer qasa Aa Ed Bwn ERA OMA waqaq 29 2 2 1 3 Physical Layer uet QNA A M Ex ME 29 2 2 2 PCI Express Configuration Mechanism r rr 30 2 2 3 PCL Express GraphieSu secos est read E RERUM EN E 31 2 2 3 1 PCI Express Lanes Connection us aasasssssssaswassnassrasasaqsa 31 2 3 Direct Media Interface DM u esta etna aen trek ad rer na OR va da ENEE RR dee 31 2 3 4 DMI Error coire Een spei ente Eege Yg Y RN Seege 32 2 3 2 Processor PCH Compatibility Aesumptions YY eee tees e 32 Datasheet Volume 1 3 ntel 2 9 3 u 32 2 4 Processor Graphics Controller GT 33 2 4 1 3D and Video Engines for Graphics Processing 33 2 4 1 1 3D Engine Execution Units eese EEN KENNEN nent nana nn mate aaa 33 2 4 1 2 3D Pipeline uu oca desideri tache ren ed tke anda et GAMU DD E Rx on IER ERR 34 2 4 1 3 Video Engihe eiu Fw Zeen RR R
17. 3 0 0 1 0 0 1 0 o 0 1 4 VID VID VID VID 5 VID 7 o 1 r 9 o 0 1 1 0 0 1 1 0 1 0 11 1 90 1 Oo 1 1 1 HEX Vcc_Max IT S 036500 0 37000 1 0 37500 1 8 0 38000 0 1 38500 39000 1 1 0 F 0 40000 2 2 0 41500 2 D 1 E 0 39500 1 2 2 2 5 0 43000 6 0 43500 2 7 0 44000 2 2 p 0 47900 E 0 47500 F 0 48000 3 o 0 48500 3 6 0 51500 2 2 3 7 0 52000 8 0 52500 5 0 53000 3 3 C 0 54500 0 55000 0 55500 0 0 1 0 1 0 0 1 0 1 1 1 0 1 1 0 0 0 0 0 0 4 0 0 56500 0 0 1 4 1 0 57000 VID VID VID VID VID 3 2 6 5 4 VID 7 ojo Lei aa 1 0 1 0 3 A 0 53500 1 0 1 1 3 B 0 54000 97 1 25000 1 26500 1 28000 B C 0 D 3 0 58000 3 6 0 59500 8 0 50500 9 0 61000 4 0 52000 0 62500 E 0 63500 F 0 64000 4 4 4 4 4 4 4 4 4 5 0 1 1 1 Datasheet Volume 1 Electrical Specifications intel Sheet 3 of 3 inition I MVP7 Voltage I dentification Def Table 7 1 1 29000 1 29500 1 30000 1 30500 1 31000 1 31500 1 32000 1 32500 1 33000 1 33500 1 34000 1 34500 1 35000 1 35500 1 36000 1 36500 1 37000 1 37500 1 38000 1 38500 1 39000 1 39500 1 40000 1 405
18. Down 22 Up 65 3 0 GHz up to 3 9 GHz 650 MHz up to 1 35 GHz i7 3920XM pown 45 Up 65 2 9 GHz up to 3 8 GHz 650 MHz up to 1300 MHz i7 3840QM 45 2 8 GHz up to 3 8 GHz 650 MHZ up to 1 3 GHz i7 3820QM 45 2 7 GHz up to 3 7 GHz 650 MHz up to 1250 MHz i7 3740QM 2 7 GHz up to 3 7 GHz 650 MHz up to 1 3 GHz i7 3720QM 2 6 GHz up to 3 6 GHz 650 MHz up to 1250 MHz i7 3687U 2 1 GHz up to 3 3 GHz 650 MHz up to 1200 MHz i7 3540M 3 0 GHz up to 3 7 GHz 650 MHz up to 1200 MHz i7 3537U 2 0 GHz up to 3 1 GHz 350 MHz up to 1200 MHz i7 3520M 2 9 GHz up to 3 6 GHz 650 MHz up to 1250 MHz i5 3437U 1 9 GHz up to 2 9 GHz 650 MHz up to 1200 MHz i5 3380M 2 9 GHz up to 3 6 GHz 650 MHz up to 1250 MHz i5 3360M 2 8 GHz up to 3 5 GHz 650 MHz up to 1200 MHz i5 3340M 35 1200 MHz 2 7 GHz up to 3 4 GHz 650 MHz up to 1250 MHz 105 i5 3320M 35 1200 MHz 2 6 GHz up to 3 3 GHz 650 MHz up to 1200 MHz 105 18 Datasheet Volume 1 Introduction intel Table 1 1 Mobile 3rd Generation I ntel Core Processor Family Mobile I ntel Pentium Processor Family and Mobile I ntel Celeron Processor Family SKUs Sheet 2 of 2 ou UM I A Frequency Range GT Frequency Range iux i5 3230M 35 1200 MHz 2 6 GHz up to 3 2 GHz 650 MHz up to 1150 MHz 17 800 MHz i7 3667U Down 14 Up 25 LPM 2 GHz up to 3 2 GHz 350 MHz up to 1150 MHz enabled 17 800 MHz i5 3427U Down 14 Up 25 LPM 1 8 GHz up to 2 8 GHz 350 MHz up to 1150 MH
19. PWR PWR GND GND VDDO PWR PWR GND GND VDDQ SENSE VIDALERT Analog CMOS GND GND VIDSCLK VIDSOUT CMOS GND GND VSS Datasheet Volume 1 GND CMOS GND GND GND GND 155 m 8 n tel Processor Pin Signal and Package Information Table 8 3 1023 Processor Ball List Table 8 3 1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball Buffer Type Dir vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss AR41 GND vss AL33 GND 156 Datasheet Volume 1 m Processor Pin Signal and Package I nformation n tel Table 8 3 1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type bir Ball Name Ball Buffer Type bir VSS AL28 GND VSS AF48 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
20. 2 Intel DPST subsystem applies an image specific enhancement to increase image contrast brightness and other attributes 3 A corresponding decrease to the backlight brightness is applied simultaneously to produce an image with similar user perceived quality such as brightness as the original image Intel DPST 5 0 has improved the software algorithms and has minor hardware changes to better handle backlight phase in and ensures the documented and validated method to interrupt hardware phase in Automatic Display Brightness ADB This is a mobile only supported power management feature The Intel Automatic Display Brightness feature dynamically adjusts the backlight brightness based upon the current ambient light environment This feature requires an additional sensor to be on the panel front The sensor receives the changing ambient light conditions and sends the interrupts to the Intel Graphics driver As per the change in Lux current ambient light illuminance the new backlight setting can be adjusted through BLC The converse applies for a brightly lit environment Intel Automatic Display Brightness increases the back light setting Intel Seamless Display Refresh Rate Switching Technology Intel SDRRS Technology This is a mobile only supported power management feature When a Local Flat Panel LFP supports multiple refresh rates the Intel Display Refresh Rate Switching power conservation feature can be enabled The higher
21. 78 Datasheet Volume 1 5 5 6 2 Digital Thermal S6nsSOF uii oid peto Rx REP ce E RR NA nd NF Fd 78 5 6 2 1 Digital Thermal Sensor Accuracy Taccuracy 79 5 6 2 2 Fan Speed Control with Digital Thermal Gensor es 79 5 6 3 PROCHOT4 Sighal ree st eh de Se SEENEN NEE A RADAR ada SEN ere 79 5 6 3 1 Bi Directional PROCHOT FYRR a e awia 79 5 6 3 2 Voltage Regulator Protection versus 80 5 6 3 3 Thermal Solution Design and PROCHOT Behavior 80 5 6 3 4 Low Power States and PROCHOT 80 5 0 3 5 THERMTRIPZ Sigal amisna tnn Naked DRAN IER RN A RR 81 5 6 3 6 Critical Temperature Detection sss 81 5 6 4 On Demand Mode nre ree prs tasa iu YG EEN sess waa AH E de Seege 81 5 6 4 1 MSR Based On Demand Mode r 81 5 6 4 2 Emulation Based On Demand 81 5 6 5 Memory Thermal Management 82 5 6 6 Platform Environment Control Interface 82 Signal Description sa Wd HAYARN AEN rena me Ra RE aA E RR RT FARE RENE RYE 83 6 1 System Memory Interface Signals ccecceeee cere eee eee eee eee a nemen 84 6 2 Memory Reference and Compensation Signals 86 6 3 Reset and Miscellaneous S
22. There is an access to the monitored address if the state was entered using an MWAIT instruction For core C1 C1E core and core C6 C7 an interrupt directed toward a single thread wakes only that thread However since both threads are no longer at the same core C state the core resolves to CO A system reset re initializes all processor cores Core CO State The normal operating state of a core where code is being executed Core C1 CIE State C1 C1E is a low power state entered when all threads within a core execute a HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 C1E state See the Intel 64 and 32 Architecture Software Developer s Manual Volume 3A 3B System Programmer s Guide for more information While a core is in C1 C1E state it processes bus snoops and snoops from other threads For more information on C1E see Package C1 C1E Core C3 State Individual threads of a core can enter the C3 state by initiating a P_LVL2 I O read to the P BLK or an MWAIT C3 instruction A core in C3 state flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core s caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core ac
23. 3 9 mao GT1 based units 4 6 mo LLAxc Notes 1 Unless otherwise noted all specifications in this table are based on post silicon estimates and simulations or empirical data 2 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Please note this differs from the VID employed by the processor during a power or thermal management event Intel Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 106 Datasheet Volume 1 Electrical Specifications intel 3 voltage specification requirements are measured across VCC SENSE and VSS SENSE pins at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 PSxrefers to the voltage regulator power state as set by the SVID protocol 5 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have
24. Base Specification 2 0 http www pcisig com DDR3 SDRAM Specification http www jedec org DisplayPort Specification http www vesa org Intel 64 and IA 32 Architectures Software Developer s Manuals http www intel com produ cts processor manuals inde x htm Volume 1 Basic Architecture 253665 Volume 2A Instruction Set Reference A M 253666 Volume 2B Instruction Set Reference N Z 253667 Volume 3A System Programming Guide 253668 Volume 3B System Programming Guide 253669 Note Contact your Intel representative for the latest revision of this item ss 24 Datasheet Volume 1 Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor 2 1 System Memory Interface 2 1 1 System Memory Technology Supported The Integrated Memory Controller IMC supports DDR3 DDR3L DDR3L RS protocols with two independent 64 bit wide channels each accessing one or two DIMMs The IMC supports one or two unbuffered non ECC DDR3 DIMM per channel thus allowing up to four device ranks per channel Note The processor supports only JEDEC approved memory modules and devices Note 2 DIMMs per channel supported only in Quad Core rPGA package Table 2 1 Processor Mobile DI MM Support Summary by Product DDR3 DDR3L DDR3L Processor Cores Package DI MM per Channel DDR3L RS DDR3L RS at 1 5 V at 1 35 V Dus Core rPGA BGA 1 DPC 1333 1600 1333 1600 Quad Core d Quad Core rPGA 2 DPC 1333 1600 1333
25. DDR3 o SB DQ 63 DDR3 IO o UO 1 1 o 7 1 I O 1 IO DDR3 1 P 7 o 1 o 1 IO 1 o 7 IO 1 o 1 7 o 7 SB DQS2 DDR3 SB_DQS 3 DDR3 5 6 7 SB_DQS SB_DQS DDR3 DDR3 SB_DQS DDR3 SB_DQS 1 DDR3 SB_DQS 3 DDR3 SB DQS 5 DDR3 SB DQS 7 DDR3 DDR3 DDR3 DDR3 DDR3 SB MA DDR3 SB MA 11 DDR3 SB MA 13 DDR3 DDR3 SB MA 15 DDR3 DDR3 SB_ODT 1 DDR3 Datasheet Volume 1 151 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 m 8 n tel Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir SB DDR3 VAXG Y48 PWR SM_DRAMPWROK Asynch CMOS VAXG W61 PWR SM DRAMRST VAXG W56 PWR SM RCOMP 0 VAXG W55 PWR SM RCOMP 1 VAXG W53 PWR SM RCOMP 2 VAXG W52 PWR SM VREF VAXG W51 PWR TCK VAXG W50 PWR TDI VAXG V59 PWR TDO VAXG V58 PWR THERMTRIP Asynch CMOS VAXG V56 PWR TMS CMOS VAXG V55 PWR TRST CMOS VAXG V53 PWR UNCOREPWRGOOD Asynch CMOS VAXG V52 PWR VAXG VAXG V51 PWR VAXG VAXG V50 PWR VAXG VAXG V
26. DirectX Video Acceleration DXVA support for accelerating video processing Full AVC VC1 MPEG2 HW Decode Advanced Scheduler 2 0 1 0 XPDM support Windows 7 Windows XP OSX Linux OS Support DirectX 11 DirectX 10 1 DirectX 10 DirectX 9 support OpenGL 3 0 support Datasheet Volume 1 Introduction 1 2 6 Embedded DisplayPort eDP e Stand alone dedicated port unlike two generations ago that shared pins with PCIe interface 1 2 7 Intel Flexible Display I nterface Intel FDI e For SKUs with graphics carries display traffic from the Processor Graphics in the processor to the legacy display connectors in the PCH e Based on DisplayPort standard e The two Intel FDI links are capable of being configured to support three independent channels one for each display pipeline e There are two Intel FDI channels each one consists of four unidirectional downstream differential transmitter pairs Scalable down to 3X 2X or 1X based on actual display bandwidth reguirements Fixed freguency 2 7 GT s data rate e Two sideband signals for display synchronization FDI FSYNC and FDI LSYNC Frame and Line Synchronization e One Interrupt signal used for various interrupts from the PCH FDI INT signal shared by both Intel FDI Links e PCH supports end to end lane reversal across both links Common 100 MHz reference clock 1 3 Power Management Support 1 3 1 Processor Core e Full support of ACPI C state
27. GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Datasheet Volume 1 157 intel Processor Pin Signal and Package I nformation Table 8 3 1023 Processor Ball List Table 8 3 1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball Buffer Type Dir vss W13 GND vss N21 GND vss w8 GND vss N17 GND vss V61 GND vss N1 GND vss V20 GND VSS M58 GND VSS U13 GND vss M15 GND vss u8 GND vss M11 GND vss T56 GND vss M6 GND vss T55 GND vss M4 GND vss T53 GND vss L61 GND vss T52 GND vss L48 GND vss T51 GND vss L43 GND vss T50 GND vss L38 GND vss T47 GND vss L34 GND vss T1 GND vss L30 GND vss R46 GND vss L26 GND vss R20 GND vss L22 GND vss R17 GND vss L20 GND vss R4 GND vss L16 GND vss P59 GND VSS K51 GND VSS P58 GND VSS K21 GND VSS P21 GND VSS K11 GND VSS P18 GND VSS K8 GND VSS P16 GND VSS J55 GND VSS P14 GND VSS J49 GND VSS P9 GND VSS 1 GND vss N61 GND vss H58 GND vss N56 GND vss H53 GND vss N52 GND vss H21 GND vss N51 GND vss H17 GND vss N48 GND vss H14 GND vss N47 GND vss H10 GND vss N43 GND vss H4 GND vss N40 GND vss G61 GND vss N36 GND vss G51 GND vss N33 GND vss G48 GND vss N28
28. Longer exit latency L3 Lowest power state power off Longest exit latency Direct Media Interface DMI States Direct Media Interface DMI States LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency LI Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency Processor Graphics Controller States Processor Graphics Controller States DO Full on display active D3 Cold Power off I nterface State Combinations G S and C State Combinations SE G Sleep Processor System Clocks Description tate S State C State State GO S0 CO Full On On Full On GO so C6 C7 peep ower On Deep Power Down G1 S3 Power off Off except RTC Suspend to RAM G1 S4 Power off Off except RTC Suspend to Disk G2 S5 Power off Off except RTC Soft Off G3 NA Power off Power off Hard off Datasheet Volume 1 53 intel Table 4 8 4 2 4 2 1 54 Power Management D S and C State Combination TED EMT Sleep S State Package C State Description DO 50 CO Full On Displaying DO 50 C1 C1E Auto Halt Displaying DO 50 C3 Deep sleep Displaying DO 50 C6 C7 Deep Power Down Displaying D3 S0 Any Not displaying D3 S3 N A NL EN Graphics Core is D3 S4 N A Not displaying suspend to disk Processor Core Power Management While executing code Enhan
29. Note 1 Long term reliability cannot be assured in conditions above or below Max Min functional limits 105 intel Electrical Specifications Table 7 9 Processor PLL Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note PLL ly volt DC AC Voss supply voltage E 1 8 a specification TOLccPLL VccPLL Tolerance AC DC 5 K IccMAx_vccpLL Max Current for Vccp Rail 1 2 A I Thermal Design Current TDC for 1 2 A CCTDC VCCPLL VccpL Rail Note 1 Long term reliability cannot be assured in conditions above or below Max Min functional limits Table 7 10 Processor Graphics Vaxc Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Active VID Range for VAxG XE SV QC 45W SV QC 35W SV DC Ultra DC GFX VID VAXG Processor Graphics core voltage Max Current for Processor Graphics Rail XE SV QC 45W SV QC 35W SV DC GT2 SV DC GT1 Ultra DC GT2 Ultra DC GT1 Thermal Design Current TDC for Processor Graphics Rail XE SV QC 45W SV QC 35W SV DC GT2 SV DC GT1 Ultra DC GT2 TDP nominal Ultra DC GT2 TDP Up Ultra DC GT2 TDP Down Ultra DC GT1 IcCMAX_VAXG IccTDC_VAXG VaxG Tolerance PS0 PS1 PS2 PS3 PS0 PS1 18 mV 7 5 18 5 7 5 27 5 TOLAxc Ripple Tolerance SI A Ripple Loadline GT2 based units
30. PECI DC Characteristics The PECI interface operates at a nominal voltage set by Vccro The set of DC electrical specifications shown in Table 7 15 is used with devices normally operating from a interface supply nominal levels will vary between processor families All PECI devices will operate at the Vccro level determined by the processor installed in the system For specific nominal Vccro levels refer to Table 7 6 PECI DC Electrical Limits Vin Input Voltage Range 0 15 Vnysteresis Hysteresis 0 1 Vccro N A Vn Negative Edge Threshold Voltage 0 275 Vccro 0 500 Vccro Positive Edge Threshold Voltage 0 550 0 725 Vecio Cbus Bus Capacitance per Node N A 10 Cpad Pad Capacitance 1 8 Ileak000 leakage current OV 0 6 IleakO25 leakage current 0 25 Vccro 0 4 Ileak050 leakage current 0 50 Vccro 0 2 Ileak075 leakage current 0 75 Vccro 0 13 Ileak100 leakage current Vccro 0 10 Notes 1 supplies the PECI interface PECI behavior does not affect Vccro Min Max specifications 2 The leakage specification applies to powered devices on the PECI bus 3 PECI buffer internal pull up resistance measured at 0 75 Vccro I nput Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 7 2 as a guide for input buffer design Input De
31. PEG_RX 15 C32 PCIe I PEG TX 14 E26 PCIe _ 0 133 PCIe I PEG TX 15 D25 PCIe _ 1 135 PCIe I SYNC AM34 Asynch CMOS I PEG RX 2 K34 PCIe I PRDY AP29 Asynch CMOS _ 3 H35 PCIe I PREQ AP27 Asynch CMOS I PEG RX 4 H32 PCIe I PROC SELECT amp C26 N A _ 5 G34 PCIe I PROCHOT AL32 Asynch CMOS 1 0 PEG RX 6 G31 PCIe I RESET AR33 Asynch CMOS I PEG RX 7 F33 PCIe I RSVD C30 PEG RX 8 F30 PCIe I RSVD A31 PEG RX 9 E35 PCIe I RSVD B30 PEG RX 10 E33 PCIe I RSVD B29 PEG RX 11 F32 PCIe I RSVD D30 PEG RX 12 D34 PCIe I RSVD B31 PEG RX 13 E31 PCIe I RSVD A30 PEG RX 14 C33 PCIe I RSVD C29 PEG RX 15 B32 PCIe I RSVD F25 PEG TX4 0 M29 PCIe RSVD F24 PEG TX 1 M32 PCIe RSVD F23 PEG_TX 2 M31 PCIe RSVD D24 PEG TX 3 L32 PCIe RSVD G25 PEG_TX 4 L29 PCIe RSVD G24 PEG 4 5 K31 PCIe RSVD E23 PEG 4 6 K28 PCIe RSVD D23 PEG TX 7 J30 PCIe RSVD AT26 PEG TX 8 J28 PCIe RSVD AG7 PEG 4 9 H29 PCIe RSVD AE7 PEG TX 10 G27 PCIe RSVD W PEG TX 11 E29 PCIe RSVD T8 PEG TX 12 F27 PCIe RSVD L7 PEG TX 13 D28 PCIe RSVD J20 PEG TXF 14 F26 PCIe RSVD J16 PEG TX 15 E25 PCIe RSVD AM33 PEG TX 0 M28 PCIe RSVD J15 PEG TX 1 M33 PCIe RSVD H16 PEG TX 2 M30 PCIe RSVD G16 PEG TX 3 L31 PCIe RSVD B18 Datasheet Volume 1 115 m 8 n tel Processor Pin Signal and Package Information Table 8 1
32. Reset and Miscellaneous Signals Signal Name Description Bu rs Configuration Signals The CFG signals have a default value of 1 if not terminated on the board CFG 1 0 Reserved configuration lane A test point may be placed on the board for this lane CFG 2 PCI Express Static x16 Lane Numbering Reversal 1 Normal operation 0 Lane numbers reversed 3 Reserved I CFG 17 0 4 eDP enable CMOS 1 Disabled 0 Enabled CFG 6 5 PCI Express Bifurcation 00 1 x8 2 4 PCI Express 01 reserved 10 2 x8 PCI Express 11 1 x16 PCI Express CFG 17 7 Reserved configuration lanes A test point may be placed on the board for these pins PM SYNC Power Management Sync A sideband signal to communicate I power management status from the platform to the processor CMOS RESET Platform Reset pin driven by the PCH ance Reserved All signals that are RSVD and RSVD_NCTF must be left No Connect RSVD RSVD TP unconnected on the board However Intel recommends that all Test Point RSVD TP signals have via test points Non Critical to RSVD NCTF Function DDR3 DRAM Reset Reset signal from processor to DRAM devices SM_DRAMRST One common to all channels CMOS Datasheet Volume 1 8 Signal Description em 6 4 PCI Express based I nterface Signals Table 6 6 PCI Express Graphics Interface Signals idis z P PEG_ICOMPI PCI Express Input Current Compensation z PEG_IC
33. SA DQS 4 ALS DDR3 70 SB DQ 10 Fi DDR3 I O SA DQS 5 AM9 DDR3 I O SB DQ 11 G1 DDR3 I O SA DQS 6 AR11 DDR3 I O SB DQ 12 G5 DDR3 I O SA DQS 7 AM14 DDR3 I O SB DQ 13 F5 DDR3 1 0 SA_MA 0 AD10 DDR3 SB DQ 14 F2 DDR3 I O SA MA 1 wi DDR3 SB DQ 15 G2 DDR3 I O SA MA 2 w2 DDR3 SB DQ 16 17 DDR3 I O SA MA 3 W7 DDR3 SB DQ 17 J8 DDR3 I O SA MA 4 v3 DDR3 SB DQ 18 K10 DDR3 I O SA MA 5 v2 DDR3 SB DQ 19 K9 DDR3 1 0 SA_MA 6 wa DDR3 SB DQ 20 J9 DDR3 I O SA MA 7 W6 DDR3 SB_DQ 21 J10 DDR3 I O SA MA 8 V1 DDR3 SB DQ 22 K8 DDR3 70 SA MA 9 WS DDR3 SB DQI 23 K7 DDR3 I O Datasheet Volume 1 117 m 8 n tel Processor Pin Signal and Package Information Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type bir Pin Name Pin Buffer Type bir SB DQ 24 M5 DDR3 1 0 SB_DQS 7 AP15 DDR3 I O SB_DQ 25 N4 DDR3 I O SB_DQS 0 C7 DDR3 7 SB DQ 26 N2 DDR3 I O SB_DQS 1 G3 DDR3 I O SB_DQ 27 N1 DDR3 1 0 SB_DQS 2 16 DDR3 I O SB DQ 28 M4 DDR3 1 0 SB_DQS 3 M3 DDR3 1 0 SB_DQ 29 N5 DDR3 I O SB_DQS 4 AN6 DDR3 I O SB_DQ 30 M2 DDR3 I O SB_DQS 5 AP8 DDR3 I O SB_DQ 31 M1 DDR3 I O SB_DQS 6 AK11 DDR3 I O SB DQ 32 AM5 DDR3 7 SB DQS 7 AP14 DDR3 1 0 SB_DQ 33 AM6 DDR3 I O SB_MA 0 AA8 DDR3 SB DQ 34 AR3 DDR3 1 0 SB_MA 1 T7 DDR3 SB DQ 35 AP3 DDR3 7 SB MA 2 R7 DDR3 SB DQ 36 AN3 DDR3 1 0 SB
34. Signals u mre n ek IER nn nnn rex EA HEEN ee Rap qasa 88 6 11 Test Access Points TAP 4 8 5 de EEN dE EEN NEE ENEE saad nh cen RH E Ya DAR ERR dE d 88 6 12 Error and Thermal Protection Gionale nemen eem nns 89 6 13 Power Sequencing Signals ssssssssssssssssssssseese EL A ELLA RL eene emm nnns 90 6 14 Processor Power Signals ete bee UF ide De 91 Le KT 91 6 16 Ground and Non Critical to Function NCTF 92 6 17 Processor Internal Pull Up Pull Down Resistors cesses mmm 92 7 1 IMVP7 Voltage Identification Definition r r rr 94 7 2 VCCSA VID Configura tioN us pesante roce te Deka esi sw RR RE HA EEN DER ENEE Ee 97 7 3 Signal 6 51 m 98 7 4 Storage Condition Ratings ierit rene ce ani Niege ENEE EES EN waqasa RR 100 7 5 Processor Core Vcc Active and Idle Mode DC Voltage and Current Specifications 101 7 6 Processor Uncore Vccro Supply DC Voltage and Current Specifications 103 7 7 Memory Controller Vppo Supply DC Voltage and Current Specifications 103 7 8 System Agent VccsA Supply DC Voltage and Current Specifications 103 7 9 Processor PLL Supply DC Voltage and Current Specifications
35. TLP Thermal Design Power Transaction Layer Packet VaxG Graphics core power supply Vccio Processor core power supply High Frequency I O logic power supply VccpLL PLL power supply VccsA System Agent memory controller DMI PCIe controllers and display engine power supply VDDQ DDR3 power supply VGA VID Video Graphics Array Voltage Identification VLD Variable Length Decoding VLW VR Virtual Legacy Wire Voltage Regulator Processor ground VTS x1 Virtual Temperature Sensor Refers to a Link or Port with one Physical Lane x16 Refers to a Link or Port with sixteen Physical Lanes x4 x8 Refers to a Link or Port with four Physical Lanes Refers to a Link or Port with eight Physical Lanes Datasheet Volume 1 23 m e Introduction intel 1 8 Related Documents Table 1 3 Related Documents Mobile 3rd Generation Intel Core Processor Family Intel Pentium Processor Family and Intel Celeron Processor Family Datasheet Volume 2 326769 Document Number Document Location Mobile 3rd Generation Intel Core Processor Family Intel Pentium Processor Family and Intel Celeron Processor Family Specification Update 326770 Advanced Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 http www pcisig com speci fications PCI Express
36. Technologies 3 6 2 3 6 3 3 7 intel AES NI consists of six Intel SSE instructions Four instructions namely AESENC AESENCLAST AESDEC and AESDELAST facilitate high performance AES encryption and decryption The other two AESIMC and AESKEYGENASSIST support the AES key expansion procedure Together these instructions provide a full hardware for support AES offering security high performance and a great deal of flexibility PCLMULQDO Instruction The processor supports the carry less multiplication instruction PCLMULQDQ PCLMULODO is a Single Instruction Multiple Data SIMD instruction that computes the 128 bit carry less multiplication of two 64 bit operands without generating and propagating carries Carry less multiplication is an essential processing component of several cryptographic systems and standards Hence accelerating carry less multiplication can significantly contribute to achieving high speed secure computing and communication RDRAND Instruction The processor introduces a software visible random number generation mechanism supported by a high quality entropy source This capability will be made available to programmers through the new RDRAND instruction The resultant random number generation capability is designed to comply with existing industry standards in this regard ANSI X9 82 and NIST SP 800 90 Some possible usages of the new RDRAND instruction include cryptographic key generation as used in a v
37. intel Power Management 4 2 5 1 4 2 5 2 4 2 5 3 4 2 5 4 60 Package CO Package CO is the normal operating state for the processor The processor remains in the normal state when at least one of its cores is in the CO or C1 state or when the platform has not granted permission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in CO Package C1 CIE No additional power reduction actions are taken in the package C1 state However if the C1E sub state is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when e At least one core is in the C1 state e The other cores are in a C1 or lower power state The package enters the C1E state when All cores have directly requested C1E using MWAIT C1 with a C1E sub state hint e All cores are in a power state lower that C1 C1E but the package low power state is limited to C1 C1E using the PMG_CST_CONFIG_CONTROL MSR e All cores have requested C1 using HLT or MWAIT C1 and C1E auto promotion is enabled in IA32 MISC ENABLES No notification to the system occurs upon entry to C1 C1E Package C3 State A processor enters the package C3 low power state when e At least one core is in the C3 state e The other cores are in a C3 or lower power state and the processor has been granted permission b
38. the 2x8 PEG is not supported 2 5 Platform Environment Control Interface PECI The PECI is a one wire interface that provides a communication channel between a PECI client processor and a PECI master The processor implements a PECI interface to Allow communication of processor thermal and other information to the master Read averaged Digital Thermal Sensor DTS values for fan speed control 2 6 I nterface Clocking 2 6 1 I nternal Clocking Requirements Table 2 6 Reference Clock Reference Input Clock I nput Freguency Associated PLL BCLK BCLK 100 MHz Processor Memory Graphics PCIe DMI FDI DPLL REF CLK DPLL REF 120 MHz Embedded DisplayPort eDP ss 40 Datasheet Volume 1 Technologies 3 3 1 3 1 1 intel Technologies This chapter provides a high level description of Intel technologies implemented in the processor The implementation of the features may vary between the processor SKUs Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site http www intel com technology I ntel Virtualization Technology Intel VT Intel Virtualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single system Intel VT comprises technology components to support virtualiza
39. 0 0 8 O 0 88500 1 01025000 0 59000 0 0 0 1 0 01210 25500 1 0 0 0 0 1 0 8 2 0 89500 o 1 0 0 0 0 1 0 0 8 4 090500 0 0 0 5 0 27000 1 0 0 0 1 0 1 8 5 0 91000 1 0 0 0 0 1 11 1 8 7 092000 0 0 0 1 0 0 8 0 28500 1 0 0 1 0 0 0 8 8 0 92500 otooto i ototo 1 0 o a 1 0 0 1 tes 6530 o o o o 1 o 1 o o ajoz250 i o T o o o 1 0 sal 093500 0 0 0 1 0 B 0 30000 1 0 0 1 0 1 1 8 B 0 94000 o 1 0 0 0 1 1 0 1 8 D 095000 0 0 0 O 01ET0 31500 1 0 0 1 1 1 0 8 E 0 95500 o 101032500 i o o r o 096500 0 0 0 1 1 1 0 33000 1 0 0 1 0 0 0 1 1 0 97000 1 0 0 1 0 0 1 1 9 3 098000 0 0 0 0 1 4 0 34500 1 0 0 1 0 1 0 0 4 0 98500 olo jo 0 1 6 0 35500 1 0 o 1ipo 1i 1 o 9 6 0 99500 0 0 0 1 0 1 1 1 1 7 0 36000 1 0 0 0 1 1 1 9 7 1 00000 96 Datasheet Volume 1 intel Sheet 2 of 3 ion VID 6 ini Defi I MVP7 Voltage Identification Electrical Specifications Table 7 1 x lt o E x ul ac gt a cr Hl 2 1 01000 1 01500 1 02500 9 C 1 05500 1 07000 1 11500 1 13000 1 14500 1 16000 F 1 5 7 8 1 20500 1 22000 S8 100500 0 9 9 D 9 F 1 04000 A O 1 04500 E 1 1 1 0 1 REN SES 1 17500 1 18000 1 O 1 B B D cjo ca C 6 9
40. 1 05 V CCIO motherboard SENSE and Vss sENSE vccio TO Vecio Tolerance defined across DC 2 including ripple Vccro_seuse and vccio 3 IccMax vccro Max Current for Rail s 8 5 A I Thermal Design Current TDC for 8 A CCTDC_VCCIO vccro Rail 5 Note 1 Long term reliability cannot be assured in conditions above or below Max Min functional limits Memory Controller Vppg Supply DC Voltage and Current Specifications AC DC 5 IccMAX_VDDQ Max Current for VDDQ Rail I Thermal Design Current TDC CCTDC_VDDQ for VDDQ Rail I Average Current for Rail CCAVG VDDQ Standby during Standby Processor I O supply voltage Mp AC for DDR3 DC AC 1 5 specification Processor I O supply voltage SEN Ge for DDR3L DDR3L RS DC 1 35 AC specification Vppq Tolerance 3 TOLppo 2 Note 1 The current supplied to the SO DIMM modules is not included in this specification System Agent VccsA Supply DC Voltage and Current Specifications Voltage for the System Agent and VccsA SENSE VccsA TOLccsA Vecsa Tolerance Max Current for VccsA Rail XE and SV IcCMAX_VCCSA 7 Max Current for Vccsa Rail Ultra Thermal Design Current TDC for VccsA Rail XE and SV Iccrpc vccsA Thermal Design Current TDC for VccsA Rail Ultra Slew Rate Voltage Ramp rate dV dT 0 5 10 mV us
41. 2 DMI 15 CMOS I TX4 3 DMI 16 CMOS I DMI TX 0 DMI 17 CMOS I DMI TX 1 DMI DBR Asynch CMOS DMI TX 2 DMI DC TEST A4 N A DMI TX 3 DMI DC TEST A62 N A DPLL REF CLK Diff Clk I DC TEST A64 N A DPLL REF CLK Diff Clk I DC_TEST_B3 N A eDP_AUX eDP yo DC_TEST_B63 N A eDP_AUX eDP yo Datasheet Volume 1 127 intel Processor Pin Signal and Package I nformation Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type bir Ball Name Ball Buffer Type bir eDP COMPIO AC2 Analog I PEG RX2 1 H23 PCIe I eDP_HPD AE8 Asynch CMOS I PEG_RX 2 H21 I eDP_ICOMPO AB1 Analog I PEG RX 3 H19 PCIe I eDP_TX 0 AG2 eDP PEG_RX 4 120 1 eDP_TX 1 AF1 eDP _ 5 G18 PCIe I eDP_TX 2 AE6 eDP _ 6 K17 I eDP_TX 3 AG6 eDP PEG_RX 7 F15 PCIe I eDP_TX 0 AG4 eDP PEG_RX 8 H15 I eDP_TX 1 AF3 eDP _ 9 H13 PCIe I eDP_TX 2 AF7 eDP _ 10 11 1 eDP TX 3 AG8 eDP _ 11 112 1 FDI INT AD9 Asynch CMOS I PEG RX4 12 E8 I FDIO FSYNC AC8 CMOS I PEG RX4 13 G10 PCIe I FDI0_LSYNC AB7 I PEG_RX 14 18 1 FDIO_TX 0 V7 FDI _ 15 7 PCIe I FDIO_TX 1 ws FDI PEG RX 0 G22 I FDIO_TX 2 AA8 FDI _ 1 K23 PCIe I FDIO_TX 3 AC10 FDI
42. AD27 PWR VAXG AN18 PWR VCC AD28 PWR VAXG AN20 PWR VCC AD29 PWR VAXG AN21 PWR VCC AD30 PWR VAXG AN23 PWR VCC AD31 PWR VAXG AN24 PWR VCC AD32 PWR VAXG AP17 PWR VCC AD33 PWR VAXG AP18 PWR VCC AD34 PWR VAXG AP20 PWR VCC AD35 PWR VAXG AP21 PWR VCC AF26 PWR VAXG AP23 PWR VCC AF27 PWR VAXG AP24 PWR VCC AF28 PWR VAXG AR17 PWR VCC AF29 PWR VAXG AR18 PWR VCC AF30 PWR VAXG AR20 PWR VCC AF31 PWR VAXG AR21 PWR VCC AF32 PWR VAXG AR23 PWR VCC AF33 PWR VAXG AR24 PWR VCC AF34 PWR VAXG AT17 PWR VCC AF35 PWR VAXG AT18 PWR VCC AG26 PWR VAXG AT20 PWR VCC AG27 PWR Datasheet Volume 1 119 intel Processor Pin Signal and Package I nformation Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type bir Pin Name Pin Buffer Type bir AG28 PWR v35 PWR VCC AG29 PWR VCC Y26 PWR VCC AG30 PWR VCC Y27 PWR VCC AG31 PWR VCC Y28 PWR VCC AG32 PWR VCC Y29 PWR VCC AG33 PWR VCC Y30 PWR VCC AG34 PWR VCC Y31 PWR VCC AG35 PWR VCC Y32 PWR VCC P26 PWR VCC Y33 PWR VCC P27 PWR VCC Y34 PWR VCC P28 PWR VCC Y35 PWR VCC P29 PWR RSVD AH27 Analog 30 PWR VCC SENSE AJ35 Analog 31 PWR VCC VAL SENSE AJ33 Analog 32 PWR VCCIO J23 PWR 33 PWR VCCIO A11 PWR P34 PWR VCCIO A12 PWR 35 PWR VCCIO AC10 PWR R26 PWR VCCIO AG10 PWR 27 PWR VCCIO AH10 PWR R28 PWR VCCIO AH13 PWR R29 PWR
43. GND VSS L8 GND VSS F39 GND VSS K39 GND VSS F33 GND VSS K33 GND VSS F27 GND VSS K27 GND VSS E60 GND VSS GND VSS E56 GND VSS J64 GND VSS E52 GND VSS J60 GND VSS E48 GND VSS J56 GND VSS E46 GND VSS J52 GND VSS E42 GND VSS J48 GND VSS E36 GND VSS J46 GND VSS E30 GND VSS J42 GND VSS E24 GND VSS J36 GND VSS E22 GND VSS J30 GND VSS E18 GND VSS 124 GND VSS E14 GND VSS J22 GND VSS E10 GND VSS J18 GND VSS E6 GND VSS J14 GND VSS E4 GND VSS J10 GND VSS D63 GND VSS J6 GND VSS D39 GND VSS H39 GND VSS D33 GND VSS H33 GND VSS D27 GND VSS H27 GND VSS C58 GND VSS H3 GND VSS C54 GND VSS G62 GND VSS C50 GND VSS G58 GND VSS C46 GND VSS G54 GND VSS C42 GND VSS G50 GND VSS C36 GND 142 Datasheet Volume 1 8 Processor Pin Signal and Package I nformation n tel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir vss C30 GND VSSAXG_SENSE E50 Analog vss C20 GND VSSAXG_VAL_SENSE Analog vss C16 GND VSS_SENSE_VCCIO Analog vss C12 GND vss C8 GND vss B39 GND vss B33 GND vss B27 GND vss A56 GND vss A52 GND vss A42 GND vss A36 GND vss A30 GND vss A24 GND vss A20 GND vss A16 GND vss A12 GND vss 8 GND VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
44. Increased range of processor addressability in x2APIC mode Physical xAPIC ID field increases from 8 bits to 32 bits allowing for interrupt processor addressability up to 4 GB 1 processors in physical destination mode A processor implementation of x2APIC architecture can support fewer than 32 bits in a software transparent fashion Logical xAPIC ID field increases from 8 bits to 32 bits The 32 bit logical 2 ID is partitioned into two sub fields a 16 bit cluster ID and a 16 bit logical ID within the cluster Consequently 2 20 16 processors can be addressed in logical destination mode Processor implementations can support fewer than 16 bits in the cluster ID sub field and logical ID sub field in a software agnostic fashion More efficient MSR interface to access APIC registers To enhance inter processor and self directed interrupt delivery as well as the ability to virtualize the local APIC the APIC register set can be accessed only through MSR based interfaces in the x2APIC mode The Memory Mapped IO MMIO interface used by xAPIC is not supported in the x2APIC mode e The semantics for accessing APIC registers have been revised to simplify the programming of frequently used APIC registers by system software Specifically the software semantics for using the Interrupt Command Register ICR and End Of Interrupt EOI registers have been modified to allow for more efficient delivery and dispatching of interru
45. O eDP_HPD B16 Asynch CMOS I BPM 3 AT30 Asynch CMOS I O eDP ICOMPO A17 Analog I BPM 4 AP32 Asynch CMOS 1 0 eDP_TX 0 C18 eDP 5 1 Asynch CMOS 1 eDP_TX 1 E16 eDP 4 6 AT31 Asynch CMOS 1 0 eDP_TX 2 D16 eDP BPM 7 AR32 Asynch CMOS 1 eDP_TX 3 F15 eDP CATERR AL33 Asynch CMOS eDP TX 0 C17 eDP CFG 0 AK28 CMOS I eDP TX 1 F16 eDP CFG 1 AK29 CMOS I eDP TX 2 C16 eDP 2 AL26 CMOS I eDP TX 3 G15 eDP CFG 3 AL27 CMOS I FDI INT H20 Asynch CMOS I CFG 4 AK26 CMOS I FDIO FSYNC J18 CMOS I CFG 5 AL29 CMOS I FDIO LSYNC J19 CMOS I CFG 6 AL30 CMOS I FDIO_TX 0 A21 FDI CFG 7 AM31 CMOS I FDIO_TX 1 H19 FDI CFG 8 AM32 CMOS I FDIO_TX 2 E19 FDI CFG 9 AM30 CMOS I FDIO_TX 3 F18 FDI 10 28 CMOS I FDIO TX 0 A22 FDI 11 26 CMOS I FDIO TX 1 G19 FDI CFG 12 AN28 CMOS I FDIO TX 2 E20 FDI 13 AN31 CMOS I FDIO TX 3 G18 FDI 14 26 CMOS I FDI1 FSYNC J17 CMOS I CFG 15 AM27 CMOS I FDI1_LSYNC H17 CMOS I CFG 16 AK31 CMOS I FDI1_TX 0 B21 FDI CFG 17 AN29 CMOS I FDI1_TX 1 C20 FDI DBR AL35 Asynch CMOS o FDI1_TX 2 D18 FDI DMI_RX 0 B27 DMI I FDI1_TX 3 E17 FDI DMI_RX 1 B25 DMI I FDI1_TX O B20 FDI DMI_RX 2 A25 DMI I FDI1_TX 1 C19 FDI DMI_RX 3 B24 DMI I FDI1 TX 2 D19 FDI DMI_RX 0 B28 DMI I FDI1_TX 3 F17 FDI DMI RX 1 B26 DMI I KEY B1 N A N A DMI_RX 2 A24 DMI I PECI AN3
46. Os Intel FDI supports two or three independent channels one for pipe A one for pipe B and one for Pipe C Channels A and B have a maximum of four transmit Tx differential pairs used for transporting pixel and framing data from the display engine in two display configurations In three display configurations Channel A has 4 transmit Tx differential pairs while Channel B and C have two transmit Tx differential pairs Each channel has four transmit Tx differential pairs used for transporting pixel and framing data from the display engine Each channel has one single ended LineSync and one FrameSync input 1 V CMOS signaling One display interrupt line input 1 V CMOS signaling Intel FDI may dynamically scale down to 2X or 1X based on actual display bandwidth requirements Common 100 MHz reference clock e Each channel transports at a rate of 2 7 Gbps e PCH supports end to end lane reversal across both channels no reversal support required in the processor Datasheet Volume 1 39 intel Interfaces 2 4 4 Multi Graphics Controllers Multi Monitor Support The processor supports simultaneous use of the Processor Graphics Controller GT and a x16 PCI Express Graphics PEG device The processor supports a maximum of 2 displays connected to the PEG card in parallel with up to 2 displays connected to the processor and PCH Note When supporting Multi Graphics Multi Monitors drag and drop between monitors and
47. RX 12 PCIe I PCIe I FDIO FSYNC LSYNC CMOS PEG RX 13 PEG RX 14 PCIe I PCIe I FDIO TX 0 FDIO TX 1 PEG RX 15 PCIe I PCIe I FDIO TX 2 TX 3 PCIe I PCIe I FDIO TX 0 FDIO TX 1 PCIe I PCIe I FDIO TX 2 FDIO TX 3 FDI1 FSYNC FDI1 LSYNC FDI1_TX 0 FDI1_TX 1 FDI1_TX 2 FDI1_TX 3 FDI1_TX 0 FDI1_TX 1 FDI1_TX 2 FDI1_TX 3 PEG TX PECI PEG_ICOMPI PEG TX PEG TX PEG_ICOMPO PEG_RCOMPO PEG_TX PEG TX PEG RX 0 Datasheet Volume 1 PEG TX 147 intel Processor Pin Signal and Package I nformation Table 8 3 BGA1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball Buffer Type Dir PEG 4 6 RSVD BE26 PEG TX 8 RSVD PEG_TX 9 SA_DIMM_VREFDQ PEG_TX 10 RSVD BD26 PEG_TX 12 RSVD BD22 PEG_TX 14 RSVD BB21 PEG TX 0 RSVD BA22 PEG TX 2 RSVD AY22 PEG TX 4 RSVD AV19 PEG TX 6 RSVD AU19 PEG TX 8 RSVD AT21 PEG TX 10 RSVD AM14 PEG TX 11 RSVD AH2 PEG TX 12 RSVD AG13 PEG TX 14 RSVD U14 PEG TX 15 RSVD P13 SYNC Asynch CMOS RSVD N50 PRDY Asynch CMOS RSVD N42 PREQ Asynch CMOS RSVD M14 PROC_SELECT N A RSVD L47 PR
48. Removed references to the VCC_DIE_SENSE signal and changed affected balls in Chapter 8 to RSVD Added Mobile 3rd Generation Intel Core i7 3540M i5 3380M i5 3340M i7 3687U i5 3437U processors 005 Added Mobile Intel Pentium processor family and added Mobile Intel Pentium 2030M processor Added Mobile Intel Celeron processor family and added Mobile Intel Celeron 1037U 1020M 1007U 1000M processors ss Datasheet Volume 1 April 2012 June 2012 June 2012 September 2012 January 2013 em e 10 Datasheet Volume 1 I ntroduction 1 Note Note Note Note Note intel Introduction The Mobile 3rd Generation Intel Core processor family Mobile Intel Pentium processor family and Mobile Intel Celeron processor family are the next generation of 64 bit multi core mobile processors built on 22 nanometer process technology The processor is designed for a two chip platform The two chip platform consists of a processor and a Platform Controller Hub PCH and enables higher performance lower cost easier validation and improved x y footprint The processor includes Integrated Display Engine Processor Graphics and an Integrated Memory Controller The processor is designed for mobile platforms The Mobile 3rd Generation Intel Core processor family Mobile Intel Pentium processor family and Mobile Intel Celeron processor family offer either 6 or 16 graphic execu
49. Technology is a performance feature that makes use of unused package power and thermals to increase application performance The increase in frequency is determined by how much power and thermal budget is available in the package and the application demand for additional processor or graphics performance The processor core control is maintained by an embedded controller The graphics driver dynamically adjusts between P States to maintain optimal performance power and thermals Datasheet Volume 1 Power Management 4 6 6 4 6 7 4 6 8 Display Power Savings Technology 6 0 DPST This is a mobile only supported power management feature The Intel DPST technique achieves backlight power savings while maintaining a good visual experience This is accomplished by adaptively enhancing the displayed image while decreasing the backlight brightness simultaneously The goal of this technique is to provide equivalent end user perceived image quality at a decreased backlight power level 1 The original input image produced by the operating system or application is analyzed by the Intel DPST subsystem An interrupt to Intel DPST software is generated whenever a meaningful change in the image attributes is detected A meaningful change is when the Intel DPST software algorithm determines that enough brightness contrast or color change has occurred to the displaying images that the image enhancement and backlight control needs to be altered
50. VCCIO AT55 PWR VCCIO AH16 PWR VCCIO AT53 PWR VCCIO AH14 PWR 136 Datasheet Volume 1 8 Processor Pin Signal and Package I nformation n tel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir VCCIO AH11 PWR VCCSA M15 PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR VCCSA SENSE Analog PWR VCCSA VID 0 CMOS PWR VCCSA_VID 1 CMOS PWR VDDO PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR VCCIO_SEL N A PWR VCCIO_SENSE Analog PWR VCCPLL PWR PWR VCCPLL PWR PWR VCCPLL PWR PWR VCCPOE PWR PWR VCCPOE PWR PWR VCCPOE PWR PWR VCCPOE PWR PWR VCCSA PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Datasheet Volume 1 137 intel Processor Pin Signal and Package I nformation Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type bir Ball Name Ball Buffer Type Dir VDDO AU30 PWR VDDO AL34 PWR VDDO AU26 PWR VDDO AL29 PWR VDDO AU24 PWR VDDO AL27 PWR VDDO AT46 PWR VDDQ_SENSE AY19 Analog VDDQ AT42 PWR VIDALERT B51 CMOS I VDDQ 40 PWR VIDSCLK D51 VDDQ AT36 PWR VIDSOUT
51. WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request This document contains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the product is available Verify with your local sales office that you have the latest datasheet before finalizing a design Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com design literature htm Enabling Execute Disable Bit functio
52. consist of output logic and pins that transmit the display data to the associated encoding logic and send the data to the display device that is LVDS HDMI DVI SDVO and so on All display interfaces connecting external displays are now repartitioned and driven from the PCH with the exception of the eDP DisplayPort Refer to the PCH datasheet for more details on display port support Embedded DisplayPort eDP The Processor Graphics supports the Embedded Display Port eDP interface intended for display devices that are integrated into the system such as laptop LCD panel DisplayPort consolidates internal and external connection methods to reduce device complexity support cross industry applications and provide performance scalability The eDP interface supports link speeds of 1 62 Gbps and 2 7 Gbps on 1 2 or 4 data lanes The eDP supports 0 5 SSC and non SSC clock settings The eDP on the processor is compliant with VESA DP specification 1 1a except the electrical parameters that appear in Table 7 14 Embedded DisplayPort DC Specifications The eDP interface supports Alternate Scrambler Seed Reset ASSR for eDP display authentication thereby enabling secure transfer of protected content over the cable to sink device Intel Flexible Display I nterface Intel FDI The Intel Flexible Display Interface Intel FDI is a proprietary link for carrying display traffic from the Processor Graphics controller to the PCH display I
53. doooooo 290 209 0000 99 9990 9990009999 98 99 900000990 9099 999090 990 00000 990 9908 999090 oo 00 00000 ooo 999590 oo 9900900 8 88808 9990 999099 9090 99099 E 995908 5650 600808 5590 9 9 80089 88 9 0000000000080000000000000000000000000 9 00 t 899909 909 000 999 909 900 040 209 209 909 000 000 9909999 9090 0 009 ooo ooo ofo 9 690 090 000 000 0000000 i og 11095 10101019 1N3AND Ty 317815815 j 119130 1H213H 31gvMoT1v AL HT W 3803 13 3l Wid 1113030 401 3H1 02 39912 Datasheet Volume 1 166 intel 311 IHL 6 13 Y9E 1 HOI3H YO8 INS 18 13 p ms 9
54. dropped Supports the following traffic types to or from the PCH DMI DRAM DMI gt processor core Virtual Legacy Wires VLWs Resetwarn or MSIs only Processor core gt DMI APIC and MSI interrupt messaging support Message Signaled Interrupt MSI and MSI X messages Downstream SMI SCI and SERR error indication Legacy support for ISA regime protocol PHOLD PHOLDA required for parallel port DMA floppy drive and LPC bus masters DC coupling no capacitors between the processor and the PCH Polarity inversion PCH end to end lane reversal across the link Supports Half Swing low power low voltage Platform Environment Control I nterface PECI The PECI is a one wire interface that provides a communication channel between a PECI client the processor and a PECI master The processor supports the PECI 3 0 Specification Processor Graphics The Processor Graphics contains a refresh of the seventh generation graphics core enabling substantial gains in performance and lower power consumption Up to 16 EU support Next Generation Intel Clear Video Technology HD Support is a collection of video playback and enhancement features that improve the end user s viewing experience Encode transcode HD content Playback of high definition content including Blu ray Disc Superior image quality with sharper more colorful images Playback of Blu ray disc S3D content using HDMI V 1 4 with 3D
55. during power on Reset CMOS 6 10 Error and Thermal Protection Signals Table 6 12 Error and Thermal Protection Signals SS Direction Signal Name Description Buffer Type Catastrophic Error This signal indicates that the system has experienced a catastrophic error and cannot continue to operate The processor will set this for non recoverable machine check errors or other unrecoverable internal errors CATERR On the processor CATERR is used for signaling the following types of errors Legacy MCERRs CATERR is asserted for 16 BCLKs Legacy IERRs CATERR remains asserted until warm or cold reset PECI Platform Environment Control I nterface A serial uo PECI sideband interface to the processor it is used primarily for A h thermal power and error management synchronous Processor Hot PROCHOT goes active when the processor temperature monitoring sensor s detects that the processor has reached its maximum safe operating temperature This indicates CMOS Input PROCHOT that the processor Thermal Control Circuit TCC has been Open Drain activated if enabled This signal can also be driven to the Output processor to activate the TCC Thermal Trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is o set well above the normal operating temperature to ensure that TEETH there are no false trips The processor will stop all execution EE when the junction temperature exceeds app
56. family Mobile Intel Pentium processor family Mobile Intel Celeron processor family For 2nd Generation Intel Core processor family mobile the output will be high For Mobile 3rd Generation Intel Core processor family Mobile Intel Pentium processor family Mobile Intel Celeron processor family the output will be low PROC_SELECT Voltage selection for VCCIO This output signal was initially intended to select the I O voltage depending on the processor being used Since the Vccro voltage is the same for 2nd Generation Intel Core processor family mobile and Mobile 3rd Generation VCCIO_SEL Intel Core processor family Mobile Intel Pentium processor family Mobile Intel Celeron processor family the usage of this signal was changed as follows This signal should not be used 92 Datasheet Volume 1 Signal Description 6 12 Processor Power Signals Table 6 14 Processor Power Signals I Direction Signal Name Description Buffer Type VCC Processor core power rail Ref VCCIO Processor power for I O Ref VDDQ Processor I O supply voltage for DDR3 Ref VAXG Graphics core power supply Ref VCCPLL VCCPLL provides isolated power for internal processor PLLs Ref VCCSA System Agent power supply Ref VCCPQE BGA Only low noise derivative of Vccro Load current is less than Ref VCCDQ BGA Only ca low noise derivative of Vppg Load current is le
57. ge EENS AE d TRE 123 8 3 BGA1224 Ballmap right aide 124 8 4 BGA1023 Ballmap left ca ENER LLU na ku su ROEDD aa RR a d nun 142 8 5 BGA1023 Ballmap right aide 143 8 6 Processor rPGA988B 2C GT1 G24406 Mechanical Package Sheet 1 of 2 158 8 7 Processor rPGA988B 2C GT1 G24406 Mechanical Package Sheet 2 of 2 159 8 8 Processor rPGA988B 2C GT2 G23867 Mechanical Package Sheet 1 of 2 160 8 9 Processor rPGA988B 2C GT2 G23867 Mechanical Package Sheet 2 of 2 161 8 10 Processor rPGA988B 4C GT2 E95127 Mechanical Package Sheet 1 of 2 162 8 11 Processor rPGA988B 4C GT2 E95127 Mechanical Package Sheet 2 of 2 163 8 12 Processor BGA1023 2C GT1 G24405 Mechanical 164 8 13 Processor BGA1023 2C GT2 G23866 Mechanical 165 8 14 Processor BGA1224 4C GT2 G26204 Mechanical 166 Tables 1 1 Mobile 3rd Generation Intel Core Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family SKUS 16 122 Terminol6gy cau e AEN fend A RC MYR A RW YRR 19 1 3 Related Documents cerei EDD atri ANEREN SEN EN 22 2 1 Processor Mo
58. refresh rate will be used when on plugged in power or when the end user has not selected enabled this feature The graphics software will automatically switch to a lower refresh rate for maximum battery life when the notebook is on battery power and when the user has selected enabled this feature There are two distinct Intel implementations static and seamless The static Intel Display Refresh Rate Switching Technology Intel DRRS Technology method uses a mode change to assign the new refresh rate The seamless Intel Seamless Display Refresh Rate Switching Technology Intel SDRRS Technology method is able to accomplish the refresh rate assignment without a mode change and therefore does not experience some of the visual artifacts associated with the mode change SetMode method Datasheet Volume 1 67 Power Management 4 7 Graphics Thermal Power Management See Section 4 6 for all graphics thermal power management related features 88 68 Datasheet Volume 1 Thermal Management intel 5 Caution 5 1 Thermal Management The thermal solution provides both the component level and the system level thermal management To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed so that the processor Remains below the maximum junction temperature T wax specification at the maximum thermal design power TDP Conforms to syste
59. savings to be realized in the processor For package C states the processor is not required to enter CO before entering any other C state 58 Datasheet Volume 1 Power Management intel The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following e If a core break event is received the target core is activated and the break event message is forwarded to the target core If the break event is not masked the target core enters the core CO state and the processor enters package CO e If the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package remains in the higher power C state Table 4 11 shows package C state resolution for a dual core processor Figure 4 4 summarizes package C state transitions Table 4 11 Coordination of Core Power States at the Package Level Core 1 Package C State co C1 cs C6 C7 co CO CO CO CO CO C1 ci Core 0 c3 C6 C6 C7 C7 Note If enabled the package C state will be C1E if all cores have resolved a core C1 state or higher Figure 4 4 Package C State Entry and Exit Datasheet Volume 1 59
60. 0 SB_CKE 3 T10 DDR3 SA DQ 25 N10 DDR3 1 0 SB_CLK 2 AA2 DDR3 SA DQ 26 N8 DDR3 I O SB_CLK 3 AB1 DDR3 SA DQI 27 N7 DDR3 I O SB 2 AB2 DDR3 SA DQ 28 M10 DDR3 1 0 SB_CK 3 AA1 DDR3 SA 29 M9 DDR3 I O SB_CS 2 AD6 DDR3 SA DQ 30 N9 DDR3 7 SB CS 3 AE6 DDR3 SA DQ 31 M7 DDR3 1 0 SB_ODT 2 AD5 DDR3 SA DQ 32 AG6 DDR3 1 0 SB_ODT 3 AE5 DDR3 SA DQ 33 AG5 DDR3 I O SA BS 0 AE10 DDR3 SA DQ 34 AK6 DDR3 1 0 SA_BS 1 AF10 DDR3 SA DQ 35 AK5 DDR3 I O SA BS 2 V6 DDR3 SA DQ 36 AH5 DDR3 1 0 SA_CAS AER DDR3 SA DQ 37 AH6 DDR3 I O SA_CLK 0 AA6 DDR3 SA DQ 38 AJ5 DDR3 1 0 SA_CLK 1 AB5 DDR3 SA DQ 39 AJ6 DDR3 1 0 SA_CK 0 AB6 DDR3 SA DQ 40 AJ8 DDR3 7 SA CK 1 AA5 DDR3 SA DQ 41 AK8 DDR3 7 SA CKE 0 v9 DDR3 SA DQ 42 AJ9 DDR3 I O 116 Datasheet Volume 1 Processor Pin Signal and Package I nformation intel Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir SA DQI 43 AK9 DDR3 I O S
61. 00 1 41000 1 41500 1 42000 1 42500 1 43000 1 43500 1 44000 1 44500 1 45000 1 45500 1 46000 1 46500 1 47000 1 47500 1 48000 1 48500 1 49000 1 49500 1 50000 1 50500 1 51000 1 51500 1 52000 Max ul r 1 2 3 4 5 6 7 8 9 A B C D E D E E E E E E E E E E E F 0 1 1 2 0 3 4 5 6 7 1 8 9 A 0 B E C 0 0 1 2 3 1 4 0 5 6 7 8 9 1 A F B F D F F 1 E F F VID VID VID VID VID 4 1 1 5 VID VID VID 7 6 HEX VID 0 a gt VID VID 3 2 VID 4 5 3 0 66000 5 6 0 67500 5 9 0 69000 5 C 0 70500 5 F 0 72000 6 2 0 73500 6 3 0 74000 6 4 0 74500 6 5 0 75000 6 6 0 75500 6 7 0 76000 6 8 0 76500 6 9 0 77000 6 0 77500 6 B 0 78000 6 C 0 78500 6 D 0 79000 6 E 0 79500 6 F 0 80000 7 O 0 80500 711 0 81000 71410 82500 7 7 0 84000 7 0 85500 7 D 0 87000 7 E 0 87500 7 F 0 88000 VID VID VID 6 Datasheet Volume 1 98 Electrical Specifications t 7 4 System Agent SA VID The Vccsa is configured by the processor output pins VCCSA V
62. 000000 ooo 200 0000 Tw do995985 000000060000000 0000099 956500000 w ooo 99909890999 O9oopooo 900 209 0000 o9 9998 93990909999 Ze 99 5 Y cos oo 99909 oooBoo 9000 00 ooooo F ooo E 00050 o O o Gos 009 599 8 8 80 800 209 00909 9099 000000 5 52 08 990909 9990 95 50609 5 99 9899 50o v 55669 9890 ooo oo o 98 999 999 Es 998 d 9 9 0 00909909990809090009009 29008000005 08 kbh 1 050 900 200 005 000 609 999 0909009 5 i 5 90 900 595 699 ooo ooo 590 905 900 900 905 ooo 9990809 ls T 5 i f SIMI NI QIMOTIY JAY N_dodad vog L 04 318 40 5133 3 us e S w 4 t 9 L 9 Datasheet Volume 1 Processor Pin Signal and Package Information intel Figure 8 14 Processor BGA1224 4C GT2 G26204 Mechanical Package lt i gf ES 5 323 ek E 5 EJ n lt b E 8 ole a a lt 5 T In lt E SIS s o 2 c 2 m 5 Blam SEIL k SSu FF a oe E CIS lt 3 n WORKED N
63. 1 resistors COMP resistors are to Vss 3 eDP ICOMPI eDP_COMPIO are the same resistor Datasheet Volume 1 109 7 10 1 Figure 7 1 110 Electrical Specifications Platform Environmental Control Interface DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external Adaptive Thermal Monitor devices The processor contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control PECI Bus Architecture The PECI architecture based on wired OR bus which the clients as the processor PECI can pull up high with strong drive The idle state on the bus is near zero Figure 7 1 demonstrates PECI design and connectivity while the host originator can be 3rd party PECI host and one of the PECI client is the processor PECI device Example for PECI Host Clients Connection Vtt Q1 LE S lt 10pF Node Host Originator PECI Client A dditional PECI Clients Datasheet Volume 1 Electrical Specifications 7 10 2 Table 7 15 7 10 3 Figure 7 2 intel
64. 3 Asynch 1 0 DMI_RX 3 B23 DMI I PEG_ICOMPI J22 Analog I DMI_TX 0 G21 DMI _1 J21 Analog I DMI_TX 1 E22 DMI o PEG RCOMPO H22 Analog I DMI_TX 2 F21 DMI PEG RX4 0 K33 PCIe I DMI_TX 3 D21 DMI _ 1 M35 PCIe I TX 0 G22 DMI PEG RX4 2 L34 PCIe I DMI_TX 1 D22 DMI PEG RX4 3 J35 PCIe I DMI_TX 2 F20 DMI _ 4 132 PCIe I 114 Datasheet Volume 1 8 Processor Pin Signal and Package I nformation n tel Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type bir Pin Name Pin Buffer Type bir PEG RX4 5 H34 PCIe I PEG TX 4 L28 PCIe _ 6 H31 PCIe I PEG TX 5 K30 PCIe _ 7 G33 PCIe I PEG TX 6 K27 PCIe _ 8 630 PCIe I PEG TX 7 J29 PCIe _ 9 5 PCIe I PEG TX 8 J27 PCIe PEG_RX 10 E34 PCIe I PEG TX 9 H28 PCIe PEG_RX 11 E32 PCIe I PEG TX 10 G28 PCIe PEG_RX 12 D33 PCIe I PEG TX 11 E28 PCIe PEG_RX 13 D31 PCIe I PEG TX 12 F28 PCIe PEG_RX 14 B33 PCle I PEG_TX 13 D27 PCIe
65. 4 2 5 5 Package C7 State iita Ie deg NEEN Ne i Pasa Sg 59 4 2 5 6 Dynamic L3 Cache Sizing sies rrr rnnt ne nnn nu nne RH REP n DWN 59 4 3 Integrated Memory Controller IMC Power 59 4 3 1 Disabling Unused System Memory lt r 59 4 3 2 DRAM Power Management and Initialization 60 4 3 2 1 Initialization Role of nemen 61 4 3 2 2 Conditional Self Refresh eese ese ua EY ENNER EEN ENN EEN 61 4 3 2 3 Dynamic Power Down Operation 62 4 3 2 4 DRAM LO Power Management 62 4 3 3 DDR Electrical Power Gating EPG a aaa 62 4 4 PCI Express Power 63 4 5 DMI Power Management 63 4 6 Graphics Power Management 63 4 6 1 Intel Rapid Memory Power Management Intel RMPM also knowrn ds CXSR 32i EES AUR 63 4 6 2 Intel Graphics Performance Modulation Technology Intel 63 4 6 3 Graphics Render C State eene te psa daa aha saa ak ERR UR Ae 64 4 6 4 Intel Smart 2D Display Technology Intel 525 64 4 6 5 Intel Graphics Dynamic Frequency iiec iara ia nre dada 64 4 6 6 Display Power Savings Technology 6 0 DPST
66. 48 PWR VAXG VAXG V47 PWR VAXG VAXG U46 PWR VAXG VAXG T61 PWR VAXG VAXG T59 PWR VAXG VAXG T58 PWR VAXG VAXG T48 PWR VAXG VAXG P61 PWR VAXG VAXG P56 PWR VAXG VAXG P55 PWR VAXG VAXG P53 PWR VAXG VAXG P52 PWR VAXG VAXG P51 PWR VAXG VAXG P50 PWR VAXG VAXG P48 PWR VAXG VAXG P47 PWR VAXG VAXG VAXG VAXG_SENSE VAXG VAXG VAL SENSE VAXG VAXG Y61 PWR 34 PWR 152 Datasheet Volume 1 m Processor Pin Signal and Package I nformation n tel Table 8 3 1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VCC N30 PWR VCC G42 PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Datasheet Volume 1 153 m 8 n tel Processor Pin Signal and Package Information Table 8 3 BGA1023 Processor Ball List Table 8 3 1023 Processor Ball List by Ball Name Continued by Ball Name Cont
67. 49 SB DQ 50 ep DQ 51 SB DQ 52 SB DQ 53 SB DQ 54 SB DQ 55 ep DQ 56 SB DQ 57 SB DQ 58 SB DQ 59 SB DQ 60 SB DQ 61 ep DQ 62 SB DQ 63 5 AH60 AM63 DQ59 ss SB DQ 36 AN3 BD49 BF49 DQ33 SB DQ 37 AN2 BE49 BH47 DQ34 Datasheet Volume 1 171 DDR Data Swizzling 172 Datasheet Volume 1
68. 8 8 16 16 32 SODIMM RC A 4 4 N A 8 N A SODIMM RC B 4 4 N A 8 N A Mobile SFF BGA SODIMM RC C 2 2 N A 4 N A SODIMM RC F 8 8 N A 16 N A MD like RC A 4 4 N A 8 N A Mobile SFF Y MD like RC B 4 4 N A 8 N A Memory Down MD like RC C 2 2 N A 4 N A MD like RC F 8 8 16 N A 2 1 2 System Memory Timing Support 26 The IMC supports the following Speed Bins CAS Write Latency CWL and command signal mode timings on the main memory interface e tCL CAS Latency tRCD Activate Command to READ or WRITE Command delay tRP PRECHARGE Command Period CWL CAS Write Latency Command Signal modes 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks Command launch mode programming depends on the transfer rate and memory configuration Datasheet Volume 1 I nterfaces Table 2 4 Table 2 5 2 1 3 2 1 3 1 2 1 3 2 intel DDR3 DDR3L DDR3L RS at 1 5 V System Memory Timing Support Transfer tCL tRCD tRP CWL CMD i Segment Rate tCK tCK tCK tCK DPC Mode Notes MT s 1N 2N 1333 9 9 Extreme Edition 2N XE and Quad Core SV 1N 2N 1600 11 11 2N Dual Core 1333 9 9 1N 2N rage ay amp Voltage SV Ultra 1600 11 11 1N 2N Note 1 System memory timing support is based on availability and is subject to change DDR3L DDR3L RS System Memory Timing Support Transfer Se
69. 8187 430 18 su313A1 TW 1NA 1108 1 8158 5 ben 310 I BLAN AARALLLLLAAAE LLLA LLLA d l ele dg P F 11 7 o 399129 1 2 tg MA FD det E i 110 Y Y a Datasheet Volume 1 162 Processor Pin Signal and Package I nformation intel Figure 8 9 Processor rPGA988B 2C GT2 G23867 Mechanical Package Sheet 2 of 2 Za 2 St AUER i am gt i m 2 z Datasheet Volume 1 163 Processor Pin Signal and Package Information intel Figure 8 10 Processor rPGA988B 4C GT2 E95127 Mechanical Package Sheet 1 of 2
70. A MA 10 AD8 DDR3 SA DQ 44 AH8 DDR3 I O SA MA 11 va DDR3 SA DQ 45 AH9 DDR3 I O SA MA 12 wa DDR3 SA DQ 46 AL9 DDR3 I O SA MA 13 AF8 DDR3 SA DQ 47 AL8 DDR3 I O SA MA 14 V5 DDR3 SA DQ 48 AP11 DDR3 I O SA MA 15 V7 DDR3 SA DQ 49 AN11 DDR3 1 0 SA_ODT 0 AH3 DDR3 SA DQ 50 AL12 DDR3 I O SA ODT 1 AG3 DDR3 SA DQ 51 AM12 DDR3 I O SA RAS AD9 DDR3 SA DQ 52 AM11 DDR3 I O SA AF9 DDR3 SA 53 AL11 DDR3 I O SB BS 0 AA9 DDR3 SA DQ 54 AP12 DDR3 I O SB BS 1 AA7 DDR3 SA DQ 55 AN12 DDR3 I O SB BS 2 R6 DDR3 SA DQ 56 114 DDR3 I O SB CAS AA10 DDR3 SA DQ 57 AH14 DDR3 I O SB CLKZ 0 AD2 DDR3 SA DQ 58 AL15 DDR3 1 0 SB_CLK 1 AD1 DDR3 SA DQ 59 AK15 DDR3 I O SB CK 0 AE2 DDR3 SA DQ 60 AL14 DDR3 70 SB CK 1 AE1 DDR3 SA DQ 61 AK14 DDR3 I O SB CKE 0 R9 DDR3 SA 62 AJ15 DDR3 1 0 SB_CKE 1 R10 DDR3 SA_DQ 63 AH15 DDR3 1 0 SB_CS 0 AD3 DDR3 SA DQSZ 0 C4 DDR3 I O SB_CS 1 AE3 DDR3 SA_DQS 1 G6 DDR3 1 0 SB_DIMM_VREFDQ D1 Analog SA_DQS 2 33 DDR3 I O SB DQ 0 C9 DDR3 I O SA_DQS 3 M6 DDR3 1 0 SB DQ 1 A7 DDR3 I O SA_DQS 4 AL6 DDR3 1 0 SB_DQ 2 D10 DDR3 1 0 SA_DQS 5 AM8 DDR3 1 0 SB DQ 3 C8 DDR3 1 0 SA_DQS 6 AR12 DDR3 I O SB DQ 4 A9 DDR3 I O SA_DQS 7 AM15 DDR3 1 0 SB_DQ 5 A8 DDR3 I O SA DQS O D4 DDR3 I O SB DQ 6 D9 DDR3 I O SA_DOS 1 F6 DDR3 1 0 SB_DQ 7 D8 DDR3 1 0 SA_DQS 2 K3 DDR3 I O SB DQ 8 G4 DDR3 I O SA DQS 3 N6 DDR3 I O SB DQ 9 F4 DDR3 I O
71. A50 CMOS 1 0 VDDQ AT34 PWR VSS BJ56 GND VDDQ AT29 PWR VSS BJ52 GND VDDQ AT27 PWR VSS BJ48 GND VDDQ AR45 PWR VSS BJ40 GND VDDQ AR43 PWR VSS BJ32 GND VDDQ AR39 PWR VSS BJ24 GND VDDQ AR37 PWR VSS BJ20 GND VDDQ AR33 PWR VSS BJ16 GND VDDQ AR30 PWR VSS BJ12 GND VDDQ AR26 PWR VSS BJ8 GND VDDQ AR24 PWR VSS BG60 GND VDDQ AP46 PWR VSS BG56 GND VDDQ AP42 PWR VSS BG52 GND VDDQ AP40 PWR VSS BG48 GND VDDQ AP36 PWR VSS BG44 GND VDDQ AP34 PWR VSS BG36 GND VDDQ AP29 PWR VSS BG28 GND VDDQ AP27 PWR VSS BG24 GND VDDQ AN45 PWR VSS BG20 GND VDDQ AN43 PWR VSS BG16 GND VDDQ AN39 PWR VSS BG12 GND VDDQ AN37 PWR VSS BG8 GND VDDQ AN33 PWR VSS BF5 GND VDDQ AN30 PWR VSS BE62 GND VDDQ AN26 PWR VSS BE58 GND VDDQ AN24 PWR VSS BE54 GND VDDQ AL46 PWR VSS BE50 GND VDDQ AL42 PWR VSS BE46 GND VDDQ AL40 PWR VSS BE42 GND VDDQ AL36 PWR VSS BE38 GND 138 Datasheet Volume 1 8 Processor Pin Signal and Package I nformation n tel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir vss BE34 GND vss BA30 GND GND GND GND GND GND GND GND GND GND GND GND GND GND vss AY7 GND GND vss AY3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
72. C Specifications The processor DC specifications in this section are defined at the processor pins unless noted otherwise See Chapter 8 for the processor pin listings and Chapter 6 for signal definitions The DC specifications for the DDR3 signals are listed in Table 7 7 Control Sideband and Test Access Port TAP are listed in Table 7 8 e Table 7 14 lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages Care should be taken to read all notes associated with each parameter e AC tolerances for all DC rails include dynamic load currents at switching frequencies up to 1 MHz 7 9 1 Voltage and Current Specifications Note Noise measurements on SENSE pins for all voltage supplies should be made with a 20 MHz bandwidth oscilloscope Table 7 5 Processor Core Vcc Active and I dle Mode DC Voltage and Current Specifications Sheet 1 of 2 Symbol Parameter Segment Min Typ Max Unit Note XE 0 8 1 35 VID Range for Highest SV QC 35W 0 8 1 35 Frequency Mode _ 1 2 HFM_VID includes Turbo Mode SV QC 45W 0 8 1 35 V 6 8 Operation SV DC 0 8 1 35 Ultra DC 0 65 1 2 XE 0 65 0 95 SV QC 35W 0 65 0 95 LFM_VID MID Range TWE SV QC 45W 0 65 0 95 v 1 2 8 requency Mode SV DC 0 65 0 95 Ultra DC 0 65 0 9 Vcc Vcc for processor core 0 3 1 52 V a XE SV QC 45W lcu oe Processor Core SV QC 35W SV DC Ultra DC XE TDP nominal 69 5 XE TDP Up 75 0 X
73. Channel B Signals intel Signal Name Description SB BS 2 0 Bank Select These signals define which banks are selected within B5 2 0 each SDRAM rank DDR3 SB WEZ Write Enable Control Signal This signal is used with SB RAS and 9 SB CAS along with SB 954 to define the SDRAM Commands DDR3 SB RAS RAS Control Signal This signal is used with SB_CAS and SB along with SB_CS to define the SRAM Commands DDR3 SB CAS CAS Control Signal This signal is used with SB_RAS and SB_WE along with SB_CS to define the SRAM Commands DDR3 Data Strobes SB_DQS 7 0 and its complement signal group make SB_DQS 7 0 up a differential strobe pair The data is captured at the crossing point I O SB DQS 7 0 of SB DQS 8 0 and its SB DQS 7 0 during read and write DDR3 transactions Data Bus Channel B data signal interface to the SDRAM data bus 1 0 SB DQ 63 0 3 DDR3 SB 15 0 Memory Address These signals are used to provide the multiplexed MA 15 0 row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel B SDRAM Differential clock signal pair The crossing of the positive edge of SB CK and the o SB CK 3 0 negative edge of its complement SB CK are used to sample the command and control signals on the SDRAM DDR3 Signals 3 2 are used only for 2 DPC system SDRAM I nverted Differential Clock Channel B SDRAM Differential o SB CK 3 0 clock s
74. DI Interface Sheet 2 of 2 Direction Signal Name Description Buffer Type FDI1_TX 3 0 Intel Flexible Display I nterface Transmit Differential FDiI 4 3 0 Pair Pipe and C FDI n n FDI1_FSYNC 1 Intel Flexible Display Interface Frame Sync Pipe B and C I CMOS 5 Di FDI1_LSYNC 1 Intel Flexible Display I nterface Line Sync Pipe B and C I CMOS Intel Flexible Display I nterface Hot Plug Interrupt I FDI_INT Asynchronous CMOS 6 7 Direct Media Interface DMI Signals Table 6 9 Direct Media Interface DMI Signals Processor to PCH Serial Interface Signal Name Description ag DMI_RX 3 0 DMI Input from PCH Direct Media Interface receive I DMI_RX 3 0 differential pair DMI DMI_TX 3 0 DMI Output to PCH Direct Media Interface transmit DMI_TX 3 0 differential pair DMI 6 8 Phase Lock Loop PLL Signals Table 6 10 Phase Lock Loop PLL Signals Direction Signal Name Buffer Type Description BCLK Differential bus clock input to the processor I BCLK Diff Clk DPLL_REF_CLK Embedded Display Port PLL Differential Clock In 120 MHz I DPLL_REF_CLK Diff Clk 6 9 Test Access Points TAP Signals Table 6 11 Test Access Points TAP Signals Sheet 1 of 2 Signal Name Description totas Breakpoint and Performance Monitor Signals These signals BPM 7 0 are outputs from the processor that indicate the status of I O breakpoints and programmable counters used f
75. DR3 I O SB_DQ 8 AV3 yo SB DQ 45 BG54 yo SB DQ 9 AU4 DDR3 I O SB_DQ 46 BG58 DDR3 Wis SB DQ 10 BA4 yo SB DQ 47 BF59 I O SB_DQ 11 BB1 DDR3 Wis SB DQ 48 BA64 DDR3 I O 132 Datasheet Volume 1 Processor Pin Signal and Package I nformation intel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball Buffer Type Dir SB DQ 49 BC62 DDR3 yo SB_MA 6 BH27 DDR3 SB DQ 50 DDR3 yo SB_MA 7 DDR3 SB DQ 51 DDR3 yo SB_MA 8 DDR3 SB DQ 52 DDR3 yo SB_MA 9 DDR3 SB DQ 53 DDR3 yo SB_MA 10 DDR3 SB DQ 54 DDR3 yo DDR3 SB DQ 55 DDR3 yo DDR3 SB DQ 56 DDR3 yo DDR3 SB DQ 57 DDR3 yo DDR3 SB DQ 58 DDR3 yo SB_MA 15 DDR3 SB DQ 59 DDR3 yo SB ODT 0 DDR3 SB DQ 60 DDR3 yo SB_ODT 1 DDR3 SB DQ 61 DDR3 yo SB_RAS DDR3 SB DQ 62 DDR3 yo SB WE DDR3 SB DQ 63 DDR3 yo SM_DRAMPWROK Asynch CMOS I SB_DQS 0 DDR3 yo SM DRAMRST DDR3 SB_DQS 1 DDR3 yo SM_RCOMP 0 Analog yo SB_DQS 2 DDR3 yo SM RCOMP 1 Analog yo SB DQS 3 DDR3 yo SM_RCOMP 2 Analog yo SB_DQS 4 DDR3 yo SM_VREF Analog I SB_DQS 5 DDR3 yo TCK CMOS I SB_DQS 6 DDR3 I O CMOS I SB_DQS 7 DDR3 yo CMOS SB DQS 0 DDR3 yo THERMTRIP Asynch CMOS SB_DOS 1 DDR3 yo TMS CMOS I SB_DOS 2 DDR3 I O TRST CMOS I SB_DQS 3 DD
76. E TDP Down 54 6 SV QC 45W 54 6 Thermal Design SV QC 35W 32 0 Pay SV DC 32 0 Ultra nominal 15 8 Ultra TDP Up 20 0 Ultra TDP Down 10 5 XE 32 0 SV QC 45W 32 0 Icc_LFM Icc at LFM SV QC 35W 28 0 A 5 SV DC 25 0 Ultra DC 12 5 Datasheet Volume 1 103 intel Electrical Specifications Table 7 5 Processor Core Vcc Active and Idle Mode DC Voltage and Current Specifications Sheet 2 of 2 Symbol Parameter Segment Min Typ Max Unit Note XE 5 5 SV QC 45W 5 0 Icc 6 67 Icc at C6 C7 Idle state SV QC 35W 5 0 A 10 SV DC 3 0 Ultra DC 2 5 PSO 15 TOLycc Voltage Tolerance PS1 mv 7 9 PS2 PS3 PSO amp Icc gt TDC4 3096 PSO amp Icc lt TDC 30 Ripple Ripple Tolerance mV 7 9 PS1 13 PS2 7 5 18 5 PS3 27 57 27 5 VR Step VID resolution 5 mV XE TDP nom Up Down 1 9 SV QC 1 9 SLOPE Processor Loadline SV DC 1 9 mQ Ultra TDP nom Up Down 2 9 Notes 1 Unless otherwise noted all specifications in this table are based on post silicon estimates and simulations or empirical data 2 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range This differ
77. G TX 15 PCIe RSVD PEG TX 0 PCIe e SB DIMM VREFDQ Analog PEG TX 1 PCIe PEG TX 2 PCIe PEG TX 3 PCIe PEG TX 4 PCIe PEG TX 5 PCIe PEG TX 6 PCIe PEG TX 7 PCIe _ 8 PEG TX 9 PCIe SA DIMM VREFDQ Analog PEG TX 10 PCIe RSVD PCIe Asynch CMOS I Asynch CMOS Asynch CMOS I PROC DETECT Analog PROC SELECT N A PROCHOT Asynch CMOS 1 0 RESET A Asynch CMOS I Datasheet Volume 1 129 m 8 n tel Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir RSVD BA48 RSVD G52 RSVD AY45 RSVD G4 RSVD AY17 RSVD D49 RSVD AY13 RSVD D3 RSVD AW46 RSVD C24 RSVD AW14 RSVD B53 RSVD AJ6 SA BS 0 BA36 DDR3 RSVD AD5 SA BS 2 BB19 DDR3 RSVD ACA SA CKE 0 BC18 DDR3 RSVD AA4 SA CKE 1 BD17 RSVD P7 SA_CLK 0 BA32 DDR3 RSVD M9 SA CK 0 BB31 DDR3 RSVD L10 SA_CS 0 BD41 DDR3 RSVD 14 SA DQ 0 AL6 DDR3 Wis RSVD K49 SA 2 AP7 DDR3 I O RSVD K9 SA_DQ 4 AK7 DDR3 1 0 RSVD K5 SA DQ 6 AN10 DDR3 Wis RSVD 14 SA_DQ 8 AR10 DDR3 Wis RSVD J2 SA 9 AR8 I O RSVD H49 SA_DQ 10 AV7 DDR3 Wis RSVD H47 SA DQ 11 AY5 I O RSVD H5 SA_DQ 12 AT5 DDR3 1 0
78. GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Datasheet Volume 1 139 intel Processor Pin Signal and Package I nformation Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type bir Ball Name Ball Buffer Type bir VSS AU22 GND VSS AN47 GND VSS AU16 GND VSS AN41 GND VSS AU14 GND VSS AN35 GND VSS AT61 GND VSS AN28 GND VSS AT57 GND VSS AN22 GND VSS AT50 GND VSS AM61 GND VSS AT44 GND VSS AM7 GND VSS AT38 GND VSS AM3 GND VSS AT31 GND VSS AM1 GND VSS AT25 GND VSS AL57 GND VSS AT19 GND VSS AL50 GND VSS AT11 GND VSS AL44 GND VSS AT7 GND VSS AL38 GND VSS AT3 GND VSS AL31 GND VSS AT1 GND VSS AL25 GND VSS AR54 GND VSS AL19 GND VSS AR47 GND VSS AK16 GND VSS AR41 GND VSS AK14 GND VSS AR35 GND VSS AK11 GND VSS AR28 GND VSS AK9 GND VSS AR22 GND VSS AK5 GND VSS AP65 GND VSS AJ64 GND VSS AP63 GND VSS AJ62 GND VSS AP57 GND VSS AJ60 GND VSS AP50 GND VSS AJ57 GND VSS AP44 GND VSS AH7 GND VSS AP38 GND VSS AH3 GND VSS AP31 GND VSS AH1 GND VSS AP25 GND VSS AG57 GND VSS AP19 GND VSS AG17 GND VSS AP17 GND VSS AG15 GND VSS AP15 GND VSS AG12 GND VSS AP12 GND VSS AF65 GND VSS AP11 GND VSS AF63 GND VSS AP9 GND VSS AF61 GND VSS AP5 GND VSS AF11 GND VSS AN54 GND VSS AF9 GND 140 Datasheet Volume 1
79. GND vss G6 GND vss N25 GND vss F55 GND 158 Datasheet Volume 1 Processor Pin Signal and Package I nformation Table 8 3 1023 Processor Ball List by Ball Name Continued Table 8 3 BGA1023 Processor Ball List by Ball Name Continued Ball Name Ball Buffer Type bir Ball Name Ball Buffer Type Dir VSS F40 GND GND VSS A21 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSS NCTF GND GND VSS SENSE VSS SENSE VDDQ GND GND VSS VAL SENSE VSSAXG SENSE GND GND VSSAXG VAL SENSE VSS SENSE VCCIO AN17 Analog GND GND GND GND GND GND GND GND GND GND GND GND Datasheet Volume 1 GND 159 Processor Pin Signal and Package I nformation intel 8 2 Package Mechanical I nformation Figure 8 6 Processor rPGA988B 2C GT1 G24406 Mechanical Package Sheet 1 of 2
80. I Express configuration cycles To maintain compatibility with PCI configuration addressing mechanisms it is recommended that system software access the enhanced configuration space using 32 bit operations 32 bit aligned only See the PCI Express Base Specification for details of both the PCI compatible and PCI Express Enhanced configuration mechanisms and transaction rules Datasheet Volume 1 Interfaces 2 2 3 PCI Express Graphics intel The external graphics attach PEG on the processor is a single 16 lane x16 port The PEG port is being designed to be compliant with the PCI Express Base Specification Revision 3 0 2 2 3 1 PCI Express Lanes Connection Figure 2 5 demonstrates the PCIe lanes mapping Figure 2 5 PCI Express Typical Operation 16 Lanes Mapping 0 1 2 3 4 5 6 5 7 o o 0 8 KE 2 10 5 9 11 8 0 _ E 12 5 x 1 EE s 13 be o o Ke 2 6 14 x 3 7 15 Datasheet Volume 1 Lane 10 Lane 11 Lane 12 Lane 13 10 11 12 13 14 15 33 intel interfaces 2 3 Note 2 3 1 2 3 2 2 3 3 34 Direct Media I nterface DMI Direct Media Interface DMI co
81. ID 1 0 VCCSA VID 0 output default logic state is low for 2nd Generation Intel Core family mobile processors Note During boot the processor Vccsa voltage is 0 9 V The Vccsa may change only once during the reset sequence Note For Ultra products for power optimization purposes the VCCSA VID may change dynamically during the processor s operation Table 7 2 specifies the different VCCSA VID configurations Table 7 2 VID Configuration Selected Vccsa VCCSA_VID 0 VCCSA VIDI 1 XE amp SV segments Selected VccsA Ultra segment 0 0 9 V 1 0 8 V 0 0 725 V 1 0 675 V 0 75 V 7 5 Reserved or Unused Signals The following are the general types of reserved RSVD signals and connection guidelines RSVD these signals should not be connected RSVD TP these signals should be routed to a test point RSVD NCTF these signals are non critical to function and may be left un connected Arbitrary connection of these signals to Vcc Vccior VDDQ Vccsa VaxG Mee to any other signal including each other may result in component malfunction or incompatibility with future processors See Chapter 8 for a pin listing of the processor and the location of all reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss
82. L Power Supply i dene eben des nonna YRU RR yir Ra RR ke sa EEN raw sar NEE e 93 7 3 Voltage Identification VID aa qiayqa 94 7 4 System Agent SA VCC VID aliai iaa 97 7 5 Reserved or Unused Signals J a nee nene nns 97 FANE EIECTUS 98 7 7 Test Access Port TAP Connection NEEN ENNER sasa qasqa asas sasa sasa nans 100 7 8 Component Storage Condition Specifications Prior to Board Attach 100 7 9 DC qasaq ikushka a ei aaa 101 7 9 1 Voltage and Current Specifications YY LARA LARA ELE eens 101 7 10 Platform Environmental Control Interface PECI DC Specifications 108 7 10 1 PECI B s Architecture t een EEN a Se a Rx 108 7 10 2 PECL DC Characteristics esee Acces Eten rre Ren haee aa E E ene 109 7 10 3 Input Device HySteresis ep u deese ue ANN de denies hne e ag de Pon Mad exse d Rx Es 109 Processor Pin Signal and Package Information 111 8 1 _ProcessorPin Assignments eiu Su Y kx ER a 111 8 2 Package Mechanical Information 158 DDR Data ESPERA cad 167 Datasheet Volume 1 Figures 1 1 Mobile Processor Platform cists eet idet Se NEE S SEENEN GENEE ENEE nuda eas DE REA NEEN RA A ERR 10 1 2 Mobile Proces
83. Mobile 3rd Generation Intel Core Processor Family Mobile I ntel Pentium Processor Family and Mobile I ntel Celeron Processor Family Datasheet Volume 1 of 2 January 2013 Document Number 326768 005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR
84. O KINO ee de o a FL SZ KEE E o 4900000900000 o o o o oof Ee 1 0000 0 o 0 00 0 0 y E 1007000 0 0 0 0 l 25050505059 000000 in 0050505050 9900000 5 gt _ 25500050050 0002020 ES afo mI 2200008090 0009090 ES 1 40000009090 0202020 SESBEK Slee ele le le H H Ee 0509000 950 0900090 pun zou 49200002590 0000050 0 592020200 95000000000 0009000 1 050005020 o r e e E 3595920000 0020000 992900000000 s Z 3 9000000000 0000000 090909090 aill EC bil Ded a s E 0000202000 0000000 _ 080 B s 590909000 0202090 Eed al s 000000000 0000000 ES S i 0050000000 00000 x EE e 9020090000 0000000 5 e Be ie a 0200000000 9000001 o 0090000090 0000000 _ 202020002 0202020 E 00000000000 0 000 oo 000209090 990090 o 20000090 2000000 a 2099909050 9090000000909090009000900 3 100000000 0000090000504920000900000 SE E Ke See 5 E 59005050205000500000002020202020000000000 E EE s E o N E zc T zz 7 N T J m i Wr 1 Sie zd 2 52 n 1
85. O Monitor address needs to be set up before using the P LVLx I O read interface Each P LVLx is mapped to the supported MWAIT Cx instruction as shown in Table 4 10 P LVLx to MWAIT Conversion P LVLx MWAI T Cx Notes P_LVL2 MWAIT C3 P_LVL3 MWAIT C6 C6 No sub states allowed P_LVL4 MWAIT C7 C7 No sub states allowed P_LVL5 MWAIT C7 C7 No sub states allowed The BIOS can write to the C state range field of the PMG_IO_CAPTURE MSR to restrict the range of I O addresses that are trapped and emulate MWAIT like functionality Any P LVLx reads outside of this range does not cause an I O redirection to an MWAIT Cx like request They fall through like a normal I O instruction When P LVLx I O instructions are used MWAIT substates cannot be defined The MWAIT substate is always zero if I O MWAIT redirection is used By default P_LVLx I O redirections enable the MWAIT break on EFLAGS IF feature that triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF Datasheet Volume 1 Power Management intel 4 2 4 4 2 4 1 4 2 4 2 4 2 4 3 4 2 4 4 Core C states The following are general rules for all core C states unless specified otherwise A core C State is determined by the lowest numerical thread state such as Thread 0 requests C1E while Thread 1 requests C3 resulting in a core C1E state See Table 4 7 e A core transitions to CO state when An interrupt occurs
86. OCHOT Asynch CMOS RSVD L45 RESET Asynch CMOS RSVD L42 RSVD RSVD K48 RSVD RSVD K24 SB_DIMM_VREFDQ RSVD H48 RSVD BF23 SA_BS 0 BD37 DDR3 148 Datasheet Volume 1 m Processor Pin Signal and Package I nformation n tel Table 8 3 1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type bir Ball Name Ball Buffer Type bir SA BS 1 BF36 DDR3 SA DQ 26 AY17 DDR3 SA BS 2 DDR3 SA CAS DDR3 SA CKE 0 DDR3 SA CKE 1 DDR3 SA CLK 0 DDR3 SA CLK 1 DDR3 I DDR3 I DDR3 I O I I I I DDR3 EE DDR3 epe DDR3 I SA CK 0 DDR3 Es SA CS 0 DDR3 DDR3 1 DDR3 1 DDR3 1 DDR3 1 DDR3 7 1 o 1 7 1 7 1 7 DDR3 I DDR3 I DDR3 I DDR3 I DDR3 I DDR3 I DDR3 I DDR3 I DDR3 I DDR3 I DDR3 I DDR3 DDR3 I DDR3 DDR3 I Datasheet Volume 1 149 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 m 8 n tel Processor Pin Signal and Package Information
87. OMPO PCI Express Current Compensation z PEG RCOMPO PCI Express Resistance Compensation PEG RX 15 0 PCI Express Receive Differential Pair I PEG RX 15 0 PCI Express PEG TX 15 0 PCI Express Transmit Differential Pair PEG 15 0 PCI Express 6 5 Embedded DisplayPort eDP Signals Table 6 7 Embedded DisplayPort Signals P c Direction Signal Name Description Buffer Type eDP TX 3 0 Embedded DisplayPort Transmit Differential Pair eDP_TX 3 0 Diff eDP_AUX Embedded DisplayPort Auxiliary Differential Pair I O eDP_AUX Embedded DisplayPort Hot Plug Detect eDP_HPD Asynchronous CMOS eDP_COMPIO Embedded DisplayPort Current Compensation H eDP ICOMPO Embedded DisplayPort Current Compensation DPLL REF CLK Embedded DisplayPort Reference Clock Differential Pair I DPLL REF CLK Diff I I 6 6 Intel Flexible Display Intel FDI Interface Signals Table 6 8 Intel Flexible Display Intel FDI Interface Sheet 1 of 2 Direction Signal Name Description Buffer Type FDIO TX 3 0 Intel Flexible Display Interface Transmit Differential FDIO_TX 3 0 Pair Pipe A FDI amp S FDIO FSYNC 0 Intel Flexible Display Interface Frame Sync Pipe A I CMOS amp i n xvm FDIO_LSYNC O Intel Flexible Display Interface Line Sync Pipe A a Datasheet Volume 1 89 Signal Description intel Table 6 8 Intel Flexible Display Intel F
88. PWR N43 PWR VAXG T56 PWR 39 PWR VAXG R64 PWR 37 PWR VAXG R62 PWR N33 PWR VAXG R60 PWR 30 PWR VAXG R55 PWR 26 PWR VAXG R53 PWR VCC N24 PWR VAXG R48 PWR VCC N20 PWR 134 Datasheet Volume 1 Processor Pin Signal and Package I nformation intel Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball 4 Buffer Type Dir Ball Name Ball 4 Buffer Type Dir VCC M46 PWR VCC H31 PWR VCC M42 PWR VCC H29 PWR VCC M40 PWR VCC H25 PWR VCC M36 PWR VCC G44 PWR VCC M34 PWR VCC G40 PWR VCC M29 PWR VCC G38 PWR VCC M27 PWR VCC G34 PWR VCC M23 PWR VCC G32 PWR VCC M21 PWR VCC G28 PWR VCC L44 PWR VCC G26 PWR VCC L40 PWR VCC F45 PWR VCC L38 PWR VCC F43 PWR VCC L34 PWR VCC F41 PWR VCC L32 PWR VCC F37 PWR VCC L28 PWR VCC F35 PWR VCC L26 PWR VCC F31 PWR VCC L22 PWR VCC F29 PWR VCC K45 PWR VCC F25 PWR VCC K43 PWR VCC E44 PWR VCC K41 PWR VCC E40 PWR VCC K37 PWR VCC E38 PWR VCC K35 PWR VCC E34 PWR VCC K31 PWR VCC E32 PWR VCC K29 PWR VCC E28 PWR VCC K25 PWR VCC E26 PWR VCC 144 PWR VCC D45 PWR VCC 140 PWR VCC D43 PWR VCC J38 PWR VCC D41 PWR VCC 134 PWR VCC D37 PWR VCC J32 PWR VCC D35 PWR VCC J28 PWR VCC D31 PWR VCC 126 PWR VCC D29 PWR VCC H45 PWR VCC C44 PWR VCC H43 PWR VCC C40 PWR VCC H41 PWR VCC C38 PWR VCC H37 PWR VCC C34 PWR VCC H35
89. PWR VCC C32 PWR Datasheet Volume 1 135 m 8 n tel Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir C28 PWR VCCIO AT48 PWR C26 PWR VCCIO AT17 PWR 45 PWR VCCIO AT15 PWR B43 PWR VCCIO AT12 PWR B41 PWR VCCIO AR58 PWR 37 PWR VCCIO AR56 PWR 35 PWR VCCIO AR52 PWR B31 PWR VCCIO AR49 PWR 29 PWR VCCIO AR20 PWR 44 PWR VCCIO AR18 PWR 40 PWR VCCIO AR16 PWR 38 PWR VCCIO AR14 PWR 34 PWR VCCIO AP55 PWR 32 PWR VCCIO AP53 PWR 28 PWR VCCIO AP48 PWR 26 PWR VCCIO AN58 PWR RSVD F47 Analog VCCIO AN56 PWR VCC SENSE B47 VCCIO AN52 PWR VCC VAL SENSE D47 Analog VCCIO AN49 PWR VCCDO AV23 PWR VCCIO AN20 PWR VCCDO AT23 PWR VCCIO AN18 PWR VCCDO AP23 PWR VCCIO AN16 PWR VCCDO AL23 PWR VCCIO AN14 PWR VCCIO AV55 PWR VCCIO AM11 PWR VCCIO AV53 PWR VCCIO AL55 PWR VCCIO AV48 PWR VCCIO AL53 PWR VCCIO AV17 PWR VCCIO AL48 PWR VCCIO AV15 PWR VCCIO AL17 PWR VCCIO AV12 PWR VCCIO AL15 PWR VCCIO AU58 PWR VCCIO AL12 PWR VCCIO AU56 PWR VCCIO AK58 PWR VCCIO AU52 PWR VCCIO AK56 PWR VCCIO AU49 PWR VCCIO AJ17 PWR VCCIO AU20 PWR VCCIO 115 PWR VCCIO AU18 PWR VCCIO 112 PWR
90. PWR vss AB29 GND VCCIO J13 PWR vss AB30 GND VCCIO 114 PWR vss AB31 GND VCCIO_SEL A19 N A vss AB32 GND VCCIO SENSE B10 Analog vss AB33 GND VCCPLL A2 PWR vss AB34 GND VCCPLL A6 PWR vss AB35 GND VCCPLL B6 PWR vss AC2 GND VCCSA H25 PWR vss AC3 GND VCCSA H26 PWR vss AC5 GND VCCSA 124 PWR vss AC6 GND VCCSA J25 PWR vss AC8 GND VCCSA J26 PWR vss AC9 GND VCCSA L26 PWR vss AD7 GND VCCSA M26 PWR vss AE26 GND VCCSA M27 PWR vss AE27 GND VCCSA_SENSE H23 Analog vss AE28 GND VCCSA_VID 0 C22 CMOS vss AE29 GND VCCSA_VID 1 C24 CMOS vss AE30 GND VDDO AC1 PWR vss AE31 GND VDDO AC4 PWR vss AE32 GND VDDO AC7 PWR vss AE33 GND VDDO AF1 PWR vss AE34 GND VDDO AF4 PWR vss AE35 GND VDDO AF7 PWR vss AE9 GND VDDO P1 PWR vss AF2 GND VDDO P4 PWR VSS AF3 GND VDDQ P7 PWR VSS AF5 GND VDDQ U1 PWR vss AF6 GND VDDO U4 PWR vss AG4 GND VDDO U7 PWR vss AG8 GND VDDO Y1 PWR vss AG9 GND VDDO Y4 PWR vss AH16 GND VDDO Y7 PWR vss AH19 GND VIDALERT 4 AJ29 CMOS I vss AH22 GND VIDSCLK AJ30 CMOS vss AH25 GND VIDSOUT AJ28 CMOS I O vss AH26 GND vss A20 GND vss AH28 GND vss A23 GND vss AH29 GND vss A26 GND vss AH30 GND vss A29 GND vss AH32 GND vss A3 GND vss AH34 GND vss A32 GND vss AH35 GND Datasheet Volume 1 121 intel Processor Pin Signal and Package I nformation Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type bir Pin Name Pin Buf
91. Processor BGA1023 2C GT1 G24405 Mechanical Package cu au eu Tenue WOINVHOAW 39VX2Vd a Wav PINS 108 70 d 39311 feu DEER 311 8 4 1 JHL 8 1H913H YSG N 1H513H Y9 H 3 Qvo 02 51708 0 30197102 3903 30 Zo 831N32 i l 1 4343 01193410 135410 103 9900059 000 050 059000000 o 89000 000 000 0000 00 00 2000000000000 900 9 08808 90 990990 99999999 995090 9990990 90099999 9900 j 999 3898 060099999 90000 909000 99 o o o o 092900590 070 Zo 000000009 000000000 000000000 600 ooo 0000000 90000 0000000 900000000000 00000 9009599999900 I 0000999000000 999 00000000 00000000 94 oo 00000 9 990 060006990 sa 9000900000000 99 888888990 804 gao oseooon9g Lin 20000 0990000 99 900000000009 L 00000 00000000 599990000000 200000000 0 0 0 0 olo o o b o o o 000000000 95 0000009000000 5 9 000000000 900 99 0000000000000 099000 8 oo99889859000000000p00 00077 790000 000 ooo 999099 99
92. R sBDQse yo VAXG AH20 PWR SB_DQS 6 AKi2 DDR3 IO VAXG AH21 PWR 118 Datasheet Volume 1 Processor Pin Signal and Package I nformation Table 8 1 rPGA988B Processor Pin List by Pin Name Continued Table 8 1 rPGA988B Processor Pin List by Pin Name Continued intel Pin Name Pin Buffer Type bir Pin Name Pin Buffer Type Dir VAXG AH23 PWR VAXG AT21 PWR VAXG AH24 PWR VAXG AT23 PWR VAXG AJ17 PWR VAXG AT24 PWR VAXG AJ18 PWR VAXG_SENSE AK35 Analog VAXG AJ20 PWR VAXG VAL SENSE AJ31 Analog AJ21 PWR VCC AA26 PWR VAXG AJ23 PWR VCC AA27 PWR VAXG AJ24 PWR VCC AA28 PWR VAXG AK17 PWR VCC AA29 PWR VAXG AK18 PWR VCC AA30 PWR VAXG AK20 PWR VCC AA31 PWR VAXG AK21 PWR VCC AA32 PWR VAXG AK23 PWR VCC AA33 PWR VAXG AK24 PWR VCC AA34 PWR VAXG AL17 PWR VCC AA35 PWR VAXG AL18 PWR VCC AC26 PWR VAXG AL20 PWR VCC AC27 PWR VAXG AL21 PWR VCC AC28 PWR VAXG AL23 PWR VCC AC29 PWR VAXG AL24 PWR VCC AC30 PWR VAXG AM17 PWR VCC AC31 PWR VAXG AM18 PWR VCC AC32 PWR VAXG AM20 PWR VCC AC33 PWR VAXG AM21 PWR VCC AC34 PWR VAXG AM23 PWR VCC AC35 PWR VAXG AM24 PWR VCC AD26 PWR VAXG AN17 PWR VCC
93. R is set to a 1 the processor will immediately reduce its power consumption using modulation of the internal core clock independent of the processor temperature The duty cycle of the clock modulation is programmable using Bits 3 1 of the same IA32 CLOCK MODULATION MSR In this mode the duty cycle can be programmed in either 12 5 or 6 25 increments discoverable using CPUID Thermal throttling using this method will modulate each processor core s clock independently I O Emulation Based On Demand Mode I O emulation based clock modulation provides legacy support for operating system software that initiates clock modulation through I O writes to ACPI defined processor clock control registers on the chipset PROC CNT Thermal throttling using this method will modulate all processor cores simultaneously Datasheet Volume 1 83 intel Thermal Management 5 6 6 84 Memory Thermal Management The integrated memory controller IMC provides thermal protection for system memory DIMMs using memory bandwidth throttling Like processor package throttling memory throttling is initiated based on temperature The IMC offers two levels of throttling warm and hot The temperature and the amount of bandwidth reduced while throttling is programmable for the warm and hot trip points through memory mapped I O registers Memory temperature can be read directly by a physical thermal sensor on the DIMM TS on DIMM or a physical temperature sensor pl
94. R3 I O UNCOREPWRGOOD Asynch CMOS I SB_DQS 4 DDR3 yo PWR SB_DOS 5 DDR3 yo PWR SB_DOS 6 DDR3 yo PWR SB_DOS 7 DDR3 yo PWR SB MA 0 DDR3 PWR SB MA 1 DDR3 PWR SB MA 2 DDR3 PWR SB MA 3 DDR3 PWR SB MA 4 DDR3 PWR SB MA 5 DDR3 PWR Datasheet Volume 1 133 m 8 n tel Processor Pin Signal and Package Information Table 8 2 BGA1224 Processor Ball List Table 8 2 BGA1224 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type bir Ball Name Ball Buffer Type Dir VAXG AE64 PWR VAXG N64 PWR VAXG AE62 PWR VAXG N62 PWR VAXG AE60 PWR VAXG N60 PWR VAXG AD65 PWR VAXG N58 PWR VAXG AD63 PWR VAXG N56 PWR VAXG AD61 PWR VAXG N52 PWR VAXG AD58 PWR VAXG N49 PWR VAXG AD56 PWR VAXG M65 PWR VAXG AB65 PWR VAXG M63 PWR VAXG AB63 PWR VAXG M61 PWR VAXG AB61 PWR VAXG M59 PWR VAXG AB58 PWR VAXG M55 PWR VAXG AB56 PWR VAXG M53 PWR VAXG AA64 PWR VAXG M48 PWR VAXG AA62 PWR VAXG L56 PWR VAXG AA60 PWR VAXG L52 PWR VAXG Y58 PWR VAXG L48 PWR VAXG Y56 PWR VAXG_SENSE F49 Analog W64 PWR VAXG VAL SENSE B49 Analog W62 PWR 46 PWR VAXG W60 PWR R42 PWR VAXG V65 PWR 40 PWR VAXG V63 PWR 36 PWR VAXG V61 PWR 34 PWR VAXG V58 PWR R29 PWR VAXG V56 PWR 27 PWR VAXG T65 PWR 23 PWR VAXG T63 PWR 21 PWR VAXG T61 PWR N45 PWR VAXG T58
95. SENSE VSS VAL SENSE VAXG VAL SENSE VSSAXG VAL SENSE Power VCC VCCIO VCCSA VCCPLL VDDQ VAXG VCCPQE VCCDQ Ground Single Ended VSS 55 NCTF DC TEST xx No Connect Test Point RSVD RSVD_NCTF RSVD TP Other SKTOCC PROC DETECT4 PCI Express Graphics Differential PCI Express Input PEG RX 15 0 PEG_RX 15 0 Differential PCI Express Output PEG TX 15 0 PEG TX2 15 0 Single Ended Analog Input PEG ICOMPO PEG ICOMPI PEG RCOMPO Embedded DisplayPort eDP Differential eDP Output eDP TX 3 0 eDP_TX 3 0 Differential eDP Bi directional eDP AUX eDP AUX Single Ended CMOS eDP_HPD Single Ended Analog Input eDP_ICOMPO eDP_COMPIO DMI Differential DMI Input DMI_RX 3 0 DMI_RX 3 0 Differential DMI Output DMI_TX 3 0 DMI_TX 3 0 Intel FDI FDIO FSYNC FDI1 FSYNC FDIO LSYNC Single Ended CMOS Input FDI1 LSYNC Asynchronous CMOS FDI INT Single Ended Input i FDIO TX 3 0 FDIO TX2 3 0 FDI1_TX 3 0 Differential FDI Output FDI1_TX 3 0 Notes 1 Refer to Chapter 6 for signal description details 2 SAand SB refer to DDR3 Channel A and DDR3 Channel B 3 These signals only apply to BGA packages 4 The maximum Rise Fall time of UNCOREPWRGOOD is 20 ns All Control Sideband Asynchronous signals are required to be asserted deasserted for at least 10 BCLKs with a maximum of 6 ns in order for the processor to r
96. TS temperature may not be a good indicator of package Adaptive Thermal Monitor activation or rapid increases in temperature that triggers the Out of Specification status bit within the PACKAGE_THERM_STATUS MSR 1Bih and IA32 THERM STATUS MSR 19Ch Code execution is halted in C1 C7 Package temperature can still be monitored through PECI in lower C states It is not recommended to read the package temperature using the processor MSR while in any C state Doing this will bring a core back into CO Unlike traditional thermal devices the DTS outputs a temperature relative to the maximum supported operating temperature of the processor T max regardless of TCC activation offset It is the responsibility of software to convert the relative temperature to an absolute temperature The absolute reference temperature is readable in the TEMPERATURE_TARGET MSR 1A2h The temperature returned by the DTS is an implied negative integer indicating the relative offset from T max The DTS does not report temperatures greater than Tj max Datasheet Volume 1 Thermal Management intel 5 6 2 1 5 6 2 2 5 6 3 Note Note 5 6 3 1 The DTS relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point When a package DTS indicates that it has reached the TCC activation a reading of Oh except when the TCC activation offset is changed the TCC will activate and indicate a Adaptive Thermal Monitor event A TCC activation will
97. Unit Block Diagram 2 4 1 2 4 1 1 VS GS Setup Rasterize Hierachical Z Hardware Clipper Unified Execution Unit Array Texture Unit EU eee E Pixel Backend Additional Post Processing Multi Format Decode Encode Full MPEG2 VC1 AVC Decode Fixed Function Post Processing Full AVC Encode Partial MPEG2 VC1 Encode 3D and Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive All the cores are fully programmable increasing the versatility of the 3D Engine The Gen 7 0 3D engine provides the following performance and power management enhancements e Up to 16 Execution units EUs Hierarchal Z Video quality enhancements 3D Engine Execution Units e Supports up to 16 EUs The EUs perform 128 bit wide execution per clock e Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing Datasheet Volume 1 35 intel Interfaces 2 4 1 2 2 4 1 2 1 2 4 1 2 2 2 4 1 2 3 2 4 1 2 4 2 4 1 2 5 2 4 1 2 6 2 4 1 3 36 3D Pipeline Vertex Fetch VF Stage The VF stage executes 3DPRIMITIVE commands Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL Vertex Shader VS Stage The VS stage performs shading of vertices output by the VF function The VS unit pro
98. Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Datasheet Volume 1 99 Table 7 3 100 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7 3 The buffer type indicates which signaling technology and specifications apply to the signals All the differential signals and selected DDR3 and Control Sideband signals have On Die Termination ODT resistors There are some signals that do not have ODT and need to be terminated on the board Signal Groups Sheet 1 of 2 Electrical Specifications Signal Group Type Signals System Reference Clock Differential CMOS Input PEL BELE DPLL REF CLK DPLL REF CLK DDR3 Reference Clocks Differential DDR3 Output SA CK 1 0 SA CK 1 0 SB CK 1 0 SB CK 1 0 DDR3 Command Signals Single Ended DDR3 Output SA BS 2 0 SB BS 2 0 SA WE SB SA RAS SB RAS SA CAS SB CAS SA MA 15 0 SB MA 15 0 DDR3 Control Signals Single Ended DDR3 Output SA CKE 1 0 SB CKE 1 0 SA CS 1 0 SB_CS 1 0 SA ODT 1 0 SB ODT 1 0 SM_DRAMRST DDR3 Data Signals2 Single ended Differential DDR3 Bi d
99. VCCIO B12 PWR 30 PWR VCCIO 11 PWR 31 PWR VCCIO C12 PWR R32 PWR VCCIO D11 PWR VCC R33 PWR VCCIO D12 PWR 34 PWR VCCIO E11 PWR R35 PWR VCCIO E12 PWR U26 PWR VCCIO Fil PWR 027 PWR VCCIO F12 PWR U28 PWR VCCIO G12 PWR U29 PWR VCCIO H11 PWR VCC U30 PWR VCCIO H12 PWR 031 PWR VCCIO 111 PWR U32 PWR VCCIO J12 PWR 033 PWR VCCIO L10 PWR 034 PWR VCCIO P10 PWR 035 PWR VCCIO U10 PWR V26 PWR VCCIO Y10 PWR V27 PWR VCCIO A13 PWR V28 PWR VCCIO A14 PWR V29 PWR VCCIO B14 PWR V30 PWR VCCIO C13 PWR V31 PWR VCCIO C14 PWR V32 PWR VCCIO D13 PWR v33 PWR VCCIO D14 PWR V34 PWR VCCIO E14 PWR 120 Datasheet Volume 1 Processor Pin Signal and Package I nformation intel Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type bir Pin Name Pin Buffer Type Dir VCCIO F13 PWR vss A35 GND VCCIO F14 PWR vss AB26 GND VCCIO G13 PWR vss AB27 GND VCCIO G14 PWR vss AB28 GND VCCIO H14
100. VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_SENSE Analog VSS_SENSE_VDDQ Analog VSS VAL SENSE Analog Datasheet Volume 1 143 intel Figure 8 4 BGA1023 Ballmap left side Processor Pin Signal and Package Information 58 57 56 55 54 53 52 51 50 gt gt lt lt 51 50 49 49 48 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 47 46 45 44 43 42 41 40 39 38 37 36 35 34 144 Datasheet Volume 1 Processor Pin Signal and Package I nformation Figure 8 5 BGA1023 Ballmap right side moommorceczxrzzumaccs Datasheet Volume 1 145 intel Processor Pin Signal and Package I nformation Table 8 3 1023 Processor Ball List Table 8 3 1023 Processor Ball List by Ball Name by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir BCLK Diff Clk DC TEST BD61 BCLK Diff Clk DC_TEST_BE1 BCLK_ITP Diff Clk DC_TEST_BE3 BCLK_ITP Diff Clk DC_TEST_BE59 BPM 0 Asynch CMOS DC_TEST_BE61 BPM 1 Asynch CMOS DC TEST BG1 BPM 2 Asynch CMOS DC_TEST_BG3 BPM 3 Asynch CMOS DC_TEST_BG4 BPM 4 Asynch CMOS DC_TEST_BG58 BPM 5 Asynch CMOS DC_TEST_BG59 BPM 6 Asynch CMOS DC_TEST_BG61 BG61 N A BPM 7 Asynch CMOS DC_TEST_C4 C4 N A CATERR Asy
101. _MA 3 T6 DDR3 SB DQ 37 AN2 DDR3 I O SB_MA 4 T2 DDR3 SB DQ 38 AN1 DDR3 I O SB_MA 5 T4 DDR3 SB DQ 39 AP2 DDR3 I O SB_MA 6 T3 DDR3 SB DQ 40 AP5 DDR3 1 0 SB_MA 7 R2 DDR3 SB DQ 41 AN9 DDR3 1 0 SB_MA 8 T5 DDR3 SB DQ 42 AT5 DDR3 I O SB_MA 9 R3 DDR3 SB DQ 43 AT6 DDR3 I O SB_MA 10 AB7 DDR3 SB DQ 44 AP6 DDR3 7 SB MA 11 R1 DDR3 SB DQ 45 AN8 DDR3 1 0 SB_MA 12 Ti DDR3 SB DQ 46 AR6 DDR3 I O SB_MA 13 AB10 DDR3 SB DQ 47 ARS DDR3 1 0 SB_MA 14 R5 DDR3 SB DQ 48 AR9 DDR3 I O SB_MA 15 R4 DDR3 SB DQ 49 AJ11 DDR3 I O SB_ODT 0 AE4 DDR3 SB DQ 50 AT8 DDR3 I O SB_ODT 1 AD4 DDR3 SB DQ 51 9 DDR3 I O SB_RAS AB8 DDR3 SB DQ 52 AH11 DDR3 1 0 SB_WE AB9 DDR3 SB DQ 53 AR8 DDR3 1 0 SKTOCC AN34 Analog SB DQ 54 112 DDR3 1 0 SM_DRAMPWROK V8 Asynch CMOS I SB_DQ 55 AH12 DDR3 I O SM_DRAMRST R8 DDR3 SB DQ 56 AT11 DDR3 I O SM_RCOMP 0 AK1 Analog I O SB DQ 57 AN14 DDR3 7 RCOMP 1 5 Analog I O SB DQ 58 AR14 DDR3 I O SM_RCOMP 2 A4 Analog I O SB DQ 59 AT14 DDR3 1 0 SM_VREF AL1 Analog I SB DQ 60 AT12 DDR3 I O TCK AR26 CMOS I SB_DQ 61 AN15 DDR3 I O TDI AR28 CMOS I SB DQ 62 AR15 DDR3 I O TDO AP26 CMOS SB DQ 63 AT15 DDR3 1 0 THERMTRIP AN32 Asynch CMOS SB_DQS 0 D7 DDR3 1 0 TMS AR27 CMOS I SB_DQS 1 F3 DDR3 I O TRST AP30 CMOS I SB DQS 2 DDR IO UNCOREPWRGOOD AP33 Asynch CMOS I SB_DQS 3 N3 DDR3 1 0 VAXG AH17 PWR SB_DQS 4 AN5 DDR3 7 VAXG AH18 PW
102. a ran 34 2 4 1 4 2D 35 2 4 2 Processor Graphics 36 2 4 2 1 Display Planes rh te Ex ven YRR ax Ad RR REN AR RR 36 24 2 2 Display 37 2 4 2 3 Display Ports nth rex RR RR 37 2 4 2 4 Embedded DisplayPort ep 37 2 4 3 Intel Flexible Display Interface Intel EDD 37 2 4 4 Multi Graphics Controllers Multi Monitor 38 2 5 Platform Environment Control Interface PECI eee eee ee ee eee eee 38 2 6 Interface ClOCKING ba pele ntn dac e UD auntie NERO AYRA Y tend bie de 38 2 6 1 Internal Clocking Requirements sess nemen enne 38 Technologies coe eter HAR YARLL YRR a ERAN ER RR PERIERE uapa qaa KR tarde 39 3 1 Intel Virtualization Technology Intel VT nnne 39 3 1 1 Intel Virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Objectives ens 39 3 1 2 Intel Virtualization Technology Intel VT for IA 32 pintel 64 and Intel Architecture Intel VT x Feat res d als YN ela ced ead 40 3 1 3 Intel Virtualization Technology Intel VT for Directed I O Intel E Me EE 40 3 1 4 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Pegbles ia
103. accesses and if it expires the rank may enter power down while no new transactions to the rank arrive to queues The idle counter begins counting at the last incoming transaction arrival Datasheet Volume 1 Power Management intel Note 4 3 2 1 4 3 2 2 It is important to understand that since the power down decision is per rank the MC can find a lot of opportunities to power down ranks even while running memory intensive applications savings may be significant up to a few Watts depending on DDR configuration This becomes more significant when each channel is populated with more ranks Selection of power modes should be according to power performance or thermal trade offs of a given system When trying to achieve maximum performance and power or thermal consideration is a non issue use no power down In a system that tries to minimize power consumption try to use the deepest power down mode possible DLL off or APD_DLLoff In high performance systems with dense packaging that is tricky thermal design the power down mode should be considered in order to reduce the heating and avoid DDR throttling caused by the heating Control of the power mode through CRB BIOS BIOS selects by default no power down Another control is the idle timer expiration count This is set through PM_PDWN_config bits 7 0 MCHBAR 4CBO As this timer is set to a shorter time the IMC will have more opportunities to put DDR in pow
104. aced on the motherboard TS on Board Memory throttling based on physical temperature sensor readings is known as Closed Loop Thermal Throttling CLTT The memory temperature readings are reported from the platform to the memory controller using PECI If no physical thermal sensor is available the memory controller can estimate the temperature based on memory activity Memory thermal throttling that is initiated with no direct temperature reading is known as Open Loop Thermal Throttling OLTT The processor features the Virtual Temperature Sensor VTS for OLTT Platform Environment Control I nterface PECI The Platform Environment Control Interface PECI is a one wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices The processor implements a PECI interface to allow communication of processor thermal information to other devices on the platform The processor provides a digital thermal sensor DTS for fan speed control The DTS is calibrated at the factory to provide a digital representation of relative processor temperature Averaged DTS values are read using the PECI interface The PECI physical layer is a self clocked one wire bus that begins each bit with a driven rising edge from an idle level near zero volts The duration of the signal driven high depends on whether the bit value is a Logic O or Logic 1 PECI also includes variable data transfer rate establ
105. age near the silicon VCCIO SENSE and VSS SENSE VCCIO provide an isolated low can be used to sense or measure voltage near the silicon VCCIO SENSE impedance connection to the processor VCCIO voltage and VSS SENSE VCCIO ground They can be used to sense or measure voltage near the Analog silicon VDDQ SENSE and VSSD SENSE provides an isolated low VDDQ SENSE h g VSSD SENSE impedance connection to the Vppg voltage and ground They Analog Datasheet Volume 1 93 Signal Description intel Table 6 15 Sense Signals Sheet 2 of 2 Sieg Direction Signal Name Description Buffer Type VDDQ SENSE VDDQ SENSE and VSS SENSE VDDQ provides an isolated low o VSS SENSE VDD impedance connection to the Vppo voltage and ground They Anal Q can be used to sense or measure voltage near the silicon nagg VCCSA SENSE provide an isolated low impedance connection o VCCSA SENSE to the processor system agent voltage It can be used to sense Anal or measure voltage near the silicon nalog VCC VAL SENSE VCC Validation Sense VSS VAL SENSE Analog VAL SENSE VAXG Validation Sense VSSAXG VAL SENSE Analog 6 14 Ground and Non Critical to Function NCTF Signals Table 6 16 Ground and Non Critical to Function NCTF Signals Direction Signal Name Description Buffer Type VSS Processor ground node GND Non Critical to Function These signals are for package VSS_NCTF BGA On
106. an DLL off Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP The difference relative to APD mode is that when waking up in PPD mode all page buffers are empty 3 DLL off In this mode the data in DLLs on DDR are off Power saving in this mode is the best among all power modes Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP and tXPDLL 10 20 according to the DDR type until first data transfer is allowed The processor supports 6 different types of power down The different modes are the power down modes supported by DDR3 and combinations of these The type of CKE power down is defined by configuration The options are as follows 1 No power down 2 APD The rank enters power down as soon as the idle timer expires independent of the bank status 3 PPD When idle timer expires the MC sends PRE all to rank and then enters power down 4 DLL off Same as option 2 but DDR is configured to DLL off 5 APD change to PPD APD PPD Begins as option 1 and when all page close timers of the rank are expired it wakes the rank issues PRE all and returns to PPD 6 APD change to DLL off APD_DLLoff Begins as option 1 and when all page close timers of the rank are expired it wakes the rank issues PRE all and returns to DLL off power down The CKE is determined per rank when it is inactive Each rank has an idle counter The idle counter starts counting as soon as the rank has no
107. any available thermal capacitance within the thermal solution The duration and time of such operation can be limited by platform runtime configurable registers within the processor Thermal solutions and platform cooling that are designed to less than thermal design guidance may experience thermal and performance issues since more applications will tend to run at or near the maximum power limit for significant periods of time Datasheet Volume 1 69 intel Thermal Management Note 5 3 5 3 1 70 Intel Turbo Boost Technology Power Monitoring When operating in the Turbo mode the processor will monitor its own power and adjust the Turbo frequency to maintain the average power within limits over a thermally significant time period The package processor core and graphic core powers are estimated using architectural counters and do not rely on any input from the platform The following considerations and limitations apply to the Intel Turbo Boost Technology power monitoring Internal power monitoring is calibrated per processor family and is not conducted on a part by part basis Therefore some difference between actual and reported power may be observed Power monitoring is calibrated with a variety of common realistic workloads near Ti Max Workloads with power characteristics markedly different from those used during the calibration process or lower temperatures may result in increased differences between actual an
108. ariety of applications including communication digital signatures secure storage and so on Intel 64 Architecture x2API C The Intel x2APIC architecture extends the xAPIC architecture that provides key mechanism for interrupt delivery This extension is intended primarily to increase processor addressability Specifically x2APIC Retains all key elements of compatibility to the xAPIC architecture delivery modes interrupt and processor priorities interrupt sources interrupt destination types e Provides extensions to scale processor addressability for both the logical and physical destination modes e Adds new features to enhance performance of interrupt delivery Reduces complexity of logical destination mode interrupt delivery on link based architectures The key enhancements provided by the x2APIC architecture over xAPIC are the following e Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations Datasheet Volume 1 47 intel Technologies Note 3 8 48 In xAPIC compatibility mode APIC registers are accessed through memory mapped interface to a 4 KB page identical to the xAPIC architecture In x2APIC mode APIC registers are accessed through Model Specific Register MSR interfaces In this mode the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery e
109. atasheet Volume 1 73 intel Thermal Management 5 5 Thermal and Power Specifications The following notes apply to the tables in this section Note Definition The TDPs given are not the maximum power the processor can generate Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained periods of time TDP workload may consist of a combination of a processor core intensive and a graphics core intensive applications The thermal solution needs to ensure that the processor temperature does not exceed the maximum junction temperature T max limit as measured by the DTS and the critical temperature bit The processor junction temperature is monitored by Digital Temperature Sensors DTS For DTS accuracy refer to Section 5 6 2 1 Digital Thermal Sensor DTS based fan speed control is required to achieve optimal thermal performance Intel recommends full cooling capability well before the DTS reading reaches An example of this would be T max 10 C The idle power specifications are not 100 tested These power specifications are determined by the characterization at higher temperatures and extrapolating the values for the junction temperature indicated At Tj of Tj max At T of 50 C 10 11 12 13 14 At Tj of 35 C Can be modified at runtime by MSR writes with MMIO and with PECI commands Tur
110. ating DDR EPG during normal operation S0 mode while the processor is at package C3 or deeper power state During EPG the Vccro internal voltage rail will be powered down while Vppq and the un gated Vccjo will stay powered on The processor will transition in and out of DDR EPG mode on an as needed basis without any external pins or signals Datasheet Volume 1 Power Management 4 4 Note Note 4 5 4 6 4 6 1 4 6 2 There is no change to the signals driven by the processor to the DIMMs during DDR IO EPG mode During EPG mode all the DDR IO logic will be powered down except for the Physical Control registers that are powered by the un gated Vccrio power supply Unlike S3 exit at DDR EPG exit the DDR will not go through training mode Rather it will use the previous training information retained in the physical control registers and will immediately resume normal operation PCI Express Power Management e Active power management support using LOs and L1 states e All inputs and outputs disabled in L2 L3 Ready state PCIe interface does not support Hot Plug An increase in power consumption may be observed when PCIe Active State Power Management ASPM capabilities are disabled DMI Power Management e Active power management support using LOs L1 state Graphics Power Management Intel Rapid Memory Power Management Intel RMPM also known as CxSR The Intel Rapid Memory Power Management Int
111. bile DIMM Support Summary by 23 2 2 Supported DDR3 DDR3L DDR3L RS SO DIMM Module Configurations 24 2 3 Supported Maximum Memory Size Per DIMNM eene nemen 24 2 4 DDR3 DDR3L DDR3L RS at 1 5 V System Memory Timing Support 25 2 5 DDR3L DDR3L RS System Memory Timing Support 25 2 6 Reference Clock ic trina NSA CAR AUU O RA a pa dn gon MR RUN RU ened 38 4 1 System States u Ee SEENEN REEF ERE PRICE RE 50 4 2 Processor Core Package State SUpport nemen eene eene 50 4 3 Integrated Memory Controller States 50 4 4 PCI Express Link SEN EN KENE CAR RNA nd ax ends e rae EEN a IN RR C db 51 4 5 Direct Media Interface DMI States LEL LARLL EE ER EL ED LA nnn 51 4 6 Processor Graphics Controller Gtates LLY enne 51 4 7 G S and C State Combinations iis ua D b eh Y CA Loa gu TN ved ava YAR dE EEN e 51 4 8 D S and C State Combination ein GWRW YR kr vu CAD none oy 52 4 9 Coordination of Thread Power States at the Core Level 54 Datasheet Volume 1 7 4 10 P LVLx to MWAIT Copnversion nnnm nnnm nnnm nh RA AREA RE RA aaa aan ann nnn 54 4 11 Coordination of Core Power States at the Package 57 4 12 Targeted Memory State Cond
112. bo Time Parameter is a mathematical parameter seconds that controls the processor Turbo algorithm using a moving average of energy usage Do not set the Turbo Time Parameter to a value less than 0 1 seconds Refer to Section 5 3 3 for further information Shown limit is a time averaged power based upon the Turbo Time Parameter Absolute product power may exceed the set limits for short durations or under virus or uncharacterized workloads Processor will be controlled to specified power limit as described in Section 5 2 If the power value and or Turbo Time Parameter is changed during runtime it may take a short period of time approximately 3 to 5 times the Turbo Time Parameter for the algorithm to settle at the new control limits This is a hardware default setting and not a behavioral characteristic of the part 15 16 17 For controllable Turbo workloads limit may be exceeded for up to 10 ms Refer to Table 5 2 for the definitions of TDP Nominal TDP Up TDP Down LPM power level is an opportunistic power and is not an ensured value as usages and implementations may vary LPM power level assumes 1 core active processor core frequency at MFM Graphics Core running at non Turbo frequency and running an application according to Note 2 18 19 Power limits may vary depending on if the product supports the TDP up and or TDP down modes Default power limits can be found in the PKG_PWR_SKU MSR 614h Mi
113. ced Intel SpeedStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P state When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C state In general lower power C states have longer entry and exit latencies Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology e Multiple frequency and voltage points for optimal performance and power efficiency These operating points are known as P states e Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on the selected frequency and the number of active processor cores If the target frequency is higher than the current frequency Vcc is ramped up in steps to an optimized voltage This voltage is signaled by the SVID bus to the voltage regulator Once the voltage is established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling the target voltage on SVID bus All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested amongst all active cores is selected Software requested transitions are accepted at any time If a previous tran
114. cesses cacheable memory Core C6 State Individual threads of a core can enter the C6 state by initiating a P LVL3 I O read or an MWAIT C6 instruction Before entering core C6 the core will save its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts During exit the core is powered on and its architectural state is restored Datasheet Volume 1 57 intel Power Management 4 2 4 5 Core C7 State Note The terms Core C6 state and Core C7 state defines the same individual core power state In both cases the processor cores that request either C6 or C7 will enter the C6 state Individual threads of a core can enter the C7 state by initiating a P_LVL4 I O read to the P BLK or by an MWAIT C7 instruction The core C7 state exhibits the same behavior as the core C6 state unless the core is the last one in the package to enter the C7 state If it is that core is responsible for flushing L3 cache ways The processor supports the C7s substate When an MWAIT C7 command is issued with a C7s sub state hint the entire L3 cache is flushed one step as opposed to flushing the L3 cache in multiple steps 4 2 4 6 C State Auto Demotion In general deeper C states such as C6 or C7 have long latencies and have higher energy entry exit costs The resulting performance and energy penalties become significant when the entry exit frequency of a deeper C state is high Therefore incorrect or in
115. creasing the efficiency of system memory protocol 2 1 5 3 Out of Order Scheduling While leveraging the Just in Time Scheduling and Command Overlap enhancements the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency If there are multiple requests to the same open page these requests would be launched in a back to back manner to make optimum use of the open memory page This ability to reorder requests on the fly allows the IMC to further reduce latency and increase bandwidth efficiency 2 1 6 Data Scrambling The memory controller incorporates a DDR3 Data Scrambling feature to minimize the impact of excessive di dt on the platform DDR3 VRs due to successive 1s and 0s on the data bus Past experience has demonstrated that traffic on the data bus is not random Rather it can have energy concentrated at specific spectral harmonics creating high di dt that is generally limited by data patterns that excite resonance between the package inductance and on die capacitances As a result the memory controller uses a data scrambling feature to create pseudo random patterns on the DDR3 data bus to reduce the impact of any excessive di dt 2 1 7 DRAM Clock Generation Every supported DIMM has two differential clock pairs There are total of four clock pairs driven directly by the processor to two DIMMs Datasheet Volume 1 29 2 2 2 2 1 Figure 2 2 30 I nterfaces DDR3 Refer
116. ct specific rasterization algorithms The WIZ unit rasterizes objects into the corresponding set of pixels The Windower is also capable of performing dithering whereby the illusion of a higher resolution when using low bpp channels in color buffers is possible Color dithering diffuses the sharp color bands seen on smooth shaded objects Video Engine The video engine is part of the Intel Processor Graphics for image processing play back and transcode of Video applications The Processor Graphics video engine has a dedicated fixed hardware pipe line for high quality decode and encode of media content This engine supports Full hardware acceleration for decode of AVC H 264 VC 1 and MPEG 2 contents along with encode of MPEG 2 and AVC H 264 apart from various video processing features The new Processor Graphics Video engine adds support for processing features such as frame rate conversion image stabilization and gamut conversion Datasheet Volume 1 I nterfaces 2 4 1 4 2 4 1 4 1 2 4 1 4 2 intel The Display Engine fetches the raw data from the memory puts the data into a stream converts the data into raw pixels organizes pixels into images blends different planes into a single image encodes the data and sends the data out to the display device 2D Engine The Display Engine executes its functions with the help of three main functional blocks Planes Pipes and Ports except for eDP The Planes and Pipes are in the pr
117. d at the crossing point I O SA_DQS 7 0 of SA_DQS 7 0 and its SA_DQS 7 0 during read and write DDR3 transactions Data Bus Channel A data signal interface to the SDRAM data bus yo SA DQ 63 0 9 DDR3 SA MAT15 0 Memory Address These signals are used to provide the multiplexed MA 15 0 row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel A SDRAM Differential clock signal pair The crossing of the positive edge of SA CK and the negative edge o SA CK 3 0 of its complement SA_CK are used to sample the command and _CK 3 0 DDR3 control signals on the SDRAM Signals 3 2 are used only for 2 DPC system SDRAM I nverted Differential Clock Channel A SDRAM Differential o SA_CK 3 0 clock signal pair complement DORS Signals 3 2 are used only for 2 DPC system Clock Enable 1 per rank These signals are used to e Initialize the SDRAMs during power up o SA CKE 3 0 e Power down SDRAM ranks DDR3 Place all SDRAM ranks into and out of self refresh during STR e Signals 3 2 are used only for 2 DPC system Chip Select 1 per rank These signals are used to select particular SA CS I3 0 SDRAM components during the active state There is one Chip Select A_CS 3 0 for each SDRAM rank DDR3 Signals 3 2 are used only for 2 DPC system On Die Termination Active Termination Control SA ODT 3 0 3 0 Signals 3 2 are used only for 2 DPC system DDR3 Datasheet Volume 1 Signal Description Table 6 3 Memory
118. d estimated power e In the event an uncharacterized workload or power virus application were to result in exceeding programmed power limits the processor Thermal Control Circuitry TCC will protect the processor when properly enabled Adaptive Thermal Monitor must be enabled for the processor to remain within specification It is recommended to use TCC Activation Offset to optimize thermal control of the processor while in Turbo See Section 5 6 1 1 for more information Intel Turbo Boost Technology Power Control Illustration of Intel Turbo Boost Technology power control is shown in the following sections and figures Multiple controls operate simultaneously allowing for customization for multiple system thermal and power limitations These controls allow for Turbo optimizations within system constraints and are accessible using MSR MMIO or PECI interfaces Package Power Control Intel Turbo Boost Technology package power control allows for customization in order to implement optimal Turbo within platform power delivery and package thermal solution limitations The control settings are shown in Table 5 1 while the behavior is illustrated in Figure 5 1 Datasheet Volume 1 Thermal Management m Table 5 1 Intel Turbo Boost Technology Package Power Control Settings MSR MSR TURBO POWER LIMIT Address 610h Control Bit Default Description This value sets the exponentially weighted moving average power limit over a lo
119. different settings within the VID range This differs from the VID employed by the processor during a power or thermal management event Intel Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States Table 7 11 DDR3 DDR3L DDR3L RS Signal Group DC Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Units Notes VIL Input Low Voltage SM VREF 0 1 V 2 4 11 Vin VIL Input High Voltage Input Low Voltage SM DRAMPWROK Input High Voltage SM DRAMPWROK SM VREF 0 1 Vppo 0 55 0 1 Vppo 0 55 0 1 V 3 1 11 B 10 Von Output Low Voltage Output High Voltage Vppo 2 R ARS ca V Ro RoN FRTERM 2 V Row uP DQ DDR3 Data Buffer pull up Resistance 20 28 6 Ron_DN DQ DDR3 Data Buffer pull down Resistance 20 28 6 Ropr DQ Vopr pc DDR3 On die termination eguivalent resistance for data signals DDR3 On die termination DC working point driver set to receive mode 40 50 RON_UP CK DDR3 Clock Buffer pull up Resistance 20 26 40 o DN CK DDR3 Clock Buffer pull down Resistance 20 26 40 o 12 RON_UP CMD DDR3 Command Buffer pull up Resistance 15 20 25 o 12 RON_DN CMD DDR3 Command Buffer pull down Resistance 15 20 25 o 12
120. duces an output vertex reference for every input vertex reference received from the VF unit in the order received Geometry Shader GS Stage The GS stage receives inputs from the VS stage Compiled application provided GS programs specifying an algorithm to convert the vertices of an input object into some output primitives For example a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges Clip Stage The Clip stage performs general processing on incoming 3D objects However it also includes specialized logic to perform a Clip Test function on incoming objects The Clip Test optimizes generalized 3D Clipping The Clip unit examines the position of incoming vertices and accepts rejects 3D objects based on its Clip algorithm Strips and Fans SF Stage The SF stage performs setup operations required to rasterize 3D objects The outputs from the SF stage to the Windower stage contain implementation specific information required for the rasterization of objects and also supports clipping of primitives to some extent Windower IZ WIZ Stage The WIZ unit performs an early depth test which removes failing pixels and eliminates unnecessary processing overhead The Windower uses the parameters provided by the SF unit in the obje
121. e 9 P t POWER LIMIT 1 TIME in N A 1 N A 10 11 package TURBO_POWER LIMIT MSR 0610h bits 5 14 23 17 Long duration Turbo power limit Extreme Long P POWER LIMIT 1 in 10 12 Edition XE package TURBO POWER LIMIT MSR 0610h bits N A ae N A 13 14 14 0 Short duration Turbo power limit Short P POWER LIMIT 2 in 1 25 x 10 14 N A N A w package TURBO POWER LIMIT MSR 0610h bits 55 15 46 32 WEE Turbo long duration time window urbo lime Parameter POWER LIMIT 1 TIME in 0 001 1 64 S 10 11 package TURBO POWER LIMIT MSR 0610h bits 14 23 17 Long duration Turbo power limit 10 12 Quad Core Long P POWER LIMIT 1 in SV 45W package TURBO POWER LIMIT MSR 0610h bits 36 SS 607 WA w 13 14 14 0 Short duration Turbo power limit Short P POWER LIMIT 2 in 36 1 25X 72 N A w 10 14 package TURBO POWER LIMIT MSR 0610h bits 45 CR 15 20 46 32 oe Turbo long duration time window urbo lime as Parameter POWER LIMIT 1 TIME in 0 001 1 64 S 10 11 package TURBO POWER LIMIT MSR 0610h bits 14 23 17 Quad Core Long duration Turbo power limit 10 12 an Long P POWER LIMIT 1 in DualCore package TURBO POWER LIMIT MSR 0610h bits a SV 35 W 14 0 Short duration Turbo power limit Short P POWER_LIMIT_2 in 24 1 25X 56 w 10 14 package TURBO_POWER_LIMIT MSR 0610h bits 35 CES 15 20 46 32 a Turbo long duration time wi
122. e and affect the long term reliability of the processor May be incapable of cooling the processor even when the TCC is active continuously in extreme situations Low Power States and PROCHOT Behavior If the processor enters a low power package idle state such as C3 or C6 C7 with PROCHOT asserted PROCHOT will remain asserted until e The processor exits the low power state e The processor junction temperature drops below the thermal trip point For the package C7 state PROCHOT may de assert for the duration of C7 state residency even if the processor enters the idle state operating at the TCC activation temperature The PECI interface is fully operational during all C states and it is expected that the platform continues to manage processor core and package thermals even during idle states by regularly polling for thermal data over PECI Datasheet Volume 1 Thermal Management intel 5 6 3 5 5 6 3 6 5 6 4 5 6 4 1 5 6 4 2 THERMTRI P Signal Regardless of enabling the automatic or on demand modes in the event of a catastrophic cooling failure the package will automatically shut down when the silicon has reached an elevated temperature that risks physical damage to the product At this point the THERMTRIP signal will go active Critical Temperature Detection Critical Temperature detection is performed by monitoring the package temperature This feature is intended for graceful shutdown before the THERMTRIP
123. e assembly and disassembly of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs Data Link Layer The middle layer in the PCI Express stack the Data Link Layer serves as an intermediate stage between the Transaction Layer and the Physical Layer Responsibilities of Data Link Layer include link management error detection and error correction The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer calculates and applies data protection code and TLP sequence number and submits them to Physical Layer for transmission across the Link The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing On detection of TLP error s this layer is responsible for requesting retransmission of TLPs until information is correctly received or the Link is determined to have failed The Data Link Layer also generates and consumes packets which are used for Link management functions Physical Layer The Physical Layer includes all circuitry for interface operation including driver and input buffers parallel to serial and serial to parallel conversion PLL s clock recovery circuits and impedance matching circuitry It also includes logical functions related to interface initializati
124. echanisms to ensure the above measurement is protected and stored in a secure location e Protection mechanisms that allow the MLE to control attempts to modify itself For more information refer to the Intel9 TXT Measured Launched Environment Developer s Guide in http www intel com content www us en software developers intel txt software development guide html Intel Hyper Threading Technology Intel HT Technology The processor supports Intel Hyper Threading Technology Intel HT Technology that allows an execution core to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled using the BIOS and requires operating system support Intel recommends enabling Intel HT Technology with Microsoft Windows 7 Microsoft Windows Vista Microsoft Windows XP Professional Windows XP Home and disabling Intel HT Technology using the BIOS for all previous versions of Windows operating systems For more information on Intel HT Technology see http www intel com technology platform technology hyper threading Datasheet Volume 1 Technologies 3 4 Note 3 4 1 intel Intel Turbo Boost Technology Intel Turbo Boost Technology will increase the ratio of application power to TDP Thus thermal solutions and pla
125. ecognize the proper signal state See Section 7 9 for the DC specifications Datasheet Volume 1 101 7 8 Table 7 4 102 intel Electrical Specifications Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level The processor supports Boundary Scan JTAG IEEE 1149 1 2001 and IEEE 1149 6 2003 standards Some small portion of the I O pins may support only one of these standards Component Storage Condition Specifications Prior to Board Attach This section applies to component level storage prior to board attach Environmental storage condition limits define the temperature and relative humidity to which the device is exposed to while being stored in applicable Intel shipping media trays reels moisture barrier bags and Boxes and the component is not electrically connected Post board attach storage conditions and limits are not specified for non intel branded boards Table 7 4 specifies absolute maximum and minimum storage temperature and humidity limits for given time durations Failure to adh
126. efficient usage of deeper C states have a negative impact on battery life To increase residency and improve battery life in deeper C states the processor supports C state auto demotion There are two C State auto demotion options C7 C6 to C7 C6 C3 To C1 The decision to demote a core from C6 C7 to C3 or C3 C6 C7 to C1 is based on each core s immediate residency history Upon each core C6 C7 request the core C state is demoted to C3 or C1 until a sufficient amount of residency has been established At that point a core is allowed to go into C3 C6 or C7 Each option can be run concurrently or individually This feature is disabled by default BIOS must enable it in the PMG CST CONFIG_ CONTROL register The auto demotion policy is also configured by this register 4 2 5 Package C States The processor supports CO C1 C1E C3 C6 and C7 power states The following is a summary of the general rules for package C state entry These apply to all package C states unless specified otherwise e A package C state request is determined by the lowest numerical core C state amongst all cores A package C state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C state The platform may allow additional power
127. el RMPM puts rows of memory into self refresh mode during C3 C6 C7 to allow the system to remain in the lower power states longer Processors routinely save power during runtime conditions by entering the C3 C6 or C7 state Intel RMPM is an indirect method of power saving that can have a significant effect on the system as a whole Intel Graphics Performance Modulation Technology Intel GPMT Intel Graphics Power Modulation Technology Intel GPMT is a method for saving power in the graphics adapter while continuing to display and process data in the adapter This method will switch the render frequency and or render voltage dynamically between higher and lower power states supported on the platform based on render engine workload When the system is running in battery mode and if the end user launches applications such as 3D or Video the graphics software may switch the render frequency dynamically between higher and lower power performance states depending on the render engine workload In products where Intel Graphics Dynamic Frequency also known as Turbo Boost Technology is supported and enabled the functionality of Intel GPMT will be maintained by Intel Graphics Dynamic Frequency also known as Turbo Boost Technology Datasheet Volume 1 65 intel Power Management Caution 4 6 4 4 6 5 66 Graphics Render C State Render C State RC6 is a technique designed to optimize the average power to the graphics render en
128. em data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector A VMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software 3 1 3 I ntel virtualization Technology Intel VT for Directed I O Intel VT d Objectives The key Intel VT d objectives are domain based isolation and hardware based virtualization A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated Virtualization allows for the creation of one or more partitions on a single system This could be multiple partitions in the same operating system or there can be multiple operating system instances running on the same system offering benefits such as system consolidation legacy migration activity partitioning or security 42 Datasheet Volume 1 Technologies 3 1 4 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Features The processor supports the following Intel VT d features Memory controller and processor graphics comply with Intel VT d 1 2 specification Two VT d DMA remap engines iGFX DMA remap engine DMI PEG Support for root entry context entry and default context 39 bit guest physical address and host physical address widths Support for 4K page sizes only Supp
129. emory Controller Gtates sess nene 50 4 1 4 PCI Express Link States er YRR ela dee a ioca oa ex ERR CER 51 4 1 5 Direct Media Interface DMI States nme 51 4 1 6 Processor Graphics Controller States Y A RY LLY YY RR ens 51 4 1 7 Interface State Combinations EN KEREN SEN KE CR EE EU ene ku nan ausa n EX a RR RR ERE awasqa 51 4 2 Processor Core Power Management 52 Datasheet Volume 1 4 2 1 Enhanced Intel SpeedStep Technology 52 4 2 2 Low Power Idle States SEN rere dE FAWD AD Cy YD DER RA DAR RL 53 4 2 3 Requesting Low Power Idle States Y LLA eene 54 42 4 57 u LOR gegen qaw aen Rana RACE SEENEN ead as 55 4 2 4 1 Core State e yen AER ENNEN AR gege 55 4 2 4 2 Core CIE Stat e FR ANG au orta susiana aaa 55 4 2 4 3 Cre e EE 55 4 2 4 4 CO State ec u aaa Dion psu Y TY NN O I EE 55 22 4 5 Core TEE 56 4 2 4 6 CGZStatehuto Demetion Uu ER NENNEN REED RO 56 4 2 5 Package C States cesses pepe EE EA UND CU 56 4 2 5 1 Package CO vez 58 4 2 5 2 Package Cl C TE ia eege tb eR aine ia Du Ra n fae SEN e 58 4 2 5 3 Package C3 State ciiin iet ecc se ses ee da E edu ea EEN SE 58 4 2 5 4 Package C6 State iiis cesses ient ge egi SES 58
130. ence Voltage Generation The processor memory controller has the capability of generating the DDR3 Reference Voltage VREF internally for both read RDVREF and write VREFDQ operations The generated VREF can be changed in small steps and an optimum VREF value is determined for both during a cold boot through advanced DDR3 training procedures in order to provide the best voltage and signal margins PCI Express Interface This section describes the PCI Express interface capabilities of the processor See the PCI Express Base Specification for details of PCI Express The processor has one PCI Express controller that can support one external x16 PCI Express Graphics Device The primary PCI Express Graphics port is referred to as PEG O PCI Express Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers may operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The processor external graphics ports support Gen 3 speed as well At 8 GT s Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2 operation The 16 lane PCI Express graphics port can operate at either 2 5 GT s 5 GT s or 8 GT s PCI Express Gen 3 uses a 128 130b encoding scheme eliminating nearly all of the overhead of the 8b 10b encoding scheme used in Gen 1 and Gen 2 operation The PCI Express architecture is
131. ensure that the voltage provided to the processor remains within the specifications listed in Table 7 3 Failure to do so can result in timing violations or reduced lifetime of the processor Voltage Rail Decoupling The voltage regulator solution must e provide sufficient decoupling to compensate for large current swings generated during different power mode transitions e provide low parasitic resistance from the regulator to the socket e meet voltage and current specifications as defined in Table 7 3 PLL Power Supply An on die PLL filter solution is implemented on the processor Datasheet Volume 1 95 Electrical Specifications 7 3 Voltage Identification VI D The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages Table 7 4 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself See the VR12 IMVP7 PWM Specification for further details The VID codes will change due to temperature and or current load changes in order to minimize the power of the part A voltage range is provided in Table 7 4 The specifications are set so that one voltage regulator can operate with all supported frequencies Individual
132. ent and system design Intel Turbo Boost Technology Frequency The processor s rated frequency assumes that all execution cores are active and are at the sustained thermal design power TDP However under typical operation not all cores are active or at executing a high power workload Therefore most applications are consuming less than the TDP at the rated frequency Intel Turbo Boost Technology takes advantage of the available TDP headroom and active cores are able to increase their operating frequency To determine the highest performance frequency amongst active cores the processor takes the following into consideration to recalculate turbo frequency during runtime The number of cores operating in the CO state e The estimated core current consumption e The estimated package prior and present power consumption The package temperature Any of these factors can affect the maximum frequency for a given workload If the power current or thermal limit is reached the processor will automatically reduce the frequency to stay with its TDP limit Turbo processor frequencies are only active if the operating system is requesting the PO state For more information on P states and C states refer to Chapter 4 Power Management Datasheet Volume 1 45 intel Technologies Note 3 5 3 6 3 6 1 46 Intel Turbo Boost Technology Graphics Frequency The graphics render frequency is selected dynamically based on graphic
133. ependant many workloads will allow some Turbo frequencies at power at or below TDP Figure 5 1 Package Power Control P gt Power limit 2 Short duration turbo lt 10msec exceedence power limit Power limit 2 Long duration turbo power limit Power limit 1 Datasheet Volume 1 71 intel Thermal Management 5 3 2 5 3 3 5 4 5 4 1 Note 72 Power Plane Control The processor core and graphics core power plane controls allow for customization to implement optimal Turbo within voltage regulator thermal limitations It is possible to use these power plane controls to protect the voltage regulator from overheating due to extended high currents Power limiting per plane cannot be ensured in all usages This function is similar to the package level long duration Turbo control Graphics Turbo frequencies can be efficiently limited by setting the Secondary Plane Turbo Power Limit to an artificially low setting that may be designed in certain cases Primary Plane Turbo Power Limit lower settings are bound to the same limits as found in the PACKAGE MIN POWER MSR 0x614 30 16 Turbo Time Parameter Turbo Time Parameter is a mathematical parameter units in seconds that controls the Intel Turbo Boost Technology algorithm using an exponentially weighted moving average of energy usage During a maximum power Turbo event of about 1 25 x TDP the processor could sustain POWER LIMIT 2 for up to ap
134. er down The minimum recommended value for this register is 15 There is no BIOS hook to set this register Customers who choose to change the value of this register can do it by changing the BIOS For experiments this register can be modified in real time if BIOS did not lock the MC registers In APD APD PPD and APD DLLoff there is no point in setting the idle counter in the same range of page close idle timer Another option associated with CKE power down is the S_DLL off When this option is enabled the SBR I O slave DLLs go off when all channel ranks are in power down Do not confuse it with the DLL off mode in which the DDR DLLs are off This mode reguires an I O slave DLL wakeup time be defined I nitialization Role of CKE During power up CKE is the only input to the SDRAM that has its level recognized other than the DDR3 reset pin once power is applied The signal must be driven LOW by the DDR controller to make sure the SDRAM components float DO and DOS during power up CKE signals remain LOW while any reset is active until the BIOS writes to a configuration register Using this method CKE is ensured to remain inactive for much longer than the specified 200 us after power and clocks to SDRAM devices are stable Conditional Self Refresh Intel Rapid Memory Power Management Intel RMPM conditionally places memory into self refresh in the package C3 C6 and C7 low power states Intel RMPM functionality depends on graphics dis
135. er has expired the TCC goes inactive and clock modulation ceases Clock modulation is automatically engaged as part of the TCC activation when the frequency voltage targets are at their minimum settings Processor performance will be decreased by the same amount as the duty cycle when clock modulation is active Snooping and interrupt processing are performed in the normal manner while the TCC is active Digital Thermal Sensor Each processor execution core has an on die Digital Thermal Sensor DTS that detects the core s instantaneous temperature The DTS is the preferred method of monitoring processor die temperature because e It is located near the hottest portions of the die e It can accurately track the die temperature and ensure that the Adaptive Thermal Monitor is not excessively activated Temperature values from the DTS can be retrieved through A software interface using the processor Model Specific Register MSR e A processor hardware interface as described in Section 5 6 6 Platform Environment Control Interface PECI on page 84 When temperature is retrieved by the processor MSR it is the instantaneous temperature of the given core When temperature is retrieved using PECI it is the average of the highest DTS temperature in the package over a 256 ms time window Intel recommends using the PECI reported temperature for platform thermal control that benefits from averaging such as fan speed control The average D
136. eration TOM Non interleaved access Dual channel interleaved access CHA CHB CH A and CH B can be configured to be physical channels O or 1 B The largest physical memory amount of the smaller size memory module C The remaining physical memory amount of the larger size memory module Dual Channel Symmetric Mode Dual Channel Symmetric mode also known as interleaved mode provides maximum performance on real world applications Addresses are ping ponged between the channels after each cache line 64 byte boundary If there are two requests and the second request is to an address on the opposite channel from the first that request can be sent before data from the first request has returned If two consecutive cache lines are requested both may be retrieved simultaneously since they are ensured to be on opposite channels Use Dual Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being the same When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory the IMC operates completely in Dual Channel Symmetric mode The DRAM device technology and width may vary from one channel to the other Rules for Populating Memory Slots In all System Memory Organization Modes the frequency and latency timings of the system mem
137. ere to the specified limits could result in physical damage to the component If this is suspected Intel recommends a visual inspection to determine possible physical damage to the silicon or surface components Storage Condition Ratings Symbol Parameter Min Max Notes Device storage temperature when exceeded for an Tabsolute storage length of IG 25 125 C 1 2 3 4 The ambient storage temperature and time for up to Tshort term storage 72 hours a 2 85 C 1 2 3 4 Tsustained storage rime The ambient storage temperature and time for up to 5 C 40 1 234 and Temp 30 months rr 2 The maximum device storage relative humidity for u RHsustained storage to 30 months B y P 60 24 C 1 2 3 4 Notes 1 Specified temperatures are not to exceed values based on data collected Exceptions for surface mount reflow are specified by the applicable JEDEC standard Non adherence may affect processor reliability 2 Component product device storage temperature qualification methods may follow JESD22 A119 low temp and JESD22 A103 high temp standards when applicable for volatile memory 3 Component stress testing is conducted in conformance with JESD22 A104 4 The JEDEC J JSTD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag Datasheet Volume 1 Electrical Specifications intel 7 9 D
138. est low power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from CO is required before entering any other C state Datasheet Volume 1 55 intel Table 4 9 4 2 3 Note Table 4 10 Note 56 Power Management Coordination of Thread Power States at the Core Level Processor Core Thread 1 C State eo i m CO CO CO CO CO a C1 CO Thread 0 CO C6 CO C7 CO Note If enabled the core C state will be C1E if all cores have resolved a core C1 state or higher Reguesting Low Power I dle States The primary software interfaces for reguesting low power idle states are through the MWAIT instruction with sub state hints and the HLT instruction for C1 and C1E However software may make C state requests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P_LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions using I O reads To seamless support of legacy operating systems P_LVLx I O reads are converted within the processor to the equivalent MWAIT C state request Therefore P LVLx reads do not directly result in I O reads to the system The feature known as I O MWAIT redirection must be enabled in the BIOS The P LVLx I
139. fer Type bir VSS AH4 GND VSS AM7 GND VSS AH7 GND VSS AN10 GND VSS AJ1 GND VSS AN13 GND VSS AJ10 GND VSS AN16 GND VSS AJ13 GND VSS AN19 GND VSS AJ16 GND VSS AN22 GND VSS AJ19 GND VSS AN25 GND VSS AJ2 GND VSS AN27 GND VSS AJ22 GND VSS AN30 GND VSS AJ25 GND VSS AN4 GND VSS AJ3 GND VSS AN7 GND VSS AJ4 GND VSS AP1 GND VSS AJ7 GND VSS AP10 GND VSS AK10 GND VSS AP13 GND VSS AK13 GND VSS AP16 GND VSS AK16 GND VSS AP19 GND VSS AK19 GND VSS AP22 GND VSS AK22 GND VSS AP25 GND VSS AK25 GND VSS AP28 GND VSS AK27 GND VSS AP31 GND VSS AK30 GND VSS AP34 GND VSS AK33 GND VSS AP4 GND VSS AK4 GND VSS AP7 GND VSS AK7 GND VSS AR10 GND VSS AL10 GND VSS AR13 GND VSS AL13 GND VSS AR16 GND VSS AL16 GND VSS AR19 GND VSS AL19 GND VSS AR2 GND VSS AL2 GND VSS AR22 GND VSS AL22 GND VSS AR25 GND VSS AL25 GND VSS AR4 GND VSS AL28 GND VSS AR7 GND VSS AL31 GND VSS AT10 GND VSS AL34 GND VSS AT13 GND VSS AL4 GND VSS AT16 GND VSS AL7 GND VSS AT19 GND VSS AM1 GND VSS AT22 GND VSS AM10 GND VSS AT25 GND VSS AM13 GND VSS AT27 GND VSS AM16 GND VSS AT29 GND VSS AM19 GND VSS AT3 GND VSS AM2 GND VSS AT32 GND VSS AM22 GND VSS AT35 GND VSS AM25 GND VSS AT4 GND VSS AM29 GND VSS AT7 GND VSS AM3 GND VSS B11 GND VSS AM4 GND VSS B13 GND 122 Datasheet Volume 1 Processor Pin Signal and Package I nformation intel
140. ght be changed based on SKU 20 74 Unlimited max power limit requires the latest BIOS revision Datasheet Volume 1 Thermal Management Table 5 3 Thermal Design Power TDP Specifications Processor Segment State care Graphics Core Thermal Units Notes requency frequency Design Power TDP Up 65 7 1 9 GHz TDP Nominal HFM up to 3 8 GHz 55 Extreme Edition XE TDP Down 400 MHZ up to 45 w 1200 MHz 40 800 MHz 35 2 3 GHz up to 45 Quad Core SV 3 7 GHz sure w 1 2 7 1200 MHz 35 2 1 GHz up to 3 1 GH as Quad Core SV 2 w 1 2 7 1200 30 2 4 GHz up to 35 3 6 GHz 350 MHz up to Dual Core SV 1250 MHz w 1 2 7 1200 MHz 30 TDP Up 25 TDP Nominal HFM to 17 Dual Core i 350 MHz up to 1 2 7 17 Ultra 1100 MHz 14 w 18 800 MHz 14 800 MHz 12 5 Table 5 4 Junction Temperature Specification Segment Symbol Package Turbo Parameter Min Default Max Units Notes Extreme Edition XE Tj Junction temperature limit 0 105 C 354 5 Quad Core SV Tj Junction temperature limit 0 105 C 845 Dual Core SV Tj Junction temperature limit 0 105 3 4 5 16 Ultra Tj Junction temperature limit 0 105 3 4 5 Datasheet Volume 1 75 Thermal Management intel Table 5 5 Package Turbo Parameters Segment Symbol Package Turbo Parameter Min Max Units Notes Turbo long duration time window urbo lim
141. gine during times of idleness of the render engine Render C state is entered when the graphics render engine blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions When the idleness condition is met then the Integrated Graphics will program the VR into a low voltage state 90 V through the SVID bus Long term reliability cannot be assured unless all the Low Power Idle States are enabled Intel Smart 2D Display Technology Intel S2DDT Intel S2DDT reduces display refresh memory traffic by reducing memory reads required for display refresh Power consumption is reduced by less accesses to the IMC S2DDT is only enabled in single pipe mode Intel S2DDT is most effective with Display images well suited to compression such as text windows slide shows and so on Poor examples are 3D games e Static screens such as screens with significant portions of the background showing 2D applications processor benchmarks and so on or conditions when the processor is idle Poor examples are full screen 3D games and benchmarks that flip the display image at or near display refresh rates Intel Graphics Dynamic Frequency Intel Graphics Dynamic Frequency Technology is the ability of the processor and graphics cores to opportunistically increase frequency and or voltage above the ensured processor and graphics frequency for the given part Intel Graphics Dynamic Frequency
142. gment Rate MT s 1333 Extreme Edition XE and Quad Core SV 1600 Dual Core 1333 See Voltage SV and Ultra 1600 Note 1 System memory timing support is based on availability and is subject to change System Memory Organization Modes The IMC supports two memory organization modes single channel and dual channel Depending upon how the DIMM Modules are populated in each memory channel a number of different configurations can exist Single Channel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order but not both Dual Channel Mode Intel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode Memory is divided into a symmetric and a asymmetric zone The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached In this mode the system runs with one zone of dual channel mode and one zone of single channel mode simultaneously across the whole memory array Datasheet Volume 1 27 intel Interfaces Note Figure 2 1 2 1 3 2 1 Note 2 1 4 28 Channels A and B can be mapped for physical channel O and 1 respectively or vice versa however channel A size must be greater or equal to channel B size I ntel Flex Memory Technology Op
143. he PCI Express Base Specification for more details Low impedance defined during signaling Parameter is captured for 5 0 GHz by RLTX DIFF COMP resistance must be provided on the system board with 1 resistors COMP resistors are to PEG ICOMPO PEG ICOMPI PEG RCOMPO are the same resistor Intel allows using 24 9 O 1 resistors DC impedance limits are needed to ensure Receiver detect The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance constrained by RLRX CM to 50 20 must be within the specified range by the time Detect is entered Embedded DisplayPort DC Specifications Symbol Parameter Min Typ Max Units Notes eDP HPD VIL Input Low Voltage 0 1 0 3 Vccro V the receiving device Vin Input High Voltage 0 7 Vccio Vccio V eDP AUX eDP AUX AUX Peak to Peak Voltage at Vaux brFFp p the transmitting device 0 4 0 6 y 1 VAUX DIFFp p RX AUX Peak to Peak Voltage at 0 32 1 36 1 Notes eDP COMPs eDP ICOMPI Comp Resistance 24 75 25 25 25 o 2 3 eDP_COMPIO Comp Resistance 24 75 25 25 25 o 2 3 1 Vaux pirrp p 2 lVauxp Vauxul Refer to the VESA DisplayPort Standard specification for more details 2 COMP resistance must be provided on the system board with
144. ignal pair complement DDRS Signals 3 2 are used only for 2 DPC system Clock Enable 1 per rank These signals are used to e Initialize the SDRAMs during power up o SB CKE 3 0 e Power down SDRAM ranks DDR3 Place all SDRAM ranks into and out of self refresh during STR e Signals 3 2 are used only for 2 DPC system Chip Select 1 per rank These signals are used to select particular SDRAM components during the active state There is one Chip Select 5 _ 5 3 0 for each SDRAM rank DDR3 Bits 3 2 are used only for 2 DPC system On Die Termination Active Termination Control SB ODT 3 0 E 3 0 Bits 3 2 are used only for 2 DPC system DDR3 Datasheet Volume 1 87 6 3 Table 6 5 88 Signal Description Memory Reference and Compensation Signals Memory Reference and Compensation 4 Direction iiis iud SM_RCOMP 2 0 System Memory I mpedance Compensation 2 DDR3 DDR3L DDR3L RS Reference Voltage This signal is SM VREF used as a reference voltage to the DDR3 DDR3L DDR3L RS A controller Memory Channel A B DI MM DQ Voltage Reference These output pins are connected to the DIMMs and are programmed to SA DIMM VREFDQ have a reference voltage with optimized margin SB_DIMM_VREFDO The nominal source impedance for these pins is 150 O A The step size is 7 7 mV for DDR3 with no load and 6 99 mV for DDR3L DDR3L RS with no load Reset and Miscellaneous Signals
145. ignals 9 9YYYYY LLY RALL AL EAR ELE AEL LEE 86 6 4 PCI Express based Interface Signals LEA ALLE REAL LEE LEL Y 87 6 5 Embedded DisplayPort eDP Signals menm 87 6 6 Intel Flexible Display Intel FDI Interface 5 87 6 7 Direct Media Interface DMI Signals meme 88 6 8 Phase Lock Loop PLL Signals nemen emen nemen enn 88 6 9 Test Access Points TAP 5 5 ersten poi EN E geed REENEN cs 88 6 10 Error and Thermal Protection Gionals menm 89 6 11 Power Sequencing Signals or reete DAY YAR tes Ne duce ee dae ER da DDAN E RR SEENEN 90 6 12 Processor 5 See Zeie SSES RUN ynn SEENEN haves dE RY RR 91 mENECTITIDESPRLIeR m 91 6 14 Ground and Non Critical to Function NCTF Signals 92 6 15 Processor Internal Pull Up Pull Down Resistors Y ee eee LY me 92 Electrical SPecifiCatI nsS aii ien ER sine CE GR RR RR 93 7 1 Powerand Ground Pins iioi ataqa Ynya RG DO Rd ADN ee deed Red SEN RUE 93 74 2 Decoupling Guidelines i i Ea menta tes ea ce cepe hime dae SEENEN awasqa 93 7 2 1 Voltage Rail Decoupling eege DNK cn nana ne hae ca nea deed 93 7 2 2 PL
146. ing EU Execution Unit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and IA 32 Architectures Software Developer s Manuals for more detailed information HDMI HFM IMC High Definition Multimedia Interface High Frequency Mode Integrated Memory Controller Intel 64 Technology 64 bit memory extensions to the IA 32 architecture Intel Virtualization Technology Datasheet Volume 1 Intel DPST Intel Display Power Saving Technology Intel FDI Intel Flexible Display Interface Intel TXT Intel Trusted Execution Technology Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform 21 Introduction intel Table 1 2 Terminology Sheet 2 of 3 22 Intel virtualization Technology Intel VT for Directed I O Intel VT d is a hardware assist under system software Virtual Machine Manager or operating system control Intel VT d for enabling I O device virtuali
147. inued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type Dir VCC_SENSE VCCIO VCC_VAL_SENSE VCCIO VCCDO VCCIO VCCDO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO_SEL VCCIO VCCIO_SENSE VCCIO VCCPLL VCCIO VCCPLL BC1 PWR VCCIO VCCPLL BB3 PWR VCCIO VCCPOE VCCIO VCCPOE VCCIO VCCSA W20 PWR VCCIO VCCSA V21 PWR VCCIO VCCSA V18 PWR VCCIO VCCSA V17 PWR VCCIO VCCSA V16 PWR VCCIO VCCSA U15 PWR VCCIO VCCSA R21 PWR VCCIO VCCSA R18 PWR VCCIO VCCSA R16 PWR VCCIO VCCSA P20 PWR VCCIO VCCSA P17 PWR VCCIO VCCSA N22 PWR VCCIO AG16 PWR VCCSA N20 PWR 154 Datasheet Volume 1 Processor Pin Signal and Package I nformation Table 8 3 1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type bir VCCSA N16 PWR VSS BG49 GND PWR VCCSA_SENSE PWR GND GND VCCSA_VID 0 VCCSA_VID 1 Analog CMOS CMOS GND GND VDDO PWR PWR GND GND PWR PWR GND GND PWR PWR GND GND PWR PWR GND GND PWR PWR GND GND PWR PWR GND GND PWR PWR PWR PWR GND GND PWR PWR GND GND PWR PWR GND GND PWR PWR GND GND
148. irectional DDR3 Bi directional SA_DQ 63 0 SB_DQ 63 0 SA_DQS 7 0 SA_DQS 7 0 SB_DQS 7 0 SB_DQS 7 0 DDR3 Compensation Analog Bi directional SM_RCOMP 2 0 DDR3 Reference TAP ITP Analog Input SM_VREF Output Input BCLK_ITP BCLK_ITP Single Ended CMOS Input TCK TDI TMS TRST Single Ended Open Drain Output TDO Single Ended Output DBR Asynchronous CMOS Bi BPM 7 0 Single Ended Directional Asynchronous CMOS PREQ Single Ended Input Single Ended Asynchronous CMOS PRDY Control Sideband Input Single Ended CMOS Input CFG 17 0 Asynchronous PROCHOT Single Ended CMOS Open Drain Bi directional Single Ended Asynchronous CMOS THERMTRIP CATERR Output Single Ended Asynchronous CMOS SM_DRAMPWROK UNCOREPWRGOOD PM SYNC RESET Datasheet Volume 1 Electrical Specifications Table 7 3 Note Signal Groups Sheet 2 of 2 Power Ground Other Signal Group Type Signals Single Ended Hi PECI CMOS Input VIDALERT Single Ended Open Drain Output VIDSCLK Bi directional VIDSOUT Voltage Regulator Single Ended CMOS Input VIDALERT Single Ended CMOS Output VCCSA VID 1 0 Single Ended Open Drain Output VIDSCLK Single Ended pud S pen PEN pr Single Ended Analog Output VCCSA SENSE VCC SENSE VSS SENSE VCCIO SENSE VSS SENSE VCCIO Differential Analog Output SENSE VSSAXG SENSE VCC VAL
149. is activated However the processor execution is not ensured between critical temperature and THERMTRIP If the Adaptive Thermal Monitor is triggered and the temperature remains high a critical temperature status and sticky bit are latched in the PACKAGE THERM STATUS MSR 1B1h and also generates a thermal interrupt if enabled For more details on the interrupt mechanism refer to the Intel 64 and IA 32 Architectures Software Developer s Manuals On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption using clock modulation This mechanism is referred to as On Demand mode and is distinct from Adaptive Thermal Monitor and bi directional PROCHOT The processor platforms must not rely on software usage of this mechanism to limit the processor temperature On Demand Mode can be done using processor MSR or chipset I O emulation On Demand Mode may be used in conjunction with the Adaptive Thermal Monitor However if the system software tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode If the I O based and MSR based On Demand modes are in conflict the duty cycle selected by the I O emulation based On Demand mode will take precedence over the MSR based On Demand Mode MSR Based On Demand Mode If Bit 4 of the IA32 CLOCK MODULATION MS
150. is iun eir eit YA A FOA ap A RA 41 3 1 5 Intel Virtualization Technology Intel VT for Directed 1 0 Intel VT d Features Not Supported eene 41 3 2 Intel Trusted Execution Technology Intel Tv 42 3 3 Intel Hyper Threading Technology Intel HT 42 3 4 Intel Turbo Boost Technolog ysu inihi dd 43 3 4 1 Intel8Turbo Boost Technology Frequency SYL nennen 43 3 4 2 Intel Turbo Boost Technology Graphics 44 3 5 Intel Advanced Vector Extensions Intel 44 3 6 Security and Cryptography Technologies 44 3 6 1 Intel Advanced Encryption Standard New Instructions Intel AES NI 44 3 6 2 PCEMULODO InstriictiOD 4 ANEN EEN GAD RE ERE GNAU DA SA O Rn REENEN CN 45 3 6 3 RDRAND Instr ctlori EES Rer eR RRRR REN 45 3 7 Intel 64 Architecture bc 45 3 8 Supervisor Mode Execution Protection SMEP 46 3 9 Power Aware Interrupt Routing PAIR 47 Power Management ue sociis enne RHAG RYAN AUD ARTE HE HUN 49 4 1 Advanced Configuration and Power Interface ACPI States Supported uu u ERE xau Fun akapa GODA RR RA 50 41 1 System States EEN 50 4 1 2 Processor Core Package Idle Gtates enne 50 4 1 3 Integrated M
151. ished with every message The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components Bus speed error checking and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information ss Datasheet Volume 1 Signal Description 6 Signal Description This chapter describes the processor signals They are arranged in functional groups according to their associated interface or category The following notations are used to describe the signal type Notations Signal Type I Input Signal Output Signal Bi directional Input Output Signal The signal description also includes the type of buffer used for the particular signal see Table 6 1 Table 6 1 Signal Description Buffer Types Signal Description PCI Express interface signals These signals are compatible with PCI Express 3 0 PCI Express Signalling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Refer to the PCIe specification Embedded Display Port interface signals These signals are compatible with VESA eDP Revision 1 1a DP specifications and the interface is AC coupled The buffers are not 3 3 V tolerant Intel Flexible Display interface signals These signals are based on PCI Express 2 0 Intel FDI Signaling En
152. itions u SENENNERENENN dada 62 5 1 Intel Turbo Boost Technology Package Power Control Settings a 69 5 2 Configurable Thermal Design Power CTDP Modes mme 71 5 3 Thermal Design Power TDP Specifications YY LY eee eee mmm 73 5 4 Junction Temperature Specification u T EEN EN canes facets ned cus na daa dama eaa ek an wadd 73 5 5 Package Turbo Paramieters a nunt ta pna tal aaa UDA ORUC A ava area pras See ER say rir Re ees 74 5 6 Idle Power Specifications NENNEN EN NENNEN nan RAN EN ENNER E NENNEN NENNEN 75 6 1 Signal Description Buffer 83 6 2 Memory Channel A Gionals ness senes AEL EE LL sns 84 6 3 Memory Channel B SignalS RE EARN RA EN DL S aL qa a Fyw 85 6 4 Memory Reference and Compensation eee 86 6 5 Reset and Miscellaneous Signals 9 YYYY eee ee eee eee LARA HL ALAR ELE EA eene nnns 86 6 6 PCI Express Graphics Interface Signals 87 6 7 Embedded DisplayPort Signals ALL RE LEL AL LEL ALAR ELE eee eee ED LEL nnns 87 6 8 Intel Flexible Display Intel FDI Interface 87 6 9 Direct Media Interface DMI Signals Processor to PCH Serial Interface 88 6 10 Phase Lock Loop PLL
153. l 6 7 Series Chipset Families U J Digital Display x3 VDS Flat Pane Analog CRT SPI SMBUS 2 0 Controller Link 1 8 PCI Express 2 0 x1 Ports 5 GTis GPIO Note 1 USB 30 is supported on the Intel 7 Series Chipset family only 12 Datasheet Volume 1 Introduction intel 1 1 Processor Feature Details Four or two execution cores A 32 KB instruction and 32 KB data first level cache L1 for each core A 256 KB shared instruction data second level cache L2 for each core Up to 8 MB shared instruction data third level cache L3 shared among all cores 1 1 1 Supported Technologies Intel virtualization Technology Intel VT for Directed I O Intel VT d Intel virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Intel Active Management Technology Intel AMT 8 0 Intel Trusted Execution Technology Intel TXT Intel Streaming SIMD Extensions 4 1 Intel SSE4 1 Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 Intel Hyper Threading Technology Intel HT Technology Intel 64 Architecture Execute Disable Bit Intel Turbo Boost Technology Intel Advanced Vector Extensions Intel AVX Intel Advanced Encryption Standard New Instructions Intel AES NI PCLMULODO Instruction RDRAND instruction for random number generation SMEP Supervisor Mode Execution Protection PAIR Power Aware Interrupt Routing 1 2 I
154. l reboot G3 Mechanical off All power AC and battery removed from system Processor Core Package Idle States Processor Core Package State Support State Description CO Active mode processor executing code C1 AutoHALT state CIE AutoHALT state with lowest frequency and voltage operating point C3 Execution cores in C3 flush their L1 instruction cache L1 data cache and L2 cache to the L3 shared cache Clocks are shut off to each core C6 Execution cores in this state save their architectural state before removing core voltage C7 Execution cores in this state behave similarly to the C6 state If all execution cores request C7 L3 cache ways are flushed until it is cleared I ntegrated Memory Controller States I ntegrated Memory Controller States State Description Power up Pre charge Power Down CKE asserted Active mode CKE de asserted not self refresh with all banks closed Active Power Down CKE de asserted not self refresh with minimum one bank active Self Refresh CKE de asserted using device self refresh Datasheet Volume 1 Power Management m 4 1 4 Table 4 4 4 1 5 Table 4 5 4 1 6 Table 4 6 4 1 7 Table 4 7 PCI Express Link States PCI Express Link States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency L1 Lowest Active Power Management
155. lator Protection versus PROCHOT PROCHOT may be used for thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR will cool down as a result of reduced processor power consumption Bi directional PROCHOT can allow VR thermal designs to target thermal design current Iccrpc instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure Overall the system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP Thermal Solution Design and PROCHOT Behavior With a properly designed and characterized thermal solution it is anticipated that PROCHOT will only be asserted for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable However an under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may Cause a noticeable performance loss e Result in prolonged operation at or above the specified maximum junction temperatur
156. ler less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts e More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system Datasheet Volume 1 41 Technologies 3 1 2 Intel Virtualization Technology Intel VT for I A 32 Intel 64 and Intel Architecture Intel VT x Features The processor core supports the following Intel VT x features e Extended Page Tables EPT EPT is hardware assisted page table virtualization It eliminates VM exits from guest operating system to the VMM for shadow page table maintenance e Virtual Processor IDs VPID Ability to assign a VM ID to tag processor core hardware structures such as TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead e Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest operating system after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS guarantees Descriptor Table Exiting Descriptor table exiting allows a VMM to protect a guest operating system from internal malicious software based attack by preventing relocation of key syst
157. lower both IA core and graphics core frequency voltage or both Changes to the temperature can be detected using two programmable thresholds located in the processor thermal MSRs These thresholds have the capability of generating interrupts using the core s local APIC Refer to the Intel 64 and IA 32 Architectures Software Developer s Manuals for specific register and programming details Digital Thermal Sensor Accuracy Taccuracy The error associated with DTS measurement will not exceed 5 C at Tj max The DTS measurement within the entire operating range will meet a 25 C accuracy Fan Speed Control with Digital Thermal Sensor Digital Thermal Sensor based fan speed control Tran is a recommended feature to achieve optimal thermal performance At the Tray temperature Intel recommends full cooling capability well before the DTS reading reaches T An example of this would be TFAN Tj max 10 C PROCHOT Signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature Tj max See Figure 5 2 Frequency and Voltage Ordering on page 79 for a timing diagram of the PROCHOT signal assertion relative to the Adaptive Thermal Response Only a single PROCHOT pin exists at a package level When any core arrives at the TCC activation point the PROCHOT signal will be asserted PROCHOT assertion policies are independent of Adaptive Thermal Monitor enabling B
158. ly mechanical reliability DC_TEST_xx Daisy Chain These signals are for solder joint reliability and BGA Only non critical to function 6 15 Processor Internal Pull Up Pull Down Resistors Table 6 17 Processor Internal Pull Up Pull Down Resistors Signal Name Pull Up Pull Down BPM 7 0 Pull Up PRDY Pull Up 65 1650 PREQ Pull Up 65 165 O TCK Pull Down TDI Pull Up TMS Pull Up TRST Pull Up CFG 17 0 Pull Up VCCIO 5 15 kQ 5 8 94 Datasheet Volume 1 Electrical Specifications t 7 7 1 7 2 Caution 7 2 1 7 2 2 Electrical Specifications Power and Ground Pins The processor has VCC VCCIO VDDQ VCCPLL VCCSA VAXG and VSS ground inputs for on chip power distribution All power pins must be connected to their respective processor power planes while all VSS pins must be connected to the system ground plane Use of multiple power and ground planes is recommended to reduce I R drop The VCC pins and VAXG pins must be supplied with the voltage determined by the processor Serial Voltage I Dentification SVID interface Table 7 4 specifies the voltage level for the various VIDs Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states To keep voltages within specification output decoupling must be properly designed Design the board to
159. m constraints such as system acoustics system skin temperatures and exhaust temperature requirements Thermal specifications given in this chapter are on the component and package level and apply specifically to the processor Operating the processor outside the specified limits may result in permanent damage to the processor and potentially other components in the system Thermal Considerations The processor TDP is the maximum sustained power that should be used for design of the processor thermal solution TDP represents an expected maximum sustained power from realistic applications TDP may be exceeded for short periods of time or if running a power virus workload The processor integrates multiple CPU and graphics cores on a single die This may result in differences in the power distribution across the die and must be considered when designing the thermal solution Intel Boost Technology allows processor cores and processor graphics cores to run faster than the baseline frequency It is invoked opportunistically and automatically as long as the processor is conforming to its temperature power delivery and current specification limits When Intel Turbo Boost Technology is enabled e Applications are expected to run closer to TDP more often as the processor will attempt to maximize performance by taking advantage of available TDP headroom in the processor package e The processor may exceed the TDP for short durations to utilize
160. me Continued by Ball Name Continued Ball Name Ball Buffer Type bir Ball Name Ball Buffer Type bir SA MA 7 BD21 DDR3 SB DQ 12 AV1 DDR3 I O SA_MA 8 BC22 SB DQ 13 AU2 Wis SA MA 9 BB21 DDR3 SB DQ 14 BA2 DDR3 Wis SA MA 10 AW38 SB DQ 15 BB3 Wis SA MA 11 AW22 DDR3 SB DQ 16 BC2 DDR3 1 0 SA_MA 12 BA20 SB DQ 17 BF7 Wis SA MA 13 BB45 DDR3 SB DQ 18 BF11 DDR3 Wis SA MA 14 BE20 SB DQ 19 BJ10 Wis SA MA 15 AW18 DDR3 SB DQ 20 BC4 DDR3 Wis SA ODT 0 BB41 SB DQ 21 BH7 Wis SA_ODT 1 BC46 DDR3 SB DQ 22 BH11 DDR3 Wis SA_RAS BE36 SB 23 BG10 Wis SA WEI BA44 DDR3 SB DQ 24 BJ14 DDR3 I O SB_BS 0 BJ38 SB DQ 25 BG14 Wis SB BS 1 BD37 DDR3 SB DQ 26 BF17 DDR3 Wis SB BS 2 AY29 SB DQ 27 BJ18 Wis SB 54 BH39 DDR3 SB DQ 28 BF13 DDR3 1 0 SB_CKE 0 BD25 SB 29 BH13 Wis SB CKE 1 BJ26 DDR3 SB DQ 30 BH17 DDR3 I O SB_CLK 0 BH33 SB DQ 31 BG18 Wis SB CLKZ 1 BH37 DDR3 SB DQ 32 BH49 DDR3 I O SB_CK 0 BF33 SB DQ 33 BF47 Wis SB CK 1 BF37 DDR3 SB DQ 34 BH53 DDR3 yo SB CS 0 BE40 SB DQ 35 BG50 I O SB_CS 1 BH41 DDR3 SB DQ 36 BF49 DDR3 Wis SB DQ 0 AL4 Wis SB DQ 37 BH47 Wis SB DQ 1 AK3 DDR3 Wis SB DQ 38 BF53 DDR3 I O SB_DQ 2 AP3 Wis SB DQ 39 BJ50 Wis SB_DO 3 AR2 DDR3 Wis SB DQ 40 BF55 DDR3 I O SB_DQ 4 AL2 I O SB_DQ 41 BH55 I O SB DQ 5 AK1 DDR3 Wis SB DQ 42 BJ58 DDR3 Wis SB DQ 6 AP1 Wis SB DQ 43 BH59 Wis SB DQ 7 AR4 DDR3 Wis SB DQ 44 BJ54 D
161. nality reguires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Enhanced Intel SpeedStep Technology See the Processor Spec Finder or contact your Intel representative for more information 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see http www intel com technology security Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functi
162. nch CMOS DC_TEST_C59 C59 N A CFG 0 MOS DC TEST C61 C61 N A CFG 1 DC TEST D1 D1 N A CFG 2 DC_TEST_D3 D3 N A CFG 3 DC_TEST_D61 D61 N A CFG 4 DMI_RX 0 M2 DMI I CFG 5 DMI_RX 1 P6 DMI I CFG 6 DMI_RX 2 P1 DMI I CFG 7 DMI_RX 3 CFG 8 DMI_RX 0 CFG 9 DMI_RX 1 CFG 10 DMI RX 2 P3 DMI I CFG 11 DMI RX 3 CFG 12 DMI_TX 0 13 DMI_TX 1 M8 DMI CFG 14 TX4 2 N4 DMI 15 DMI_TX 3 R2 DMI 16 DMI TX 0 K3 DMI 17 MOS DMI TX 1 M7 DMI DBR Asynch CMOS DMI TX 2 P4 DMI DC TEST A4 A4 N A DMI TX 3 DC TEST A58 A58 N A DPLL_REF_CLK Diff Clk DC TEST A59 A59 N A DPLL REF CLK Diff Clk DC TEST A61 A61 N A eDP_AUX eDP DC_TEST_BD1 BD1 N A eDP_AUX AG4 eDP yo 146 Datasheet Volume 1 Processor Pin Signal and Package I nformation Table 8 3 1023 Processor Ball List Table 8 3 BGA1023 Processor Ball List by Ball Name Continued by Ball Name Continued Ball Name Ball Buffer Type Dir Ball Name Ball Buffer Type bir eDP COMPIO AF3 Analog I PEG RX4 1 J21 PCIe I eDP HPD Asynch CMOS PEG RX eDP ICOMPO eDP_TX 0 Analog PEG_RX PEG_RX PCIe I PCIe I eDP_TX 1 eDP_TX 2 PEG_RX PEG_RX PCIe I PCIe I eDP_TX 3 eDP_TX 0 PEG_RX PEG_RX PCIe I PCIe I eDP TX 1 eDP TX 2 PEG RX PEG RX 10 PCIe I PCIe I eDP TX 3 FDI INT Asynch CMOS PEG RX 11 PEG
163. ndow urbo lime POWER LIMIT 1 TIME in 10 11 Parameter TURBO POWER LIMIT MSR 0610h bits 0001 3 32 14 package 23 17 Long duration Turbo power limit 18 35 Dual Core Long P POWER LIMIT 1 in 14 Ultra package TURBO POWER LIMIT MSR 0610h bits 0 xd a 13 44 14 0 Short duration Turbo power limit 10 14 Short P POWER_LIMIT_2 in 0 1 25X 144 N A W 467 package TURBO POWER LIMIT MSR 0610 bits 17 13 43 46 32 76 Datasheet Volume 1 Thermal Management Table 5 6 Idle Power Specifications Segment Extreme Edition Quad Core SV 45W Dual Core and Quad Core SV 35W Dual Core Ultra 5 6 5 6 1 Idle power in the Package C6 Idle power in the Package C7state Idle power in the Package C6 state Symbol I dle Parameter Min Typ Max Units Notes Idle power in the Package C7state Idle power in the Package C6 state Idle power in the Package C7state Thermal Management Features Thermal management features for the entire processor complex including the processor core the graphics core and integrated memory controller hub will be referred to as processor package or by simply the package Occasionally the package will operate in conditions that exceed its maximum allowable operating temperature This can be due to internal overheating or due to overheating in the entire system To protect processor package and the system from
164. ng time period This is normally aligned to the TDP of the part and steady state cooling capability of the thermal solution This limit may be set lower than TDP real time for specific needs such as responding to a thermal event If set lower than TDP the processor may not be able to honor POWER LIMITI PLL 14 9 SKU TDP this limit for all workloads since this control only applies in the Turbo frequency range a very high powered application may exceed POWER LIMIT 1 even at non Turbo frequencies PL1 limit may be set slightly higher than TDP If set higher than TDP the processor could stay at that power level continuously and cooling solution improvements may be required This value is a time parameter that adjusts the algorithm behavior The exponentially weighted moving average Turbo algorithm will use this parameter to 23 17 maintain time averaged power at or below POWER LIMIT 1 The default value is 1 second but 28 seconds is recommended for most mobile applications POWER LIMIT 1 TIME Turbo Time Parameter Establishes the upper power limit of Turbo operation above TDP primarily for platform power supply considerations Power may exceed this limit for up to 10 ms The default for this limit is 1 25 x nominal TDP POWER LIMIT 2 PL2 46 32 1 25 x TDP Setting this limit to TDP will limit the processor to only operating up to TDP but it does not disable Turbo Because Turbo is opportunistic and power temperature d
165. nnects the processor and the PCH Next generation DMI 2 0 is supported Only DMI x4 configuration is supported DMI Error Flow DMI can only generate SERR in response to errors never SCI SMI MSI PCI INT or GPE Any DMI related SERR activity is associated with Device O Processor PCH Compatibility Assumptions The processor is compatible with the Intel 7 Series Chipset PCH products DMI Link Down The DMI link going down is a fatal unrecoverable error If the DMI data link goes to data link down after the link was up then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption This link behavior is controlled by the PCH Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal No completions from downstream non posted transactions are returned upstream over the DMI link after a link down event Datasheet Volume 1 I nterfaces 2 4 Processor Graphics Controller GT New Graphics Engine Architecture includes 3D compute elements Multi format hardware assisted decode encode pipeline and Mid Level Cache MLC for superior high definition playback video guality and improved 3D performance and Media The Display Engine handles delivering the pixels to the screen and is the primary channel interface for display memory accesses and PCI like traffic in and out Figure 2 6 Processor Graphics Controller
166. ns visual processing recognition data mining synthesis gaming physics cryptography and other application areas The enhancement in Intel AVX allows for improved performance due to wider vectors new extensible syntax and rich functionality including the ability to better manage rearrange and sort data In the processor new instructions were added to allow graphics media and imaging applications to speed up the processing of large amount of data by reducing the memory bandwidth and footprint The new instructions convert operands between single precision floating point values and half precision 16 bit floating point values For more information on Intel AVX see http www intel com software avx Security and Cryptography Technologies I ntel Advanced Encryption Standard New Instructions Intel AES NI The processor supports Intel Advanced Encryption Standard New Instructions Intel AES NI that are a set of Single Instruction Multiple Data SIMD instructions that enable fast and secure data encryption and decryption based on the Advanced Encryption Standard AES Intel AES NI are valuable for a wide range of cryptographic applications for example applications that perform bulk encryption decryption authentication random number generation and authenticated encryption AES is broadly accepted as the standard for both government and industry applications and is widely deployed in various protocols Datasheet Volume 1
167. nterfaces 1 2 1 System Memory Support Datasheet Volume 1 Two channels of DDR3 DDR3L DDR3L RS memory with Unbuffered Small Outline Dual In Line Memory Modules SO DIMM with a maximum of two DIMMs per channel Note 2 DIMMs per channel supported only in Quad Core rPGA package only Single channel and dual channel memory organization modes Data burst length of eight for all memory organization modes System Memory Interface I O Voltage of 1 35 V and 1 5 V DDR3 DDR3L and DDR3L RS DIMMs DRAMs running at 1 5 V DDR3L and DDR3L RS DIMMs DRAMS running at 1 35 V Support memory configurations that mix DDR3 DIMMs DRAMs with DDR3L DDR3L RS DIMMs DRAMs running at 1 5 V 64 bit wide channels Non ECC Unbuffered DDR3 DDR3L DDR3L RS SO DIMMs only Theoretical maximum memory bandwidth of 21 3 GB s in dual channel mode assuming DDR3 1333 MT s 25 6 GB s in dual channel mode assuming DDR3 1600 MT s 13 1 2 2 14 Introduction Processor on die Reference Voltage VREF generation for both DDR3 Read RDVREF and Write VREFDQ 1Gb 2Gb and 4Gb DDR3 DRAM device technologies are supported Using 4Gb DRAM device technologies the largest memory capacity possible is 32 GB assuming Dual Channel Mode with four x8 dual ranked DIMM memory configuration Up to 64 simultaneous open pages 32 per channel assuming 8 ranks of 8 bank devices Command launch modes of 1N 2N On Die Termination ODT Asynchronous ODT In
168. o frequency Low Power Mode Low Power Mode LPM can provide an operation point at lower power than TDP down By combining several active power limiting techniques the processor can consume less power while running at equivalent low frequencies Active power is defined as processor power consumed while a workload is running and does not refer to the power consumed during idle modes of operation LPM is only available using the Intel DPTF driver Through the DPTF driver LPM can be configured to use each of the following methods to reduce active power e Restricting Turbo Boost Power limits and IA core Turbo Boost availability e Off Lining core activity Move processor traffic to a subset of cores e Placing an IA Core at LFM or MFM Minimum Frequency Mode e Utilizing IA clock modulation Off lining core activity is the ability to execute a workload on a limited subset of cores in conjunction with a lower Turbo power limit However not all processor activity is ensured to be able to shift to a subset of cores Shifting a workload to a limited subset of cores allows other cores to remain idle and save power Therefore when LPM is enabled with core offlining less power is consumed at equivalent frequencies Minimum Frequency Mode MFM of operation has been incorporated into the processor to allow clocked frequencies at or below the Low Frequency Mode LFM When MFM is lower than LFM it allows more active power reduction versus LFM D
169. oard with 1 resistors SM RCOMPx resistors are to Vss SM DRAMPWROK must have a maximum of 15 ns rise or fall time over Vppg 0 55 200 mV and the edge must be monotonic SM VREF is defined as Vppo 2 Ron tolerance is preliminary and might be subject to change Control Sideband and TAP Signal Group DC Specifications Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Buffer on Resistance Input Leakage Current Notes 108 Unless otherwise noted all specifications in this table apply all processor frequencies The Vccro referred to in these specifications refers to instantaneous Vccio For Vi between 0 V and Vccro Measured when the driver is tristated and Voy may experience excursions above Vccro However input signal drivers must comply with the signal guality specifications Datasheet Volume 1 Electrical Specifications Table 7 13 Table 7 14 PCI Express DC Specifications Symbol Parameter Min Typ Max Units Notes DC Differential Tx Impedance ZTX DIFF DC Gen 1 Only 80 120 2 DC Differential Tx Impedance Gen2and Gen 3 120 2 ZRX DC DC Common Mode Rx Impedance 40 60 Q 3 4 DC Differential Rx Impedance _ ZRX DIFF DC Gen1 Only 80 120 Q PEG ICOMPO Comp Resistance 25 5 6 PEG ICOMPI Comp Resistance 5 6 PEG RCOMPO Comp Resistance 5 6 Notes GYM OX o F Refer to t
170. ocessor while the Ports reside in the PCH Intel FDI connects the display engine in the processor with the Ports in the PCH The 2D Engine adds a new display pipe C that enables support for three simultaneous and concurrent display configurations Processor Graphics Registers The 2D registers consists of original VGA registers and others to support graphics modes that have color depths resolutions and hardware acceleration features that go beyond the original VGA standard Logical 128 Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows operating systems The 128 bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations The BLT engine can be used for the following Move rectangular blocks of data between memory locations Data alignment To perform logical operations raster ops The rectangular block of data does not change as it is transferred between memory locations The allowable memory transfers are between cacheable system memory and frame buffer memory frame buffer memory and frame buffer memory and within system memory Data to be transferred can consist of regions of memory patterns or solid color fills A pattern is always 8 x 8 pixels wide and may be 8 16 or 32 bits per pixel The BLT engine expands monochrome data into a color depth of 8 16 or 32 bits BLTs can be either opaque or transparent Opaque transfers move
171. ocessors The processor core will scale the operating points such that The voltage will be optimized according to the temperature the core bus ratio and number of cores in deep C states The core power and temperature are reduced while minimizing performance degradation Once the temperature has dropped below the maximum operating temperature operating frequency and voltage transition will go back to the normal system operating point This is illustrated in Figure 5 2 Datasheet Volume 1 Thermal Management intel Figure 5 2 Frequency and Voltage Ordering m Temperature lt Frequency PROCHOT Time Once a target freguency bus ratio is resolved the processor core will transition to the new target automatically On an upward operating point transition the voltage transition precedes the frequency transition On a downward transition the frequency transition precedes the voltage transition When transitioning to a target core operating voltage a new VID code to the voltage regulator is issued The voltage regulator must support dynamic VID steps to support this method During the voltage change e It will be necessary to transition through multiple VID steps to reach the target operating voltage Each step is 5 mV for Intel MVP 7 0 compliant VRs The processor continues to execute instructions However the processor will halt instruction exec
172. omponent package The term processor core refers to Si die itself that can contain multiple execution Processor Core cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the L3 cache Processor Graphics Intel Processor Graphics Rank A unit of DRAM corresponding four to eight devices in parallel ignoring ECC These devices are usually but not always mounted on a single side of a SO DIMM SCI System Control Interrupt Used in ACPI protocol Intel SDRRS Intel Seamless Display Refresh Rate Switching Technology Technology SMEP Supervisor Mode Execution Protection A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have Storage Conditions any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Datasheet Volume 1 Introduction Table 1 2 Terminology Sheet 3 of 3 Term SVID Description Serial Voltage IDentification interface TAC Thermal Averaging Constant TAP TCC Test Access Point Thermal Control Circuit TDC Thermal Design Current TDP
173. on and maintenance The Physical Layer exchanges data with the Data Link Layer in an implementation specific format and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device Datasheet Volume 1 31 intel Interfaces PCI Express Configuration Mechanism The PCI Express external graphics link is mapped through a PCI to PCI bridge structure Figure 2 4 PCI Express Related Register Structures in the Processor 32 PCI PCI Bridge representing PCI Compatible root PCI Host Bridge Express ports Device Device 1 and Device 0 Device 6 DMI PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the Conventional PCI Specification PCI Express configuration space is divided into a PCI compatible region that consists of the first 256 bytes of a logical device s configuration space and an extended PCI Express region that consists of the remaining configuration space The PCI compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section The PCI Express Host Bridge is required to translate the memory mapped PCI Express configuration space accesses from the host processor to PC
174. onality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Active Management Technology requires the computer system to have an Intel AMT enabled chipset network hardware and software as well as connection with a power source and a corporate network connection Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality It may also require modifications of implementation of new business processes With regard to notebooks Intel AMT may not be available or certain capabilities may be limited over a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see http www intel com technology platform technology intel amt Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see http www intel com technology turboboost Intel processor numbers are not a measure of performance Processo
175. or monitoring CMOS processor performance BCLK_ITP These signals are connected in parallel to the top side debug BCLK_ITP probe to enable debug capacities DBR is used only in systems where no debug port is implemented on the system board DBR is used by a debug DBR port interposer so that an in target probe can drive system reset 90 Datasheet Volume 1 Signal Description Table 6 11 Test Access Points TAP Signals Sheet 2 of 2 intel z Sr Direction Signal Name Description Buffer Type PRDY is a processor output used by debug tools to determine 0 PRDY processor debug readiness Asynchronous CMOS PREQ is used by debug tools to request debug operation of the I PREQ processor Asynchronous CMOS Test Clock This signal provides the clock input for the I TCK processor Test Bus also known as the Test Access Port TCK CMOS must be driven low or allowed to float during power on Reset Test Data In This signal transfers serial test data into the I TDI processor TDI provides the serial input needed for JTAG CMOS specification support Test Data Out This signal transfers serial test data out of the o TDO processor TDO provides the serial output needed for JTAG o Drai specification support pem Se TMS Test Mode Select A JTAG specification support signal used by I debug tools CMOS TRST Test Reset This signal resets the Test Access Port TAP logic I TRST must be driven low
176. ort for register based fault recording only for single entry only and support for MSI interrupts for faults Support for both leaf and non leaf caching Support for boot protection of default page table Support for non caching of invalid page table entries Support for hardware based flushing of translated but pending writes and pending reads on IOTLB invalidation Support for page selective IOTLB invalidation MSI cycles MemWr to address FEEx_xxxxh not translated Translation faults result in cycle forwarding to VBIOS region byte enables masked for writes Returned data may be bogus for internal agents PEG DMI interfaces return unsupported request status Interrupt Remapping is supported Queued invalidation is supported VT d translation bypass address range is supported Pass Through Note Intel VI d Technology may not be available on all SKUs 3 1 5 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Features Not Supported The following features are not supported by the processor with Intel VT d Datasheet Volume 1 No support for PCIe endpoint caching ATS No support for Intel VT d read prefetching snarfing that is translations within a cacheline are not stored in an internal buffer for reuse for subsequent translations No support for advance fault reporting No support for super pages No support for Intel VT d translation bypass address range such usage models need to be resolved
177. ory is the lowest supported frequency and slowest supported latency timings of all memory DIMM modules placed in the system as determined through the SPD registers Datasheet Volume 1 Interfaces intel 2 1 5 Technology Enhancements of Intel Fast Memory Access Intel FMA The following sections describe the Just in Time Scheduling Command Overlap and Out of Order Scheduling Intel FMA technology enhancements 2 1 5 1 Just in Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next The most efficient request is picked from all pending requests and issued to system memory Just in Time to make optimal use of Command Overlapping Thus instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time they can be started without interfering with the current request allowing for concurrent issuing of requests This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol 2 1 5 2 Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate Precharge and Read Write commands normally used as long as the inserted commands do not affect the currently executing command Multiple commands can be issued in an overlapping manner in
178. ot populated This is due to the fact that when CKE is tri stated with a SO DIMM present the SO DIMM is not ensured to maintain data integrity SCKE tri state should be enabled by BIOS where appropriate since at reset all rows must be assumed to be populated Datasheet Volume 1 61 intel Power Management 4 3 2 62 DRAM Power Management and I nitialization The processor implements extensive support for power management on the SDRAM interface There are four SDRAM operations associated with the Clock Enable CKE signals that the SDRAM controller supports The processor drives four CKE pins to perform these operations The CKE is one means of power saving When CKE is off the internal DDR clock is disabled and the DDR power is reduced The power saving differs according to the selected mode and the DDR type used For more information refer to the IDD table in the DDR specificaiton The DDR defines 3 levels of power down that differ in power saving and in wakeup time 1 Active power down APD This mode is entered if there are open pages when de asserting CKE In this mode the open pages are retained Power saving in this mode is the lowest Power consumption of DDR is defined by IDD3P Exiting this mode is defined by tXP small number of cycles 2 Precharged power down PPD This mode is entered if all banks in DDR are precharged when de asserting CKE Power saving in this mode is intermediate better than APD but less th
179. play state relevant only when processor graphics is being used as well as memory traffic patterns generated by other connected I O devices When entering the S3 Suspend to RAM STR state or SO conditional self refresh the processor core flushes pending cycles and then enters all SDRAM ranks into self refresh the CKE signals remain LOW so the SDRAM devices perform self refresh Datasheet Volume 1 63 intel The target behavior is to enter self refresh for the package C3 C6 and C7 states as long as there are no memory requests to service Table 4 12 Targeted Memory State Conditions 4 3 2 3 4 3 2 4 4 3 3 64 Power Management Mode Memory State with Processor Graphics Memory State with External Graphics Dynamic memory rank power down based on Dynamic memory rank power down based on CO C1 CIE ai yR idle conditions idle conditions If the processor graphics engine is idle and If there are no memory reguests then enter there are no pending display reguests then self refresh Otherwise use dynamic memory C3 C6 C7 enter self refresh Otherwise use dynamic rank power down based on idle conditions memory rank power down based on idle conditions S3 Self Refresh Mode Self Refresh Mode S4 Memory power down contents lost Memory power down contents lost Dynamic Power Down Operation Dynamic power down of memory is employed during normal operation Based on idle condition
180. processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings This is shown in the VID range values in Table 7 5 The processor provides the ability to operate while transitioning to an adjacent VID and its associated voltage This will represent a DC shift in the loadline Note Transitions above the maximum specified VID are not permitted Table 7 5 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained At condition outside functional operation condition limits neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded on exposure to conditions exceeding the functional operation condition limits The VR used must be capable of regulating its output to the value defined by the new VID values issued DC specifications for dynamic VID transitions are included in Table 7 5 and Table 7 10 Table 7 1 7 Voltage Identification Definition Sheet 1 of 3 VID VID VID VID VID VID VID VID T VID VID VID VID VID VID VID VID y 7 6 5 4 3 2 1 0 MAX 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 00000 1 0 0 0 0 0
181. proximately 1 5 times the Turbo Time Parameter If the power value and or Turbo Time Parameter is changed during runtime it may take a period of time possibly up to approximately 3 to 5 times the Turbo Time Parameter depending on the magnitude of the change and other factors for the algorithm to settle at the new control limits There is an individual Turbo Time parameter associated with Package Power Control and another associated with each power plane Configurable Thermal Design Power cTDP and Low Power Mode LPM Configurable TDP cTDP and Low Power Mode LPM form a new design vector where the processor s behavior and package TDP are dynamically adjusted to a desired system performance and power envelope Configurable TDP and Low Power Mode technologies are not battery life improvement technologies but they offer new opportunities to differentiate system design while running active workloads using Intel s premium processor products through scalability configurability and adaptability The scenarios or methods by which each technology is used are customizable but typically involve changes to TDP with a resultant change in performance depending on system s usage Either technology can be triggered by but are not limited to changes in operating system power policies or hardware events such as docking a system flipping a switch or pressing a button cTDP and LPM are designed to be configured dynamically and do not require an opera
182. pts The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the x2APIC mode To benefit from x2APIC capabilities a new operating system and a new BIOS are both needed with special support for the x2APIC mode The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations Intel x2APIC technology may not be available on all SKUs For more information refer to the Intel 64 Architecture x2APIC specification at http www intel com products processor manuals Supervisor Mode Execution Protection SMEP The processor introduces a new mechanism that provides next level of system protection by blocking malicious software attacks from user mode code when the system is running in the highest privilege level This technology helps to protect from virus attacks and unwanted code to harm the system For more information please refer to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A see Section 1 8 Related Documents on page 24 Datasheet Volume 1 Technologies intel 3 9 Power Aware Interrupt Routing PAIR The processor added enhanced power performance technology which routes interrupts to threads or cores based on their sleep states For example concerning energy savings it routes the interrupt to the active cores without waking the deep idle cores For Performance it ro
183. r numbers differentiate features within each processor family not across different processor families See www intel com products processor number for details Intel Intel Core Pentium Celeron and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2013 Intel Corporation All rights reserved 2 Datasheet Volume 1 Contents 1 PNTOGDUCTION ep 9 1 1 Processor Feat re Details eec tes e e adwn ywy Y FY ck ud nete x Da sx daa dE cx ee de adie 11 1 1 1 Supported Technologies u inrer nsn ia aa Ee ER ue 11 etre der eH da senna cages SER o X ERA E DA EE Ne bon PR ERR wk NAU 11 1 2 1 System Memory Support negro pog gege qaa 11 12 2 PGCEBXDIreSS LTEM 12 1 2 3 Direct Media Interface DMI uu u aaa SEENEN ERR 13 1 2 4 Platform Environment Control Interface 14 1 2 5 Processor GraphiCS de n Ep ad Eege 14 1 2 6 Embedded DisplayPort ef 15 1 2 7 Intel Flexible Display Interface Intel EDIT 15 1 5 ower Management Support ene nones dee E 15 1 3L PFOCESSOR E T 15 19 5 E 15 1 3 3 Memory Controller a DR RARE ERR ERAN 15 1 3 4 PGLEXpressS Ea Sg Sege ta GRH GY RR
184. rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type bir Pin Name Pin Buffer Type bir RSVD AK32 sacku vio DDR o RSVD AK2 SACS O AK3 55535 O RSVD AJ32 sAG1 n AL3 DBS O RSVD J27 SADIMMVREFDO Analog O RSVD AJ26 _ 5 cS DBS yo RSVD NCTF AT34 sapqi D DDR yo RSVD NCTF B35 san02 o3 DBS Yo RSVD NCTF B34 sapqi3 DDR yo RSVD NCTF A34 pe DBS yo RSVD NCTF A33 sAD05 ce DDR yo RSVD NCTF AT33 6 c2 bors yo RSVD NCTF AT2 sapq7 bors yo RSVD NCTF ATi sADQ I8 FO DR IO RSVD NCTF AR35 saADpq p DDR IO RsvbNCTF AR4 sapqio Ten DDR yo RSVD NCTF AR1 sapqii DDR Yo RSVD NCTF AP35 sapq i2 DDR yo RSVD NCTF C35 SADQ13 F DBS yo SA CKE 2 Wa DDR3 saua G8 DDR yo SA CKE 3 W10 DDR3 SA DQ 15 G7 DDR3 1 0 SA_CLK 2 AA4 DDR3 SA DQ 16 K4 DDR3 1 0 SA_CLK 3 AA3 DDR3 SA DQ 17 K5 DDR3 1 0 SA_CK 2 AB4 DDR3 SA DQ 18 Ki DDR3 1 0 SA_CK 3 AB3 DDR3 SA DQ 19 11 DDR3 I O SA CS 2 AG1 DDR3 SA DQ 20 J5 DDR3 1 0 SA_CS 3 AH1 DDR3 SA DQ 21 J4 DDR3 I O SA ODT 2 AG2 DDR3 SA 22 J2 DDR3 7 SA ODT 3 AH2 DDR3 SA DQI 23 K2 DDR3 I O SB_CKE 2 T9 DDR3 SA DQ 24 M8 DDR3 1
185. ration Retry status PCI Express reference clock is 100 MHz differential clock Power Management Event PME functions Dynamic width capability Message Signaled Interrupt MSI and MSI X messages Polarity inversion Static lane numbering reversal Does not support dynamic lane reversal as defined optional by the PCI Express Base Specification Supports Half Swing low power low voltage mode Note The processor does not support PCI Express Hot Plug 1 2 3 Direct Media Interface DMI Datasheet Volume 1 DMI 2 0 support Four lanes in each direction 5 GT s point to point DMI interface to PCH is supported Raw bit rate on the data pins of 5 0 Gb s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface Does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 2 GB s in each direction simultaneously for an aggregate of 4 GB s when DMI x4 Shares 100 MHz PCI Express reference clock 15 1 2 4 1 2 5 16 Introduction 64 bit downstream address format however the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be
186. rchical PCI compliant configuration mechanism for downstream devices Traditional PCI style traffic asynchronous snooped PCI ordering Datasheet Volume 1 Introduction intel PCI Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space The remaining portion of the fixed 4 KB block of memory mapped space above that starting at 100h is known as extended configuration space PCI Express Enhanced Access Mechanism Accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Traditional AGP style traffic asynchronous non snooped PCI X Relaxed ordering Peer segment destination posted write traffic no peer to peer read traffic in Virtual Channel 0 DMI gt PCI Express Port 0 DMI gt PCI Express Port 1 PCI Express Port 0 gt DMI PCI Express Port 1 gt DMI 64 bit downstream address format however the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format however the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Re issues Configuration cycles that have been previously completed with the Configu
187. rcuit is factory calibrated and is not user configurable The default value is software visible in the TEMPERATURE TARGET 1A2h MSR bits 23 16 The Adaptive Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines The Adaptive Thermal Monitor is not intended as a mechanism to maintain processor TDP The system design should provide a thermal solution that can maintain TDP within its intended usage range Adaptive Thermal Monitor protection is always enabled TCC Activation Offset TCC Activation Offset can be used to activate the TCC at temperatures lower than max It is the preferred thermal protection mechanism for Intel Turbo Boost operation since ACPI passive throttling states will pull the processor out of Turbo mode operation when triggered An offset in degrees Celsius can b e written to TEMPERATURE_TARGET 1A2h MSR bits 27 24 This value will be subtracted from the value found in bits 23 16 The default offset is 0 C where throttling will occur at T max The offset should be set lower than any other protection such as ACPI _PSV trip points Frequency Voltage Control Upon TCC activation the processor core attempts to dynamically reduce processor core power by lowering the frequency and voltage operating point The operating points are automatically calculated by the processor core itself and do not require the BIOS to program them as with previous generations of Intel pr
188. rmat and location of a rectangular region of memory that can be displayed on display output device and delivers that data to a display pipe This is clocked by the Core Display Clock Primary Planes A B and C Planes A B and C are the main display planes and are associated with Pipes A B and C respectively Sprite A B and C Sprite A and Sprite B are planes optimized for video decode and are associated with Planes A and B respectively Sprite A and B are also double buffered Cursors A B and C Cursors A and B are small fixed sized planes dedicated for mouse cursor acceleration and are associated with Planes A and B respectively These planes support resolutions up to 256 x 256 each Video Graphics Array VGA VGA is used for boot safe mode legacy games and so on It can be changed by an application without operating system driver notification due to legacy requirements Datasheet Volume 1 I nterfaces 2 4 2 2 2 4 2 3 2 4 2 4 2 4 3 Display Pipes The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed The display pipes A B and C operate independently of each other at the rate of 1 pixel per clock They can attach to any of the display ports Each pipe sends display data to eDP or to the PCH over the Intel Flexible Display Interface Intel FDI Display Ports The display ports
189. rocessor VCCSA VID 1 0 VCCIO_SEL B Game PROC SELECT 3G Core 0 Need to be disconnected 2G Core 4 To use same Voltage 3G Core 0 Selected DMI VCCSA VID O VCCSA VID 1 Dura poop y termination Notes 1 2G Core 2nd Generation Intel Core processor family mobile and Intel Celeron processor family mobile 2 3G Core Mobile 3rd Generation Intel Core processor family Mobile Intel Pentium processor family and Mobile I ntel Celeron processor family 20 Datasheet Volume 1 Introduction 1 7 Table 1 2 Terminology Terminology Sheet 1 of 3 Execute Disable Bit Term Description ACPI Advanced Configuration and Power Interface ADB Automatic Display Brightness APD Active Power Down ASPM Active State Power Management BGA Ball Grid Array BLT Block Level Transfer CLTT Closed Loop Thermal Throttling CRT Cathode Ray Tube cTDP Configurable Thermal Design Power DDDR3L RS DDR3L Reduced Standby Power DDR3 Third generation Double Data Rate SDRAM memory technology DDR3L DDR3 Low Voltage DMA Direct Memory Access DMI Direct Media Interface DP DisplayPort DPST Display Power Savings Technology DTS Digital Thermal Sensor EC Embedded Controller ECC Error Correction Code eDP Embedded DisplayPort Enhanced Intel Technology that provides power management capabilities to laptops SpeedStep Technology EPG Electrical Power Gat
190. roximately 130 C This is signaled to the system by the THERMTRIP signal Datasheet Volume 1 91 Signal Description intel 6 11 Power Sequencing Signals Table 6 13 Power Sequencing Signals Tem Direction SES Ruiter SM DRAMPWROK Processor Input Connects to PCH I SM DRAMPWROK DRAMPWROK Asynchronous CMOS The processor requires this input signal to be a clean indication that the VccsA Vecio and Vppo power supplies are stable and within specifications This requirement applies regardless of the S state of the processor Clean implies that I UNCOREPWRGOOD the signal will remain low capable of sinking leakage current Asynchronous without glitches from the time that the power supplies are CMOS turned on until they come within specification The signal must then transition monotonically to a high state This is connected to the PCH PROCPWRGD signal SKTOCC Socket Occupied PROC DETECT Processor SKTOCC rPGA only Detect This signal is pulled down directly 0 Ohms on the PROC DETECT BGA processor package to the ground There is no connection to the processor silicon for this signal System board designers may use this signal to determine if the processor is present Processor Select This signal is an output that indicates if the processor used is 2nd Generation Intel Core processor family mobile or Mobile 3rd Generation Intel Core processor
191. s a given memory rank may be powered down The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state The processor core controller can be configured to put the devices in active power down CKE de assertion with open pages or precharge power down CKE de assertion with all pages closed Precharge power down provides greater power savings but has a bigger performance impact since all pages will first be closed before putting the devices in power down mode If dynamic power down is enabled all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh DRAM 1 O Power Management Unused signals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused memory channel Clocks can be controlled on a per SO DIMM basis Exceptions are made for per SO DIMM control signals such as CS CKE and ODT for unpopulated SO DIMM slots The I O buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should be disabled and any DLL circuitry related ONLY to unused signals should be disabled The input path must be gated to prevent spurious results due to noise on the unused signals typically handled automatically when input receiver is disabled DDR Electrical Power Gating EPG The DDR I O of the processor supports on die Electrical Power G
192. s as implemented by the following processor C states CO C1 C1E C3 C6 C7 e Enhanced Intel SpeedStep Technology 1 3 2 System 50 S3 S4 S5 1 3 3 Memory Controller e Conditional self refresh Intel Rapid Memory Power Management Intel RMPM Dynamic power down 1 3 4 PCI Express e LOs and L1 ASPM power management capability 1 3 9 Direct Media Interface DMI e LOs and L1 ASPM power management capability Datasheet Volume 1 17 Introduction intel 1 3 6 Processor Graphics Controller GT e Intel Rapid Memory Power Management Intel RMPM CxSR e Intel Graphics Performance Modulation Technology Intel GPMT e Intel Smart 2D Display Technology Intel S2DDT Graphics Render C State RC6 Intel Seamless Display Refresh Rate Switching with eDP port 1 3 7 Thermal Management Support Digital Thermal Sensor Intel Adaptive Thermal Monitor THERMTRIP and PROCHOT support On Demand Mode Open and Closed Loop Throttling Memory Thermal Throttling e External Thermal Sensor TS on DIMM and TS on Board e Render Thermal Throttling Fan speed control with DTS 1 4 Processor Family SKU Definition Table 1 1 Mobile 3rd Generation Intel Core Processor Family Mobile Intel Pentium Processor Family and Mobile Intel Celeron Processor Family SKUs Sheet 1 of 2 Gu IA Frequency Range GT Frequency Range Frequency 17 3940
193. s from the VID employed by the processor during a power or thermal management event Intel Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 3 The voltage specification requirements are measured across VCC SENSE and VSS SENSE pins at the socket with a 20 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 Processor core VR to be designed to electrically support this current 5 Processor core VR to be designed to thermally support this current indefinitely 6 This specification assumes that Intel Turbo Boost Technology is enabled 7 Longterm reliability cannot be assured if tolerance ripple and core noise parameters are violated 8 Long term reliability cannot be assured in conditions above or below Max Min functional limits 9 PSx refers to the voltage regulator power state as set by the SVID protocol 10 Refer to Configurable TDP in Chapter 5 Thermal Management for TDP Up and TDP Down definition 104 Datasheet Volume 1 Electrical Specifications Table 7 6 Table 7 7 Table 7 8 Datasheet Volume 1 intel Processor Uncore Vccio Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Voltage for the memory controller and V shared cache defined at the _
194. s workload demand as permitted by the processor turbo control The processors can optimize both processor and integrated graphics performance through power sharing The processor cores and the integrated graphics core share a package power limit If the graphics core is not consuming enough power to reach the package power limit the cores can increase frequency to take advantage of the unused thermal power headroom The opposite can happen when the processor cores are not consuming enough power to reach the package power limit For the integrated graphics this could mean an increase in the render core frequency above its rated frequency and increased graphics performance Both the processor core s and the graphics render core can increase frequency higher than possible without power sharing The processor Utilization of turbo graphic frequencies requires that the Intel Graphics driver to be properly installed Turbo graphic frequencies are not dependent on the operating system processor P state requests and may turbo while the processor is in any processor P states I ntel Advanced Vector Extensions Intel AVX Intel Advanced Vector Extensions Intel AVX is the latest expansion of the Intel instruction set It extends the Intel Streaming SIMD Extensions Intel SSE from 128 bit vectors to 256 bit vectors Intel AVX addresses the continued need for vector floating point performance in mainstream scientific and engineering numerical applicatio
195. sition is in progress the new transition is deferred until the previous transition is completed e The processor controls voltage ramp rates internally to ensure glitch free transitions Because there is low transition latency between P states a significant number of transitions per second are possible Datasheet Volume 1 Power Management intel 4 2 2 Low Power Idle States When the processor is idle low power idle states C states are used to save power More power savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Resolution of C states occur at the thread processor core and processor package level Thread level C states are available if Intel HT Technology is enabled Caution Long term reliability cannot be assured unless all the Low Power Idle States are enabled Figure 4 2 Idle Power Management Breakdown of the Processor Cores Thread O Thread 1 Thread O 1 Core 0 State Core 1 State Processor Package State Entry and exit of the C States at the thread and core level are shown in Figure 4 3 Figure 4 3 Thread and Core C State Entry and Exit 0 Eh lt MWAIT C1 HLT SS ks i r CPU MWAIT C7 P_LVL4 I 0 Read MWAIT CT MWAITIC6 P LVL2 1 0 Read 1 Y 1 L tie Ee Wide n EGO While individual threads can requ
196. sor Compatibility Diagram nemen LEL NEN nens 18 2 1 Intel Flex Memory Technology Operation 26 2 2 PCLExpress Layering gt ae FARN YRR EON RH RWY NUW O NEEN ORAU ge wasa 28 2 3 Packet Flow Through the Layers uuu a NEEN RENE NENNEN NENNEN AER 29 2 4 PCI Express Related Register Structures in the 30 2 5 PCI Express Typical Operation 16 Lanes 31 2 6 Processor Graphics Controller Unit Block Diagram sss 33 2 7 Processor Display Block Diagramm 36 4 1 Processor Power St tes iiec bessere EE ge DN 49 4 2 Idle Power Management Breakdown of the Processor Cores 53 4 3 Thread and Core C State Entry and Est 53 4 4 Package C State Entry and Exit iei eie RHO Y EE RR DRWY EE rae Dra ada ga sense Das RR RR 57 5 1 Package Power ContfOl a i tee AA SE de duda cei Ee EEN dae rad Edad e deeg dee 69 5 2 Frequency and Voltage Ordering YY YL YHA eee payaa emen 77 7 1 Example for Host Clients Connection LY LARA EAR eee eee nnne 108 7 2 Input Device Hysteresis eiie is a EP ek D iu a 109 8 1 rPGA988B Socket G2 Pin Map 111 8 2 BGA1224 Ballmap left sid amp uei i rich nen pena een geg geed B
197. specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries Refer to Figure 2 2 for the PCI Express layering diagram PCI Express Layering Diagram Transaction Transaction Data Link Data Link Physical Physical Logical Sub block Logical Sub block Electrical Sub block Electrical Sub block RX TX RX TX Datasheet Volume 1 I nterfaces Figure 2 3 2 2 1 1 2 2 1 2 2 2 1 3 intel PCI Express uses packets to communicate information between components Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component As the transmitted packets flow through the other layers they are extended with additional information necessary to handle packets at those layers At the receiving side the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally for Transaction Layer Packets to the form that can be processed by the Transaction Layer of the receiving device Packet Flow Through the Layers Ww p 1 ume eie L lr I L Transaction Layer _ Jj Data Link Layer Physical Layer Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is th
198. ss than Ref VIDALERT VIDSCLK and VIDSCLK comprise a three signal VIDSOUT serial synchronous interface used to transfer power CMOS I OD O VIDSCLK management information between the processor and the ODO VIDALERT voltage regulator controllers This serial VID interface replaces CMOS I the parallel VID interface on previous processors Voltage selection for VCCSA For the platforms this signal o VCCSA VID 1 must have a pull down resistor to ground The output may be CMOS high or low and may change dynamically Voltage selection for VCCSA For 2nd Generation Intel Core processor family mobile the output will be low i i i O VCCSA VID 011 For Mobile 3rd Generation Intel Core processor family 0 Mobile Intel Pentium processor family Mobile Intel CMOS Celeron processor family the output may be high or low and may change dynamically Note 1 The VCCSA VID can toggle at most once in 500 uS The slew rate of VCCSA VID is 1 V nS 6 13 Sense Signals Table 6 15 Sense Signals Sheet 1 of 2 e Direction Signal Name Description Buffer Type VCC SENSE and VSS SENSE provide an isolated low VCC SENSE impedance connection to the processor core voltage and VSS SENSE ground They can be used to sense or measure voltage near the Analog silicon VAXG SENSE VAXG SENSE and VSSAXG SENSE provide an isolated low VSSAXG SENSE impedance connection to the Vayg voltage and ground They can be used to sense or measure volt
199. ta SA DQ 29 M9 AU14 SA DQ 30 BB14 SA DQ 31 BB17 BE12 DQ26 SA DQ 32 AG6 BA45 SA DQ 33 AG5 AR43 SA DQ 34 AW48 BE52 DQ32 38 SA DO SA DQ 35 AK5 BC48 SA DQ 36 AHS BC45 SA DQ 37 ARAS BE48 DO35 1 A5 AT48 BA52 DQ37 Table 9 1 DDR Data Swizzling DDR Data Swizzling Table Channel A MC Pin BGA1023 BGA1224 Name AJ6 AY48 AY51 DQ34 AJ8 BA49 BC54 DQ45 AK8 AV49 AY53 DQ44 AJ9 BB51 AW54 DQ43 AK9 AY53 AY55 DQ41 AH8 BB49 BD53 DO46 AH9 AU49 BB53 DO47 AL9 BA53 BE56 DO40 AL8 BB55 BA56 DO42 AP11 BA55 BD57 DO52 AN11 AV56 BF61 DQ53 AL12 AP50 BA60 DQ50 AM12 AP53 BB61 DQ51 AM11 AV54 BE60 DQ54 AL11 AT54 BD63 DQ55 AP12 AP56 BB59 DQ48 AN12 AP52 BC58 DQ49 AJ14 AN57 AW58 DO61 AH14 AN53 AY59 D063 l 115 AG56 AL60 DQ59 1 15 AG53 AP61 DQ58 AL14 AN55 AW60 DQ62 1 14 AN52 Ae DQ60 1 A315 AG55 Anso DQ57 SA DQ 63 AH15 AK56 Apen DQ56 Datasheet Volume 1 m DDR Data Swizzling n tel Table 9 2 DDR Data Swizzling Table 9 2 DDR Data Swizzling Table for Package Table for Package Channel B Channel B Pin Ball Ball wc pi Ball Pin Name Number Number Number di Pin Name Number Number Number rPGA BGA1023 BGA1224 Name rPGA BGA1023 BGA1224 SB DQ 38 BF53 ep DQ 39 ep DQ 40 ep DQ 41 SB DQ 42 SB DQ 43 SB DQ 44 SB DQ 45 SB DQ 46 SB DQ 47 SB DQ 48 SB DQ
200. tate and maximize its power savings Upon exit of the package C7 state the L3 cache is not immediately re enabled It re enables once the processor has stayed out of the C6 or C7 state for a preset amount of time Power is saved since this prevents the L3 cache from being re populated only to be immediately flushed again Dynamic L3 Cache Sizing Upon entry into the package C7 state the L3 cache is reduced by N ways until it is completely flushed The number of ways N is dynamically chosen per concurrent C7 entry Similarly upon exit the L3 cache is gradually expanded based on internal heuristics Integrated Memory Controller I MC Power Management The main memory is power managed during normal operation and in low power ACPI Cx states Disabling Unused System Memory Outputs Any System Memory SM interface signal that goes to a memory module connector in which it is not connected to any actual memory devices such as SO DIMM connector is unpopulated or is single sided is tri stated The benefits of disabling unused SM signals are Reduced power consumption Reduced possible overshoot undershoot signal quality issues seen by the processor I O buffer receivers caused by reflections from potentially un terminated transmission lines When a given rank is not populated the corresponding chip select and CKE signals are not driven At reset all rows must be assumed to be populated until it can be proven that they are n
201. tel Fast Memory Access Intel FMA Just in Time Command Scheduling Command Overlap Out of Order Scheduling PCI Express The PCI Express lanes PEG 15 0 TX and RX are fully compliant to the PCI Express Base Specification Revision 3 0 including support for 8 0 GT s transfer speeds PCI Express supported configurations in mobile products Configuration Organization Mobile 1x8 1 Graphics I O 2x4 2 2x8 Graphics I O 3 1x16 Graphics I O The port may negotiate down to narrower widths Support for x16 x8 x4 x2 x1 widths for a single PCI Express mode 2 5 GT s 5 0 GT s and 8 0 GT s PCI Express frequencies are supported Gen1 Raw bit rate on the data pins Gen 2 Raw bit rate on the data pins of 5 0 GT s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 8 GB s in each direction simultaneously for an aggregate of 16 GB s when x16 Gen 2 Gen 3 raw bit rate on the data pins of 8 0 GT s resulting in a real bandwidth per pair of 984 MB s using 128b 130b encoding to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 16 GB s in each direction simultaneously for an aggregate of 32 GB s when x16 Gen 3 Hiera
202. tform cooling that are designed to less than thermal design guidance might experience thermal and performance issues since more applications will tend to run at the maximum power limit for significant periods of time Intel Turbo Boost Technology may not be available on all SKUs Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating core and or render clock frequency when there is sufficient power headroom and the product is within specified temperature and current limits The Intel Turbo Boost Technology feature is designed to increase performance of both multi threaded and single threaded workloads The processor supports a Turbo mode where the processor can use the thermal capacity associated with the package and run at power levels higher than TDP power for short durations This improves the system responsiveness for short bursty usage conditions The turbo feature needs to be properly enabled by BIOS for the processor to operate with maximum performance Since the turbo feature is configurable and dependent on many platform design limits outside of the processor control the maximum performance cannot be ensured Turbo Mode availability is independent of the number of active cores however the Turbo Mode frequency is dynamic and dependent on the instantaneous application power load the number of active cores user configurable settings operating environm
203. the data specified to the destination Transparent transfers compare destination color to source color and write according to the mode of transparency selected Data is horizontally and vertically aligned at the destination If the destination for the BLT overlaps with the source memory location the BLT engine specifies which area in memory to begin the BLT transfer Hardware is included for all 256 raster operations source pattern and destination defined by Microsoft including transparent BLT The BLT engine has instructions to invoke BLT and stretch BLT operations permitting software to set up instruction buffers and use batch processing The BLT engine can perform hardware clipping during BLTs Datasheet Volume 1 37 Figure 2 7 2 4 2 1 2 4 2 1 1 2 4 2 1 2 2 4 2 1 3 2 4 2 1 4 38 Interfaces Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components e Display Planes e Display Pipes e Embedded DisplayPort and Intel FDI Processor Display Block Diagram Transcoder eDP eDP Tx side eDP Mux Transcoder Memory ME FDI 0 _ Tx side a Outside of Display Transcoder Cross Engine Point Mux FDI 1 Tx side x4 Transcoder Display Planes A display plane is a single displayed surface in memory and contains one image desktop cursor overlay It is the portion of the display hardware logic that defines the fo
204. thermal failure several thermal management features exist to reduce package power consumption and thereby temperature in order to remain within normal operating limits Furthermore the processor supports several methods to reduce memory power Adaptive Thermal Monitor The purpose of the Adaptive Thermal Monitor is to reduce processor core power consumption and temperature until it operates at or below its maximum operating temperature Processor core power reduction is achieved by e Adjusting the operating frequency using the core ratio multiplier and input voltage using the SVID bus Modulating starting and stopping the internal processor core clocks duty cycle The Adaptive Thermal Monitor can be activated when any package temperature monitored by a digital thermal sensor DTS meets or exceeds its maximum junction temperature specification T max and asserts PROCHOT The assertion of PROCHOT activates the thermal control circuit TCC and causes both the processor core and graphics core to reduce frequency and voltage adaptively The TCC will remain active as long as any package temperature exceeds its specified limit Therefore the Adaptive Thermal Monitor will continue to reduce the package frequency and voltage until the TCC is de activated Datasheet Volume 1 77 intel Thermal Management Note 5 6 1 1 5 6 1 2 78 The temperature at which the Adaptive Thermal Monitor activates the thermal control ci
205. ting system reboot Configurable TDP cTDP Configurable TDP is limited to a subset of Ultra and Extreme Edition parts but is subject to change With cTDP the processor is now capable of altering the TDP power with an alternate ensured frequency Configurable TDP allows operation in situations where extra cooling is available or situations where a cooler and quieter mode of operation is desired Configurable TDP can be enabled using an Intel driver or through Hardware Embedded Controller EC firmware Implementing cTDP using the DPTF driver is recommended as Intel does not provide specific application or Embedded Controller EC source code Datasheet Volume 1 Thermal Management intel Table 5 2 5 4 2 The cTDP consists of three modes as shown in Table 5 2 Configurable Thermal Design Power cTDP Modes Mode Description Nominal This is the processor s rated frequency and TDP When extra cooling is available this mode specifies a higher TDP and higher ensured frequency versus the nominal mode TDP Up When a cooler or quieter mode of operation is desired this mode specifies a lower TDP and TDP Down A lower ensured frequency versus the nominal mode In each mode the Intel Turbo Boost Technology power and frequency ranges are reprogrammed and the operating system is given a new effective HFM operating point The driver assists in all these operations The cTDP mode does not change the maximum Turb
206. tion of platforms based on Intel architecture microprocessors and chipsets Intel virtualization Technology for IA 32 Intel 64 and Intel Architecture Intel VT x added hardware support in the processor to improve the virtualization performance and robustness Intel Virtualization Technology for Directed I O Intel VT d adds chipset hardware implementation to support and improve I O virtualization performance and robustness Intel VT x specifications and functional descriptions are included in the Intel 64 and 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals index htm Other Intel VT documents can be referenced at http www intel com technology virtualization index htm Intel virtualization Technology Intel VT for 32 Intel 64 and Intel Architecture Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of IA platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved reliable virtualized platform By using Intel VT x a VMM is Robust VMMs no longer need to use paravirtualization or binary translation This means that they will be able to run off the shelf operating systems and applications without any special steps Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on IA x86 processors More reliable Due to the hardware support VMMs can now be smal
207. tion units EUs The number of EU engines supported may vary between processor SKUs The processor is offered in a rPGA988B BGA1224 or BGA1023 package The Datasheet provides DC specifications pinout and signal definitions interface functional descriptions thermal specifications and additional feature information pertinent to the implementation and operation of the processor on its respective platform Throughout this document the Mobile 3rd Generation Intel Core processor family Mobile Intel Pentium processor family and Mobile Intel Celeron processor family may be referred to simply as processor Throughout this document the Mobile 3rd Generation Intel Core processor family Mobile Intel Pentium processor family and Mobile Intel Celeron processor family refer to the processors listed in Table 1 1 Throughout this document the Intel 6 7 Series Chipset Platform Controller Hub may be referred to as PCH Some processor features are not available on all platforms Refer to the processor specification update for details The term MBL refers to mobile platforms Datasheet Volume 1 11 Introduction Figure 1 1 Mobile Processor Platform PCI Express 3 0 1 x16 or 2x8 Discrete dde graphics FEM Intel Processor Embedded Display Port DDR3 DDR3L DDR3L RS PECI Intel Flexible Display Interface Intel Management V Engine ay Inte
208. us snooping and interrupt latching are active while the TCC is active For the package C7 state PROCHOT may de assert for the duration of the C7 state residency even if the processor enters the idle state operating at the TCC activation temperature The PECI interface is fully operational during all C states and it is expected that the platform continues to manage processor package thermals even during idle states by regularly polling for thermal data over PECI Bi Directional PROCHOT By default the PROCHOT signal is defined as an output only However the signal may be configured as bi directional When configured as a bi directional signal PROCHOT can be used for thermally protecting other platform components should they overheat as well When PROCHOT is driven by an external device e the package will immediately transition to the minimum operation points voltage and frequency supported by the processor and graphics cores This is contrary to the internally generated Adaptive Thermal Monitor response e Clock modulation is not activated Datasheet Volume 1 81 intel Thermal Management Note 5 6 3 2 5 6 3 3 5 6 3 4 82 The TCC will remain active until the system de asserts PROCHOT The processor can be configured to generate an interrupt upon assertion and de assertion of the PROCHOT signal Toggling PROCHOT more than once in 1 5 ms period will result in constant Pn state of the processor Voltage Regu
209. utes the interrupt to the idle C1 cores without interrupting the already heavily loaded cores This enhancement is mostly beneficial for high interrupt scenarios like Gigabit LAN WLAN peripherals and so on ss Datasheet Volume 1 49 50 Technologies Datasheet Volume 1 Power Management intel a Power Management This chapter provides information on the following power management topics e Advanced Configuration and Power Interface ACPI States e Processor Core e Integrated Memory Controller IMC PCI Express e Direct Media Interface DMI e Processor Graphics Controller Figure 4 1 Processor Power States C0 Active mode C1 Auto halt C1E Auto halt low freq low voltage L1 L2 caches flush clocks off C6 save core states before shutdown C7 similar to C6 L3 flush Note Power states availability may vary between the different SKUs Datasheet Volume 1 51 4 1 1 Table 4 1 4 1 2 Table 4 2 4 1 3 Table 4 3 52 Power Management Advanced Configuration and Power I nterface ACPI States Supported The ACPI states supported by the processor are described in this section System States System States State Description 60 50 Full On G1 S3 Cold ME STR Context saved to memory S3 Hot is not supported by the G1 S4 Suspend to Disk STD All power lost except wakeup on PCH G2 S5 Soft off All power lost except wakeup on PCH Tota
210. ution for frequency transitions If a processor load based Enhanced Intel SpeedStep Technology P state transition through MSR write is initiated while the Adaptive Thermal Monitor is active there are two possible outcomes e If the P state target frequency is higher than the processor core optimized target frequency the p state transition will be deferred until the thermal event has been completed e If the P state target frequency is lower than the processor core optimized target frequency the processor will transition to the P state operating point Datasheet Volume 1 79 intel Thermal Management 5 6 1 3 5 6 2 Note Note 80 Clock Modulation If the frequency voltage changes are unable to end an Adaptive Thermal Monitor event the Adaptive Thermal Monitor will utilize clock modulation Clock modulation is done by alternately turning the clocks off and on at a duty cycle ratio between clock on time and total time specific to the processor The duty cycle is adjusted dynamically based on the throttling need and cannot be modified The period of the duty cycle is configured to 32 microseconds when the TCC is active Cycle times are independent of processor frequency A small amount of hysteresis has been included to prevent excessive clock modulation when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis tim
211. vice Hysteresis Vr FZ AG Maximum Vg PECI High Range Minimum Vp Minimum Valid Input Hysteresis Signal Range Maximum Vy Minimum Vy PECI Low Range PECI Ground Datasheet Volume 1 111 112 858 Electrical Specifications Datasheet Volume 1 Processor Pin Signal and Package I nformation L D 8 Processor Pin Signal and Package I nformation 8 1 Processor Pin Assignments Figure 8 1 rPGA988B Socket G2 Pin Map 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AT AR AP LAN AM AL AR LA AR AG L AE AD AC AB Aa LY W LV LU LR LP N LA LEI LK ER LE KA E KX LE LA gt moommorTuAxArZ zUm uc lt S lt B Datasheet Volume 1 113 intel Processor Pin Signal and Package I nformation Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name by Pin Name Continued Pin Name Pin Buffer Type bir Pin Name Pin Buffer Type bir BCLK A28 Diff Clk I DMI TX 3 C21 DMI BCLK A27 Diff Clk I DPLL_REF_CLK A16 Diff Clk I BCLK_ITP AN35 Diff Clk I DPLL REF CLK A15 Diff Clk I BCLK_ITP AM35 Diff Clk I eDP_AUX C15 eDP I O BPM 0 AT28 Asynch CMOS I O eDP_AUX D15 eDP I O BPM 1 AR29 Asynch CMOS I O eDP COMPIO A18 Analog I BPM 2 AR30 Asynch CMOS I
212. vironment AC Specifications 2 7 GT s but are DC coupled The buffers are not 3 3 V tolerant Direct Media Interface signals These signals are compatible with PCI Express 2 0 DMI Signaling Environment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant CMOS CMOS buffers DDR3 DDR3 buffers 1 5 V tolerant DDR3L DDR3L buffers 1 35 V tolerant A Analog reference or output May be used as a threshold voltage or for buffer compensation Ref Voltage reference signal Asynchronous Signal has no timing relationship with any reference clock Note 1 Qualifier for a buffer type Datasheet Volume 1 85 intel 6 1 Table 6 2 86 Signal Description System Memory Interface Signals Memory Channel A Signals Sis suffer Type SA BS 2 0 Bank Select These signals define which banks are selected within 0 BS 2 0 each SDRAM rank DDR3 SA WE Write Enable Control Signal This signal is used with SA_RAS and SA_CAS along with SA_CS to define the SDRAM Commands DDR3 SA RAS RAS Control Signal This signal is used with SA_CAS and SA_WE along with SA_CS to define the SRAM Commands DDR3 SA CAS CAS Control Signal This signal is used with SA_RAS and SA_WE E along with SA_CS to define the SRAM Commands DDR3 Data Strobes SA DQS 7 0 and its complement signal group make SA DQS 7 0 up a differential strobe pair The data is capture
213. vss N29 GND Datasheet Volume 1 123 m 8 n tel Processor Pin Signal and Package Information Table 8 1 rPGA988B Processor Pin List Table 8 1 rPGA988B Processor Pin List by Pin Name Continued by Pin Name Continued Pin Name Pin Buffer Type bir Pin Name Pin Buffer Type bir VSS N33 GND VSS N34 GND VSS N35 GND VSS P2 GND VSS P3 GND VSS P5 GND VSS P6 GND VSS P8 GND VSS P9 GND VSS T26 GND VSS T27 GND VSS T28 GND VSS T29 GND VSS T30 GND VSS T31 GND VSS T32 GND VSS T33 GND VSS T34 GND VSS T35 GND VSS U2 GND VSS U3 GND VSS U5 GND VSS U6 GND VSS U8 GND VSS U9 GND VSS W26 GND VSS W27 GND VSS W28 GND VSS W29 GND VSS W30 GND VSS w31 GND VSS w32 GND VSS w33 GND VSS W34 GND VSS w35 GND VSS Y2 GND VSS Y3 GND VSS Y5 GND VSS Y6 GND VSS Y8 GND VSS Y9 GND VSS SENSE AJ34 Analog VSS SENSE VCCIO A10 Analog 124 Datasheet Volume 1 m Processor Pin Signal and Package I nformation n tel Figure 8 2 BGA1224 Ballmap left side 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 Y w U T R P N M L K J H G F E D 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 Datasheet Volume 1 125 m n tel Processor Pin Signal and Package I nformation Figure 8 3 BGA1224 Ballmap right side 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
214. with VMM help in setting up the page tables correctly 43 intel Technologies 3 3 44 Intel Trusted Execution Technology Intel TXT Intel Trusted Execution Technology Intel TXT defines platform level enhancements that provide the building blocks for creating trusted platforms The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute These extensions enhance two areas The launching of the Measured Launched Environment MLE e The protection of the MLE from potential corruption The enhanced platform provides these launch and control interfaces using Safer Mode Extensions SMX The SMX interface includes the following functions e Measured Verified launch of the MLE e M
215. y the platform e The platform has not granted a request to a package C6 C7 state but has allowed a package C6 state In package C3 state the L3 shared cache is valid Package C6 State A processor enters the package C6 low power state when e At least one core is in the C6 state e The other cores are in a C6 or lower power state and the processor has been granted permission by the platform e The platform has not granted a package C7 request but has allowed a C6 package state In package C6 state all cores have saved their architectural state and have had their core voltages reduced to zero volts The L3 shared cache is still powered and snoopable in this state The processor remains in package C6 state as long as any part of the L3 cache is active Datasheet Volume 1 Power Management 4 2 5 5 4 2 5 6 4 3 4 3 1 Package C7 State The processor enters the package C7 low power state when all cores are in the C7 state and the L3 cache is completely flushed The last core to enter the C7 state begins to shrink the L3 cache by N ways until the entire L3 cache has been emptied This allows further power savings Core break events are handled the same way as in package C3 or C6 However snoops are not sent to the processor in package C7 state because the platform by granting the package C7 state has acknowledged that the processor possesses no snoopable information This allows the processor to remain in this low power s
216. z enabled i3 3130M 35 1200 MHz 2 6 GHz 650 MHz up to 1100 MHz i3 3227U 17 800 MHz 1 9 GHz 350 MHz up to 1100 MHz 2030M 35 1200 MHz 650 MHz up to 1100 MHz 1020M 35 1200 MHz 650 MHz up to 1000 MHz 1037U 17 800 MHz 350 MHz up to 1000 MHz 1000M 35 1200 MHz 1 8 GHz 650 MHz up to 1000 MHz 105 1007U 17 800 MHz 1 5 GHz 350 MHz up to 1000 MHz 105 1 5 Package The processor is available on two packages A 37 5 x 37 5 mm rPGA package rPGA988B A 31 x 24 mm BGA package BGA1023 for dual core processors or BGA1224 for quad core processors Datasheet Volume 1 19 Introduction 1 6 Processor Compatibility The Mobile 3rd Generation Intel Core processor family Mobile Intel Pentium processor family and Mobile Intel Celeron processor family have specific platform requirements that differentiate it from a 2nd Generation Intel Core processor family mobile processor and Intel Celeron processor family mobile Platforms intending to support both processor families need to address the platform compatibility requirements detailed in Figure 1 2 Figure 1 2 Mobile Processor Compatibility Diagram VAXG 2 ph required for some SKUs 2 x 330 HF 2 x 330 UF 1 placeholder DDR3 DDR3 3L PEG AC Decoupling PEG Gen 1 2 100 nF PEG Gen 1 2 3 220 nF 2G Core 1 5V 3G Core 1 5 Vor 1 35 V 2G Core 1 05 V T T 3G Core 1 05V 1 35 V for BGA DC only Mobile P
217. zation Intel VT d also brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d IOV I O Virtualization ISA Industry Standard Architecture This is a legacy computer bus standard for IBM PC compatible computers ITPM Integrated Trusted Platform Module LCD Liquid Crystal Display LFM Low Frequency Mode LPC Low Pin Count LPM Low Power Mode LVDS Low Voltage Differential Signaling A high speed low power data transmission standard used for display connections to LCD panels MSI Message Signaled Interrupt Non Critical to Function NCTF locations are typically redundant ground or non critical NCTF reserved so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality ODT On Die Termination PAIR Power Aware Interrupt Routing Platform Controller Hub The chipset with centralized platform capabilities including the PCH main I O interfaces along with display connectivity audio features power management manageability security and storage features PECI Platform Environment Control Interface PCI Express Graphics External Graphics using PCI Express Architecture A high PEG speed serial interface whose configuration is software compatible with the existing PCI specifications PGA Pin Grid Array PLL Phase Lock Loop PME Power Management Event PPD Precharged Power Down Processor The 64 bit single core or multi core c

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