Samsung MZMPC256HBGJ-00000 solid state drive
Contents
1. Table 5 1 Register Host to Device layout 48bit LBA mode EXT commands NCQ commands Feat FIS Type 27h Device Head i i i Sector Number Reserved 0 Reserved 0 Control Sector Count Reserved 0 Reserved 0 Table 5 2 Register Host to Device layout CHS mode Feat FIS Type 27h Device LBA 27 24 LBA 7 0 Reserved 0 Reserved 0 Control Sector Count Reserved 0 Reserved 0 Table 5 3 Register Host to Device layout 28bit LBA mode SAMSUNG ELECTRONICS 10 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 5 2 2 Device to Host Devic LBA M Features exp BA Mid exp BA Low Reserved 0 Sector Count exp Sector Count Reserved 0 Reserved 0 Reserved 0 Table 5 4 Register Device to Host layout 48bit LBA mode FIS Type 34h Device Head Cylinder High i Sector Number Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Sector Count Reserved 0 Reserved 0 Reserved 02. 32 PECES 32 8 2 3 Partial Slumber to 32 82 3 eoim etoile i Lue Ad ere AR 32 8 2 3 2 Device Initiated 2 C 32 8 24 PHYRDY to Partial SIUmbD6r iioi tient rottura EOE OE aa a eaaa 33 8 2 4 1 Host Initiated for Partlal 33 8 2 4 2 Device Initiated for 33 9 0 SATA Il Optional Feature nici ee Fa e ocean ea aaa theese 34 9 1 Asynchrorio us Sigtiall cue icut reset true etna ERE xu ade tp aeu cu EE Dd n aes EROR ERE RR GRE Ey 34 10 0 Identify 1 EDT RM 35 11 0 Ordering Information a ke oes ec A Eg 37 12 00 Prod ct Gine a eae 37 SAMSUNG ELECTRONICS ie Rev 1 0 550 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 1 0 Genera
3. Table 5 5 Register Device to Host layout CHS mode FIS Type 34h Device LBA 27 24 LBA 7 0 Reserved 0 Reserved 0 Reserved 0 Sector Count Reserved 0 Reserved 0 Table 5 6 Register Device to Host layout 28bit LBA mode SAMSUNG ELECTRONICS 11 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 5 3 Data 2 1 7 7 7 Reserved 0 Reserved 0 Reserved 0 FIS Type 48h N DWORDs of data minimum of DWORD maximum of 2048 DWORDs JE E op Sees tee Table 5 7 Register Data FIS layout 5 4 PIO FIS Type 34h LBA Low LBA Low exp Sector Count Table 5 8 Register Setup layout 48bit LBA mode Read Write Sector EXT FIS Type 34h Device Head i i i Sector Number Reserved 0 Reserved 0 _ STATU Sector Count Table 5 9 PIO Set up layout CHS mode Commands include PIO data transfer SAMSUNG ELECTRONICS 12 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 5 5 DMA Activate Device to Host 2 1 1 7 7 7 3
4. 8 4 0 Electrical Interface Specification MERE REBATE vaa 8 4 1 Serial ATA Interface uae eeepc terrae rto beni Fa e FE Sg End Dna Rp EPA EGER eee RE 8 4 2 ICI 9 5 0 Frame Information Structure FS aiii ioter rito tarte titt etai Panier evita te ESO FTO REIR RP 10 5 1 Register HOSt 10 DEVICE c 10 5 2 Register Device to HOST eei o dte ii quatre Geant avec duree Ghani casta rave a ak RUE 11 GN Ebr epee 12 radere 12 5 5 DMA Activate Device to eterne een nere 13 SB VEST 0 o M 13 5 7 Set Device Bits Device to ia E T BEP HA SOR BER REL EE AEAEE 13 6 0 Shadow Register Block registers 14 0 1 Command Register EE S 14 6 2 Device Control Beglster ERE dp Eh eau RSEN NERA 14 6 21
5. 24 7 3 2 7 Off line data collection capability eseseeeeneenneen mene nennen enne 24 7 3 2 8 5 e ipa 25 1 3 2 9 Error 25 7 3 210 Selt test failure check polht 3 1 mint UE i EORR DECRE SERM goes 25 7 3 2 11 Self test completion time ed Re Yee coda ee 25 7 3 2 12 Data Structure 25 7 3 3 Device Attribute Thresholds data 25 7 3 3 1 Data Structure Revision NUMBER eds cota e eroe ea Po LE EXP RES ai aninda sesbateadisteease 25 7 3 3 2 Individual Thresholds Data 5 26 7 3 3 3 Attribute ID 26 7 3 9 4 Attribute Threshold bici ea Pise ao EAR pon Dee oS banded SERE Pa SU 26 7 3 3 5 Data Structure 26 ES MERE S MEEicu 26 7 35 SMART Eco PER r 2
6. The device is unable to write to its Attribute Values data structure 10h or 40h Table 7 9 SMART Error Codes 8 0 OOB signaling and Phy Power State 8 1 00B signaling 8 1 1 00B signal spacing There shall be three Out Of Band OOB signals used detected by the Phy COMRESET COMINIT and COMWAKE Each burst is followed by idle peri ods at common mode levels having durations as depicted in following Figure and Table The COMWAKE OOB signaling is used to bring the Phy out of a power down state Partial or Slumber COMRESET COMINIT COMWAKE 106 7 ns 320 ns SAMSUNG ELECTRONICS 31 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 8 2 Phy Power State 8 2 1 COMRESET sequence state diagram Host Host Host Device Releases Host On COMRESET COMWAKE Align Host Host Releases Host Host COMRESET Calibrate COMWAKE D102 Data Host TX AN AAAA AAXA Device RX NXXXXXXy y Device TX 27 A AN AXXAXAXA Host RX NYYYVXYXYXXXXXXYY Device Device COMINIT Calibrate Align Device Device Device Releases COMWAKE Data COMINIT 8 2 2 Interface Power States 8 2 2 1 PHYRDY The Phy logic and main PLL are both on and active The interface is synchronized and capable of r
7. SSD
8. Set EN 17 7 21 SECURITY mode default setting ii iiie eh acd a Ede DER ERE NEL Sec pv sede 17 7 2 2 Initial setting of the user 17 7 2 3 SECURITY mode operation from 17 2 4 Password losl itti eb Erster Pt fe be PIED DUI UE E 17 7 3 SMART FEATURE Set BOh oett etae cce rca Huan ee ie pce ke EF os 17 es ESSE 17 7 3 1 1 S M A R T Read Attribute Values subcommand 01 17 7 3 1 2 S M A R T Read Attribute Thresholds subcommand D1h esee 18 7 3 1 3 S M A R T Enable Disable Attribute Autosave subcommand 2 18 7 3 1 4 S M A R T Save Attribute Values subcommand 18 7 3 1 5 S M A R T Execute Off line Immediate subcommand D4h seem 18 7 3 1 6 S M A R T Selective self test routine ince nens Van BE na a Ene cua dpa ot 19 7 3 1 7 S M A R T Read Log Sector subcommand D5h seen nennen rennen 20 7 3 1 8 S M A R T Write Log Sector subcommand 6 n
9. Starting LBA for test span 4 R W 58 65 Ending LBA for test span 4 R W 66 73 Starting LBA for test span 5 R W 74 81 Ending LBA for test span 5 R W 82 337 Reserved Reserved 338 491 Vendor specific Vendor specific 492 499 Current LBA under test Read 500 501 Current span under test Read 502 503 Feature flags R W 504 507 Vendor Specific Vendor specific 508 509 Selective self test pending time R W 510 Reserved Reserved 511 Data structure checksum SAMSUNG ELECTRONICS R W MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPCO32HBCD 00000 1 3 8 Error reporting The following table shows the values returned in the Status and Error Registers when specific error conditions are encountered by a device A S M A R T FUNCTION SET command was received by the device without the required key being loaded into the LBA High and LBA Mid registers A S M A R T FUNCTION SET command was received by the device with a subcommand value in the Features Register that is either invalid or not supported by this device A S M A R T FUNCTION SET command subcommand other than S M A R T ENABLE OPERATIONS 04h was received by the device while the device was in a S M A R T Disabled state The device is unable to read its Attribute Values or Attribute Thresholds data structure 10h or 04h
10. 0 Reserved 0 Reserved 0 Reserved 0 FIS Type 39h Table 5 10 DMA Activate Layout Write DMA Write DMA Queued Service 5 6 DMA Setup 313 2 2 2 2 2 2 2 2 2 2 1 11 1 1 1 4 11 1 9 8 7 6 5 4 3 2 1109 87 6 5 4 32 109 8 7 6 5 4 3 2 Reserved 0 Reserved 0 I D Reserved 0 FIS Type Ath 0 TAG 1 3 Reserved 0 4 DMA Buffer Offset DMA Transfer Count Reserved 0 Table 5 11 DMA Setup layout NCQ Read Write FpDMA Queued 5 7 Set Device Bits Device to Host 3322222 222 2 2 1 11 1 4 1 4 4 1 1 9 8 7 6 5 4 109 8 7 6 5 4 32 10 9 8 7 6 5 4 3 2 R tus Hi R tusLo 2 1 0 Sta i Sta erved 0 FIS Type Ath SActive 31 0 Table 5 12 Set Device Bits layout NCQ Result of Read Write Queued commands SAMSUNG ELECTRONICS 13 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 6 0 Shadow Register Block registers Description 6 1 Command Register This register contains the command code being sent to the device Command execution begins immediately after this register is written All other registers required for the command must be set up before writing the Command Register 6 2 Device Control
11. 3 855015 Figure 2 1 Physical dimension SAMSUNG ELECTRONICS 6 en MZMPC256HBGJ 00000 MZMPC128HBFU 00000 MZMPC064HBDR 00000 MZMPC032HBCD 00000 3 0 Product Specifications 3 1 System Interface and Configuration Burst read write rate is 600 MB sec 6 0 Gb sec e Fully compatible with ATA 7 Standard Partially Complies with ATA ATAPI 8 3 2 System Performance Sequential Read Sector Up to 500MB s Rev 1 0 SSD Sequential Write Sector Up to 90MB s Up to 170MB s Up to 255MB s Up to 260MB s Actual performance may vary depending on use conditions and environment Note 1 Performance measured using OMeter 2008 with queue depth 32 2 Measurements are performed on whole LBA range 3 Write cache enabled 4 1MB sec 1 048 576 bytes sec was used in sequential performance 3 3 Drive Capacity 32 GB 64 GB 128 GB 256 GB 62 533 296 125 045 424 250 069 680 500 118 192 512 Bytes NOTE 1 Megabyte MB 1 Million bytes 1 Gigabyte GB 1 Billion bytes Actual usable capacity may be less due to formatting partitioning operating system applications or otherwise 3 4 Supply Voltage Allowable voltage 3 3V 5 Allowable noise ripple 100 p p or less 3 5 System Power Consumption Active 911mA 3 007W Idle 27mA 0 087W NOTE Active power is measured during execution of Mobilemark 2007 in Windows Idle power is measured on window7 id
12. At the end of the command this register is updated to reflect the current LBA Bits 8 15 When 48 bit addressing commands are used the most recently written content contains LBA Bits 8 15 and the previous content contains Bits 32 39 6 8 Sector Number LBA low Register This register contains Bits 0 7 At the end of the command this register is updated to reflect the current LBA Bits 0 7 When 48 bit commands are used the most recently written content contains LBA Bits 0 7 and the previous content contains Bits 24 31 6 9 Sector Count Register This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the device If the value in the register is set to 0 a count of 256 sectors in 28 bit addressing or 65 536 sectors in 48 bit addressing is specified If the register is zero at command completion the command was successful If not successfully completed the register contains the number of sectors which need to be transferred in order to complete the request The contents of the register are defined otherwise on some commands These definitions are given in the command descriptions 6 10 Status Register This register contains the device status The contents of this register are updated whenever an error occurs and at the completion of each command If the host reads this register when an interrupt is pending it is considered to be the interrupt acknowledge Any
13. Field bit descripto m R 14 63 Device Head R6egister eoo erit iere o POE fe PUER e 14 6 3 1 Field 5 T E 14 6 4 Ertor Reglster PEE UBER HRK FUE ee I EUH NRI IE KNEE UE ETE E PAR PE MERERI ub 14 6 4 1 bit E 14 0 5 Features Registeh va E 15 0 6 Cylinder High LBA High Register occi iuit ro ort rre eno rn Ri iaoa Ce ER wwsdetawitipeeataterwecctaictenee 15 6 7 Cylinder Low EBA Mid Register cient nce HL anne dL cane dedu Tag Ede do aaa 15 0 8 Sector Number low Reglstet Rr x rae 15 0 9 Sector Soins rc 15 6 10 Status REISTE scrion totes ES E Ln FREIE 15 6 10 1 Field DIE 15 7 0 16 1 1 Supported ATA Cornmands irruere aae aede runde 16 72 SECURITY FEATURE
14. Register This register contains the command code being sent to the device Command execution begins immediately after this register is written All other registers required for the command must be set up before writing the Command Register 6 2 1 Field bit description e HOB is defined by the 48bit Address feature set A write to any Command register shall clear the HOB bit to zero SRST is the host software reset bit SRST 1 indicates that the drive is held reset and sets BSY bit in Status register Setting SRST 0 re enables the device e nlEN is the enable bit for the device Assertion of INTRQ to the host When nIEN O and the device is selected by Drice select bit in DEVICE HEAD register device interrupt to the host is enabled When this bit is set the I bit in the Register Host to Device PIO setup Set Device Bits and DMA Set Up will be set whether pending interrup is found or not 6 3 Device Head Register 6 3 1 Field bit description The content of this register shall take effect when written Binary encoded address mode select When L 0 addressing is by CHS mode When L 1 addressing is by LBA mode DEV Device select Cleared to zero selects Device 0 Set to one selects Device HS3 HS2 HS1 HSO Head select bits The HS3 through 50 contain bits 24 27 of the LBA At command completion these bits are updated to reflect the current LBA bits 24 27 6 4 Error Register This register contains
15. pending interrupt is cleared whenever this register is read If BSY 1 no other bits in the register are valid And read write operations of any other register are negated in order to avoid the returning of the contesnts of this register instead of the other registers contents 6 10 1 Field bit description e BSY Busy BSY 1 whenever the device is accessing the registers The host should not read or write any registers when BSY 1 If the host reads any register when BSY 1 the contents of the Status Register will be returned e DRDY Device Ready RDY 1 indicates that the device is capable of responding to a command RDY will be set to 0 during power on until the device is ready to accept a command e DF Device Fault DF 1 indicates that the device has detected a write fault condition DF is set to 0 after the Status Register is read by the host e DSC Device Seek Complete DSC 1 indicates that a seek has completed and the device head is settled over a track DSC is set to 0 by the device just before a seek begins When an error occurs this bit is not changed until the Status Register is read by the host at which time the bit again indicates the current seek complete status When the device enters into or is in Standby mode or Sleep mode this bit is set by device in spite of not spinning up Data Request DRQ 1 indicates that the device is ready to transfer a word or byte of data between the host and the device The host
16. recovery when the host receives an unsolicited COMINIT the host shall issue a COMRESET to the device When a COMRESET is sent to the device in response to an unsolicited COMINIT the host shall set the Status register to 7Fh and shall set all other Shadow Command Block Registers to FFh When the COMINIT is received in response to the COMRESET which is associated with entry into state HP2B HR AwaitNoCOMINIT the Shadow Status register value shall be updated to either FFh or 80h to reflect that a device is attached SAMSUNG ELECTRONICS 34 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 10 0 Identify Device Data General information Obsolete Specific configuration Obsolete Retired Obsolete Reserved for the CompactFlash Association Retired Serial Number ATA string Retired Obsolete Firmware revision ATA string Model number Number of sectors on multiple commands Trusted Computing feature set options Capabilities Capabilities Obsolete Reserved Obsolete Obsolete Obsolete Obsolete Multiple sector setting Total number of user addressable logical sectors for 28 bit commands Multi word DMA transfer Flow control PIO transfer modes supported Minimum Multiword DMA transfer cycle time per word Manufacturer s recommended Multiword DMA transfer cycle time Minimum PIO t
17. should not write the Command register when DRQ 1 e CORR Corrected Data Always 0 e IDX Index IDX 1 once per revolution Since IDX 1 only for a very short time during each revoltion the host may not see it set to 1 even if the host is reading the Status Register continuously Therefore the host should not attempt to use IDX for timing purposes e ERR ERR 1 indicates that an error occurred during execution of the previous command The Error Register should be read to determine the error type The device sets ERR 0 when the next command is received from the host SAMSUNG ELECTRONICS 15 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 MZMPC064HBDR 00000 MZMPC032HBCD 00000 7 0 Command Descriptions 7 1 Supported ATA Commands CHECK POWER MODE E5h 98h SEEK Rev 1 0 SSD 70h DEVICE CONFIGURATION FREEZE LOCK B1h C1h SET FEATURES EFh DEVICE CONFIGURATION IDENTIFY B1h C2h SET MAX ADDRESS F9h 00h DEVICE CONFIGURATION RESTORE B1h COh SET MAX ADDRESS EXT 37h DEVICE CONFIGURATION SET B1h C3h SET MAX FREEZE LOCK F9h 04h DOWNLOAD MICROCODE 92h SET MAX LOCK F9h 02h EXECUTE DEVICE DIAGNOSTIC 90h SET MAX SET PASSWORD F9h 01h FLUSH CACHE E7h SET MAX UNLOCK F9h 03h FLUSH CACHE EXT EAh SET MULTIPLE MODE C6h IDENTIFY DEVICE ECh SLEEP E6h 99h IDLE E3h 97h SMART DISABLE OPERATIONS BOh D9h IDLE IMMEDI
18. specific 506 507 Vendor specific 508 Self test log pointer 509 510 Reserved 511 Data structure checksum Table 7 8 Self test log data structure Note N is 0 through 20 The data structure contains the descriptor of the Self test that the device has performed Each descriptor is 24 bytes long and the self test data structure is capable to contain up to 21 descriptors After 21 descriptors has been recorded the oldest descriptor will be overwritten with the new descriptor The self test log pointer points to the most recent descriptor When there is no descriptor the value is 0 When there are descriptor s the value is 1 through 21 7 3 7 Selective self test log data structure The Selective self test log is a log that may be both written and read by the host This log allows the host to select the parameters for the self test and to monitor the progress of the self test The following table defines the contents of the Selective self test log which is 512 bytes long All multi byte fields shown in these data structures follow the specifications for byte ordering 0 1 Data structure revision R W 2 9 Starting LBA for test span 1 R W 10 17 Ending LBA for test span 1 R W 18 25 Starting LBA for test span 2 R W 26 33 Ending LBA for test span 2 R W 34 41 Starting LBA for test span 3 R W 42 49 Ending LBA for test span 3 R W 50 57
19. the center of module s top ePerformance eShock Host transfer rate 600 MB s Shock 1500G duration 0 5ms Half Sine Wave Sequential Read Up to 500MB s 32 64 128 256GB Vibration 7 800Hz 3 08Grms 30min axis X Y Z Sequential Write Up to 260MB s 256GB Up to 255MB s 128GB Applicable only for cased product Up to 170MB s 64GB Up to 90MB s 32GB Actual performance may vary depending on use conditions and environment 1 500 000 Hours Notes 1 Performance measured using 2008 with queue depth 32 Weight TBD 2 Measurements are performed on whole LBA range 32GB 7g 3 Write cache enabled 64 128 256GB Max 8g 4 1 1 048 576 bytes sec was used in sequential performance eNSSD Functional Block Diagram INAND 8 NAND NAND NAND NAND 8 Serial ATA interface Buffer 6 0Gb s 600MB s Manager 32 Flash HOST Memory NAND Controller 8 m 4 NAND Q ppl em INAND SAMSUNG ELECTRONICS 5 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPCO32HBCD 00000 2 0 Mechanical Specification 2 1 Physical dimensions and Weight Physical dimensions and Weight 32GB Max 7g 32 64 128 256GB 3 75 0 10 29 85 0 15 50 80 0 15 64 128 256GB Max 8g TOP VIEW BOTTOM VIEW SIDE VIEW 00 0 10 MAX1 35 MAX1 40 3 755040
20. the command code being sent to the device Command execution begins immediately after this register is written All other registers required for the command must be set up before writing the Command Register 6 4 1 Field bit description e ICRC Interface CRC Error CRC 1 indicates a CRC error has occurred on the data bus during a Ultra DMA transfer e UNC Uncorrectable Data Error UNC 1 indicates an uncorrectable data error has been encountered e IDNF ID Not Found IDN 1 indicates the requested sector s ID field cound not be found e ABRT Aborted Command ABT 1 indicates the requested command has been aborted due to a device status error or an invalid parameter in an output register TKONF Track 0 Not Found TON 1 indicates track 0 was not found during a Recalibrate command e AMNF Address Mark Not Found When AMN 1 it indicates that the data address mark has not been found after finding the correct ID field for the requested sector SAMSUNG ELECTRONICS 14 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 6 5 Features Register This register is command specific This is used with the Set Features command S M A R T Function Set command 6 6 Cylinder High LBA High Register This register contains Bits 16 23 At the end of the command this register is updated to reflect the current LBA Bits 16 23 6 7 Cylinder Low LBA Mid Register This register contains Bits 8 15
21. 7 IA ESSE Pu dniuicme 27 7 3 5 2 zeit M EE 27 7 35 3 DEVICE SIMON COUPE oio eo eerte dias ce EP nas ach eee 27 7 3 5 4 Error log data SITUCIUFG aed ee eee et pepe eee ee 27 7 35 5 GOMMANG data SIPUCLUEG 3 22 cose su eo DESEE Roo r EC uM EDesd ces ue De E LED TREES 28 1230 6 Error data str cture niece cete ce cei scere eo cea VR ee Dx op a e I dose aco vo do eo Pec eee 29 1 30 StU CLUS Cm 30 7 3 7 Selective self test log data structure nnne antena Lo 30 es Ez dro 31 8 0 signaling and Phy Power State Raine inepto Eua ata aea aine dun 31 P E 31 8 11 SIGNALS PACING rcm 31 8 2 1 a 32 8 21 COMRESET Sequence State dia Gra 32 8 2 2 Interface Power 32 8 2 2 1 PHYRDY 2 cvteeechascteenaumers H 32 82 22
22. ATE E1h 95h SMART ENABLE OPERATIONS BOh D8h INITIALIZE DEVICE PARAMETERS 91h SMART ENABLE DISABLE ATTRIBUTE AUTOSAVE BOh D2h READ BUFFER E4h Enable Disable Auto Offine BOh DBh READ DMA EXT 25h SMART EXECUTE OFF LINE IMMEDIATE BOh D4h READ DMA with Retry C8h SMART READ ATTRIBUTE THRESHOLDS BOh D1h READ DMA without Retry C9h SMART READ DATA BOh DOh READ LOG EXT 2Fh SMART READ LOG BOh D5h READ MULTIPLE C4h SMART RETURN STATUS BOh DAh READ MULTIPLE EXT 29h SMART SAVE ATTRIBUTE VALUES BOh D3h READ NATIVE MAX ADDRESS F8h SMART WRITE LOG BOh D6h READ NATIVE MAX ADDRESS EXT 27h STANDBY E2h 96h READ SECTORS EXT 24h STANDBY IMMEDIATE 94 READ SECTORS with Retry 20h WRITE BUFFER E8 READ SECTORS without Retry 21h WRITE DMA EXT 35 READ VERIFY SECTORS EXT 42h WRITE DMA with Retry CA READ VERIFY SECTORS with Retry 40h WRITE DMA without Retry CB READ VERIFY SECTORS without Retry 41h WRITE LOG EXT 3F SECURITY DISABLE PASSWORD F6h WRITE MULTIPLE C5 SECURITY ERASE PREPARE F3h WRITE MULTIPLE EXT 39 SECURITY ERASE UNIT F4h WRITE SECTORS EXT 34 SECURITY FREEZE LOCK F5h WRITE SECTORS with Retry 30 SECURITY SET PASSWORD F1h WRITE SECTORS without Retry 31 SECURITY UNLOC
23. CS 27 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 7 3 5 5 Command data structure Data format of each command data structure is shown below Content of the Device Control register when the Command register was written Content of the Features Control register when the Command register was written Content of the Sector Count Control register when the Command register was written Content of the LBA Low register when the Command register was written Content of the LBA Mid register when the Command register was written Content of the LBA High register when the Command register was written Content of the Device Head register when the Command register was written Content written to the Command register Timestamp Timestamp Timestamp Timestamp Table 7 6 Command data structure Timestamp shall be the time since power on in milliseconds when command acceptance occurred This timestamp may wrap around SAMSUNG ELECTRONICS 28 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 MZMPC064HBDR 00000 MZMPC032HBCD 00000 7 3 5 6 Error data structure Data format of error data structure is shown below Reserved Rev 1 0 550 Content written to the Error register after command completion occurred Content written to the Sector Count register after command completion occurred Content written to the LBA Low register after com
24. Fh into the LBA Mid register C2h into the LBA High register clears BSY and asserts INTRQ If the device detects a Threshold Exceeded Condition for prefailure attributes the device loads F4h into the LBA Mid register 2Ch into the LBA High reg ister clears BSY and asserts INTRQ Advisory attributes never result in a negative reliability condition 7 3 1 12 S M A RT Enable Disable Automatic Off line subcommand DBh This subcommand enables and disables the optional feature that cause the device to perform the set of off line data collection activities that automatically collect attribute data in an off line mode and then save this data to the device s nonvolatile memory This subcommand may either cause the device to automatically initiate or resume performance of its off line data collection activities or cause the automatic off line data collection feature to be disabled This subcommand also enables and disables the off line read scanning feature that cause the device to perform the entire read scanning with defect real location as the part of the off line data collection activities The Sector Count register shall be set to specify the feature to be enabled or disabled Sector Count Feature Description 00h Disable Automatic Off line F8h Enable Automatic Off line A value of zero written by the host into the device s Sector Count register before issuing this subcommand shall cause the automatic off line data collec tion feature to be disabl
25. Initiated for Partial For Slumber the same sequence applies except PMREQ_PP is replaced with PMREQ_SP and Partial is replaced with Slumber SAMSUNG ELECTRONICS Host to Partial Host TX Device RX Device TX Host RX Device PMACK Device to Partial Host to Partial Host PMACK Host TX Device RX X WI Device TX Host RX Device Partial PMREQ_P Mode Device to Partial 33 Rev 1 0 SSD MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 9 0 SATA II Optional Feature 9 1 Asynchronous Signal Recovery Phys may support asynchronous signal recovery for those applications where the usage model of device insertion into a receptacle does not apply When signal is lost both the host and the device may attempt to recover the signal A host or device shall determine loss of signal as represented by a transition from PHYRDY to PHYRDYn which is associated with entry into states LSI NoCommErr LS2 NoComm within the Link layer Note that negation of PHYRDY does not always constitute a loss of signal Recovery of the signal is associated with exit from state LS2 NoComm If the device attempts to recover the signal before the host by issuing a COMINIT the device shall return its signature following completion of the OOB sequence which included COMINIT If a host supports asynchronous signal
26. K SAMSUNG ELECTRONICS F2h 16 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 7 2 SECURITY FEATURE Set The Security mode features allow the host to implement a securtity password system to prevent unauthorized access to the disk drive 7 2 1 SECURITY mode default setting The NSSD is shipped with master password set to 20h value ASCII blanks and the lock function disabled The system manufacturer dealer may set a new master password by using the SECURITY SET PASSWORD command without enableing the lock func tion 7 2 2 Initial setting of the user password When a user password is set the drive automatically enters lock mode by the next powered on 1 2 3 SECURITY mode operation from power on In locked mode the NSSD rejects media access commands until a SECURITY UNLOCK command is successfully completed 7 2 4 Password lost If the user password is lost and High level security is set the drive does not allow the user to access any data However the drive can be unlocked using the master password If the user password is lost and Maxium security level is set it is impossible to access data However the drive can be unlocked using the ERASE UNIT command with the master password The drive will erase all user data and unlock the drive 7 3 SMART FEATURE Set BOh The SMART Feature Set command provides access to the Attribute Values the Attribute Thresholds and
27. MMEDIATE command with OFh Abort off line test routine in the LBA Low register shall abort Selective self test regardless of where the device is in the execution of the command If a second self test is issued while a selective self test is in progress the selec tive self test is aborted and the newly requested self test is executed SAMSUNG ELECTRONICS 19 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 7 3 1 7 5 Read Log Sector subcommand 051 This command returns the indicated log sector contents to the host Sector count sepcifies the number of sectors to be read from the specified log The log transfferred by the drive shall start at the first sector in the speicified log regardless of the sector count requested Sector nubmer indicates the log sector to be returned as described in the following Table 00h Log directory 01h SMART error log 02h Comprehensive SMART error log 04h 05h Reserved 06h SMART self test log 08h Reserved 09h Selective self test log OAh 7Fh Reserved 80h 9Fh Host vendor specific AOh FFh Reserved RO Log is read only by the host R W Log is read or written by the host VS Log is vendor specific thus read write ability is vendor specific 7 3 1 8 S M A R T Write Log Sector subcommand D6h This command writes 512 bytes of data to the specified log sector The 512 bytes of data are transferred at a c
28. N A N A N A N A A port 1 SATA Differential RX based on SSD N A N A N A N A N A N A A port 1 SATA Differential RX based on SSD N A N A GND Return Current Path GND Return Current Path GND Return Current Path N A N A Reserved No Connect N A N A GND Return Current Path N A N A Reserved No Connect N A N A 3 3V 3 3V Source N A N A GND Return Current Path GND Return Current Path 3 3V 3 3V Source N A N A N A N A N A N A N A N A GND Return Current Path N A N A N A N A Reserved N A N A N A N A N A GND Return Current Path Reserved N A N A N A N A N A B port 1 SATA Differential DA DSS Device Activity Disable Staggered Spin up 3 3V 3 3V Source GND Return Current Path B port 1 SATA Differential Presence Detection Shall be pulled to GND by device GND SAMSUNG ELECTRONICS Return Current Path 3 3V 3 3V Source MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPCO32HBCD 00000 5 0 Frame Information Structure FIS 5 1 Host to Device FIS Type 27h Device i i LBA Low Features exp i i LBA Low exp Control Sector Count Reserved 0 Reserved 0
29. Rev 1 0 Feb 2012 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 MZMPCOGAHBDR 00000 MZMPCO032HBCD 00000 mSATA 6 0Gb s MLC SSD WAND based Solid State Drive SSCS SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS INFORMATION AND SPECIFICATIONS WITHOUT NOTICE Products and specifications discussed herein are for reference purposes only All information discussed herein is provided on an AS 18 basis without warranties of any kind This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics No license of any patent copyright mask work trademark or any other intellectual property right is granted by one party to the other party under this document by implication estoppel or other wise Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply For updates or additional information about Samsung products contact your nearest Samsung office All brand names trademarks and registered trademarks belong to their respective owners 2012 Samsung Electronics Co Ltd All rights reserved SAMSUNG ELECTRONICS 1 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 MZMPC064HBDR 00000 MZMPC032HBCD 00000 Revision Hist
30. Thresholds data structure The following defines the 512 bytes that make up the Attribute Threshold information This data structure is accessed by the host in its entirety using the S M A R T Read Attribute Thresholds All multibyte fields shown in these data structures follow the ATA ATAPI 6 specification for byte ordering that is that the least significant byte occupies the lowest numbered byte address location in the field The sequence of active Attribute Thresholds will appear in the same order as their corresponding Attribute Values 0 1 Data structure revision number 2 361 1st 30th Individual attribute data 362 379 Reserved 380 510 Vendor specific 511 Data structure checksum Table 7 2 Device Attribute Thresholds Data Structure 7 3 3 1 Data Structure Revision Number This value is the same as the value used in the Device Attributes Values Data Structure SAMSUNG ELECTRONICS 25 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPCO32HBCD 00000 1 3 3 2 Individual Thresholds Data Structure The following defines the 12 bytes that make up the information for each Threshold entry in the Device Attribute Thresholds Data Structure Attribute entries in the Individual Threshold Data Structure are in the same order and correspond to the entries in the Individual Attribute Data Structure Attribute ID Number 01h to FFh Attribute Threshold for comparison with Attribute Values fr
31. UNG ELECTRONICS 17 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 7 3 1 2 S M A R T Read Attribute Thresholds subcommand This subcommand returns the device s Attribute Thresholds to the host Upon receipt of the S M A R T Read Attribute Thresholds subcommand from the host the device reads the Attribute Thresholds from the Attribute Threshold sectors and then waits for the host to transfer the 512 bytes of Attribute Thresholds information from the device 7 3 1 3 S M A R T Enable Disable Attribute Autosave subcommand D2h This subcommand enables and disables the attribute auto save feature of the device The S M A R T Enable Disable Attribute Autosave subcommand allows the device to automatically save its updated Attribute Values to the Attribute Data Sector at the timing of the first transition to Active idle mode and after 15 minutes after the last saving of Attribute Values This subcommand causes the auto save feature to be disabled The state of the Attribute Autosave feature either enabled or disabled will be preserved by the device across the power cycle A value of 00h written by the host into the device s Sector Count Register before issuing the S M A R T Enable Disable Attribute Autosave subcom mand will cause this feature to be disabled Disabling this feature does not preclude the device from saving Attribute Values to the Attribute Data sectors during some other no
32. ability 370 Error logging capability 7 1 Reserved 0 1 Device error logging supported 371 Self test failure check point 372 Short self test routine recommended polling time in minutes 373 Extended self test routine recommended polling time in minutes 374 510 Reserved 511 Data structure checksum Table 7 1 Device Attribute Data Structure 1 3 2 1 Data Structure Revision Number The Data Structure Revision Number identifies which version of this data structure is implemented by the device This revision number will be set to 0005h This revision number identifies both the Attribute Value and Attribute Threshold Data structures SAMSUNG ELECTRONICS 22 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 7 3 2 2 Individual Attribute Data Structure The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure 0 Attribute ID number 01 FFh Status flag bit 0 pre failure advisory bit bit 0 0 If attribute value is less than the threshold the drive is in advisory condtion Product life period may expired bit 0 1 If attribut value is less than the threshold the drive is in pre failure condition The drive may have failure 1 2 bit 1 on line data collection bit bit 1 0 Attribute value will be changed during off line data collection operation bit 1 1 Attrib
33. ables S M A R T capabilities and functions clears BSY and asserts INTRQ After receipt of the device of the S M A R T Disable Operations subcommand from the host all other S M A R T subcommands with the exception of S M A R T Enable Operations are disabled and invalid and will be aborted by the device including the S M A R T Disable Operations subcommand returning the error code as specified in Table 7 9 S M A R T Error Codes on page 30 Any Attribute Values accumulated and saved to volatile memory prior to receipt of the S M A R T Disable Operations command will be preserved in the device s Attribute Data Sectors If the device is re enabled these Attribute Values will be updated as needed upon receipt of a S M A R T Read Attribute Values or a S M A R T Save Attribute Values command SAMSUNG ELECTRONICS 20 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 7 3 1 11 S M A R T Return Status subcommand DAh This subcommand is used to communicate the reliability status of the device to the host s request Upon receipt of the S M A R T Return Status subcom mand the device asserts BSY saves any updated Attribute Values to the reserved sector and compares the updated Attribute Values to the Attribute Thresholds If the device does not detect a Threshold Exceeded Condition or detects a Threshold Exceeded Condition but involving attributes are advisory the device loads 4
34. ache Options 220 221 Reserved 222 Transport major version number 223 Transport minor version number 224 233 Reserved for CE ATA 234 Minimum number of 512 byte data blocks per DOWNLOAD MICROCODE command for mode 03h 235 Maximum number of 512 byte data blocks per DOWNLOAD MICROCODE command for mode 03h 236 254 Reserved 255 SAMSUNG ELECTRONICS Integrity word 36 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 MZMPC064HBDR 00000 MZMPC032HBCD 00000 11 0 Ordering Information MZXXXXXXXXXX XXXXX 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 1 Memory M 2 Module Classification Z SSD 3 FormFactor M SATA mSATA 4 Line Up P PM PC Client 2bit MLC 5 SSD CTRL 541 204 01 6 8 SSD Density 032 32GB 064 64GB 128 128GB 256 256GB 9 PKG Voltage BGA 12 0 Product Line up MZMPC256HBGJ 00000 10 Flash Generation 2nd Generation C 4th Generation M 1st Generation B 3rd Generation D 5th Generation 11 12 NAND Density CD 64G DDP 2CE FU 256G ODP 8CE DR 128G QDP 4CE 512G 16CE 13 wo 14 Default 0 15 HW revision 0 No revision 1 1st revision 16 Packing type 0 Bulk 17 18 Customer 00 General MZMPC128HBFU 00000 MZMPCO64HBDR 00000 mSATA SSD MZMPCOS32HBCD 00000 SAMSUNG ELECTRONICS 37 Rev 1 0
35. ds and any errors encountered shall not be reported to the host Instead error locations may be logged for future reallocation If the device is powered down before the off line scan is completed the off line scan shall resume when the device is again powered up From power up the resumption of the scan shall be delayed the time indicated in the Selective self test pending time field in the Selective self test log During this delay time the pending flag shall be set to one and the active flag shall be set to zero in the Selective self test log Once the time expires the active flag shall be set to one and the off line scan shall resume When the entire media has been scanned the off line scan shall terminate both the pending and active flags shall be cleared to zero and the off line data collection status in the SMART READ DATA response shall be set to 02h indicating completion During execution of the Selective self test the self test executions time byte in the Device SMART Data Structure may be updated but the accuracy may not be exact because of the nature of the test span segments For this reason the time to complete off line testing and the self test polling times are not valid Progress through the test spans is indicated in the selective self test log A hardware or software reset shall abort the Selective self test except when the pending bit is set to one in the Selective self test log see 7 3 7 The receipt of a SMART EXECUTE OFF LINE I
36. eceiving and sending data 8 2 2 2 Partial The Phy logic is powered but is in a reduced power state Both signal lines on the interface are at a neutral logic state common mode voltage The exit latency from this state shall be no longer than 10 us 8 2 2 3 Slumber The Phy logic is powered but is in a reduced power state The exit latency from this state shall be no longer than 10 ms 8 2 3 Partial Slumber to PHYRDY 8 2 3 1 Host Initiated The host may initiate a wakeup from the Partial or Slumber states by entering the power on sequence at the Host COMWAKE point in the state machine Calibration and speed negotiation is bypassed since it has already been performed at power on and system performance depends on quick resume latency The device therefore shall transmit ALIGNP primitives at the speed determined at power on 8 2 3 2 Device Initiated The device may initiate a wakeup from the Partial or Slumber states by entering the power on sequence at the Device COMWAKE point in the state machine Calibration and speed negotiation is bypassed since it has already been performed at power on and system performance depends on quick resume latency The device therefore shall transmit ALIGNP primitives at the speed determined at power on SAMSUNG ELECTRONICS 82 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 MZMPC064HBDR 00000 MZMPC032HBCD 00000 8 2 4 PHYRDY to Partial Slumber 8 2 4 1 Host Initiated for Partial 8 2 4 2 Device
37. ed Disabling this feature does not preclude the device from saving attribute values to nonvolatile memory during some other nor mal operation such as during a power on during a power off sequence or during an error recovery sequence A value of F8h written by the host into the device s Sector Count register before issuing this subcommand shall cause the automatic Off line data collec tion feature to be enabled Any other non zero value written by the host into this register before issuing this subcommand is vendor specific and will not change the current Auto matic Off Line Data Collection and Off line Read Scanning status However the device may respond with the error code specified in Table 7 9 S M A R T Error Codes on page 30 SAMSUNG ELECTRONICS 21 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 7 3 2 Device Attribute Data Structure The following defines the 512 bytes that make up the Attribute Value information This data structure is accessed by the host in its entirety using the S M A R T Read Attribute Values subcommand 0 1 Data structure revision number 2 361 1st 30th Individual attribute data 362 Off line data collection status 363 Self test execution status 364 365 Total time in seconds to complete off line data collection activity 366 Vendor Specific 367 Off line data collection capability 368 369 SMART cap
38. ennen 20 7 3 1 9 S M A R T Enable Operations subcommand D685h sess eene nnne 20 7 3 1 10 S M A R T Disable Operations subcommand 9 20 7 3 1 11 S M A R T Return Status subcommand 21 SAMSUNG ELECTRONICS Rev 1 0 550 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 MZMPC064HBDR 00000 MZMPCO032HBCD 00000 7 3 1 12 S M A R T Enable Disable Automatic Off line subcommand 21 7 3 2 Device Attribute Data Structure ii ioc eee dete Feet dened Ee Ea ean aa ad co dece LRL Edna eda 22 7 3 2 1 Data Structure Revision 22 7 3 2 2 Individual Attribute Data 23 7 3 2 3 Off Line Data Collection 24 7 3 2 4 Self test execution 24 7 3 2 5 Total time in seconds to complete off line data collection activity 24 7 3 2 6 Current segnient polnter 1t ep leid peche Hago eed ie De E EET REN TREO eR a2 EUR RUMOR Y SER YER
39. f the routine the device sets the execution result in the Self test execution status byte see Table 7 1 Device Attribute Data Structure on page 23 and ATA registers and then executes the command completion See definitions below Status Set ERR to one when the self test has failed Error Set ABRT to one when the self test has failed LBA Low Set to F4h when the self test has failed LBA High Set to 2Ch when the self test has failed SAMSUNG ELECTRONICS 18 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 7 3 1 6 S M A R T Selective self test routine When the value in the LBA Low register is 4 or 132 the Selective self test routine shall be performed This selftest routine shall include the initial tests per formed by the Extended self test routine plus a selectable read scan The host shall not write the Selective self test log while the execution of a Selective self test command is in progress The user may choose to do read scan only on specific areas of the media To do this user shall set the test spans desired in the Selective self test log and set the flags in the Feature flags field of the Selective self test log to indicate do not perform off line scan In this case the test spans defined shall be read scanned in their entirety The Selective self test log is updated as the self test proceeds indicating test progress When all specified test spans have been completed the test is term
40. inated and the appropriate self test execution status is reported in the SMART READ DATA response depending on the occur rence of errors Figure on page 21 shows an example of a Selective selftest definition with three test spans defined In this example the test terminates when all three test spans have been scanned User LBA space Starting LBA for Starting LBA for Starting LBA for test span 1 test span 2 test span 3 Ending LBA for Ending LBA for Ending LBA for test span 1 test span 2 test span 3 After the scan of the selected spans described above a user may wish to have the rest of media read scanned as an off line scan In this case the user shall set the flag to enable off line scan in addition to the other settings If an error occurs during the scanning of the test spans the error is reported in the self test execution status in the SMART READ DATA response and the off line scan is not executed When the test spans defined have been scanned the device shall then set the offline scan pending and active flags in the Selective self test log to one the span under test to a value greater than five the self test execution status in the SMART READ DATA response to 001 set a value of 03h in the off line data collection status the SMART READ DATA response and shall proceed to do an off line read scan through all areas not included in the test spans This off line read scan shall completed as rapidly as possible no pauses between block rea
41. ine is not implemented 0 Selective self test routine is not implemented 1 Selective self test routine is implemented 7 Reserved 0 SAMSUNG ELECTRONICS 24 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 7 3 2 8 5 Capability This word of bit flags describes the S M A R T capabilities of the device The device will return 03h indicating that the device will save its Attribute Values prior to going into a power saving mode and supports the S M A R T ENABLE DISABLE ATTRIBUTE AUTOSAVE command Bit Definition 0 Pre power mode attribute saving capability If bit 1 the device will save its Attribute Values prior to going into a power saving mode Standby or Sleep mode 1 Attribute auto save capability If bit 1 the device supports the S M A R T ENABLE DISABLE ATTRIBUTE AUTOSAVE command 2 15 Reserved 0 7 3 2 9 Error logging capability Bit Definition 7 1 Reserved 0 0 The Error Logging support bit If bit 1 the device supports the Error Logging 7 3 2 10 Self test Failure check point This byte indicates the section of self test where the device detected a failure 7 3 2 11 Self test completion time These bytes are the minimum time in minutes to complete the self test 1 3 2 12 Data Structure Checksum The Data Structure Checksum is the 2 s compliment of the result of a simple 8 bit addition of the first 511 bytes in the data structure 1 3 3 Device Attribute
42. it commands QWord 102 103 Total Number of User Addressable Logical Sectors for 48 bit commands QWord 104 Streaming Transfer Time PIO 105 Maximum number of 512 byte data blocks of LBA Range Entries per DATA SET MANAGEMENT command 106 Physical sector size logical sector size 107 Inter seek delay for ISO 7779 standard acoustic testing 108 World wide name 109 World wide name 110 World wide name 111 World wide name 112 116 Reserved 117 118 Logical sector size Dword 119 Commands and feature sets supported 120 Commands and feature sets supported or enabled 121 126 Reserved for expanded supported and enabled settings 127 Obsolete 128 Security status 129 159 Vendor specific 160 CFA power mode 161 167 Reserved for the CompactFlash Association 168 Reserved 169 DATA SET MANAGEMENT is supported 170 205 Additional Product Identifier Current media serial number ATA string 206 SCT Command Transport 207 208 Reserved for CE ATA 209 Alignment of logical blocks within a physical block 210 211 Write Read Verify Sector Count Mode 3 212 213 Write Read Verify Sector Count Mode 2 214 NV Cache Capabilities 215 216 NV Cache Size in Logical Blocks DWord 217 Nominal media rotation rate 218 Reserved 219 NV C
43. l Description The NSSD Nand based Solid State Drive of Samsung Electronics fully consists of semiconductor devices using NAND Flash Memory which provide high reliability and high performance for a storage media The NSSD doesn t have any moving parts such as platter disk and head media which provides a better solution in a notebook PC and Tablet PC for a storage device providing higher performance reduced latencies and a low power consumption in a small form factor The NSSD could also provide rug ged features in industrial PC with an extreme environment with a high MTBF For easy adoption the NSSD has the same host interface with Hard Disk Drives and has a same physical dimension eDensity ePower Consumption 32 64 128 256GB is available Active 911mA 3 007W Idle 27mA 0 087W Form Factor Active power is measured during execution of Mobilemark 2007 in Full Mini PCle type Windows7 29 85 0 15 x 50 80 0 15 x 3 75 0 10 mm DIPM enabled value Environment Host interface System Intel Core i5 2540M 2 60Ghz DDR3 4GB Serial ATA interface of 6 0Gbps OS Windows 7 x64 script Autoconfig 2 4 1 Fully complies with ATA ATAPI 7 Standard External 3 3V provided for mSATA Partially Complies with ATA ATAPI 8 Power Saving Modes HIPM DIPM Partial Slumber mode Support NCQ Up to 32 depth Synchronous Signal Recovery eTemperature Operating 0 C to 70 C Measuring at
44. le status with DIPM on Environment System Dell E6420 Intel Core i5 2540M 2 60Ghz DDR3 4GB OS Windows 7 x64 script Autoconfig 2 4 1 DIPM HIPM support SAMSUNG ELECTRONICS MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPC064HBDR 00000 MZMPC032HBCD 00000 3 6 System Reliability 1 MTBF is Mean Time Between Failure As same word annual failure ratio is 0 4 3 7 Environmental Specifications Operating Non Operating 0 C to 70 C 55 C to 95 C 5 to 95 non condensing 7 800 3 08Grms 30min axis X Y Z 1500G duration 0 5ms Half Sine Wave Notes 1 Temperature specification is following JEDEC standard Expressed temperature must be measured right on the case 2 Humidity is measured in non condensing 3 Test condition for shock 0 5ms duration with half sine wave 4 Test condition for vibration 10Hz to 2 000Hz 15mins axis on 3axis 4 0 Electrical Interface Specification 4 1 Serial ATA Interface connector Drive Connector PCle type 52pins Pin are marked as 1 52 in the below dimension lt TOP VIEW gt lt BOTTOM VIEW gt 25 7 2 30 SAMSUNG ELECTRONICS 8 ex MZMPC256HBGJ 00000 MZMPC128HBFU 00000 MZMPC064HBDR 00000 MZMPC032HBCD 00000 4 2 Pin Assignments N A N A GND Rev 1 0 SSD Return Current Path 3 3V 3 3V source N A N A N A N A GND Return Current Path GND Return Current Path
45. lf test routine in either captive or off line mode The LBA Low register shall be set to specify the operation to be executed Execute S M A R T off line data collection routine immediately Execute S M A R T Short self test routine immediately in off line mode Execute S M A R T Extended self test routine immediately in off line mode Reserved Execute S M A R T Selective self test routine immediately in off line mode Reserved Abort off line mode self test routine Execute S M A R T short self test routine immediately in captive mode Execute S M A R T Extended self test routine immediately in captive mode Execute S M A R T selective self test routine immediately in captive mode Reserved Off line mode The device executes command completion before executing the specified routine During execution of the routine the device will not set BSY nor clear DRDY If the device is in the process of performing its routine and is interrupted by a new command from the host the device will abort or suspend its routine and service the host within two seconds after receipt of the new command After servicing the interrupting command the device will resume its routine automatically or not start its routine depending on the interrupting command Captive mode When executing self test in captive mode the device sets BSY to one and executes the specified self test routine after receipt of the command At the end o
46. mand completion occurred Content written to the LBA Mid register after command completion occurred Content written to the LBA High register after command completion occurred Content written to the Device Head register after command completion occurred Content written to the Status register after command completion occurred Extended error information State Life Timestamp least significant byte Life Timestamp most significant byte Table 7 7 Error data structure Extended error information will be vendor specific State field contains a value indicating the device state when command was issued to the device Unknown Sleep x2h Standby x3h Active Idle with BSY cleared to zero x4h Executing SMART off line or self test x5h xAh Reserved xBh xFh Vendor unique The value of x is vendor specific and may be different for each state SAMSUNG ELECTRONICS 29 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 MZMPC064HBDR 00000 MZMPC032HBCD 00000 7 3 6 Self test log structure The following defines the 512 bytes that make up the Self test log sector 0 1 Data structure revision Rev 1 0 550 24 2 Self test number n 24 3 Self test execution status n 24 4 n 24 5 Life timestamp n 24 6 Self test failure check point n 24 7 n 24 10 LBA of first failure n 24 11 n 24 25 Vendor
47. om 00h to FFh always passing threshold value to be used for code test purposes 01h minimum value for normal operation FDh maximum value for normal operation FEh invalid for threshold value FFh always failing threshold value to be used for code test purposes Reserved 00h 1 3 3 3 Attribute ID Numbers Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures 1 3 3 4 Attribute Threshold These values are preset at the factory and are not meant to be changeable However the host might use the S M A R T Write Attribute Threshold sub command to override these preset values in the Threshold sectors 1 3 3 5 Data Structure Checksum The Data Structure Checksum is the 2 s compliment of the result of a simple 8 bit addition of the first 511 bytes in the data structure 7 3 4 S M A R T Log Directory The following defines the 512 bytes that make up the S M A R T Log Directory The S M A R T Log Directory is on S M A R T Log Address zero and is defined as one sector long S M A R T Logging Version Number of sectors in the log at log address 1 Reserved Number of sectors in the log at log address 2 Reserved Number of sectors in the log at log address 255 Reserved Table 7 3 S M A R T Log Directory The value of the S M A R T Logging Version word shall be 01h The logs at log addresses 80 9Fh are defined as 16 sectors l
48. ommand and the LBA Low value shall be set to one The LBA Low shall be set to specify the log sector address If a Rea Only log sector is specified the device returns ABRT error 7 3 1 9 S M A R T Enable Operations subcommand D8h This subcommand enables access to all S M A R T capabilities within the device Prior to receipt of a S M A R T Enable Operations subcommand Attri bute Values are neither monitored nor saved by the device The state of S M A R T either enabled or disabled will be preserved by the device across power cycles Once enabled the receipt of subsequent S M A R T Enable Operations subcommands will not affect any of the Attribute Values Upon receipt of the S M A R T Enable Operations subcommand from the host the device asserts BSY enables S M A R T capabilities and functions clears BSY and asserts INTRQ 7 3 1 10 S M A RT Disable Operations subcommand D9h This subcommand disables all S M A R T capabilities within the device including the device s attribute auto save feature After receipt of this subcom mand the device disables all S M A R T operations Non self preserved Attribute Values will no longer be monitored The state of S M A R T either enabled or disabled is preserved by the device across power cycles Note that this subcommand does not preclude the device s power mode attribute auto saving Upon receipt of the S M A R T Disable Operations subcommand from the host the device asserts BSY dis
49. ong SAMSUNG ELECTRONICS 26 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPCO32HBCD 00000 1 3 5 5 error log sector The following defines the 512 bytes that make up the S M A R T error log sector All multibyte fields shown in these data structures follow the ATA ATAPI 6 specifications for byte ordering 0 S M A R T error log version 1 Error log pointer 2 91 1st error log data structure 92 181 2nd error log data structure 182 271 3rd error log data structure 272 361 4th error log data structure 362 451 5th error log data structure 452 453 Device error count 454 510 Reserved 511 Data structure checksum Table 7 4 S M A R T error log sector 1 3 5 1 5 error log version This value is set to O1h 7 3 5 2 Error log pointer This points to the most recent error log data structure Only values 1 through 5 are valid 1 3 5 3 Device error count This field contains the total number of errors The value will not roll over 7 3 5 4 Error log data structure The data format of each error log structure is shown below n n 11 1st command data structure 12 23 2nd command data structure 24 35 3rd command data structure n 36 n 47 4th command data structure n 48 n 59 5th command data structure n 60 n 89 Error data structure Table 7 5 Error log data structure SAMSUNG ELECTRONI
50. ory Revision No History 0 1 Preliminary version 02 Fixing performance value Modifying SMART attribute info 1 0 Final version SAMSUNG ELECTRONICS Draft Date Oct 24 2011 Dec 02 2011 Feb 15 2012 Rev 1 0 SSD Remark Editor Preliminary Phil LEE Phil LEE Final Taehyun Yoon MZMPC256HBGJ 00000 MZMPC128HBFU 00000 2 064 00000 MZMPCO032HBCD 00000 Table Of Contents 1 0 cht cance E M 5 2 0 Mechanical Speci Cation Mn 6 2 1 Physical dimensions and Weight retiro R r ea Eaa raa 6 3 0 Product Specifications rriren 7 3 1 System Interface and Configuration sessirnir aerae Aae Ta aiara i daN aia ana raar aR 7 3 2 System Performance LA TOR E RV De Ede AA a Ea aaan 7 3 3 DRIVE CAPACI Y M M 7 3 4 Supply Voltage ee eee na eee 7 3 0 System POWer e H 7 RRONES I MERIICIeE C 8 3 7 Environmental
51. other low level subcommands that can be used for logging and reporting purposes and to accommodate special user needs The SMART Feature Set command has several separate subcommands which are selectable via the device s Features Register when the SMART Feature Set command is issued by the host In order to select a subcommand the host must write the subcommand code to the device s Features Register before issuing the SMART Feature Set command 1 3 1 Sub Command In order to select a subcommand the host must write the subcommand code to the device s Features Register before issuing the S M A R T Function Set command The subcommands and their respective codes are listed below SMART READ DATA SMART WRITE LOG SMART READ ATTRIBUTE THRESHOLDS SMART ENABLE OPERATIONS SMART ENABLE DISABLE ATTRIBUTE AUTOSAVE SMART DISABLE OPERATIONS SMART SAVE ATTRIBUTE VALUES SMART RETURN STATUS SMART EXECUTE OFF LINE IMMIDIATE SMART ENABLE DISABLE AUTOMATIC OFF LINE SMART READ LOG 7 3 1 1 S M A R T Read Attribute Values subcommand This subcommand returns the device s Attribute Values to the host Upon receipt of the S M A R T Read Attribute Values subcommand from the host the device asserts BSY saves any updated Attribute Values to the Attribute Data sectors asserts DRQ clears BSY asserts INTRQ and then waits for the host to transfer the 512 bytes of Attribute Value information from the device via the Data Register SAMS
52. ransfer cycle time without flow control Minimum PIO transfer cycle time with IORDY flow control Addtional supported Reserved Queue depth Serial ATA capabilites Reserved for future Serial ATA definition Serial ATA features supported Seral ATA features enabled Major version number Minor version number Commands and feature sets supported Commands and feature sets supported Commands and feature sets supported Commands and feature sets supported or enabled Commands and feature sets supported or enabled Commands and feature sets supported or enabled Ultra DMA transfer SAMSUNG ELECTRONICS 35 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 MZMPCOG4HBDR 00000 MZMPC032HBCD 00000 89 Rev 1 0 SSD Time required for Normal Erase mode SECURITY ERASE UNIT command 90 Time required for an Enhanced Erase mode SECURITY ERASE UNIT command 91 Current advanced power management value 92 Master Password Revision Code 93 Hardware reset result 94 Current automatic acoustic management value 95 Stream Minimum Request Size 96 Streaming Transfer Time DMA 97 Streaming Access Latency DMA and PIO 98 99 Streaming Performance Granularity DWord 100 Total Number of User Addressable Logical Sectors for 48 bit commands QWord 101 Total Number of User Addressable Logical Sectors for 48 b
53. rmal operation such as during a power up or a power down A value of F1h written by the host into the device s Sector Count Register before issuing the S M A R T Enable Disable Attribute Autosave subcom mand uwill cause this feature to be enabled Any other nonzero value written by the host into this register before issuing the S M A R T Enable Disable Attribute Autosave subcommand will not change the current Autosave status The device will respond with the error code specified in Table 7 9 S M A R T Error Codes on page 30 The S M A R T Disable Operations subcommand disables the auto save feature along with the device s S M A R T operations Upon the receipt of the subcommand from the host the device asserts BSY enables or disables the Autosave feature clears BSY and asserts INTRQ 1 3 1 4 S M A R T Save Attribute Values subcommand D3h This subcommand causes the device to immediately save any updated Attribute Values to the device s Attribute Data sector regardless of the state of the Attribute Autosave feature Upon receipt of the S M A R T Save Attribute Values subcommand from the host the device asserts BSY writes any updated Attribute Values to the Attribute Data sector clears BSY and asserts INTRQ 7 3 1 5 S M A R T Execute Off line Immediate subcommand D4h This subcommand causes the device to immediately initiate the set of activities that collect Attribute data in an offline mode off line routine or execute a se
54. self test routine is in progress 7 3 2 5 Total time in seconds to complete off line data collection activity This field tells the host how many seconds the device requires to complete the off line data collection activity 7 3 2 6 Current segment pointer This byte is a counter indicating the next segment to execute as an off line data collection activity Because the number of segments is 1 01h is always returned in this field 7 3 2 7 Off line data collection capability Bit Definition 0 Execute Off line Immediate implemented bit 0 S M A R T Execute Off line Immediate subcommand is not implemented 1 S M A R T Execute Off line Immediate subcommand is implemented 1 Enable disable Automatic Off line implemented bit 0 S M A R T Enable disable Automatic Off line subcommand is not implemented 1 S M A R T Enable disable Automatic Off line subcommand is implemented 2 Abort restart off line by host bit 0 The device will suspend off line data collection activity after an interrupting command and resume it after a vendor specific event 1 The device will abort off line data collection activity upon receipt of a new command Bit Definition 3 Off line Read Scanning implemented bit 0 The device does not support Off line Read Scanning 1 The device supports Off line Read Scanning 4 Self test implemented bit 0 Self test routing is not implemented 1 Self test routine is implemented 5 Reserved 0 6 Selective self test rout
55. ute value will be changed during normal operation bit 2 Performance Attribute bit bit 3 Error rate Attribute bit bit 4 Event Count Attribute bit bit 5 Self Preserving Attribute bit bit 6 15 Reserved Attribute value 01h FDh 1 00h FEh FFh Not in use 3 01h Minimum value 64h Initial value Fdh Maximum value Worst Ever normalized Attribute Value valid values from 01h FEh Raw Attribute Value 5 10 Attribute specific raw data FFFFFFh reserved as saturated value 11 Reserved 00h 1 For ID 199 CRC Error Count Attribute ID Numbers Any nonzero value in the Attribute ID Number indicates an active attribute The device supports following Attribute ID Numbers ID Attribute Name 5 Reallocated Sector Count 9 Power on Hours 12 Power on Count 177 Wear Leveling Count 179 Used Reserved Block Count total 180 Unused Reserved Block Count total 181 Program Fail Count total 182 Erase Fail Count total 183 Runtime Bad Count total 187 Uncorrectable Error Count 190 Airflow Temperature 195 ECC Error Rate 199 CRC Error Count 235 Power Recovery Count 241 Total LBA Written SAMSUNG ELECTRONICS 23 MZMPC256HBGJ 00000 MZMPC128HBFU 00000 Rev 1 0 MZMPCO64HBDR 00000 SSD MZMPC032HBCD 00000 7 3 2 3 Off Line Data Collection Status The value of this byte defines the current status of the off line activities of the device Bit 7 indicates an Automatic Off line Data Collection Status Bit 7 A
56. utomatic Off line Data Collection Status 0 Automatic Off line Data Collection is disabled 1 Automatic Off line Data Collection is enabled Bits 0 6 represent a hexadecimal status value reported by the device Value Definition Off line data collection never started All segments completed without errors In this case the current segment pointer is equal to the total segments required Off line activity in progress Off line data collection is suspended by the interrupting command Off line data collecting is aborted by the interrupting command Off line data collection is aborted with a fatal error ouahwnd 7 3 2 4 Self test execution status Bit Definition 0 3 Percent Self test remaining An approximation of the percent of the self test routine remaining until completion given in ten percent increments Valid values are 0 through 9 4 7 Current Self test execution status The self test routine completed without error or has never been run The self test routine was aborted by the host The self test routine was interrupted by the host with a hard or soft reset The device was unable to complete the self test routine due to a fatal error or unknown test error The self test routine was completed with an unknown element failure The self test routine was completed with an electrical element failure The self test routine was completed with a servo element failure The self test routine was completed with a read element failure 5 The
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