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Elixir 8GB DDR3

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1. 5954 M 0054 1 DM4 1 DM CS 005 095 DM 65 Das Das DM CS 605 Das DM CS Das Das N oo voo 2032 woo voo we VO 1 pass 1 1 N 2 yo 2 02 yo 2 N vos DO D8 0035 N 03 D4 012 N o4 vO 4 pase N 1 04 VO 4 N 705 VO5 DQ37 05 yo 5 voe Vo 6 pass 06 yo 6 WM 7 Ex VO7 za 0089 07 zo x 07 za 4 pass m n 0055 M 1 DM5 t DM CS DOS Dos DM CS DOS DM CS DOS Dos DM CS DOS 005 N woo voo oo VO 0 Aw 1 VO 1 DQ41 1 VO 1 o2 yo 2 2042 02 yo 2 vos D1 D9 N 03 05 wv VO 4 0044 04 VO 4 N 05 VO5 0045 05 yo 5 N voe 6 0046 06 yo 6 wN voz za 5 za 0047 W 07 za 07 za 7 pase M I p 0056 1 DM6 DM CS Das 005 DM CS 0505 005 DM CS Das DOS DM CS 0605 005 roo voo 2048 N voo WwW 01 VO 1 DQ49 N 1 1 vo2 yo 2 DQ50 2 yo 2 vos D2 vO3 510 2051 103 06
2. SDRAMs 00 07 Bon BAION 50 W SDRAMs 00 07 cko CK SDRAMs 00 07 cKO CK SDRAMs 00 07 SDRAM RESET ____________ RESET SDRAMs 00 07 oe Notes 1 DQ to I O wiring is shown as recommended but may changed 2 DQ DQS DQS ODT DM CKBE S relationships must be maintained as shown 3 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 2400 1 4 One SPD exists per module 5 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram BGB 2 Ranks 512Mx8 DDR3 SDRAMs 51 50 0050 0950 DQO DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQs2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 0021 0922 DQ23 5053 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
3. S Cumulative error across 8 cycles tERR _______ Cumulative error aoross 9 oyoles Cumulative error across 10 cycles Cumulative error across 11 cycles as ___ S Cumulative error across 12 ts S tERR nper min 1 0 68In n tJIT per min Cumulative error across 13 14 49 50 cycles tERR nper tERR nper max 1 0 68In n tJIT per max DOS DAS to DA skew per group peraccess _ 00 5 005 DOlowimpedane metomCK CKE 28 DQhighimpedenetimetomCK CKF oo _____ 225 tDS Data setup time to DQS DQS referenced to Vih ac Vil ac levels AC175 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels AC180 10 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 DQandDMipupusewidhforeachinput pg sss mee cte c een 205 204 differential READ Preamble oo 9 DOS DOSE differential READ Postamble os ____ DOS DASE differential output hightime jo ___ DOS DASE differential outputiowtime pos o4 ___ DOS DOSE different
4. Detail A Detail B 250 8 0 8 O 0 05 Li gt 3 80 0000 0010000 Eli 1 00Pitch 1 50 0 10 Units Millimeters REV 1 0 22 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 li PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SDRAM DIMM Package Dimensions BGB 2 Ranks 512Mx8 DDR3 SDRAMs FRONT 133 35 0 15 gt 8 4 00 Max o S THT e E Detail A P Detail BUS x 1 27 0 07 0 10 5 00 Detail A Detail B 250 jos 0 80 0 05 poo 0010000 1 00 Pitch 1 50 0 10 Units Millimeters Note Device position and scale are only for reference REV 1 0 23 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SDRAM DIMM Package Dimensions BGB 2 Ranks 512Mx8 DDR3 SDRAMs Heat Sink
5. gt CK SDRAMs 00 07 sao Ao gt 50 CK SDRAMs 00 07 9 i We cki CK SDRAMs 08 015 gt A CKI p CK SDRAMs 08 015 RESET RESET SDRAMs 08 015 REV 1 0 07 2012 Notes 1 DQ to I O wiring is shown as recommended but may be changed resistor is 2400 1 One SPD exists per module DQ DQS DQS ODT DM CKBE S relationships must be maintained as shown For each DRAM a unique ZQ resistor is connected to ground The ZQ NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SDRAM DIMM Environmental Requirements TOPR Module Operating Temperature Range ambient 0 to 55 C 3 Hopr Operating Humidity relative 10 to 90 1 Storage Temperature Plastic 55 to 100 C 1 HsrG Storage Humidity without condensation 5 to 95 1 Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions fo
6. PR Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax tWRPDEN BL8OTF BL8MRS 4 tWRPDENmax mmm e BL8MRS 4 tWRAPDENmax IWRPDENmin WL 2 WR tCK avg WRPDENmax vr eee pem tWRAPDEN BC4MRS tWRAPDENmax GGG NUN Timing of REF command to Power Down entry tREFPDEN tREFPDENmax Timing of MRS command to Power Down entry tMRSPDEN ODT Timings mE NENNEN NEN ODT high time without write command or ODTH4min 4 ODTH4 with write command and 4 ODTH4max ODT high ti ith Writ id and BL8 ODTH8 DIRMI 6 CK me rite command an n ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on tAON Ooo om zs e RTT Nom and RTT turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew tADC Pos ____ Write Leveling Timings First DQS DQS rising edge after tWLMRD write leveling mode is programmed DQS DQS delay after write leveling mode is programmed nk S Write leveling setup time from rising CK CK bed di epu nnd WLS 165 crossing to rising DQS DQS crossing Write leveling hold time from rising DQS DQS tWLH 165 crossing to rising CK CK crossing
7. I N REV 1 0 10 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e i x r Unbuffered DDR3 SDRAM DIMM DDR3 1600MHz Symbol Mir Internal read command to first data 1125 920 ms ACT to internal read or write delay time O 1125 ms PRE command period ms O ACT to ACT or REF command period 1 1 4625 _ ms ACT to PRE command period RAS 35000 _ ms oo CWL 5 2250 330 1 5 WL 6 ICK AVG Reserved _ ns o lt WL 7 CK AVG Reserved Reserved ins WL 5 CK AVG WL 6 CK AVG WL 7 CK AVG WL 5 CK AVG WL 6 CK AVG WL 7 CK AVG WL 5 CK AVG WL 6 CK AVG 1 875 25 ns o WL 7 CK AVG 1 5 lt 1 875 15 1875 o WL 5 CK AVG Reserved Reserved ns o lt WL 6 CK AVG Reserved Reserved ins WL 7 CK AVG 4 500 lt 1 875 ______ WL 8 CK AVG 1 25 lt 1 5 12515 WL 5 CK AVG Reserved Reserved o o WL 6 CK AVG Reserved Reserved ins WL 7 CK AVG 4 500 lt 1 875 ims WL 8 CK AVG 425 15 125415 WL 5 CK AVG Reserved Reserved ins WL 6 CK AVG Reserved Reserved o WL 7 CK AVG Reserve
8. PRE command period 13 125 Eo ms ACT to ACT or REF command period 50 625 ACT to command period tRAS 37 500 9 tREFI ns m CWL 5 tCK AVG 3 000 3 300 Ins CWL 6 tCK AVG Reserved mS CWL 5 2500 330 CWL 5 tCK AVG 2 500 3 300 CL 7 CWL 0 gCKAVG Reserved cwL 5 QCKAVG Reserved ms CWL CKAVG ___ 18755 _ lt 5 so m CWL 5 QCKAVG Reserved ___ ms CWL 6 JCKAVGQ 18 5 25 ms DDR3 1333MHz 5 Unit l M Ma l 13 5 Internal read command to first data 13 125 5 20 000 13 5 ACT to internal read or write delay time tRCD 13 125 Jom 13 125 ACT to ACT or REF command period t My P 49 125 5 Zu ACT to PRE command period RAS 36 000 9 tREFI ns CK AVG 3 me e CL 5 iL A 2 lt o olo m Ci IS AS gt lt lt Qo iL A gt lt 25 0 E 1 500 _____ lt 1 875 ns A 2 lt qu gt gt lt lt GHI N gt gt lt lt 9o rr an lt lt lt lt 9o 0 875 A 2 lt g I N 5 d i a o Bla I LALA LA gt lt
9. REV 1 0 17 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N Celi 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 eixir Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1600MHz C a 1 e O O Parameter Symbol Units P E Minimum Glock Cycle Time DLL off mode Average Clock Period Reter to Standard Speed Bin es Wwemgehghpusewdh oo 04 05 oag Average low pulsewidth 0 oao Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth 04 0 Absolute clock LOW pulse tabs 09 e o e Clock Period Jitter during DLL locking period Cycle to Cycle Period siter S Cycle to Cycle Period Jitter during DLL locking period _____ Duty Cyce ster __ ey Ps Cumwatveemoracross2cydes Cumuatveemoraeoss3cydes Cumulative erroracross4cycles HERA __ 130 Cumulative eror across Scycles Cumulative eroracross6cycles RN amp pe Cumulative error across 7 oyoles
10. to CASH command delay eeo a Auto precharge write recovery precharge time WRerowdupiRP Kavg Multi Purpose Register Recovery Time merr ___ ok ____ PRECHARGE command period RAS Standard Speed Bins tRRDmin max 4nCK 6ns ACTIVE to ACTIVE command period for 1KB page size tRRDmax tRRDmin max 4nCK 7 5ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size posts f Four activate window for 2KB page size IFAW ___ rs Command and Address setup time to CK CK tlS base referenced to Vih ac Vil ac levels Command and Address hold time from CK CK tlH base 120 referenced to Vih dc Vil dc levels Command and Address setup time to CK CK tlS base AC150 170 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input ___ f Calibration Timing uuu Power up and RESET calibration time zai Normal operation Full calibration time Ope __ ___ ck ___ Normal operation Short calibration time 12008 Reset Timing a eee MU aaa tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR Nl M tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requi
11. 107 0047 N 07 za 5052 0956 DQS2 pase M Tq DM2 DM6 DM CS Das Das DM CS Das DAS pais N 00 DO48 N 100 DQ17 N VO 1 DQ49 1 pais N 02 DQ50 N 4 O2 DQi9 N 03 D2 0051 103 D6 DQ20 1 04 0052 N 1 04 0021 N 105 DQ53 N 1 05 0022 N 1 06 0054 N 1 06 0023 N 1 07 0055 N 1 07 za 5953 M 5957 09 3 DQS7 DM3 DM7 DM CS Das Das DM CS Das DAS 0024 N 1 00 0056 N 100 0025 1 01 0057 101 2926 N 2 0058 1 02 0027 N 1 03 D3 0059 N 03 D7 0028 N 1 04 2060 N 104 0029 N 105 0061 N 105 DQ30 N 1 06 0062 N 06 N 107 0063 N 107 za n SCL SCL Vobsep gt SPD sao 3 Ao SPD VooVoo 00 07 sai 99 A1 gt SDA Vnerba lt 00 07 gt A2 Vss 00 7 gt 00 07 cS 2 SDRAMs 00 07 15 Jy 15 SDRAMs 00 07 RAS SDRAMs 00 07 DDR3 CAS p CAS SDRAMs 00 07 SDRAM SDRAMs 00 07 A 15 0
12. DQS low impedance time i tLZ DQS 500 tCK avg Referenced from RL 1 DQS DQS high impedance time SUP tHZ DQS tCK avg Referenced from RL E E 005 DOS amp difeeniainpuhghpusewidh 045 DOS DASE rising edge to CK rising edge Doass os DOS DASE taling edge setup time to CK foss Ke DOS DOS falling edge hold time from CK CK rising edge ___ CommandandAdaressTimin __ __ _ o REV 1 0 15 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N mE 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 eixir Unbuffered DDR3 SDRAM DIMM tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time Pts Mode Register Set command cycle time ____ tMODmin max 12nCK 15ns Mode Register Set command update delay to internal read or write delaytime command period JACTIO ACT or REF command period ee __ ICAS to CASH command delay too ok ____ Auto precharge write recovery precharge time __________ _ WRerowdupiRP Kavg M
13. FRONT 13335 h 0 15 126 00 0 2 X N e D 5 60 Max 8 o 8 3 e 1 27 0 07 0 10 M Detail A Detail B g 2 50 a 0 8 0 0 05 ER 00081110000 0000000 1 1 00Pitch 1 50 4 0 10 Units Millimeters Note Device position and scale are only for reference REV 1 0 24 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Revision Log Rev Date Modification 0 1 03 2012 Preliminary Release 1 0 07 2012 Official Release REV 1 0 25 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
14. WRPDENMin WL 2 WR tCK avg WRPDENmax NN NN NN CNN tWRAPDEN BCAMRS tWRAPDENmax m Timing of REF command to Power Down entry tREFPDEN tREFPDENmax Timing of MRS command to Power Down entry tMRSPDEN grid 3 ODT Timings mr ODT high time without write command or ODTH4min 4 ODTH4 nCK with write command and BC4 ODTH4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay 2 tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on es RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew Write Leveling Timings BENE First DQS DQS rising edge after tWLMRD 40 write leveling mode is programmed DAS DQS delay after write leveling mode is programmed o o o o ck ____ Write leveling setup time from rising CK CK tWLS 245 crossing to rising 005 DQS crossing Write leveling hold time from rising DQS Di ite leveling hold time from rising DQS DQS 245 crossing to rising CK CK crossing Write leveling output delay WLO Eo 0000 rs Write leveling output error __ rs REV 1 0 14 07 2012 NANYA TECHNOLOGY CORPORATION NANYA re
15. tHZ DQS Referenced from RL BL 2 tCK avg tCK avg Note 19 3 3 3 Dass 055 REV 1 0 07 2012 tDLLK 00 00 00 512 12 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N mE 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time Register Set command cycle time web o 00 ck tMODmin max 12nCK 15ns Mode Register Set command update delay to internal read or write delaytime 0 0 0 0 0 0 0 0 0 0 S command period IO ACT or REF command period ee __ ICAS to CASH command delay too ok Auto precharge write recovery precharge time __ _ _ WReromdupiRe Kavg Multi Purpose Register Recovery Time merr PRECHARGE commandperiod eas Standard Speed Bins to ACTIVE command period for 18 page size RRD tRRDmin max 4nCK 10ns ACTIVE to ACTIVE command period for 2KB page size
16. 014 we 4 04 2052 1 04 4 05 VO5 2053 05 105 Ww voe 6 0054 1 06 yo 6 N voz zo VO7 0055 07 zo A 07 za 0057 ES 0057 gt t DM7 DM CS DOS 905 DM 65 Das 005 DM CS DOS Das DM CS 505 005 N roo voo 2056 N 100 voo we VO 1 DQ57 N 1 VO 1 we 02 yo 2 pass 102 yo 2 N D3 V O3 Di 2059 103 D7 O3 015 Aw 4 VO 4 104 VO 4 5 VO5 N 05 yo 5 Ww voe 6 2062 1 06 yo 6 N 07 za x VO7 za 0063 07 za x 07 za 9 SPD SDRAM Voo Vooa 00 015 0 A 15 0 Vreroa gt 00 015 RAS CAS WE I Vss e e 00 015 ODT 1 0 BA 2 0 S 1 0 Vacrca _ _ gt 00 015 2 gt 2 SDRAMs 00 015 15 5 15 SDRAMs 00 015 DDR3 RAS ___________ RAS SDRAMs 00 015 SDRAM CAS SDRAMs 00 015 WE SDRAMs 00 015 FW CKE SDRAMs 00 07 CKE1 p SDRAMs 08 015 gt ODT SDRAMs D0 D7 ODT1 SDRAMs 08 015 SCL scL so
17. On Die Termination support SDRAMs are in 78 ball BGA Package RoHS compliance and Halogen free product Description M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N are 240 Pin Double Data Rate 3 DDR3 Synchronous DRAM Unbuffered Dual In Line Memory Module UDIMM organized as one rank of 512Mx64 4GB and two ranks of 1024Mx64 8GB high speed memory array Modules use eight 512Mx8 4GB and sixteen 512Mx8 8GB 78 ball BGA packaged devices These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR3 SDRAM DIMMs provide a high performance flexible 8 byte interface in 5 25 long space saving footprint The DIMM is intended for use in applications operating of 800MHz clock speeds and achieves high speed data transfer rates of 1333Mbps 12800Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs A0 A15 and inputs BAO BA2 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial EEPROM using a standard IIC protocol The first 128 bytes of SPD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV 1 0 1 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications with
18. tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax tXPmin max 3nCK 7 5ns tXPmax S v m 5 lt 5 m A n 2 5 g 5 8 E a Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands tXPDLLmin max 10nCK 24ns tXPDLLmax tCKEmin max 3nCK 5 625ns tCKEmax tCPDEDmin 1 tCPDED tCPDEDmin tXPDLL requiring a locked DLL CKE minimum pulse width tCKE Command pass disable delay tPDmin tCKE min Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 tACTPDENmax Timing of ACT command to Power Down entry tPRPDENmin 1 Timing of PRE or PREA command to Power Down entry iPREDENmS tRDPDENmin RL 4 1 tRDPDENmax Timing of RD RDA command to Power Down entry 5 gt EN ES U gt 2 REV 1 0 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N m m 4GB 512M x 64 8GB 1024M x 64 elixir PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM BL8MRS 4 IWRPDENmax mm _ tWRAPDEN BL8MRS 4 tWRAPDENmax
19. M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 eixir Unbuffered DDR3 SDRAM DIMM Based on 512Mx8 SDRAM B Die Features Performance Speed Sort PC3 10600 PC3 12800 PC3 12800 CG DG DI Unit DIMM CAS Latency 9 9 11 fck Clock Freqency 667 800 800 MHz tck Clock Cycle 1 5 1 25 1 25 ns fDQ DQ Burst Fregency 1333 1600 1600 Mbps Programmable Operation 240 Pin Dual In Line Memory Module UDIMM DIMM CAS Latency 5 6 7 8 9 10 11 512Mx64 4GB 1024Mx64 8GB DDR3 Unbuffered DIMM Burst Type Sequential or Interleave 12Mx8 DDR3 SDRAM B Di ices based on 5 x8 3S ie devices Burst Length BC4 BL8 el ded for 800MH licati UD LS Operation Burst Read and Write VDD VDDQ 1 5V 0 075V Standard S Q andarg Power Supply Two different termination values Rtt Nom amp Rtt_WR SDRAMs have 8 internal banks for concurrent operation P 16 10 1 row column rank Addressing for 4GB Diff tial clock input 16 10 2 row column rank Addressing for 8GB Data is read or written on both clock edges Extended operating temperature rage DRAM DLL aligns DQ and DQS transitions with clock transitions 9 8 Q Auto Self Refresh option Address and control signals are fully synchronous to positive 9 ind P Serial Presence Detect clock edge 9 Gold contacts Nominal D i Die Terminati ominal and Dynamic
20. NC 159 5 69 189 V 99 DQ48 219 0053 10 003 130 Vss 40 CB1 NC 160 Vss 70 A10 AP 190 BA1 100 DQ49 220 Vss DM6 11 131 0012 41 161 DM amp DQS17 74 191 101 Vas 221 00515 TDQS17 NC TDOSIS md NC DOS17 Ee San NC 12 132 DQ13 42 0058 162 72 Vo 192 RAS 102 0056 222 00515 TDOST TDOS 13 DQ9 133 Vss 43 0098 163 Vss 73 WE 193 50 103 0056 223 Vss 14 Vas 134 uc 44 164 CB6NC 74 CAS 194 104 Vs 224 0054 15 DOSI 135 pun 45 2 165 CB7ZNC 75 V 195 105 0050 225 0055 16 0051 136 Vss 46 CB3 NC 166 Vss 76 SINC 196 A13 106 0051 226 Vss 17 137 0014 47 167 NC TEST 77 ODTINC 197 V 107 Va 227 18 0010 138 0015 48 168 RESET 78 Vp 198 S3 NC 108 0056 228 0061 19 0011 139 Vss 49 169 79 S2NC 199 Vs 109 0057 229 Veg DM7 20 140 DQ20 50 CKEO 170 Voo 80 200 0036 110 Vss 230 00516 TDOSI6 NC 21 0016 141 0021 51 V 171 15 81 0032 201 0037 111 0057 231 00516 150576 22 0017 142 Vss 52 BA2 172 A14 82 DQ33 202 Vs 112 DQS7 232 Vss DM4 23 Vss 143 53 Our 173 Voo 83 Va 203 00513 113 Vss 233 0062 NG TDQS13 NC DOS71 en NG 24 DOSZ 144 0051 174 84 DOS 204 00513 114 0058 234 0063 00513 150513 25 0052 145 Vss 55 AM 175 A9 85 0054 205 Vs 115 0059 235 Vss 26 Vss 146 DQ22 56 7 176 Vos 86 206 0038 116 Vss 236 27 0018 147 0023 57 177 A8 87 207 0039 117 SAO 237
21. RPDENmin WL 4 tCK avg BL8OTF BL8MRS 4 tWRPDENmax a NNNM tWRAPDEN BL8MRS 4 tWRAPDENmax IWRPDENmin WL 2 WR tCK avg WRPDENmax pem tWRAPDEN BC4MRS tWRAPDENmax JUN NUN Timing of REF command to Power Down entry tREFPDEN tREFPDENmax Timing of MRS command to Power Down entry tMRSPDEN aA ODT Timings NENNEN ODT high time without write command or ODTH4min 4 ODTH4 with write command and 4 ODTH4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on tAON e RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew tADC Poo O o7 ___ Write Leveling Timings nn First DQS DQS rising edge after tWLMRD write leveling mode is programmed DOS DOS delay after write leveling mode is programmed WLDOSEN fh nk S Write leveling setup time from rising CK CK WLS crossing to rising DQS DQS crossing Write leveling hold time from rising DQS DQS crossing to rising CK CK crossing Write leveling output delay WLO ___ T wi Write leveling output error __ 00 rs
22. SA1 28 DQI9 148 Vss 58 A5 178 A6 88 DQ35 208 Vs 118 SCL 238 SDA 29 149 0028 59 4 179 Von 89 209 0044 119 SA2 239 Vss 30 DQ24 150 DQ29 60 Vo 180 A3 90 0040 210 0045 120 Vm 240 Vr Note CK1 CKE1 S1 and ODT1 are for 8GB modules only REV 1 0 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 elixir PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Input Output Functional Description Symbol CKO CK1 CKO CK1 CKE1 0 RAS CAS WE ODTO ODT1 DMO DM8 DQS0 DQS8 DQS0 0058 BAO BA1 BA2 A0 A9 A10 AP A11 A12 BC A13 A15 DQO DQ63 Vss Vnerpa VREFCA SDA SCL SA2 EVENT RESET REV 1 0 07 2012 Type Polarity Cross Input point Active Input High Active Input Low Active Input Low Active Input High Active Input High Cross VO point Input x Input Input Input Input Output Input Function The system clock inputs All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK A Delay Locked Loop DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock A
23. Write leveling output delay WLO L0 S vs fe T Write leveling output error o 00 rs REV 1 0 20 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 li PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SDRAM DIMM Package Dimensions 4GB 1 Rank 512Mx8 DDR3 SDRAMs FRONT 133 35 0 15 lt gt SIDE m x o 2 57 4 9 T 8 _ Detail A vote Detail B 5 175 47 00 71 00 1 27 0 07 0 10 Detail A Detail B P 250 a 0 80 0 05 Aem 4 1 00 Pitch 1 50 0 10 Units Millimeters REV 1 0 21 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Package Dimensions 4GB 1 Rank 512Mx8 DDR3 SDRAMs Heat Sink FRONT 13335 2 0 15 Celixir 126 0 2 SIDE 4 30 Max gt ie 25 00 0 2 30 00 0 5 0 15 1 27 0 07 0 10
24. ctivates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by SO Rank 1 is selected by S1 When sampled at the positive rising edge of CK and falling edge of CK signals RAS CAS WE define the operation to be executed by the SDRAM Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR3 SDRAM mode register The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect The data strobes associated with one data byte sourced with data transfers In Write mode the data strobe is sourced by the controller and is centered in the data window In Read mode the data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window DQS signals are complements and timing is relative to the cross point of respective DQS and DAQS If the module is to be operated in single ended strobe mode all DQS signals must be tied on the system board to Vss and DDR3 SDRAM mode registers programmed appropriately Selects
25. d Reserved ns o WL 8 CK AVG M25 ____ lt 15 ns SC Supported CL Settings Supported CWL Settings Optional SPS FS ei fot ot 2 2 215 2 15 515 52152 7 CL 11 REV 1 0 11 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1066MHz DDR3 1066 Parameter Symbol Units Clock Timing __ Minimum Clock Cycle Time DLL off mode _ ___ rs S Average Clock Period Reter to Standard Speed Bin es Average high pulsewidth hoew ____ Average low pulsewidth oss ___ Max tCK avg max tJIT per max Absolute clock HIGH pulse width __ _ 0 Absolute clock LOW pulsewidth Clock Period siter site je Clock Period Jitter during DLL locking period __ Cycle to Period siter ___ ____ tsps S Cycle to Cycle Period Jiter during DLL locking period _______ 10 tos S Duty Cyce ster Ps Cumulative erroracross2cycles ae S Cumulati
26. echarge SAO SA1 Serial Presence Detect Address Inputs A12 BC Address Input Burst Chop Vtt Termination voltage BAO BA2 SDRAM Bank Address Inputs Vss Ground ODTO ODT1 Active termination control lines Vop Core and I O power SCL Serial Presence Detect Clock Input NC No Connect SDA Serial Presence Detect Data input output REV 1 0 2 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM DDR3 SDRAM Pin Assignment Pin Front Pin Pin Front Pin Pin Front Pin Back Pin Front Pin Back 1 121 Vss 31 0025 151 Vss 61 2 181 Ai 91 0041 21 DMS 2 122 DQ4 32 Va 152 62 Vo 182 Vp 92 212 00514 TDOS14 59512 NC 3 000 123 DQ5 0953 153 0512 183 Vo 93 0055 213 DOS TDOST 150514 4 001 124 Vss 34 DQS3 154 Vss 64 184 CKO 94 0055 214 Vss 5 Vs 125 cea 35 155 00930 65 185 CKO 95 Vss 215 0046 6 0050 126 jx 36 DQ26 156 0031 66 186 96 0042 216 0047 7 paso 127 Vss 37 0027 157 Vss 67 Vaerca 187 zn 97 0043 217 Vss 8 Va 128 DQ6 38 158 CBANC 68 cu 188 AO 98 Va 218 0052 Daz 129 DQ7 39 CBO
27. es where all DRAM specifications will be supported During operation the DRAM case temperature must be maintained between 0 to 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 and 95 C case temperature Full specifications are supported in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh to 7 8 5 in the Extended Temperature Range Please refer to supplier data sheet and or the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 Ob and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 Ob Please refer to the supplier data sheet and or the DIMM SPD for Auto Self Refresh option availability Extended Temperature Range support and tREFI requirements in the Extended Temperature Range REV 1 0 7 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 li PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM DC Electrical Characte
28. ial WRITE Preamble were ___ DOS DASE differential WRITE west os __ __ ____ ___ Dex ri Emi DQS and DQS low impedance time b i tLZ DQS 450 tCK avg Referenced from RL 1 DQS DQS high impedance time d tHZ DQS tCK avg Referenced from RL E _ cuu us 8 DOS DOS amp difeemiainpuhghpusewidh 045 DOS DASE rising edge to CK risingedge Doass onr ____ DOS 005 falling edge setup time to CK CK risingedge joss ote Kev DOS DASE falling edge hold time CK rsingedge te Gommand and o REV 1 0 18 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N mE 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 eixir Unbuffered DDR3 SDRAM DIMM tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time Pts Mode Register Set command cycle time ____ tMODmin max 12nCK 15ns Mode Register Set command update delay to internal read or write delaytime eeo 00 0 00 0 0 0 0 S command period ACT or REF command period ee __
29. o exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX ICKSRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Power Down Timings Exit Power Down with DLL on to valid command tXPmin max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands tXPmax not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands XPDLL tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax tCKEmin max 3nCK 5 625ns CKE minimum pulse width tCKE tCKEmax tCPDEDmin 1 Command pass disable delay tCPDED tCPDEDmin tPDmin tCKE min Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDEN tACTPDENmax tPRPDENmin 1 Timing of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmax REV 1 0 16 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N m m 4GB 512M x 64 8GB 1024M x 64 elixir PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM e BRI Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax Timing of WR command to Power Down entry IWRPDEN tW
30. out notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e IXI r Unbuffered DDR3 SDRAM DIMM Ordering Information M2F4G64CB88B7N CG 0083 1333 PC3 10600 667MHz 1 5ns CL 9 512Mx64 M2F8G64CB8HB5N CG 0083 1333 PC3 10600 667 2 1 5ns 9 1024 64 M2X4G64CB88B7N DG DDR3 1600 12800 800MHz 1 25 5 9 512Mx64 M2F4G64CB88B7N DI DDR3 1600 12800 800MHz 1 25ns CL 11 512 64 e M2X8G64CB8HB5N DG DDR3 1600 PC3 12800 800MHz 1 25 5 9 1024Mx64 TT od M2F8G64CB8HB5N DI DDR3 1600 12800 800MHz 1 25ns 11 1024Mx64 M2X4G64CB88BHN DG DDR3 1600 PC3 12800 800MHz 1 25 9 512 64 M2F4G64CB88BHN DI DDR3 1600 12800 800MHz 1 25 5 11 512 64 M2X8G64CB8HB9N DG DDR3 1600 PC3 12800 800MHz 1 25 5 9 1024Mx64 M2F8G64CB8HB9N DI DDR3 1600 12800 800MHz 1 25ns 11 1024Mx64 Pin Description CKO CK1 Clock Inputs positive line 090 0063 Data input output CKO CK1 Clock Inputs negative line DQS0 DQS8 Data strobes CKEO CKE1 Clock Enable DQS0 DQS8 Data strobes complement RAS Row Address Strobe Data Masks CAS Column Address Strobe EVENT Temperature event pin WE Write Enable RESET Reset pin S0 S1 Chip Selects Vnerba Input Output Reference 9 A11 A13 A15 Address Inputs Vopspp SPD and Temp sensor power A10 AP Address Input Auto Pr
31. put Logic Low vss Vref 0 100 vss Vref 0 100 vss 0 100 V 1 VIH DQ AC Input Logic High Vref 0 175 Note2 Vref 0 15 _ 2 Vref 0 15 Note2 V 1 2 5 VIL DQ AC AC Input Logic Low Note2 0 175 Note2 0 15 2 0 15 V 1 2 5 Vrerpa oc dpi Voltage for DQ DM 0 49x VDD 0 51xVDD 0 49xVDD 0 51 x VDD 0 49xVDD 0 51xVDD V 3 4 Note 1 For input only pins except RESET Vref VrefDQ DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 Single ended swing requirement for DQS DQS is 350 mV peak to peak Differential swing requirement for DQS DQS is 700 mV peak to peak REV 1 0 8 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Operating Standby and Refresh Currents Tease 0 85 Vona Voo 1 5V 0 075V PC3 10600 4GB 8GB IDDO IDD1 IDD2PO IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 Operating One Bank Active Precharge Current Operating One Bank Active Read Precharge Current Precharge Power Down Current Slow Exit Precharge Powe
32. r Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current Normal Temperature Range Operating Bank Interleave Read Current Operating Standby and Refresh Currents Tease 0 85 1 5V 0 075V PC3 12800 4GB 8GB IDDO IDD1 IDD2PO IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 REV 1 0 07 2012 Operating One Bank Active Precharge Current Operating One Bank Active Read Precharge Current Precharge Power Down Current Slow Exit Precharge Power Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current Normal Temperature Range Operating Bank Interleave Read Current NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 e i x r Unbuffered DDR3 SDRAM DIMM Standard Speed Bins DDR3 1066MHz IF nF 7 7 7 E Unit Parameter Symbol Mir Max Internal read command to first data 13 125 20 000 nS ACT to internal read or write delay time tRCD 13 125
33. r extended periods may affect reliability 2 Up to 9850 ft 3 The component maximum case temperature shall not exceed the value specified in the component spec Absolute Maximum DC Ratings Vpp Voltage on VDD pins relative to Vss 0 4 V 1 975 V V Voltage on pins relative to 55 0 4 V 1 975 V V 1 3 Vin Vout Voltage on I O pins relative to Vss 0 4 V 1 975 V V 1 Storage Temperature 55 to 100 C 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300 mV of each other at all times and VREF must be not greater Operating temperature Conditions Normal Operating Temperature Range 0 to 85 1 OPER Extended Temperature Range 85 to 95 C T 3 Note 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the JEDEC document JESD51 2 2 The Normal Temperature Range specifies the temperatur
34. ring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX ICKSRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Power Down Timings Exit Power Down with DLL on to valid command tXPmin max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands tXPmax not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands XPDLL tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax tCKEmin max 3nCK 5ns CKE minimum pulse width tCKE tCKEmax tCPDEDmin 1 Command pass disable delay tCPDED tCPDEDmin tPDmin tCKE min Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDEN tACTPDENmax tPRPDENmin 1 Timing of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmax REV 1 0 19 07 2012 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N m m 4GB 512M x 64 8GB 1024M x 64 elixir PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM
35. ristics and Operating Conditions VDD Supply Voltage 1 425 1 575 VDDQ Output Supply Voltage 1 425 1 5 1 575 V 2 Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Single Ended AC and DC atc Levels for Command and M VIH CA DC DC Input Logic High Vref 0 100 Vref 0 100 Vref 0 100 VD V VIL CA DC DC Input Logic Low VSS Vref 0 100 VSS Vref 0 100 VSS Vref 0 100 V VIH CA AC AC Input Logic High Vref 0 175 Note 2 Vref 0 175 Note 2 Vref 0 175 Note 2 V 1 VIL CA AC Input Logic Low Note 2 Vref 0 175 Note 2 Vref 0 175 Note 2 Vref 0 175 V 1 VIH CA AC150 AC Input Logic High Vref 0 15 Note 2 Vref 0 15 Note 2 Vref 0 15 Note 2 V 1 VIL CA AC150 AC Input Logic Low Note 2 Vref 0 15 Note 2 Vref 0 15 Note 2 Vref 0 15 V 1 Reference Voltage Vaecapo for ADD CMD 0 49xVDD 0 51xVDD 0 49xVDD 0 51xVDD 049xVDD 0 51 x VDD V 3 4 Inputs Note 1 For input only pins except RESET Vref VrefCA DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Single Ended AC and DC Input Levels for _ lt DM VIH DQ DC DC Input Logic High Vref 0 100 VDD Vref 0 100 VDD Vref 0 100 VDD VIL DQ DC DC In
36. s S Cumulative error across 10 cycles __ 25 265 S Cumulative error across 11 cycles aoo ets S Cumulative error across i2cydes tERR nper min 1 0 68In n tJIT per min Cumulative error across 13 14 49 50 cycles tERR nper tERR nper max 1 0 68In n tJIT per max pump m Mcr DOS DAS to DA skew per group peraccess feasa 100 5 0056 __ DOQlowimpedance zoo so S DQhighimpedenetimetromCK CKF tDS Data setup time to DQS DQS referenced to Vih ac Vil ac levels 175 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels AC180 30 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 DQandDMipupusewidhforeachinut ow p sss mee cce c oen DOQS DOS differential READ Preamble meRE oo DOS 005 differential READ Postamble ___ meSr os ____ DOS DASE differential output hightime OSH o4 __ DOS DASE differential outputiowtime pos __ __ ____ DOS DOSE differential WRITE Preamble were 09 ____ ___ DOS DOSE differential WRITE Postamble west os ____ ___ Dre DQS
37. serves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N Celi 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 eixir Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1333MHz C a 1 O Parameter Symbol Units Minimum Glock Cycle Time DLL off mode Average Clock Period Reter to Standard Speed Average high pulsewidth ooo 04 ___ Average low pulsewidth Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth 04 Absolute clock LOW pulse ces 09 Clock Period siter sitio ____ ____ _ je S Clock Period Jitter during DLL locking period Cycle Cycle Period siter ___ twos S Cycle to Cycle Period Jitter during DLL locking period Duty Cyce ster ftir __ __ __ s Cumulative error across 2 cycles Cumuatveemoraeoss3cydes HERS Cumulative eroracross4cycles Cumulative error across Scycles Cumulative eror across 6oyoles ___ ts S Cumulative error across 7 oyoles HERAT Cumulative error across 8 cycles tERR _____ s Cumulative error aoross 9 oyoles __ __ t
38. signal resets the DDR8 SDRAM NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F X 4G64CB88B7 H N M2F X 8G64CB8HB5 9 N 4GB 512M x 64 8GB 1024M x 64 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 4GB 1 Rank 512Mx8 DDR3 SDRAMs REV 1 0 07 2012 eiXxir 50 paso M 5054 paso M T DQS4 N T 3 M DM CS Das Das DM CS Das DAS N 00 DQ32 N O 0 pai JN VO 1 0033 N VO 1 paz 02 N 102 WV 103 0035 N 3 D4 004 N 104 DQ36 N O 4 005 N 05 0037 05 N 06 N 106 DQ7 N 07 0039 N O 7 za DAST M 5955 DASI DQS5 004 N 3 DM5 N 3 DM CS Das Das DM CS Das DAS OO0 0040 N 100 009 JN VO 1 DQ4 VO 1 DQ10 02 0042 02 0011 N 103 D1 0043 N 103 D5 DQ12 04 0044 JN 04 0013 N 105 0045 N 105 DQi4 N 106 0046 N 106 0015 N
39. tRRDmax Four activate window for 1KB page size Four activate window for 2KB page size tFAW o Command and Address setup time to CK tlS base 125 referenced to Vih ac Vil ac levels Command and Address hold time from CK CK tIH base 200 referenced to Vih dc Vil dc levels Command and Address setup time to CK CK id tlS base AC150 1254150 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input O z Calibration Timing E eS LEER MIND Power up and RESET calibration time _____ __ __ y Normal operation Full calibration time Zooper 29 Normal operation Short calibration time 12008 pwc Reset Timing ____ ______ y tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR max Self Refresh Timings pae Racer Enc ees tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns tCKSREmax in Valid Clock Requirement before Self Refresh Exit SRX
40. ulti Purpose Register Recovery Time merr PRECHARGE commandperiod eas Standard Speed Bins tRRDmin max 4nCK 6ns ACTIVE to ACTIVE command period for 1KB page size tRRDmax tRRDmin max 4nCK 7 5ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size bw Four activate window for 2KB page size IFAW Command and Address setup time to CK tlS base referenced to Vih ac Vil ac levels Command and Address hold time from CK CK tlH base 140 referenced to Vih dc Vil dc levels Command and Address setup time to CK CK tlS base AC150 65 125 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input _____ _____ Timing SS SSS SSS See Power up and RESET calibration time zai Normal operation Full calibration time Normal operation Short calibration time 12008 Reset Timing a eee MU aaa tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR Nl tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry t
41. ve erroracrossScycles Cumualveemoracoss4cydes IERR 5per 188 8 s ____ Cumulative error across 6 cydes 200 200 Cumulative error across 7 cycles tERR 7per 209 209 tERR 217 tERR 224 tERR 231 tERR 237 237 tERR 242 242 tERR nper min 1 0 68In n tJIT per min tERR nper max 1 0 68In n tJIT per max Max Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles 8per 224 3 N X 10per 11per 12per Cumu Data setup time to DQS DQS referenced to Vih ac Vil ac levels Data setup time to DQS DQS referenced to Vih ac Vil ac levels Data hold time from DQS DQS referenced to Vih dc Vil dc levels ative error across n 13 14 49 50 cycles nper tDQSQ tQH DQ t 150 tLZ tHZ DQ DS base AC175 tDS base AC150 DH base C100 DIPW m 5 a e DQ and DM Input pulse width for each input RPRE RPST tQSH tQSL tWPRE tWPST tDQSCK t t t Note 11 DQS DQS differential output low time DQS DQS differential WRITE Preamble DQS DQS differential WRITE Postamble DQS DQS rising edge output access time from rising CK CK DQS and DQS low impedance time tLZ DQS Referenced from RL 1 DQS and DQS high impedance time
42. which DDR3 SDRAM internal bank of four or eight is activated During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write command cycle defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK In addition to the column address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BAn defines the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge Data Input Output pins Power supplies for core I O Serial Presence Detect Temp sensor and ground for the module Reference voltage for SSTL15 inputs This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor A resistor must be connected from the SDA bus line to Vopsep on the system planar to act as a pull up This signal is used to clock data into and out of the SPD EEPROM and Temp sensor Address pins used to select the Serial Presence Detect and Temp sensor base address The EVENT pin is reserved for use to flag critical module temperature This

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