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Intel Celeron 430

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1. Lane 0 0 Ep 0 1 Lane 1 1 2 Lane 2 2 3 e 4 da 4 5 Lane 5 5 6 Lane 6 6 5 7 Lane 7 7 8 Lane 8 0 e 8 p 8 x 1 9 Lane 9 9 2 10 Lane 10 10 E Lane 11 9 3 11 qe l E 0 2E 12 e m i2 5 x J 15 13 on 8 2 6 14 lg bane 4 44 x 3 7 15 e 5 2 3 Direct Media Interface DMI Direct Media Interface DMI connects the processor and the PCH Next generation DMI2 is supported Note Only DMI x4 configuration is supported 2 3 1 DMI Error Flow DMI can only generate SERR in response to errors never SCI SMI MSI PCI INT or GPE Any DMI related SERR activity is associated with Device 0 2 3 2 Processor PCH Compatibility Assumptions The processor is compatible with the Intel 6 Series Chipset The processor is not compatible with any previous PCH products Datasheet Volume 1 27 intel Interfaces 2 4 DMI Link Down The DMI link going down is a fatal unrecoverable error If the DMI data link goes to data link down after the link was up then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption This link behavior is controlled by the PCH Downstream transactions that had been successfully transmitted across the link pr
2. 65 6 7 Intel Flexible Display Interface Intel FDI ccccccccsecescececcseseneeuenencecsccecseseneneeeenas 65 6 8 Direct Media Interface DMI Signals Processor to PCH Serial Interface 66 6 9 Phase Lock Loop PLL Signals siir oia keen nee parnm Er aa nenn 66 6 10 Test Access Points TAP Signals eo side tren then na ad tx ER ra OR A aa RE RA a ER RA En 66 6 Datasheet Volume 1 6 11 Error and Thermal Protection 8 5 nennen nun nenn nenn nn nennen nn nn nn 67 6 12 Power Sequencing Signals tied cer t acis anna Ba a a neh 67 6 13 Processor Power Signals 5 3 rrr a RN 68 6 14 Sense Signals ciue Oxon tnu nn catt ta tian aided Rie a CARN eG nen AUR UE 68 6 15 Ground and Non Critical to Function NCTF Signals 68 6 16 Processor Internal Pull Up Pull Down Resistors eee eee 69 7 1 VR 12 0 Voltage Identification Definition nenn nn nenn anne nennen anne 73 7 2 NCESA VID COHNfIiguration szene AERE REA AEN RN 76 7 3 Sigal Groups 1 ee ee eek 77 7 4 St rage C
3. Datasheet Volume 1 m 8 Processor Pin and Signal Information n tel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin 4 Buffer Type Dir Pin Name Pin Buffer Type Dir SB_DQS 6 AL33 DDR3 1 0 SM_DRAMRST AW18 DDR3 SB DQS 7 AG35 DDR3 1 0 SM_VREF AJ22 Analog I SB DQS 8 AN16 DDR3 IO TCK M40 TAP I SB_DQS 0 AH6 DDR3 1 0 L40 TAP I SB_DQS 1 AL8 DDR3 TDO L39 TAP SB_DQS 2 AP8 DDR3 1 0 THERMTRIP G35 Async CMOS SB_DQS 3 AN12 DDR3 1 0 TMS 138 I SB_DQS 4 AN28 DDR3 1 0 TRST 139 I SB_DQS 5 AR33 DDR3 I O UNCOREPWRGOOD J40 Async CMOS I SB_DQS 6 AM33 DDR3 VCC A12 PWR SB_DQS 7 AG34 DDR3 1 0 A13 PWR FSB DQse 8 ANi5 DDR3 yo vcc A14 PWR RSVD AL16 DDR3 I O VCC A15 PWR RSVD AM16 DDR3 1 0 A16 PWR RSVD AP16 DDR3 IO VCC A18 PWR RSVD AR16 DDR3 I O VCC A24 PWR RSVD AL15 DDR3 I O VCC A25 PWR RSVD AM15 DDR3 IO VCC A27 PWR RSVD AR15 DDR3 I O VCC A28 PWR RSVD AP15 DDR3 IO VCC B15 PWR SB MA 0 AK24 DDR3 Oo VCC B16 PWR SB_MA 1 AM20 DDR3 Oo VCC 8 PWR SB MA 2 AM19 DDR3 Oo VCC B24 PWR SB_MA 3 AK18 DDR3 Oo VCC B25 PWR SB_MA 4 AP19 DDR3 Oo VCC B27 PWR SB_MA 5 AP18 DDR3 VCC B28 PWR SB_MA 6 AM18 DDR3 VCC B30 PWR SB_MA 7 AL18 DDR3 VCC B31 PWR SB_MA 8 AN18 DDR3 VCC B33 PW
4. 30 2 4 2 Processor Graphics Display sic e En nrc et 31 2 4 2 1 Display Plahes re tenen herr 31 2 4 2 2 Display Pipes eoe exer ne nie ha nn sega pe eR Hosa s 32 2 4 2 3 Display Ports 32 2 4 3 Intel Flexible Display Interface Intel FDI ccccsssssccccccseecnseccceeeseseneceas 32 2 4 4 Multi Graphics Controller Multi Monitor 5 32 2 5 Platform Environment Control Interface PECI nn nenn 33 2 6 Interface ented an UR NICA denne 33 2 6 1 Internal Clocking Requirements eee nenne nen eee en nn nn 33 Technologies a 35 3 1 Intel Virtualization Technology Intel VT asia pid priu tus cad Read Refs 35 3 1 1 Intel virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Objectives erret nn 35 3 1 2 Intel Virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel ann anne he naar 36 3 1 3 Intel Virtualization Technology Intel VT for Directed 1 0 Intel VT d Objectives icccsssesssesscsasevsssacascvesevedcasatausnsusesauere
5. intel 2nd Generation Intel Core Processor Family Desktop I ntel Pentium Processor Family Desktop and Intel Celeron Processor Family Desktop Datasheet Volume 1 Supporting Intel Core i7 i5 and i3 Desktop Processor Series Supporting Intel Pentium Processor G800 and G600 Series Supporting Intel Celeron Processor G500 and G400 Series This is Volume 1 of 2 June 2013 Document Number 324641 008 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined
6. PECI 135 Async IO PEG TX 8 F8 PCI Express PEG_COMPI B4 Analog I PEG_TX 9 G10 PCI Express D PEG ICOMPO B5 Analog I PEG TX 10 G5 PCI Express PEG_RCOMPO C4 Analog I PEG TX 11 K7 PCI Express PEG RX 0 B11 PCI Express I PEG TX 12 15 PCI Express PEG_RX 1 D12 PCI Express I PEG_TX 13 M8 PCI Express PEG_RX 10 H3 PCI Express I PEG TX 14 L6 PCI Express PEG_RX 11 11 PCI Express I PEG TX 15 N5 PCI Express PEG RX 12 K3 PCI Express I PEG C14 PCI Express PEG RX 13 Li PCI Express I PEG TX 1 E13 PCI Express PEG RX 14 M3 PCI Express I PEG TX 2 G13 PCI Express PEG RX 15 N1 PCI Express I PEG TX 3 F11 PCI Express Oo PEG RX 2 C10 PCI Express I PEG TX 4 J13 PCI Express PEG_RX 3 E10 PCI Express I PEG TX 5 D7 PCI Express PEG_RX 4 B8 PCI Express I PEG_TX 6 C3 PCI Express PEG RX 5 C6 PCI Express I PEG_TX 7 E5 PCI Express PEG RX 6 A5 PCI Express I PEG TX 8 F7 PCI Express PEG_RX 7 E2 PCI Express I PEG 4 9 G9 PCI Express PEG RX 8 F4 PCI Express I PEG TX 10 G6 PCI Express PEG RX 9 G2 PCI Express I PEG TX 11 K8 PCI Express PEG_RX 0 B12 PCI Express I PEG_TX 12 J6 PCI Express PEG_RX 1 Dil PCI Express I PEG_TX 13 M7 PCI Express PEG_RX 10 H4 PCI Express I PEG TX 14 L5 PCI Express PEG_RX 11 J2 PCI Express I PEG_TX 15 N6 PCI Express PEG_RX 12 K4 PCI Express I PM_SYNC E38 CMOS I PEG_RX 13 L2 PCI Express I PRDY K38 Async GTL PEG_R
7. Package C6 State A processor enters the package C6 low power state when At least one core is in the C6 state The other cores are in a C6 or lower power state and the processor has been granted permission by the platform In package C6 state all cores have saved their architectural state and have had their core voltages reduced to zero volts The L3 shared cache is still powered and snoopable in this state The processor remains in package C6 state as long as any part ofthe L3 cache is active Integrated Memory Controller IMC Power Management The main memory is power managed during normal operation and in low power ACPI Cx states Disabling Unused System Memory Outputs Any system memory SM interface signal that goes to a memory module connector in which it is not connected to any actual memory devices such as DIMM connector is unpopulated or is single sided is tri stated The benefits of disabling unused SM signals are Reduced power consumption Reduced possible overshoot undershoot signal quality issues seen by the processor I O buffer receivers caused by reflections from potentially un terminated transmission lines When a given rank is not populated the corresponding chip select and CKE signals are not driven At reset all rows must be assumed to be populated until it can be proven that they are not populated This is due to the fact that when CKE is tristated with an DIMM present the DIMM is
8. 0 0 0 0 0 1 2 3 4 5 6 VID VID VID VID VID VID VID VID 7 73 Datasheet Volume 1 Electrical Specifications intel Sheet 2 of 3 VID VID VID VID VID VID VID VID inition VR 12 0 Voltage Identification Def Table 7 1 1 10000 1 10500 1 11000 1 11500 1 12000 1 12500 1 13000 1 13500 1 14000 1 14500 1 15000 1 15500 1 16000 1 16500 1 17000 1 17500 1 18000 1 18500 1 19000 1 19500 1 20000 1 20500 1 21000 1 21500 1 22000 1 22500 1 23000 1 23500 1 24000 1 24500 1 25000 1 25500 1 26000 1 26500 1 27000 1 27500 1 28000 1 28500 1 29000 1 29500 1 30000 1 30500 1 31000 HEX max E F 1 3 5 E F 1 3 5 1 3 5 AJB AJC AJD A B 0 B B 2 B B 4 B B 6 B 7 B 8 B 9 B B BIC B D B B cjo c 2 4 C 6 7 c 8 c 9 CJA C B C D 0 D D 2 D D 4 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 8 4 5 6 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 49000
9. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order All products platforms dates and figures specified are preliminary based on current expectations and are subject to change without notice All dates specified are target dates are provided for planning purposes only and are subject to change No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see http www intel com technology secu
10. 8 8 6 0 91500 8 7 0 92000 8 8 0 92500 8 9 0 93000 8 A 0 93500 8 B 0 94000 8 C 0 94500 8 D 0 95000 8 8 9 0 0 96500 9 9 2 0 97500 9 9 4 0 98500 9 9 6 0 99500 9 7 9 8 9 9 9 A 9 B 9 cC 9 D 9 9 AJO A 2 4 A 6 A 7 8 A 9 AJA 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 25000 0 27000 0 33000 0 35000 0 41000 0 43000 HEX Vcc_max 1 3 0 26000 5 0 31500 0 32000 0 0 32500 1 2 0 33500 3 0 34000 4 0 34500 5 6 0 35500 7 0 36000 8 0 36500 9 0 37000 A 0 37500 B 0 38000 C 0 38500 D 0 39000 E 0 39500 F 0 40000 0 0 40500 1 2 0 41500 3 0 42000 5 6 0 43500 7 0 44000 8 0 44500 9 0 45000 O O 0 00000 0 0 2 0 25500 0 0 4 0 26500 0 0 6 0 27500 0 7 0 28000 0 8 0 28500 0 9 0 29000 0 A 0 29500 0 B 0 30000 0 C 0 30500 0 D 0 31000 0 0 1 1 1 1 1 1 1 1 1 1 1 al 1 1 1 1 2 2 2 2 2 4 0 42500 2 2 2 2 2 2 A 0 45500 0 0 0 0 0 0
11. Processor Graphics Rank A unit of DRAM corresponding four to eight devices in parallel These devices are usually but not always mounted on a single side of a SO DIMM SCI System Control Interrupt Used in ACPI protocol Storage Conditions A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material TAC Thermal Averaging Constant TAP Test Access Point TDP Thermal Design Power VaxG Graphics core power supply Vcc Processor core power supply Vccio High Frequency I O logic power supply VccPLL PLL power supply Mee System Agent memory controller DMI PCIe controllers and display engine power supply VDDQ DDR3 power supply VLD Variable Length Decoding Vss Processor ground xi Refers to a Link or Port with one Physical Lane x16 Refers to a Link or Port with sixteen Physical Lanes x4 Refers to a Link or Port with four Physical Lanes x8 Refers to a Link or Port with eight Physical Lanes Datashe
12. instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time they can be started without interfering with the current request allowing for concurrent issuing of requests This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate Precharge and Read Write commands normally used as long as the inserted commands do not affect the currently executing command Multiple commands can be issued in an overlapping manner increasing the efficiency of system memory protocol Out of Order Scheduling While leveraging the Just in Time Scheduling and Command Overlap enhancements the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency If there are multiple requests to the same open page these requests would be launched in a back to back manner to make optimum use of the open memory page This ability to reorder requests on the fly allows the IMC to further reduce latency and increase bandwidth efficiency Memory Type Range Registers MTRRs Enhancement The processor has 2 additional MTRRs total 10 MTRRs These additional MTRRs are specially important in supporting larger system memory beyond 4 GB Data Scrambling The memory controller i
13. 0 57000 0 65000 HEX Vcc_max E 0 47500 F 0 48000 1 2 0 49500 3 0 50000 4 0 50500 5 0 51000 6 0 51500 7 0 52000 8 0 52500 B 0 54000 E 0 55500 F 0 56000 1 2 0 57500 3 0 58000 5 0 59000 7 0 60000 E 0 63500 F 0 64000 0 0 64500 1 2 0 65500 3 0 66000 4 0 66500 5 0 67000 2 B 0 46000 2 C 0 46500 2 0 47000 2 2 3 0 0 48500 3 3 3 3 3 3 3 3 3 9 0 53000 3 A 0 53500 3 3 C 0 54500 3 D 0 55000 3 3 4 0 0 56500 4 4 4 4 4 0 58500 4 4 6 0 59500 4 4 8 0 60500 4 9 0 61000 4 A 0 61500 4 B 0 62000 4 C 0 62500 4 D 0 63000 4 4 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 8 4 5 6 VID VID VID VID VID VID VID VID 7 Datasheet Volume 1 74 intel Electrical Specifications Sheet 3 of 3 VID VID VID VID VID VID VID VID inition VR 12 0 Voltage Identification Def Table 7 1 1 31500 1 32000 1 32500 1 33000 1 33500 1 34000 1 34500 1 35000 1 35500 1 36000 1 36500 1 37000 1 37500 1 38000 1 38500 1 39000 1 39500 1 40000 1 40500 1 41000 1 41500 1 42000 1 42500 1 43000 1 43500 1 44000 1
14. 8096 ale 6 7 A prolonged or extended period of time Tim sustained storage typically associated with customer shelf life 0 Months 30 Months Y Timeshort term storage A short period of time 0 hours 72 hours Notes 1 Refers to a component device that is not assembled in a board or socket and is not electrically connected to a voltage reference or I O signal 2 Specified temperatures are not to exceed values based on data collected Exceptions for surface mount reflow are specified by the applicable JEDEC standard Non adherence may affect processor reliability 3 Tabsolute storage APplies to the unassembled component only and does not apply to the shipping media moisture barrier bags or desiccant 4 Component product device storage temperature qualification methods may follow JESD22 A119 low temp and JESD22 A103 high temp standards when applicable for volatile memory 5 Intel branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only Non Operating Temperature Limit 40 C to 70 C and Humidity 50 to 90 non condensing with a maximum wet bulb of 28 C Post board attach storage temperature limits are not specified for non Intel branded boards 6 The JEDEC J JSTD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag 7 Nominal temperature and humidity conditions
15. DDR3 clock buffer pull down Ron_DNCck raean 20 8 26 31 2 Q 5 DDR3 command buffer pull up RON UP CMD resistance Im 24 9 z DDR3 command buffer pull down Ron_DN CMD resistance in DDR3 control buffer pull up RON_UP CTL resistance m 20 Q DDR3 control buffer pull down DN CTL resistance 16 20 24 Q 5 Vit_sm_pramp Input Low Voltage for RO SM DRAMPWROK ea ei VW 9 VIH_sm_DRAMP Input High Voltage for SM_DRAMPWROK 55 0 1 V 9 Input Leakage Current DQ CK t 0 75 Ir 0 2 Vppg X 0 55 mA 0 8 0 9 VDDQ t 1 4 Input Leakage Current CMD CTL X 0 85 Ij 0 2 Vppo 0 65 mA VDDQ X 1 65 Notes 84 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vy is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 Viu is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 signal quality specifications 5 This is the pull up down driver resistance 6 7 8 9 must be monotonic Rrerm is the termination on the DIMM and in not controlled by the processor The minimum and maximum values for these signals are programmable by BIOS to one of the two sets DDRS3 values are pre silicon estimations and subject to change SM DRAMPWROK must have a maximum of 15 ns rise or fall time over Vppg 0 55 200
16. VSS AM37 GND VSS AR27 GND VSS AM38 GND VSS AR30 GND VSS AM39 GND VSS AR36 GND VSS AMA GND VSS AR5 GND VSS AM40 GND VSS AT1 GND VSS AM5 GND VSS AT10 GND VSS AN10 GND VSS AT12 GND VSS AN11 GND VSS AT13 GND VSS AN14 GND VSS AT15 GND vss GN vss AT16 GND VSS AN19 GND VSS AT17 GND VSS AN22 GND VSS AT2 GND VSS AN24 GND VSS AT25 GND VSS AN27 GND VSS AT27 GND VSS AN30 GND VSS AT28 GND VSS AN31 GND VSS AT29 GND VSS AN32 GND VSS AT3 GND VSS AN33 GND VSS AT30 GND VSS AN34 GND VSS AT31 GND VSS AN35 GND VSS AT32 GND VSS AN36 GND VSS AT33 GND VSS AN5 GND VSS AT34 GND VSS AN6 GND VSS AT35 GND VSS AN7 GND VSS AT36 GND VSS AN8 GND VSS AT37 GND VSS GND VSS AT38 GND VSS AP1 GND VSS AT39 GND VSS AP11 GND VSS AT4 GND VSS AP14 GND VSS AT40 GND VSS AP17 GND VSS AT5 GND VSS AP22 GND VSS AT6 GND VSS AP25 GND VSS AT7 GND VSS AP27 GND VSS ATS GND VSS AP30 GND VSS AT9 GND VSS AP36 GND VSS AU1 GND VSS AP37 GND VSS AU15 GND VSS AP4 GND VSS AU26 GND VSS AP40 GND VSS AU34 GND VSS AP5 GND VSS AU4 GND vss auai cub vss AU6 GND VSS AR14 GND VSS AU8 GND VSS AR17 GND VSS AV10 GND 104 Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Nam
17. processors with 35 W TDP 2011A processors with 35 W TDP processors may also use the loadline slope TOB and ripple specifications for the 2011D processors with 95 W TDP 2011C processors with 65 W TDP and 2011B processors with 45 W TDP 81 intel Table 7 6 Electrical Specifications Processor System Agent O Buffer Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note VccsA Voltage for the system agent 0 879 0 925 0 971 V 2 Processor I O supply voltage for VDDQ DDR3 1 425 1 5 1 575 V PLL supply voltage DC AC specification Tent Lg 1783 y Processor I O supply voltage for 257 30 Vccio other than DDR3 2 3 1 05 2 3 V 3 Isa Current for the system agent 8 8 A Sustained current for the system Isa agent y 8 2 A Processor I O supply current for IppQ DDR3 4 75 A 1 Processor I O supply sustained _ 4 75 A DDQ current for DDR3 1 Processor I O supply standby 1 STANDBY current for DDR3 PLL supply current 1 5 Icc PLL sustained supply current 0 93 Icc vccio Processor I O supply current 8 5 I Processor I O supply sustained 8 5 A CC VCCIO TDC current zu 82 Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be
18. used as well as memory traffic patterns generated by other connected I O devices The target behavior is to enter self refresh as long as there are no memory requests to service When entering the S3 Suspend to RAM STR state or SO conditional self refresh the processor core flushes pending cycles and then enters all SDRAM ranks into self refresh The CKE signals remain LOW so the SDRAM devices perform self refresh 54 Datasheet Volume 1 Power Management 4 3 2 3 4 3 2 4 4 4 Note Note 4 5 Dynamic Power down Operation Dynamic power down of memory is employed during normal operation Based on idle conditions a given memory rank may be powered down The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state The processor core controller can be configured to put the devices in active power down CKE de assertion with open pages or precharge power down CKE de assertion with all pages closed Precharge power down provides greater power savings but has a bigger performance impact since all pages will first be closed before putting the devices in power down mode If dynamic power down is enabled all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh DRAM I O Power Management Unused signals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused me
19. 0 0 0 0 0 0 0 0 1 2 8 4 5 6 7 75 Datasheet Volume 1 e Electrical Specifications intel Table 7 2 7 6 76 System Agent SA VCC VID The VCCc is configured by the processor output pin VCCSA VID VCCSA VID output default logic state is low for the processors logic high is reserved for future compatibility Table 7 2 specifies the different VCCSA VID configurations VCCSA VID configuration Processor Family VCCSA VID Selected VCCSA 2nd Generation Intel Core processor family desktop Intel Pentium processor family desktop 0 0 925 V Intel Celeron processor family desktop Future Intel processors 1 Note 1 Notes 1 Some of Vccsa configurations are reserved for future Intel processor families Reserved or Unused Signals The following are the general types of reserved RSVD signals and connection guidelines RSVD These signals should not be connected RSVD NCTF These signals are non critical to function and may be left un connected Arbitrary connection of these signals to Vector VDDQ Vecsa VCCAXG Vss or to any other signal including each other may result in component malfunction or incom
20. 1 0 XPDM support Windows 7 XP Windows Vista OSX Linux OS Support DX10 1 DX10 DX9 support OGL 3 0 support Switchable graphics support on desktop AIO platforms with MxM solutions only 1 2 6 Intel Flexible Display Interface Intel FDI For SKUs with graphics Intel FDI carries display traffic from the Processor Graphics in the processor to the legacy display connectors in the PCH Based on DisplayPort standard Two independent links one for each display pipe Four unidirectional downstream differential transmitter pairs Scalable down to 3X 2X or 1X based on actual display bandwidth requirements Fixed frequency 2 7 GT s data rate Two sideband signals for Display synchronization FDI FSYNC and FDI LSYNC Frame and Line Synchronization One Interrupt signal used for various interrupts from the PCH FDI INT signal shared by both Intel FDI Links PCH supports end to end lane reversal across both links Common 100 MHz reference clock Datasheet Volume 1 Introduction 1 3 1 3 1 1 3 2 1 3 3 1 3 4 1 3 5 1 3 6 1 4 intel Power Management Support Processor Core e Full support of Advanced Configuration and Power Interface ACPI C states as implemented by the following processor C states CO C1 C1E C3 C6 e Enhanced Intel SpeedStep Technology System 50 S3 S4 55 Memory Controller Conditional self refresh Intel Rapid Memory Power Management Intel RMPM Dy
21. 4 Memory Reference and Compensation Xm Direction Signal Name Description Buffer Type SM VREF DDR3 Reference Voltage This provides reference voltage to the I DDR3 interface and is defined as Vppo 2 A Datasheet Volume 1 63 Signal Description intel 6 3 Reset and Miscellaneous Signals Table 6 5 Reset and Miscellaneous Signals Direction Signal Name Description Buffer Type Configuration Signals The CFG signals have a default value of 1 if not terminated on the board e CFG 1 0 Reserved configuration lane A test point may be placed on the board for this lane e CFG 2 PCI Express Static x16 Lane Numbering Reversal 1 Normal operation 0 Lane numbers reversed e CFG 3 Reserved CFG 17 0 CFG 4 Reserved configuration lane A test point may be placed on I the board for this lane CMOS e CFG 6 5 PCI Express BifurcationNetet 00 1 x8 2 x4 PCI Express 01 Reserved 10 2 x8 PCI Express 11 1 x16 PCI Express e CFG 17 7 Reserved configuration lanes A test point may be placed on the board for these lands FC x FC signals are signals that are available for compatibility with other processors A test point may be placed on the board for these lands PM SYNC Power Management Sync A sideband signal to communicate power I management status from the platform to the processor CMOS Platform Reset pin driven by the PCH I RESET CMOS RSVD RESERVED All signals t
22. 44 4 3 Integrated Memory Controller States sss sse nennen nnn 44 4 4 PCI Express Link States mer seinen reir a an han dann a ann ann be ea sane ana nnd 44 4 5 Direct Media Interface DMI States 0 ccccccececenecececeececaneneasaeceecceneceaeceeeeeaarasasaeenecees 45 4 6 Processor Graphics Controller 9 8 665 nennen nn en nun une nn emen eee nenn nenn 45 4 7 G Sand C State Combinations zsu2s 20 n0nonnennn nun non nen nun nn nn nun nun nun nun nun nn nun nennen nenn 45 4 8 Coordination of Thread Power States at the Core Level sss 47 4 9 P LVLx to MWAIT ConVversiOn sen an sata ae ead Pe a es ok a Pera ora e CREDE EDD 48 4 10 Coordination of Core Power States at the Package Level ssssesseeesene 50 6 1 Signal Description Buffer 6 nenn sehen eem seen 61 6 2 Memory Channel A Signals eine 62 6 3 Memory Channel B Signals ssi cece nun n nn eee seen nennen nn 63 6 4 Memory Reference and Compensation ussssesenesnnnnnnnnnnnnnen nenn anna nn nenn n nun nennen 63 6 5 Reset and Miscellaneous 9 6 8 5 nn nennen nn nennen nennen nennen eee 64 6 6 PCI Express Graphics Interface 5 5
23. 44500 1 45000 1 45500 1 46000 1 46500 1 47000 1 47500 1 48000 1 48500 1 49000 1 49500 1 50000 1 50500 1 51000 1 51500 1 52000 HEX Vcc E F 0 1 2 3 5 6 7 8 9 B E F 0 1 2 3 4 5 6 7 8 9 B C D E F D 6 D 7 D 8 D 9 D A DB D D D D E E E E E 4 E E E E E EJA E FIA F F F F 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 73000 0 75000 0 81000 0 83000 HEX max 6 0 67500 7 0 68000 8 0 68500 9 0 69000 B 0 70000 C 0 70500 D 0 71000 E 0 71500 F 0 72000 1 3 0 74000 5 E 0 79500 F 0 80000 0 0 80500 1 2 0 81500 3 0 82000 4 0 82500 5 6 0 83500 7 0 84000 8 0 84500 9 0 85000 B 0 86000 C 0 86500 D 0 87000 E 0 87500 F 0 88000 5 5 5 5 5 0 69500 5 5 5 5 5 6 0 0 72500 6 6 2 0 73500 6 6 4 0 74500 6 6 6 0 75500 6 7 0 76000 6 8 0 76500 6 9 0 77000 6 A 0 77500 6 B 0 78000 6 C 0 78500 6 D 0 79000 6 6 7 7 7 7 7 7 7 7 7 7 7 A 0 85500 7 7 7 7 7 0 0 0
24. 6 3 6 1 3 7 40 Technologies Intel Advanced Vector Extensions Intel AVX Intel Advanced Vector Extensions Intel AVX is the latest expansion of the Intel instruction set It extends the Intel Streaming SIMD Extensions Intel SSE from 128 bit vectors into 256 bit vectors Intel AVX addresses the continued need for vector floating point performance in mainstream scientific and engineering numerical applications visual processing recognition data mining synthesis gaming physics cryptography and other areas of applications The enhancement in Intel AVX allows for improved performance due to wider vectors new extensible syntax and rich functionality including the ability to better manage rearrange and sort data For more information on Intel AVX see http www intel com software avx Intel Advanced Encryption Standard New Instructions Intel AES NI The processor supports Advanced Encryption Standard New Instructions Intel AES NI that are a set of Single Instruction Multiple Data SIMD instructions that enable fast and secure data encryption and decryption based on the Advanced Encryption Standard AES Intel AES NI are valuable for a wide range of cryptographic applications such as applications that perform bulk encryption decryption authentication random number generation and authenticated encryption AES is broadly accepted as the standard for both government and industry applications and is widely deployed
25. BCLK_ITP enable debug capacities DBR is used only in systems where no debug port is implemented DBR on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset PRDY is a processor output used by debug tools to determine PRDY processor debug readiness Asynchronous CMOS PREQ is used by debug tools to request debug operation of the I PREQ processor Asynchronous CMOS TCK Test Clock This signal provides the clock input for the I TCK processor Test Bus also known as the Test Access Port TCK must be CMOS driven low or allowed to float during power on Reset TDI Test Data In This signal transfers serial test data into the I TDI processor TDI provides the serial input needed for JTAG specification CMOS support TDO Test Data Out This signal transfers serial test data out of the processor TDO provides the serial output needed for JTAG Drai specification support pen rain TMS TMS Test Mode Select A JTAG specification support signal used by I debug tools CMOS TRST TRST Test Reset This signal resets the Test Access Port TAP I logic TRST must be driven low during power on Reset CMOS 66 Datasheet Volume 1 Signal Description 6 9 Error and Thermal Protection Signals Table 6 11 Error and Thermal Protection Signals ntel 3 Direction Signal Name Description Buff
26. ERERLRE CECI RA 71 7 2 Decoupling 6 eee eee 71 7 2 1 Voltage Rail Decoupling cerisa rae RR 71 7 3 Processor Clocking BCLK 0 0 72 7 3 1 Phase Lock Loop PLL Power Supply seseess mmm 72 7 4 Vec Voltage Identification VID nemen ns 72 7 5 System Agent SA VCC VID nee a a SR DR E RR 76 7 6 Reserved or Unused Signals ere enhn hance enne a ana Sa 76 7 7 Signal Groups eoe na rua eds nha aca aA E oe Lxx Quo da eee da a RR re 77 7 8 Test Access Port TAP Connection nn a a ao de FR RR YAN FR MR MEE 78 7 9 Storage Conditions Specifications erectione casas cans t tu nn ea a RR Rd 79 FAG DC Specification S s ced iba ea 80 7 10 1 Voltage and Current 5 en non neuen nn eee nn nennen nennen nn nn 80 7 11 Platform Environmental Control Interface PECI DC Specifications ss 86 7 11 1 PECI Bus ArchitectUre i a a nenn dade I AO n dE 86 711 2 DC Characternisties ins diae ea Oe Oba emdx e
27. EXiUt ii ioci cesser id E ia nnn pesa sai a an ESENE TERANE 51 7 1 Example for PECI Host clients Connection sssssssssssssssessse eene nnn 86 7 2 Input Device HyStereslS zoo dass naire E ume a redi ee en ee ee 87 8 1 Socket Pinmap Top View Upper Left Quadrant sssssessssssee mmn 90 8 2 Socket Pinmap Top View Upper Right Quadrant sese 91 8 3 Socket Pinmap Top View Lower Left Quadrant eee eee teeta sees eee anne 92 8 4 Socket Pinmap Top View Lower Right Quadrant nenn nennen nennen nn 93 Tables 1 1 PCI Express Supported Configurations in Desktop 5 12 1 2 TOrmiNOlO Gy ARE 16 1 3 Related Documents 1 Int rt ann RA XE EPA eR cba De Paw ar 18 2 1 Supported UDIMM Module 5 eee en nun nn nenn nn nn nenn eene 20 2 2 Supported SO DIMM Module Configurations AIO Only He 20 2 3 DDR3 System Memory Timing SUPPOFt sess nenne nnns 21 2 4 Reference ClOCK uc 33 4 1 System States uiuere BR a a na 44 4 2 Processor Core Package State eee eee eee nenn nenn ann nn nennen nn nnn
28. Environment Developer s Guide http www intel com technology security Intel 64 Architecture x2APIC Specification http www intel com products pr ocessor manuals PCI Express Base Specification 2 0 http www pcisig com DDR3 SDRAM Specification http www jedec org DisplayPort Specification http www vesa org Intel 64 and IA 32 Architectures Software Developer s Manuals http www intel com products pr ocessor manuals index htm Volume 1 Basic Architecture 253665 Volume 2A Instruction Set Reference A M 253666 Volume 2B Instruction Set Reference N Z 253667 Volume 3A System Programming Guide 253668 Volume 3B System Programming Guide 253669 55 Datasheet Volume 1 Interfaces intel 2 Interfaces This chapter describes the interfaces supported by the processor 2 1 System Memory Interface 2 1 1 System Memory Technology Supported The Integrated Memory Controller IMC supports DDR3 protocols with two independent 64 bit wide channels each accessing one or two DIMMs The type of memory supported by the processor is dependant on the PCH SKU in the target platform Refer to Chapter 1 for supported memory configuration details It supports a maximum of two DDR3 DIMMs per channel thus allowing up to four device ranks per channel DDR3 Data Transfer Rates 1066 MT s PC3 8500 1333 MT s PC3 10600 DDR3 SO DIMM Modules Raw Card A Dual Rank
29. Intel Core i5 2320 i3 2125 i3 2130 and i3 2120T processors 003 e Added Intel Celeron processor family desktop Intel Celeron 4540 64530 45301 and 440 processors e Added Intel Pentium 860 5630 and G630T processors 004 e Added Intel Core i7 2700K processor a 005 e Added Intel Celeron G460 processor E 006 Added Intel Core i5 2550K i5 2450P i5 2380P processors oodd ne e Added Intel Pentium G645 G645T processors September e Added Intel Celeron G555 G550T 6465 processors 2012 008 e Added Intel Celeron 470 processors June 2013 8 8 Datasheet Volume 1 Introduction 1 Note Note Note Note Note Note Note Datasheet Volume 1 Introduction The 2nd Generation Intel Core processor family desktop Intel Pentium processor family desktop and Intel Celeron processor family desktop are the next generation of 64 bit multi core desktop processor built on 32 nanometer process technology Based on a new micro architecture the processor is designed for a two chip platform consisting of a processor and Platform Controller Hub PCH The platform enables higher performance lower cost easier validation and improved x y footprint The processor includes Integrated Display Engine Processor Graphics PCI Express ports and Integrated Memory Controller The processor is designed for desktop platforms It supports up to 12 Processor Graphics execution units EUs
30. Note Table 4 9 Note 4 2 4 4 2 4 1 48 Requesting Low Power I dle States The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub state hints and the HLT instruction for C1 and C1E However software may make C state requests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P_LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions using I O reads For legacy operating systems P_LVLx I O reads are converted within the processor to the equivalent MWAIT C state request Therefore P_LVLx reads do not directly result in 1 0 reads to the system The feature known as I O MWAIT redirection must be enabled in the BIOS The P_LVLx I O Monitor address needs to be set up before using the P_LVLx I O read interface Each P LVLx is mapped to the supported MWAIT Cx instruction as shown in Table 4 9 P_LVLx to MWAIT Conversion P_LVLx MWAIT Cx Notes P_LVL2 MWAIT C3 P_LVL3 MWAIT C6 C6 No sub states allowed The BIOS can write to the C state range field of the PMG_IO_CAPTURE MSR to restrict the range of I O addresses that are trapped and emulate MWAIT like functionality Any P LVLx reads outside of this range does not cause an I O redirection to MWAIT Cx like request They fall through like a normal I O instruction When P LVLx I O i
31. SENSE and VSSAXG SENSE lands 5 PSxrefers to the voltage regulator power state as set by the SVID protocol 6 Each processor is programmed with a maximum valid voltage identification value VID that is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 83 intel Electrical Specifications Table 7 8 DDR3 Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes 9 VIL Input Low Voltage SM VREF 0 1 V 2 4 VIH Input High Voltage SM_VREF 0 1 V 3 Output Low Voltage Vppq 2 Ron _ VoL Ront RTERM i Output High Voltage Vppo 2 V Q DDQ V 4 on Ron Ron RTerm iB uP DQ DDR3 data buffer pull up resistance 24 31 28 6 32 9 Q 5 DDR3 data buffer pull down Row DN DQ resistance 22 88 28 6 34 32 Q 5 R DDR3 on die termination equivalent 83 100 117 7 ODT DQ resistance for data signals 41 5 50 65 DDR3 on die termination DC working point driver set to receive 0 43 Vppg 0 5 Vppo 0 56 Vcc V 7 mode DDR3 clock buffer pull up RON_UP CK resistance 20 8 26 28 6 Q 5
32. The idle counter begins counting at the last incoming transaction arrival It is important to understand that since the power down decision is per rank the MC can find many opportunities to power down ranks even while running memory intensive applications and savings are significant may be a few watts according to the DDR specification This is significant when each channel is populated with more ranks Datasheet Volume 1 53 m 8 Power Management intel Selection of power modes should be according to power performance or thermal trade offs of a given system When trying to achieve maximum performance and power or thermal consideration is not an issue use no power down In a system that tries to minimize power consumption try to use the deepest power down mode possible DLL off or APD DLLoff In high performance systems with dense packaging that is complex thermal design the power down mode should be considered in order to reduce the heating and avoid DDR throttling caused by the heating Control of the power mode through CRB BIOS The BIOS selects by default no power down There are knobs to change the power down selected mode Another control is the idle timer expiration count This is set through PM PDWN config bits 7 0 MCHBAR 4CB0 As this timer is set to a shorter time the MC will have more opportunities to put DDR in power down The minimum recommended value for this register is 15 There is no BIOS ho
33. The processor is offered in an 1155 land LGA package Figure 1 1 shows an example desktop platform block diagram This document provides DC electrical specifications signal integrity differential signaling specifications pinout and signal definitions interface functional descriptions thermal specifications and additional feature information pertinent to the implementation and operation of the processor on its respective platform Throughout this document 2nd Generation Intel Core processor family desktop Intel Pentium processor family desktop and Intel Celeron processor family desktop may be referred to as simply the processor Throughout this document the Intel Core i7 desktop processor series refers to the Intel Core i7 2700K i7 2600K i7 2600S and i7 2600 processors Throughout this document the Intel Core i5 desktop processor series refers to the Intel Core i5 2550K i5 2500K i5 2500S i5 2500T i5 2500 i5 2450P i5 2400 i5 2405S i5 2400S i5 2390T i5 2380P i5 2320 i5 2310 and i5 2300 processors Throughout this document the Intel Core i3 desktop processor series refers to the Intel Core i3 2130 i3 2125 i3 2120 i3 2120T i3 2105 i3 2100 and i3 2100T processors Throughout this document the Intel Pentium processor family desktop refers to the Intel Pentium G870 G860 G860T G850 G840 G645 G645T G640 G540T G630 G630T G620 and G620T processors Throughout
34. and improve power in deeper C states the processor supports C state auto demotion There are two C State auto demotion options C6to C3 C6 C3 To C1 The decision to demote a core from C6 to C3 or C3 C6 to C1 is based on each core s immediate residency history Upon each core C6 request the core C state is demoted to C3 or C1 until a sufficient amount of residency has been established At that point a core is allowed to go into C3 C6 Each option can be run concurrently or individually This feature is disabled by default BIOS must enable it in the PMG CST CONFIG CONTROL register The auto demotion policy is also configured by this register Datasheet Volume 1 49 m 8 Power Management intel 4 2 5 Package C States The processor supports CO C1 C1E C3 and C6 power states The following is a summary of the general rules for package C state entry These apply to all package C states unless specified otherwise A package C state request is determined by the lowest numerical core C state amongst all cores A package C state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C state The platform may allow additional power savings to be realized in the processor For package C states
35. are DC coupled The buffers are not 3 3 V tolerant CMOS CMOS buffers 1 1 V tolerant DDR3 DDR3 buffers 1 5 V tolerant A Analog reference or output May be used as a threshold voltage or for buffer compensation Ref Voltage reference signal Asynchronous Signal has no timing relationship with any reference clock Notes 1 Qualifier for a buffer type Datasheet Volume 1 61 Signal Description intel 6 1 System Memory Interface Signals Table 6 2 Memory Channel A Signals Direction Signal Name Description Buffer Type SA BSI2 0 Bank Select These signals define which banks are selected within _BS 2 0 each SDRAM rank DDR3 SA WE Write Enable Control Signal This signal is used with SA RAS and SA_CAS along with SA_CS to define the SDRAM Commands DDR3 SA RAS RAS Control Signal This signal is used with SA_CAS and SA_WE O along with SA_CS to define the SRAM Commands DDR3 SA CAS CAS Control Signal This signal is used with SA_RAS and SA_WE O along with SA CS to define the SRAM Commands DDR3 Data Strobes SA DQS 8 0 and its complement signal group make SA DQS 8 0 up a differential strobe pair The data is captured at the crossing point I O SA DQSZ 8 0 of SA DQS 8 0 and its SA_DQS 8 0 during read and write DDR3 transactions SA DQ 63 0 Data Bus Channel A data signal interface to the SDRAM data bus IO DDR3 SA 15 0 Memory Address These
36. in various protocols Intel AES NI consists of six Intel SSE instructions Four instructions AESENC AESENCLAST AESDEC and AESDELAST facilitate high performance AES encryption and decryption The other two AESIMC and AESKEYGENASSIST support the AES key expansion procedure Together these instructions provide a full hardware for supporting AES offering security high performance and a great deal of flexibility PCLMULQDQ Instruction The processor supports the carry less multiplication instruction PCLMULQDQ PCLMULQDOQ is a Single Instruction Multiple Data SIMD instruction that computes the 128 bit carry less multiplication of two 64 bit operands without generating and propagating carries Carry less multiplication is an essential processing component of several cryptographic systems and standards Hence accelerating carry less multiplication can significantly contribute to achieving high speed secure computing and communication Intel 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides a key mechanism for interrupt delivery This extension is intended primarily to increase processor addressability Specifically x2APIC e Retains all key elements of compatibility to the xAPIC architecture delivery modes interrupt and processor priorities interrupt sources interrupt destination types Datasheet Volume 1 Technologies intel e Provides extensions to scale processor addre
37. min max specifications 2 Theleakage specification applies to powered devices on the PECI bus 3 The PECI buffer internal pull up resistance measured at 0 75 Vcc o I nput Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 7 2 as a guide for input buffer design Input Device Hysteresis Maximum Vp Minimum Vp Minimum s Valid Input Hysteresis Signal Range Maximum Vy Minimum Vy PECI Low Range PECI Ground 88 Datasheet Volume 1 87 88 Electrical Specifications Datasheet Volume 1 Processor Pin and Signal Information m L D 8 Processor Pin and Signal I nformation 8 1 Processor Pin Assignments The processor pinmap quadrants are shown in Figure 8 1 through Figure 8 4 Table 8 1 provides a listing of all processor pins ordered alphabetically by pin name Datasheet Volume 1 89 Processor Pin and Signal Information intel Figure 8 1 Socket Pinmap Top View Upper Left Quadrant 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ee bonn on ee ee BEE SB_CK 2 iae VCCIO VCCIO AC VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG AB VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG 90 Datasheet Volume 1 Processor Pin and Signal Information Figu
38. near the silicon nalog 6 13 Ground and Non Critical to Function NCTF Signals Table 6 15 Ground and Non Critical to Function NCTF Signals T Direction Signal Name Description Buffer Type VSS Processor ground node GND VSS_NCTF Non Critical to Function These pins are for package mechanical reliability 68 Datasheet Volume 1 Signal Description 6 14 Table 6 16 Processor Internal Pull Up Pull Down Resistors intel Processor Internal Pull Up Pull Down Resistors Signal Name Pull Up Pull Down Rail Value BPM 7 0 Pull Up VCCIO 65 165 Q PRDY Pull Up VCCIO 65 165 Q PREQ Pull Up VCCIO 65 165 Q TCK Pull Down VSS 5 15 TDI Pull Up VCCIO 5 15 TMS Pull Up VCCIO 5 15 TRST Pull Up VCCIO 5 15 CFG 17 0 Pull Up VCCIO 5 15 kQ Datasheet Volume 1 88 69 70 Signal Description Datasheet Volume 1 Electrical Specifications m L 7 7 1 7 2 Caution 7 2 1 Electrical Specifications Power and Ground Lands The processor has VCC VDDQ VCCPLL VCCSA VCCAXG VCCIO and VSS ground inputs for on chip power distribution All power lands must be connected to their respective processor power planes while all VSS lands must be connected to the system ground plane Use of multiple power and ground planes is recommended to reduce I R drop The VCC and VCCAXG lands must be supplied with the voltage determined by the pro
39. not ensured to maintain data integrity SCKE tri state should be enabled by BIOS where appropriate since at reset all rows must be assumed to be populated Datasheet Volume 1 Power Management intel 4 3 2 DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface There are four SDRAM operations associated with the Clock Enable CKE signals that the SDRAM controller supports The processor drives four CKE pins to perform these operations The CKE is one of the power save means When CKE is off the internal DDR clock is disabled and the DDR power is reduced The power saving differs according the selected mode and the DDR type used For more information please refer to the IDD table in the DDR specification The DDR specification defines 3 levels of power down that differ in power saving and in wakeup time 1 Active power down APD This mode is entered if there are open pages when de asserting CKE In this mode the open pages are retained Power saving in this mode is the lowest Power consumption of DDR is defined by IDD3P Exiting this mode is fined by tXP small number of cycles 2 Precharged power down PPD This mode is entered if all banks in DDR are precharged when de asserting CKE Power saving in this mode is intermediate better than APD but less than DLL off Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP Differe
40. on the system as a whole Intel Graphics Performance Modulation Technology Intel GPMT Intel Graphics Power Modulation Technology Intel GPMT is a method for saving power in the graphics adapter while continuing to display and process data in the adapter This method will switch the render frequency and or render voltage dynamically between higher and lower power states supported on the platform based on render engine workload In products where Intel Graphics Dynamic Frequency also known as Turbo Boost Technology is supported and enabled the functionality of Intel GPMT will be maintained by Intel Graphics Dynamic Frequency also known as Turbo Boost Technology Graphics Render C State Render C State RC6 is a technique designed to optimize the average power to the graphics render engine during times of idleness of the render engine Render C state is entered when the graphics render engine blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions When the idleness condition is met the Integrated Graphics will program the VR into a low voltage state 70 4 V through the SVID bus Intel Smart 2D Display Technology Intel S2DDT Intel S2DDT reduces display refresh memory traffic by reducing memory reads required for display refresh Power consumption is reduced by less accesses to the IMC S2DDT is only enabled in single pipe mode Intel S2DDT is most e
41. signals are used to provide the multiplexed MA 15 0 row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel A SDRAM Differential clock signal SA CK 3 0 pair The crossing of the positive edge of SA CK and the negative edge of its complement SA_CK are used to sample the command and DDR3 control signals on the SDRAM SA CK 3 0 SDRAM Inverted Differential Clock Channel A SDRAM Differential 3 0 clock signal pair complement DDR3 Clock Enable 1 per rank Used to e Initialize the SDRAMs during power up Oo SA CKE 3 0 e Power down SDRAM ranks DDR3 Place all SDRAM ranks into and out of self refresh during STR Chip Select 1 per rank Used to select particular SDRAM SA CS 3 0 components during the active state There is one Chip Select for each DDR3 SDRAM rank SA ODT 3 0 On Die Termination Active Termination Control Eus 62 Datasheet Volume 1 Signal Description intel Table 6 3 Memory Channel B Signals i Direction Signal Name Description Buffer Type SB BSI2 0 Bank Select These signals define which banks are selected within BS 2 0 each SDRAM rank DDR3 SB WEZ Write Enable Control Signal This signal is used with SB RAS and SB_CAS along with SB_CS to define the SDRAM Commands DDR3 SB RAS RAS Control Signal This signal is used with SB_CAS and SB_WE O along with SB_CS to d
42. this document the Intel Celeron processor family desktop refers to the Intel Celeron G555 G550 65501 G540 G540T G530 G530T 6470 G465 G460 and G440 processors Throughout this document the Intel 6 Series Chipset Platform Controller Hub may also be referred to as PCH Some processor features are not available on all platforms Refer to the processor specification update for details intel Introduction Figure 1 1 Desktop Platform System Block Diagram Example PCI Express 2 0 DDR3 1 x16 or 2x8 Discrete Graphics PEG Processor e PECI Intel Flexible Display DMI2 x4 Interface Serial ATA Intel Management Engine Platform USB20 Controller Hub PCH Intel HD Audio Digital Display x 3 LVDS Flat Panel Analog CRT SPI Flash x2 SMBUS 2 0 SPI Controller Link 1 WH PCI Express WiFi WiMax 8 PCI Express 2 0 x1 5 GT s GPIO 10 Datasheet Volume 1 Introduction intel 1 1 Processor Feature Details Four or two execution cores A 32 KB instruction and 32 KB data first level cache L1 for each core A 256 KB shared instruction data second level cache L2 for each core Up to 8 MB shared instruction data third level cache L3 shared among all cores 1 1 1 Supported Technologies Intel virtualization Technology Intel VT for Directed I O Intel VT d Intel Virtualization Tech
43. xcu ins 87 Datasheet Volume 1 5 7 11 3 Input Device ee Re a 87 8 Processor Pin and Signal Information ann nn nennen en eee ee nenn nn 89 8 1 Processor Pin Assignments oeste He En 89 9 DDR Data SwizzZling denter ek an tenaci nante aa KR DR a Rd a RIA DE 109 Figures 1 1 Desktop Platform System Block Diagram Example nennen nennen nn nn nennen 10 2 1 Intel Flex Memory Technology Operation eese nennen nn 22 2 2 PCLExpress Layering Diagramm rennen a sae sx SR xxt eR Bene Eh 24 2 3 Packet Flow through the L y6ts ai na ea a RR ERRARE dear tener 25 2 4 PCI Express Related Register Structures in the Processor unusesnsnnnenennnnnnn nenn namen nn 26 2 5 PCI Express Typical Operation 16 lanes Mapping esssssses mm 27 2 6 Processor Graphics Controller Unit Block Diagram sse 28 2 7 Processor Display Block 6 onen nun en nenn nenn anne nennen en nnn 31 4 1 Power States EEE 43 4 2 Idle Power Management Breakdown of the Processor Cores 47 4 3 Thread and Core C State Entry and Exit sissien orn ea e A E nenn namen an nun nenn 47 4 4 Package C State Entry and
44. 0 138 52 SA DQ 10 AR3 DQ14 SA DQ 51 AJ37 53 SA DQ 11 ARA DQ15 SA 52 AL39 DQ49 SA DQ 12 AN2 DQ09 SA 53 AL38 DQ50 SA DQ 13 AN3 DQ10 SA DQ 54 139 DQ54 SA DQ 14 AR2 DQ13 SA 55 AJ40 DQ55 SA DQ 15 AR1 DQ12 SA 56 AG40 DQ58 SA DQ 16 AV2 DQ18 SA DQ 57 AG37 DQ56 SA DQ 17 AW3 DQ19 SA 58 AE38 DQ60 SA DQ 18 5 DQ22 SA 59 AE37 DQ61 SA DQ 19 AW5 DQ20 SA DQ 60 AG39 DQ57 SA DQ 20 AU2 DQ16 SA DQ 61 AG38 DQ59 SA DQ 21 AU3 DQ17 SA 62 AE39 DQ63 SA DQ 22 AUS DQ21 SA 63 AE40 DQ62 SA 23 5 DQ23 SA DQ 24 AY7 DQ27 SA DQ 25 AU7 DQ25 SA DQ 26 AV9 DQ28 SA 27 AU9 DQ29 SA 28 AV7 DQ24 SA DQ 29 AW7 DQ26 SA DQ 30 AW9 DQ30 SA DQ 31 AY9 DQ31 SA DQ 32 AU35 DQ35 SA 33 AW37 DQ34 SA DQ 34 AU39 DQ38 SA DQ 35 36 DQ39 SA DQ 36 AW35 DQ33 SA DQ 37 AY36 DQ32 SA DQ 38 AU38 DQ36 SA DQ 39 37 DQ37 SA DQ 40 AR40 DQ43 Datasheet Volume 1 DDR Data Swizzling intel Table 9 2 DDR Data Swizzling Table 9 2 DDR Data Swizzling Table Channel B Table Channel B Pin Name Pin MC Pin Name Pin Name Pin MC Pin Name SB_DQI0 AG7 DQ03 SB DQ 41 AP31 DQ43 SB DQ 1 AG8 2 5 42 35 DQ45 SB DQI 2 AJ9 D005 SB DQ 43 AP34 DQ46 SB DQ 3 AJ8 DQ04 SB DQ 44 AR32 DQ40 SB DQ 4 AG5 DQOO SB DQ 45 AR31 DQ4
45. 1 42 Technologies Datasheet Volume 1 Power Management intel 4 Power Management This chapter provides information on the following power management topics Advanced Configuration and Power Interface ACPI States e Processor Core e Integrated Memory Controller IMC PCI Express e Direct Media Interface DMI e Processor Graphics Controller Figure 4 1 Power States CO Active mode C1 Auto halt C1E Auto halt low freq low voltage C3 L1 L2 caches flush clocks off C6 save core states before shutdown C7 similar to C6 L3 flush Note Power states availability may vary between the different SKUs Datasheet Volume 1 43 4 1 1 Table 4 1 4 1 2 Table 4 2 4 1 3 Table 4 3 4 1 4 Table 4 4 44 Power Management Advanced Configuration and Power Interface ACPI States Supported The ACPI states supported by the processor are described in this section System States System States State Description G0 SO Full On G1 S3 Cold Suspend to RAM STR Context saved to memory S3 Hot is not supported by the processor G1 S4 Suspend to Disk STD All power lost except wakeup on PCH G2 S5 Soft off All power lost except wakeup on PCH Total reboot G3 Mechanical off All power removed from system Processor Core Package Idle States Processor Core Package State Support State Description co A
46. 2 SB DQ 5 AG6 DQO1 SB DQ 46 AR35 DQ47 SB DQ 6 AJ6 DQ06 SB DQ 47 AR34 DQ41 SB DQI 7 17 DQ07 SB DQ 48 AM32 DQ51 SB_DQ 8 AL7 DQ11 SB DQ 49 AM31 DQ48 SB 9 AM7 DQ10 SB DQ 50 AL35 DQ53 SB DQ 10 AM10 DQ14 SB DQ 51 AL32 DQ50 SB DQ 11 AL10 DQ13 SB DQ 52 AM34 DQ52 SB DQ 12 AL6 08 SB DQ 53 AL31 DQ49 SB DQ 13 6 DQ09 SB DQ 54 AM35 DQ54 SB DQ 14 AL9 DQ12 SB DQ 55 AL34 DQ55 SB DQ 15 DQ15 SB 56 AH35 DQ59 SB DQ 16 AP7 DQ19 SB DQ 57 AH34 DQ58 SB DQ 17 AR7 DQ18 SB 58 AE34 DQ61 SB DQ 18 AP10 DQ21 SB DQ 59 AE35 DQ62 SB DQ 19 AR10 DQ22 SB DQ 60 135 DQ57 SB DQ 20 AP6 DQ17 SB DQ 61 134 DQ56 SB DQ 21 AR6 DQ16 SB DQ 62 AF33 DQ63 SB DQ 22 AP9 DQ20 SB DQ 63 AF35 DQ60 SB DQ 23 ARQ DQ23 SB DQ 24 AM12 DQ25 SB DQ 25 AM13 DQ30 SB DQ 26 AR13 DQ29 SB DQ 27 AP13 DQ28 88 SB DQ 28 AL12 DQ24 SB DQ 29 AL13 DQ31 SB DQ 30 AR12 DQ27 SB DQ 31 AP12 DQ26 SB DQ 32 AR28 DQ32 SB DQ 33 AR29 DQ34 SB DQ 34 AL28 DQ39 SB DQ 35 AL29 DQ37 SB DQ 36 AP28 DQ33 SB DQ 37 AP29 DQ35 SB DQ 38 AM28 DQ36 SB DQ 39 AM29 DQ38 SB DQ 40 AP32 DQ44 Datasheet Volume 1 112 DDR Data Swizzling Datasheet Volume 1
47. 20 must be within the specified range by the time Detect is entered 10 Low impedance defined during signaling Parameter is captured for 5 0 GHz by RLTX DIFF 11 These are pre silicon estimates and are subject to change Datasheet Volume 1 85 e Electrical Specifications intel 7411 1 Figure 7 1 86 Platform Environmental Control I nterface PECI DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices The processor contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control More detailed information is provided in the Platform Environment Control Interface PECI Specification PECI Bus Architecture The PECI architecture based on wired OR bus that the clients as processor PECI can pull up high with strong drive The idle state on the bus is near zero Figure 7 1 demonstrates PECI design and connectivity while the host originator can be 3rd party PECI host and one of the PECI clients is the processor PECI device Example for PECI Host clients Connecti
48. 3 SA_DQ 61 AG38 DDR3 I O SA_MA 15 AT20 DDR3 SA_DQ 62 AE39 DDR3 SA ODT 0 AV31 DDR3 SA 63 AE40 DDR3 SA_ODT 1 AU32 DDR3 SA 5 0 3 DDR3 SA ODT 2 AU30 DDR3 SA DQS 1 AP3 DDR3 I O SA ODT 3 AW33 DDR3 SA DQS 2 AWA DDR3 1 0 SA_RAS AU28 DDR3 SA DQS 3 AV8 DDR3 SA_WE AW29 DDR3 SA DQS 4 AV37 DDR3 SB BS 0 AP23 DDR3 SA DQS 5 AP38 DDR3 I O SB_BS 1 AM24 DDR3 Datasheet Volume 1 97 m 8 n tel Processor Pin and Signal I nformation Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin 4 Buffer Type Dir SB BS 2 AW17 DDR3 SB DQ 26 AR13 DDR3 7 SB_CAS AK25 DDR3 SB DQ 27 AP13 DDR3 I O SB CK 0 AL21 DDR3 SB DQ 28 AL12 DDR3 SB CK 1 AL20 DDR3 SB DQ 29 AL13 DDR3 1 0 SB_CK 2 AL23 DDR3 SB DQ 30 AR12 DDR3 1 0 SB CK 3 AP21 DDR3 SB DQ 31 AP12 DDR3 1 0 SB_CK 0 AL22 DDR3 SB DQ 32 AR28 DDR3 SB_CK 1 AK20 DDR3 SB DQ 33 AR29 DDR3 1 SB_CK 2 AM22 DDR3 SB DQ 34 AL28 DDR3 1 0 SB_CK 3 AN21 DDR3 SB DQ 35 AL29 DDR3 1 0 SB CKE 0 AU16 DDR3 SB DQ 36 AP28 DDR3 1 0 SB_CKE 1 AY15 DDR3 FSB DQ 37 AP29 DDR yo SB CKE 2 AW15 DDR3 SB DQ 38 AM28 DDR3 1 0 SB_CKE 3 AV15 DDR3 SB DQ
49. 39 AM29 DDR3 1 0 SB_CS 0 AN25 DDR3 SB DQ 40 AP32 DDR3 1 0 SB_CS 1 AN26 DDR3 SB DQ 41 AP31 DDR3 1 0 SB_CS 2 AL25 DDR3 SB DQ 42 AP35 DDR3 1 0 SB_CS 3 AT26 DDR3 SB DQ 43 AP34 DDR3 1 0 SB DQ 0 AG7 DDR3 1 0 SB DQ 44 AR32 DDR3 7 SB DQ 1 8 DDR3 1 0 SB DQ 45 AR31 DDR3 1 0 SB DQ 2 AJ9 DDR3 1 0 SB DQ 46 AR35 DDR3 1 0 SB DQ 3 AJ8 DDR3 1 0 SB DQ 47 AR34 DDR3 1 0 SB DQ 4 AG5 DDR3 1 0 SB DQ 48 AM32 DDR3 1 0 SB DQ 5 AG6 DDR3 1 0 SB DQ 49 AM31 DDR3 1 0 SB_DQ 6 AJ6 DDR3 1 0 SB DQ 50 AL35 DDR3 1 0 SB DQ 7 AJ7 DDR3 1 0 SB DQ 51 AL32 DDR3 7 SB DQ 8 AL7 DDR3 SB DQ 52 34 DDR3 1 0 SB_DQ 9 AM7 DDR3 1 0 SB DQ 53 AL31 DDR3 SB DQ 10 AM10 DDR3 1 0 SB DQ 54 AM35 DDR3 1 0 SB_DQ 11 AL10 DDR3 1 0 SB DQ 55 AL34 DDR3 7 SB DQ 12 AL6 DDR3 1 0 SB DQ 56 AH35 DDR3 1 0 SB DQ 13 AM6 DDR3 1 0 SB DQ 57 AH34 DDR3 1 0 SB DQ 14 AL9 DDR3 1 0 SB DQ 58 AE34 DDR3 1 0 SB_DQ 15 AM9 DDR3 1 0 SB DQ 59 AE35 DDR3 1 0 SB DQ 16 AP7 DDR3 1 0 SB DQ 60 AJ35 DDR3 1 0 SB DQ 17 AR7 DDR3 1 0 SB DQ 61 AJ34 DDR3 7 SB DQ 18 AP10 DDR3 1 0 SB DQ 62 AF33 DDR3 7 SB DQ 19 AR10 DDR3 1 0 SB DQ 63 AF35 DDR3 7 SB DQ 20 AP6 DDR3 1 0 SB DQS 0 AH7 DDR3 1 0 SB DQ 21 AR6 DDR3 1 0 SB DQS 1 AM8 DDR3 SB DQ 22 AP9 DDR3 SB DQS 2 8 DDR3 SB DQ 23 ARQ DDR3 yo SB DQS3 ANI3 DDR3 vo SB DQ 24 AM12 DDR3 1 0 SB DQS 4 AN29 DDR3 7 SB DQ 25 AM13 DDR3 1 0 SB DQS 5 AP33 DDR3 1 0
50. 5 PWR VCC E19 PWR VCC H16 PWR VCC E21 PWR VCC H18 PWR VCC E22 PWR VCC H19 PWR VCC E24 PWR VCC H21 PWR VCC E25 PWR VCC H22 PWR VCC E27 PWR VCC H24 PWR VCC E28 PWR VCC H25 PWR VCC E30 PWR VCC H27 PWR VCC E31 PWR VCC H28 PWR VCC E33 PWR VCC H30 PWR VCC E34 PWR VCC H31 PWR VCC E35 PWR VCC H32 PWR VCC F15 PWR VCC 112 PWR VCC F16 PWR VCC 115 PWR VCC F18 PWR 116 PWR VCC F19 PWR VCC J18 PWR VCC F21 PWR VCC J19 PWR VCC F22 PWR VCC J21 PWR VCC F24 PWR VCC J22 PWR vce F25 PwR vcc 124 PWR VCC F27 PWR VCC 125 PWR VCC F28 PWR VCC 127 PWR 100 Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VCC 128 PWR VCCAXG AB38 PWR VCC 130 PWR VCCAXG AB39 PWR VCC K15 PWR VCCAXG AB40 PWR VCC K16 PWR VCCAXG AC33 PWR VCC K18 PWR VCCAXG AC34 PWR VCC K19 PWR VCCAXG AC35 PWR VCC K21 PWR VCCAXG AC36 PWR VCC K22 PWR VCCAXG AC37 PWR VCC K24 PWR VCCAXG AC38 PWR VCC K25 PWR VCCAXG AC39 PWR VCC K27 PWR VCCAXG AC40 PWR VCC K28 PWR VCCAXG T33 PWR VCC K30 PWR VCCAXG T34 PWR VCC L13 PWR VCCAXG T35 PWR VCC L14 PWR VCCAXG 36 PWR VCC L15 PWR VCCAXG T37 PWR VCC L16 PWR VCCAXG 38 PWR VCC L18 PWR VCCAXG T39 PWR VCC L19 PWR VCC
51. 7 PS1 13 PS2 11 5 Ripple 2011D 2011C 2011B processors with 95 W 65 W and 45 W TDPs 356 VccRipple PSO 7 mV UU PS1 10 PS2 10 25 Vcc Loadline Slope 3 5 6 LL 2 9 Q i d u 2011A processors with 35 W TDP 8 Vcc Tolerance Band 2011A processors with 35 W TDP VecTOB PSO 19 296 PS1 19 PS2 11 5 Ripple 2011A processors with 35 W TDP VecRipple PSO 10 PS1 10 i PS2 10 25 Default Vcc voltage for initial _ _ Vec 800T power up 0 V 2011D processors with 95 W Icc TDPs Icc 112 A 4 ie 2011C processors with 65 W TDP _ 75 A 4 Datasheet Volume 1 Electrical Specifications intel Table 7 5 Processor Core Active and Idle Mode DC Voltage and Current Specifications Sheet 2 of 2 Symbol Parameter Min Typ Max Unit Note Icc en processors with 45 W TDP _ 60 4 Icc E 1A processors with 35 W TDP m 35 A 4 ined 2011D processors with 95 W 85 A 4 TDPs Sustained Icc I 2011C processors with 65 W TDP m 55 A 4 Sustained Icc 2011B processors with 45 W TDP z _ Sustained Icc 8 A 4 I 2011A processors with 35 W TDP _ 25 A 4 Sustained Icc Notes 1 QUUD Datasheet Volume 1 Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurem
52. 7 DDR3 1 0 SA_DQS 0 AK2 DDR3 1 0 SA_DQ 30 AW9 DDR3 1 0 SA_DQS 1 AP2 DDR3 1 0 SA DQ 31 AY9 DDR3 SA_DQS 2 AV4 DDR3 1 0 SA DQ 32 AU35 DDR3 I O SA_DQS 3 AW8 DDR3 I O SA DQI 33 AW37 DDR3 1 0 SA_DQS 4 AV36 DDR3 1 0 SA DQ 34 AU39 DDR3 SA DQSZ 5 AP39 DDR3 I O SA DQ 35 AU36 DDR3 SA_DQS 6 AK39 DDR3 1 0 SA DQ 36 AW35 DDR3 I O SA DQSZ 7 AF39 DDR3 1 0 SA_DQ 37 AY36 DDR3 I O SA_DQS 8 AV12 DDR3 I O SA_DQ 38 AU38 DDR3 I O RSVD AU12 DDR3 1 0 SA DQ 39 AU37 DDR3 RSVD AU14 DDR3 I O SA DQ 40 AR40 DDR3 1 0 RSVD AW13 DDR3 1 0 SA DQ 41 AR37 DDR3 1 0 RSVD AY13 DDR3 1 0 SA_DQ 42 AN38 DDR3 1 0 RSVD AU13 DDR3 1 0 SA DQ 43 AN37 DDR3 RSVD AU11 DDR3 I O SA DQ 44 AR39 DDR3 1 0 RSVD AY12 DDR3 I O SA_DQ 45 AR38 DDR3 I O RSVD AW12 DDR3 7 SA DQ 46 AN39 DDR3 1 0 SA MA 0 AV27 DDR3 SA DQ 47 AN40 DDR3 SA MA 1 AY24 DDR3 SA DQ 48 AL40 DDR3 1 0 SA_MA 2 AW24 DDR3 SA DQ 49 AL37 DDR3 I O SA MA 3 AW23 DDR3 SA DQ 50 AJ38 DDR3 7 SA MA 4 AV23 DDR3 SA DQ 51 AJ37 DDR3 SA MA 5 AT24 DDR3 SA DQ 52 AL39 DDR3 I O SA MA 6 AT23 DDR3 SA 53 AL38 DDR3 1 0 SA MA 7 AU22 DDR3 SA DQ 54 AJ39 DDR3 1 0 SA MA 8 AV22 DDR3 SA DQ 55 AJ40 DDR3 SA MA 9 AT22 DDR3 SA DQ 56 AG40 DDR3 SA_MA 10 AV28 DDR3 SA DQ 57 AG37 DDR3 SA_MA 11 AU21 DDR3 SA DQ 58 AE38 DDR3 I O SA_MA 12 AT21 DDR3 SA DQ 59 AE37 DDR3 I O SA MA 13 AW32 DDR3 SA DQ 60 AG39 DDR3 I O SA MA 14 AU20 DDR
53. A remap engine DMI PEG Support for root entry context entry and default context 39 bit guest physical address and host physical address widths Support for 4K page sizes only Support for register based fault recording only for single entry only and support for MSI interrupts for faults Support for both leaf and non leaf caching Support for boot protection of default page table Support for non caching of invalid page table entries Support for hardware based flushing of translated but pending writes and pending reads on IOTLB invalidation Support for page selective IOTLB invalidation MSI cycles MemWr to address FEEx_xxxxh not translated Translation faults result in cycle forwarding to VBIOS region byte enables masked for writes Returned data may be bogus for internal agents PEG DMI interfaces return unsupported request status Interrupt Remapping is supported Queued invalidation is supported VT d translation bypass address range is supported Pass Through Note Intel VT d Technology may not be available on all SKUs 3 1 5 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Features Not Supported The following features are not supported by the processor with Intel VT d Datasheet Volume 1 No support for PCISIG endpoint caching ATS No support for Intel VT d read prefetching snarfing that is translations within a cacheline are not stored in an internal buffer for reuse for subsequen
54. AXG T40 PWR VCC L21 PWR VCCAXG U33 PWR VCC L22 PWR VCCAXG U34 PWR VCC L24 PWR VCCAXG U35 PWR VCC L25 PWR VCCAXG U36 PWR VCC L27 PWR VCCAXG U37 PWR VCC L28 PWR VCCAXG U38 PWR VCC L30 PWR VCCAXG U39 PWR VCC M14 PWR VCCAXG U40 PWR VCC M15 PWR VCCAXG w33 PWR VCC M16 PWR VCCAXG W34 PWR VCC M18 PWR VCCAXG w35 PWR VCC M19 PWR VCCAXG W36 PWR VCC M21 PWR VCCAXG w37 PWR VCC M22 PWR VCCAXG w38 PWR VCC M24 PWR VCCAXG Y33 PWR VCC M25 PWR VCCAXG Y34 PWR VCC M27 PWR VCCAXG Y35 PWR VCC M28 PWR VCCAXG Y36 PWR VCC M30 PWR VCCAXG Y37 PWR VCC_SENSE A36 Analog VCCAXG 38 PWR VCCAXG AB33 PWR VCCAXG_SENSE L32 Analog VCCAXG AB34 PWR VCCIO A11 PWR VCCAXG AB35 PWR VCCIO A7 PWR VCCAXG AB36 PWR VCCIO 3 PWR VCCAXG AB37 PWR VCCIO AB8 PWR Datasheet Volume 1 101 intel 102 Processor Pin and Signal Information Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VCCIO AF8 PWR VCCPLL AK12 PWR VCCIO AG33 PWR VCCSA H10 PWR VCCIO AJ16 PWR VCCSA H11 PWR VCCIO AJ17 PWR VCCSA H12 PWR VCCIO 126 PWR VCCSA J10 PWR VCCIO 128 PWR VCCSA K10 PWR VCCIO AJ32 PWR VCCSA PWR VCCIO AK15 PWR VCCSA L11 PWR VCCIO AK17 PWR VCCSA L12 PWR VCCIO AK19 PWR VCCSA M10 PWR VCCIO AK21 PWR VCCSA M11 PWR VC
55. CIO AK23 PWR VCCSA M12 PWR VCCIO AK27 PWR VCCSA SENSE T2 Analog VCCIO 29 PWR VCCSA_VID P34 CMOS VCCIO AK30 PWR VDDQ AJ13 PWR VCCIO B9 PWR VDDQ AJ14 PWR VCCIO D10 PWR VDDQ AJ20 PWR VCCIO D6 PWR VDDQ AJ23 PWR VCCIO E3 PWR VDDQ AJ24 PWR VCCIO E4 PWR VDDQ AR20 PWR VCCIO G3 PWR VDDQ AR21 PWR VCCIO G4 PWR VDDQ AR22 PWR VCCIO 13 PWR VDDQ AR23 PWR VCCIO 14 PWR VDDQ AR24 PWR VCCIO 17 PWR VDDQ AU19 PWR VCCIO J8 PWR VDDQ AU23 PWR VCCIO L3 PWR VDDQ AU27 PWR VCCIO L4 PWR VDDQ AU31 PWR VCCIO L7 PWR VDDQ AV21 PWR VCCIO M13 PWR VDDQ AV24 PWR VCCIO N3 PWR VDDQ AV25 PWR VCCIO N4 PWR VDDQ AV29 PWR VCCIO N7 PWR VDDQ AV33 PWR VCCIO R3 PWR VDDQ AW31 PWR VCCIO RA PWR VDDQ AY23 PWR VCCIO R7 PWR VDDQ AY26 PWR VCCIO U3 PWR VDDQ AY28 PWR VCCIO U4 PWR VIDALERT A37 CMOS I VCCIO U7 PWR VIDSCLK C37 CMOS VCCIO v8 PWR VIDSOUT B37 CMOS VCCIO w3 PWR VSS A17 GND VCCIO_SEL P33 N A O VSS A23 GND VCCIO_SENSE AB4 Analog O VSS A26 GND VCCPLL AK11 PWR VSS A29 GND Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VSS A35 GND VSS AJ25 GND VSS AA33 GND VSS AJ27 GND VSS AA34 GND VSS AJ36 GND VSS AA35 GND VSS AJ5 GND VSS AA36 GND V
56. Command launch mode programming depends on the transfer rate and memory configuration Table 2 3 DDR3 System Memory Timing Support Transfer tRCD tRP CWL CMD Segment iMi tCK tCK tCK tcK ppc Mode Notes s 1 1n 2n 7 7 7 6 2 2n 1066 1 TE All Deskt nen 8 8 6 2 2n 1 1n 2n 1333 9 9 9 7 2 2n Notes 1 System memory timing support is based on availability and is subject to change 2 1 3 System Memory Organization Modes The IMC supports two memory organization modes single channel and dual channel Depending upon how the DIMM Modules are populated in each memory channel a number of different configurations can exist 2 1 3 1 Single Channel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order but not both 2 1 3 2 Dual Channel Mode Intel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode Memory is divided into a symmetric and an asymmetric zone The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached In this mode the system runs with one zone of dual channel mode and one zone of single channel mode simultaneously across the whole memory array Note Channels A and B can be mapped for physical channels 0 and 1 respectively or v
57. DC DC Differential Tx Impedance Gen1 only 80 90 120 Q 1 10 ZRX DC DC Common Mode Rx Impedance 40 45 60 1 8 9 ZRX DIFF DC DC Differential Rx Impedance Gen1 only 80 90 120 Q 1 Differential Rx input Peak to Peak Voltage E VRX DIFFp p Gen1 only 0 175 1 2 V 1 Differential Rx input Peak to Peak Voltage _ VRX DIFFP p Gen2 only 0 12 1 2 V 1 VRX_CM AC p Rx AC peak Common Mode Input Voltage 150 mV 1 7 PEG_ICOMPO Comp Resistance 24 75 25 25 25 Q 4 5 PEG_COMPI Comp Resistance 24 75 25 25 25 4 PEG_RCOMPO Comp Resistance 24 75 25 25 25 Q 4 5 Notes 1 Refer to the PCI Express Base Specification for more details 2 Vrx ac cm pp and Vryx ac cm p are defined in the PCI Express Base Specification Measurement is made over at least 1046 UI 3 As measured with compliance test load Defined as 2 Vtyp Vrxp 4 COMP resistance must be provided on the system board with 1 resistors 5 PEG ICOMPO PEG COMPI PEG RCOMPO are the same resistor 6 RMS value 7 Measured at Rx pins into a pair of 50 terminations into ground Common mode peak voltage is defined by the expression max Vd Vd V CMDC 8 DC impedance limits are needed to ensure Receiver detect 9 The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance constrained by RLRX CM to 50 Q
58. DI_TX 5 8 FDI CFG 6 L37 CMOS I FDI_TX 6 AF2 FDI CFG 7 M36 CMOS I FDI_TX 7 AG1 FDI CFG 8 138 CMOS I NCTF A38 CFG 9 L35 CMOS I NCTF AU40 DBR E39 Async CMOS AW38 DMI_RX 0 w5 DMI I NCTF c2 DMI_RX 1 v3 DMI I NCTF D1 DMI_RX 2 3 DMI I RX 0 P3 PCI Express I DMI_RX 3 AAA DMI I PE RX 1 R2 PCI Express I DMI_RX 0 w4 DMI I PE RX 2 T4 PCI Express I DMI_RX 1 v4 DMI I PE RX 3 U2 PCI Express I DMI_RX 2 Y4 DMI I PE_RX 0 P4 PCI Express I DMI_RX 3 5 DMI I PE_RX 1 R1 PCI Express I DMI TX 0 v7 DMI PE_RX 2 3 PCI Express I DMI_TX 1 W7 DMI RX 3 U1 PCI Express I DMI_TX 2 Y6 DMI O PE_TX 0 P8 PCI Express DMI_TX 3 7 DMI PE TX 1 T7 PCI Express Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir PE_TX 2 R6 PCI Express 9 PEG TX 2 G14 PCI Express 3 U5 PCI Express Oo PEG TX 3 F12 PCI Express PE_TX 0 P7 PCI Express PEG_TX 4 114 PCI Express PE_TX 1 T8 PCI Express PEG_TX 5 D8 PCI Express PE_TX 2 R5 PCI Express PEG_TX 6 D3 PCI Express PE_TX 3 U6 PCI Express PEG TX 7 E6 PCI Express
59. E B36 Analog O VSSAXG_SENSE M32 Analog O VSSIO_SENSE AB3 Analog 0 88 Datasheet Volume 1 107 n tel Processor Pin and Signal I nformation 108 Datasheet Volume 1 DDR Data Swizzling intel 9 DDR Data Swizzling To achieve better memory performance and better memory timing Intel design performed the DDR Data pin swizzling that will allow a better use of the product across different platforms Swizzling has no effect on functional operation and is invisible to the OS SW However during debug swizzling needs to be taken into consideration This chapter presents swizzling data When placing a DIMM logic analyzer the design engineer must pay attention to the swizzling table to perform an efficient memory debug Datasheet Volume 1 109 intel 110 DDR Data Swizzling Table 9 1 DDR Data Swizzling Table 9 1 DDR Data Swizzling Table Channel A Table Channel A Pin Name Pin MC Pin Name Pin Name Pin MC Pin Name SA_DQ 0 AJ3 DQO1 SA DQ 41 AR37 DQ42 SA DQ 1 AJA DQ02 SA DQ 42 AN38 DQ44 SA 2 AL3 DQ07 SA 43 AN37 DQ45 SA 3 AL4 DQO6 SA DQ 44 AR39 DQ41 SA_DQ 4 AJ2 DQ03 SA 45 AR38 DQ40 SA DQ 5 Alt DQ00 SA DQ 46 AN39 DQ46 SA DQI6 AL2 05 SA DQ 47 AN40 DQ47 SA_DQ 7 AL1 DQ04 48 40 DQ51 SA DQI8 AN1 DQ08 SA DQ 49 AL37 DQ48 SA 9 ANA DQ11 SA DQ 5
60. For more information including details on which processors support HT Technology see htp www intel com info hyperthreading Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see http www intel com technology turboboost Enhanced Intel SpeedStep Technology See the Processor Spec Finder or contact your Intel representative for more information Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See www intel com products processor number for details 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release Customers licensees and other third parties are not authorized by Intel to use code names in advertising promotion or marketing of any product or servic
61. Memory Controller States ssesssssssssseeem e 44 4 1 4 JPCLExpress Link States 00a cues xa naar nennen 44 4 1 5 Direct Media Interface DMI States sssesssssssssss nemen 45 4 1 6 Processor Graphics Controller States ssssssssssseseeemm e 45 4 1 7 Interface State Combinatiohs 1 tene etes nee a ana 45 4 2 Processor Core Power Management eisini cnn eeo ea nn nen nennen nenn nent nn 46 4 2 1 Enhanced Intel SpeedStep Technology eee 46 4 2 2 Low Power Idle States een 46 4 2 3 Requesting Low Power Idle 5 5 48 wr MEG C State PELLIT 48 4 2 4 1 Core CO State a n URREREKIRRAREEAK a 48 4 2 4 2 Core EL CIE State vu en ERROR RRERR IRA PAR AREA Ide PA AER oai 49 42 4 3 CORE C3 State nau B Mer Re Duarte 49 Core CO State uicit 49 4 2 4 5 C State Auto DemiotlOFs een een 49 4 2 5 Package a 50 Datasheet Volume 1 4 2 5 1 t en aan nen 51 4 2 5 2 Package 51 4 2 5 3 Package C3 State cis nie ne 52 4 2 5 4 Package nn ann aan de RR RR AREE X ARR 52 4 3 Integrated Memory Controller IMC Power 52 4 3 1 Disabling Unused System Memory Outputs ssss
62. Memory Type Range Registers MTRRs 8 23 2 17 Data 5 8 trm 23 2 2 PGLExpress Interface ee anne ann eu EA a RR 24 2 2 1 PGI Express Architecture eek 24 2 2 1 1 Transaction nenn nn nn nn ann nn a nn han 25 2 2 1 2 Data Lirik Layer u ecu en mier ved Da na aa hen 25 2 2 1 3 Physical Layer 25 2 2 2 PCI Express Configuration Mechanism 26 2 2 3 PCI Express POFt a a ana a HR 26 2 2 4 PCI Express Lanes 6 eee eee ee nenn nun nennen ieri 27 2 3 Direct Media Interface DMI iiis naar 27 2 3 1 DML Error FOW rinii oL a RR ne d adea REA E 27 2 3 2 Processor PCH Compatibility Assumptions cesses 27 2 3 3 JDMI Link Ex dra inca n ae ae Ba ne 28 2 4 Processor Graphics Controller GT esie esee nnn nenne nan n nada n nnn 28 2 4 1 35 and Video Engines for Graphics Processing ssssseseeese 29 2 4 1 1 3D Engine Execution Units sssssssese emen 29 Datasheet Volume 1 3 p MEI Er nn ke US 29 2 4 1 3 Video Engine u neuen xav uix eene o nn esas 30 2 4 1 4 2D Englne noun ee Sr t bent
63. Output SA RAS SB RAS SA_CAS SB_CAS SA WE SB WE SA MA 15 0 SB MA 15 0 SA BS 2 0 SB BS 2 0 SM DRAMRST SA CS 3 0 58 CS 3 0 SA ODT 3 0 SB ODT 3 0 SA CKE 3 0 SB CKE 3 0 DDR3 Data Signals Single ended DDR3 Bi directional SA_DQ 63 0 SB_DQ 63 0 Differential DDR3 Bi directional SA_DQS 8 0 SA_DQS 8 0 SB_DQS 8 0 SB_DQS 8 0 TAP ITP XDP Open Drain Output Single Ended CMOS Input TCK TDI TMS TRST Single Ended CMOS Output TDO Single Ended Asynchronous CMOS Output TAPPWRGOOD Control Sideband Single Ended CMOS Input CFG 17 0 Single Ended St Single Ended Asynchronous CMOS Output THERMTRIP CATERR Single Ended Asynchronous CMOS Input u UNCOREPWRGOOD PM SYNC Single Ended Asynchronous Bi directional PECI CMOS Input VIDALERT AS Ended on Input Power Ground Other Power VCC VCC_NCTF VCCIO VCCPLL VDDQ VCCAXG Ground No Connect and test point VSS RSVD RSVD_NCTF RSVD_TP FC_x Datasheet Volume 1 77 Electrical Specifications intel Table 7 3 Signal Groups Sheet 2 of 2 1 8 78 Signal Group Type Signals Sense Points VCC_SENSE VSS_SENSE VCCIO_SENSE VSS_SENSE_VCCIO VAXG_SENSE VSSAXG_SENSE Other SKTOCC DBR PCI Express Differential PCI Express Input PEG_RX 15 0 RX 3 0 Differential PCI Ex
64. R SB_MA 9 AY17 DDR3 VCC B34 PWR SB_MA 10 AN23 DDR3 VCC C15 PWR SB MA 11 AU17 DDR3 VCC C16 PWR SB MA 12 AT18 DDR3 VCC C18 PWR SB MA 13 AR26 DDR3 Oo VCC c19 PWR SB_MA 14 AY16 DDR3 Oo VCC C21 PWR SB MA 15 AV16 DDR3 Oo VCC C22 PWR SB_ODT 0 AL26 DDR3 Oo VCC C24 PWR SB ODT 1 AP26 DDR3 Oo VCC C25 PWR SB ODT 2 AM26 DDR3 Oo VCC C27 PWR SB_ODT 3 AK26 DDR3 VCC C28 PWR SB_RAS AP24 DDR3 VCC C30 PWR SB_WE AR25 DDR3 VCC C31 PWR SKTOCC AJ33 Analog VCC C33 PWR SM_DRAMPWROK AJ19 Async CMOS I VCC C34 PWR Datasheet Volume 1 m 8 n tel Processor Pin and Signal I nformation Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin 4 Buffer Type Dir Pin Name Pin Buffer Type Dir VCC C36 PWR VCC F30 PWR VCC D13 PWR VCC F31 PWR VCC D14 PWR VCC F32 PWR VCC D15 PWR VCC F33 PWR VCC D16 PWR VCC F34 PWR VCC D18 PWR VCC G15 PWR VCC D19 PWR VCC G16 PWR VCC D21 PWR VCC G18 PWR VCC D22 PWR VCC G19 PWR VCC D24 PWR VCC G21 PWR VCC D25 PWR VCC G22 PWR vcc dav Pwr G24 PWR VCC D28 PWR VCC G25 PWR VCC D30 PWR VCC G27 PWR VCC D31 PWR VCC G28 PWR VCC D33 PWR VCC G30 PWR VCC D34 PWR VCC G31 PWR VCC D35 PWR VCC G32 PWR VCC D36 PWR VCC G33 PWR VCC E15 PWR VCC H13 PWR VCC E16 PWR VCC H14 PWR VCC E18 PWR VCC H1
65. SS AK1 GND VSS AA37 GND VSS AK10 GND VSS AA38 GND VSS AK13 GND VSS AA6 GND VSS AK14 GND VSS AB5 GND VSS AK16 GND VSS AC1 GND VSS AK22 GND VSS AC6 GND VSS AK28 GND VSS AD33 GND VSS AK31 GND VSS AD36 GND VSS AK32 GND VSS AD38 GND VSS AK33 GND VSS AD39 GND VSS AK34 GND VSS AD40 GND VSS AK35 GND VSS AD5 GND VSS AK36 GND VSS AD8 GND VSS AK37 GND VSS AE3 GND VSS AK4 GND VSS AE33 GND VSS AK40 GND VSS AE36 GND VSS AK5 GND VSS AF1 GND VSS AK6 GND VSS AF34 GND VSS AK7 GND VSS AF36 GND VSS AK8 GND VSS AF37 GND VSS AK9 GND VSS AF40 GND VSS AL11 GND VSS AF5 GND VSS AL14 GND VSS AF6 GND VSS AL17 GND VSS AF7 GND VSS AL19 GND VSS AG36 GND VSS AL24 GND VSS AH2 GND VSS AL27 GND VSS AH3 GND VSS AL30 GND VSS AH33 GND VSS AL36 GND VSS AH36 GND VSS AL5 GND VSS AH37 GND VSS AM1 GND VSS AH38 GND VSS AM11 GND VSS AH39 GND VSS AM14 GND VSS AH40 GND VSS AM17 GND VSS AH5 GND VSS AM2 GND VSS AH8 GND VSS AM21 GND VSS AJ12 GND VSS AM23 GND VSS AJ15 GND VSS AM25 GND VSS AJ18 GND VSS AM27 GND VSS AJ21 GND VSS AM3 GND Datasheet Volume 1 103 m 8 n tel Processor Pin and Signal I nformation Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VSS AM30 GND VSS AR18 GND VSS AM36 GND VSS AR19 GND
66. To determine the highest performance frequency amongst active cores the processor takes the following into consideration The number of cores operating in the CO state The estimated current consumption The estimated power consumption The temperature Any of these factors can affect the maximum frequency for a given workload If the power current or thermal limit is reached the processor will automatically reduce the frequency to stay with its TDP limit Intel Turbo Boost Technology processor frequencies are only active if the operating system is requesting the PO state For more information on P states and C states refer to Chapter 4 Power Management Intel Turbo Boost Technology Graphics Frequency Graphics render frequency is selected by the processor dynamically based on graphics workload demand The processor can optimize both processor and Processor Graphics performance by managing power for the overall package For the Processor Graphics this allows an increase in the render core frequency and increased graphics performance for graphics intensive workloads In addition during processor intensive workloads when the graphics power is low the processor core can increase its frequency higher within the package power limit Enabling Intel Turbo Boost Technology will maximize the performance of the processor core and the graphics render frequency within the specified package power levels Datasheet Volume 1 39 3 5 3
67. VD 19 SA_CS 3 AU33 DDR3 RSVD K34 SA DQ 0 AJ3 DDR3 I O RSVD K9 SA_DQ 1 AJ4 DDR3 1 0 RSVD L31 SA_DQ 2 AL3 DDR3 1 0 RSVD L33 SA DQ 3 AL4 DDR3 1 0 RSVD L34 SA_DQ 4 AJ2 DDR3 1 0 RSVD L9 SA DQ 5 AJ1 DDR3 1 0 RSVD M34 SA DQ 6 AL2 DDR3 1 0 RSVD N33 SA DQ 7 AL1 DDR3 1 0 RSVD N34 SA_DQ 8 AN1 DDR3 1 0 RSVD P35 SA_DQ 9 AN4 DDR3 1 0 RSVD P37 SA_DQ 10 AR3 DDR3 1 0 RSVD P39 SA DQ 11 AR4 DDR3 1 0 RSVD R34 SA_DQ 12 AN2 DDR3 I O RSVD R36 SA_DQ 13 AN3 DDR3 1 0 RSVD R38 SA DQ 14 AR2 DDR3 1 0 RSVD R40 SA_DQ 15 AR1 DDR3 1 0 RSVD 131 SA DQ 16 AV2 DDR3 1 0 RSVD AD34 SA DQ 17 AW3 DDR3 1 0 RSVD AD35 SA 18 5 DDR3 1 0 RSVD K31 SA DQ 19 AWS DDR3 1 0 RSVD_NCTF AV1 SA DQ 20 AU2 DDR3 1 0 RSVD_NCTF AW2 SA_DQ 21 AU3 DDR3 1 0 RSVD_NCTF AY3 SA_DQ 22 AUS DDR3 1 0 FRSVD NCTF B39 SA _DQ 23 AY5 DDR3 1 0 5 5 0 AY29 DDR3 SA DQ 24 AY7 DDR3 I O SA_BS 1 AW28 DDR3 O SA 25 AU7 DDR3 1 0 Datasheet Volume 1 Processor Pin and Signal Information intel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir SA DQI 26 AV9 DDR3 I O SA_DQS 6 AK38 DDR3 I O SA DQI 27 AUS DDR3 SA_DQSI 7 AF38 DDR3 1 0 SA DQ 28 AV7 DDR3 1 0 SA_DQS 8 AV13 DDR3 7 SA_DQ 29 AW
68. VLWs Resetwarn or MSIs only Processor core gt DMI APIC and MSI interrupt messaging support Message Signaled Interrupt MSI and MSI X messages Downstream SMI SCI and SERR error indication Legacy support for ISA regime protocol PHOLD PHOLDA required for parallel port DMA floppy drive and LPC bus masters DC coupling no capacitors between the processor and the PCH Polarity inversion PCH end to end lane reversal across the link Supports Half Swing low power low voltage 13 intel Introduction 1 2 4 Platform Environment Control Interface PECI The PECI is a one wire interface that provides a communication channel between a PECI client the processor and a PECI master The processors support the PECI 3 0 Specification 1 2 5 Processor Graphics The Processor Graphics contains a refresh of the sixth generation graphics core enabling substantial gains in performance and lower power consumption Next Generation Intel Clear Video Technology HD support is a collection of video playback and enhancement features that improve the end user s viewing experience Encode transcode HD content Playback of high definition content including Blu ray Disc Superior image quality with sharper more colorful images Playback of Blu ray disc S3D content using HDMI V 1 4 with 3D DirectX Video Acceleration DXVA support for accelerating video processing Full AVC VC1 MPEG2 HW Decode Advanced Scheduler 2 0
69. X 14 4 PCI Express I PREQ K40 Async GTL I PEG_RX 15 N2 PCI Express I PROC_SEL K32 N A PEG_RX 2 C9 PCI Express I PROCHOT H34 Async GTL 1 0 PEG_RX 3 E9 PCI Express I RESET F36 CMOS I PEG_RX 4 B7 PCI Express I RSVD AB6 PEG_RX 5 C5 PCI Express I RSVD AB7 PEG_RX 6 A6 PCI Express I RSVD AD37 PEG_RX 7 PCI Express I RSVD AE6 PEG_RX 8 F3 PCI Express I RSVD AF4 PEG_RX 9 G1 PCI Express I RSVD AG4 PEG TX 0 C13 PCI Express RSVD AJ11 PEG TX 1 E14 PCI Express RSVD AJ29 Datasheet Volume 1 95 m 8 n tel Processor Pin and Signal I nformation Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin 4 Buffer Type Dir RSVD AJ30 SA BS 2 AV20 DDR3 RSVD AJ31 SA 54 AV30 DDR3 RSVD AN20 SA CK 0 AY25 DDR3 RSVD AP20 SA CK 1 AU24 DDR3 RSVD AT11 SA CK 2 AW27 DDR3 RSVD AT14 SA CK 3 AV26 DDR3 RSVD AU10 SA_CK 0 AW25 DDR3 RSVD AV34 SA_CK 1 AU25 DDR3 RSVD AW34 SA CK 2 AY27 DDR3 RSVD AY10 SA_CK 3 AW26 DDR3 RSVD 038 SA CKE 0 AV19 DDR3 c39 SACKE AT19 DDR3 o RSVD D38 SA CKE 2 AU18 DDR3 RSVD H7 SA CKE 3 AV18 DDR3 RSVD H8 SA_CS 0 AU29 DDR3 RSVD 133 SA_CS 1 AV32 DDR3 RSVD 134 SA_CS 2 AW30 DDR3 RS
70. ace This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 8 GB s in each direction simultaneously for an aggregate of 16 GB s when x16 Gen 2 Hierarchical PCI compliant configuration mechanism for downstream devices Traditional PCI style traffic asynchronous snooped PCI ordering PCI Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space The remaining portion of the fixed 4 KB block of memory mapped space above that starting at 100h is known as extended configuration space PCI Express Enhanced Access Mechanism accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Traditional AGP style traffic asynchronous non snooped PCI X Relaxed ordering Peer segment destination posted write traffic no peer to peer read traffic in Virtual Channel 0 DMI gt PCI Express Port 0 Datasheet Volume 1 Introduction intel 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB wil
71. akes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single system Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets Intel Virtualization Technology Intel VT x added hardware support in the processor to improve the virtualization performance and robustness Intel Virtualization Technology for Directed I O Intel VT d adds chipset hardware implementation to support and improve I O virtualization performance and robustness Intel VT x specifications and functional descriptions are included in the Intel 64 and 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals index htm The Intel VT d specification and other VT documents can be referenced at http www intel com technology virtualization index htm 3 1 1 Intel Virtualization Technology Intel VT for 32 Intel 64 and Intel Architecture Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of IA platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved a reliable virtualized platform By using Intel VT x a VMM is Robust VMMs no longer need to use paravirtualization or binary translation This means that they will be able to run off the shelf OSs and appli
72. and durations are given and tested within the constraints imposed by Tsustained storage and customer shelf life in applicable Intel boxes and bags Datasheet Volume 1 79 7 10 1 Table 7 5 80 DC Specifications Electrical Specifications The processor DC specifications in this section are defined at the processor pads unless noted otherwise See Chapter 8 for the processor land listings and Chapter 6 for signal definitions Voltage and current specifications are detailed in Table 7 5 Table 7 6 and Table 7 7 The DC specifications for the DDR3 signals are listed in Table 7 8 Control Sideband and Test Access Port TAP are listed in Table 7 9 Table 7 5 through Table 7 7 list the DC specifications for the processor and are valid only while meeting the thermal specifications as specified in the Thermal Mechanical Specifications and Guidelines clock frequency and input voltages Care should be taken to read all notes associated with each parameter Voltage and Current Specifications Processor Core Active and I dle Mode DC Voltage and Current Specifications Sheet 1 of 2 Icc Symbol Parameter Min Typ Max Unit Note VID VID Range 0 2500 1 5200 V 2 Vcc Loadline Slope LLycc 2011D 2011C 2011B processors 1 7 ma 3 5 6 with 95 W 65 W and 45 W TDPs Vcc Tolerance Band 2011D 2011C 2011B processors with 95 W 65 W and 45 W TDPs 3 5 6 MVgeTOB PSO 16
73. annel Mode with four x8 dual ranked unbuffered DIMM memory configuration 11 1 2 2 Table 1 1 12 Introduction Up to 64 simultaneous open pages 32 per channel assuming 8 ranks of 8 bank devices Command launch modes of 1n 2n On Die Termination ODT Asynchronous ODT Intel Fast Memory Access Intel FMA Just in Time Command Scheduling Command Overlap Out of Order Scheduling PCI Express PCI Express port s are fully compliant with the PCI Express Base Specification Revision 2 0 e Processor with desktop PCH supported configurations PCI Express Supported Configurations in Desktop Products Configuration Organization Desktop 1 2x8 Graphics I O 2 1x16 Graphics I O The port may negotiate down to narrower widths Support for x16 x8 x4 x1 widths for a single PCI Express mode 2 5 GT s and 5 0 GT s PCI Express frequencies are supported Geni Raw bit rate on the data pins of 2 5 GT s resulting in a real bandwidth per pair of 250 MB s given the 8b 10b encoding used to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 4 GB s in each direction simultaneously for an aggregate of 8 GB s when x16 Gen 1 Gen 2 Raw bit rate on the data pins of 5 0 GT s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interf
74. are met as defined in Table 7 5 Datasheet Volume 1 71 e Electrical Specifications intel 7 3 1 7 4 72 Processor Clocking BCLK 0 BCLK 0 The processor uses a differential clock to generate the processor core operating frequency memory controller frequency system agent frequencies and other internal clocks The processor core frequency is determined by multiplying the processor core ratio by the BCLK frequency Clock multiplying within the processor is provided by an internal phase locked loop PLL that requires a constant frequency input with exceptions for Spread Spectrum Clocking SSC The processor s maximum non turbo core frequency is configured during power on reset by using its manufacturing default value This value is the highest non turbo core multiplier at which the processor can operate If lower maximum speeds are desired the appropriate ratio can be configured using the FLEX RATIO MSR Phase Lock Loop PLL Power Supply An on die PLL filter solution is implemented on the processor Refer to Table 7 6 for DC specifications Vcc Voltage Identification VI D The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages Table 7 1 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the voltage
75. ata to the PCH over the Intel Flexible Display Interface Intel FDI Display Ports The display ports consist of output logic and pins that transmit the display data to the associated encoding logic and send the data to the display device that is LVDS HDMI DVI SDVO and so on All display interfaces connecting external displays are now repartitioned and driven from the PCH Intel Flexible Display Interface Intel FDI The Intel Flexible Display Interface Intel FDI is a proprietary link for carrying display traffic from the Processor Graphics controller to the display I Os Intel FDI supports two independent channels one for pipe A and one for pipe B Each channel has four transmit Tx differential pairs used for transporting pixel and framing data from the display engine e Each channel has one single ended LineSync and one FrameSync input 1 V CMOS signaling One display interrupt line input 1 V CMOS signaling e Intel FDI may dynamically scalable down to 2X or 1X based on actual display bandwidth requirements Common 100 MHz reference clock e Each channel transports at a rate of 2 7 Gbps PCH supports end to end lane reversal across both channels no reversal support required in the processor Multi Graphics Controller Multi Monitor Support The processor supports simultaneous use of the Processor Graphics Controller GT and a x16 PCI Express Graphics PEG device The processor su
76. atform provides these launch and control interfaces using Safer Mode Extensions SMX The SMX interface includes the following functions e Measured Verified launch of the MLE e Mechanisms to ensure the above measurement is protected and stored in a secure location e Protection mechanisms that allow the MLE to control attempts to modify itself For more information refer to the Intel9 TXT Measured Launched Environment Developer s Guide in http www intel com technology security Intel Hyper Threading Technology Intel HT Technology The processor supports Intel Hyper Threading Technology Intel HT Technology that allows an execution core to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled using the BIOS and requires operating system support Intel recommends enabling Intel HT Technology with Microsoft Windows 7 Microsoft Windows Vista Microsoft Windows XP Professional Windows XP Home and disabling Intel HT Technology using the BIOS for all previous versions of Windows operating systems For more information on Intel HT Technology see http www intel com technology platform technology hyper threading Datasheet Volume 1 Technologies 3 4 Note 3 4 1 Note 3 4 2 intel Inte
77. b 128MX8 16 2 14 10 8 8K B 4 GB 2 Gb 256MX8 16 2 15 10 8 8K 8 GB 4 Gb 512MX8 16 2 16 10 8 8K 512 MB 1 Gb 64M X 16 1 13 10 8 16K 1GB 2 Gb 128 M X 16 4 1 14 10 8 16K Note DIMM module support is based on availability and is subject to change Table 2 2 Supported SO DI MM Module Configurations AI O Only i Raw of 7 of of Banks Card Cae T oe Gent DRAM e Row Inside Page Size Version Devices Ranks Address Bits DRAM 1 GB 1 Gb 64M x 16 8 2 13 10 8 8K A 2 GB 2 Gb 128 M x 16 8 2 14 10 8 8K 1 GB 1 Gb 128Mx8 8 1 14 10 8 8K 2 GB 2 Gb 256Mx8 8 1 15 10 8 8K 512 MB 1Gb 64M x 16 4 1 13 10 8 8K 1GB 2 Gb 128 M x 16 4 1 14 10 8 8K 2 GB 1 Gb 128Mx8 16 2 14 10 8 8K F 4 GB 2 Gb 256Mx8 16 2 15 10 8 8K 8 GB 4 Gb 512Mx8 16 2 16 10 8 8K Notes 20 1 System memory configurations are based on availability and are subject to change 2 Interface does not support ULV LV memory modules or ULV LV DIMMs Datasheet Volume 1 Interfaces m L D 2 1 2 System Memory Timing Support The IMC supports the following DDR3 Speed Bin CAS Write Latency CWL and command signal mode timings on the main memory interface tc CAS Latency trcp Activate Command to READ or WRITE Command delay tgp PRECHARGE Command Period CWL CAS Write Latency Command Signal modes 1n indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks
78. can support fewer than 16 bits in the cluster ID sub field and logical ID sub field in a software agnostic fashion More efficient MSR interface to access APIC registers To enhance inter processor and self directed interrupt delivery as well as the ability to virtualize the local APIC the APIC register set can be accessed only through MSR based interfaces in the x2APIC mode The Memory Mapped IO MMIO interface used by xAPIC is not supported in the x2APIC mode The semantics for accessing APIC registers have been revised to simplify the programming of frequently used APIC registers by system software Specifically the software semantics for using the Interrupt Command Register ICR and End Of Interrupt EOI registers have been modified to allow for more efficient delivery and dispatching of interrupts The x2APIC extensions are made available to system software by enabling the local X2APIC unit in the x2APIC mode To benefit from x2APIC capabilities a new Operating System and a new BIOS are both needed with special support for the x2APIC mode The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations Note Intel x2APIC technology may not be available on all processor SKUs For more information refer to the Intel 64 Architecture x2APIC Specification at http www intel com products processor manuals 88 Datasheet Volume 1 4
79. cations without any special steps Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on IA x86 processors More reliable Due to the hardware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system Datasheet Volume 1 35 Technologies 3 1 2 Intel Virtualization Technology Intel VT for 32 Intel 64 and Intel Architecture Intel VT x Features The processor core supports the following Intel VT x features Extended Page Tables EPT is hardware assisted page table virtualization It eliminates VM exits from guest OS to the VMM for shadow page table maintenance e Virtual Processor IDs VPID Ability to assign a VM ID to tag processor core hardware structures such as TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead e Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS assurances Des
80. ce eese sen ana nn san anna ka suae nein 15 1 3 6 Processor Graphics 6 nun nenn ann nemen 15 1 4 Thermal Management Support cence hine nan he sas sanas ia nana na rn na 15 t9 PACKAGC i MR MEL 16 1 6 Terminology 22 0 0 Rennen 16 1 Related Documents ees su han da aa a ulna ann 18 2 Iinterfaces hal TET T 19 2 1 System Memory Interface esses eee nun anne nn nenn nn 19 2 1 1 System Memory Technology Supported ezerensnnnnnnnnnnnnnnn nennen nun en nn nenn 19 2 1 2 System Memory Timing SUppOrt euassennennennnnnnnnnnn mnn nnn 21 2 1 3 System Memory Organization 5 menm 21 2 1 3 1 Single Channel Mode nennen nenn 21 2 1 3 2 Dual Channel Mode Intel Flex Memory Technology Mode 21 2 1 4 Rules for Populating Memory Slots sssssssssssssn eene meme 22 2 1 5 Technology Enhancements of Intel Fast Memory Access Intel 23 2 1 5 1 Just in Time Command Scheduling ssssssssssssrsssrsssrrrnrssrrrrnrsrresrns 23 2 1 5 2 Command Overlap nee te ee rn dea trea ta Dea aaa RE ka d ede 23 2 1 5 3 4Qut of Order Scheduling petentes eet a 23 2 1 6
81. cessor Serial Voltage I Dentification SVID interface A new serial VID interface is implemented on the processor Table 7 1 specifies the voltage level for the various VIDs Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cgu r such as electrolytic capacitors supply current during longer lasting changes in current demand for example coming out of an idle condition Similarly capacitors act as a storage well for current when entering an idle condition from a running condition To keep voltages within specification output decoupling must be properly designed Design the board to ensure that the voltage provided to the processor remains within the specifications listed in Table 7 5 Failure to do so can result in timing violations or reduced lifetime of the processor Voltage Rail Decoupling The voltage regulator solution needs to provide bulk capacitance with low effective series resistance ESR a low interconnect resistance from the regulator to the socket e bulk decoupling to compensate for large current swings generated during poweron or low power idle state entry exit The power delivery solution must ensure that the voltage and current specifications
82. criptor Table Exiting Descriptor table exiting allows a VMM to protect a guest OS from internal malicious software based attack by preventing relocation of key system data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector A VMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software 3 1 3 Intel virtualization Technology Intel VT for Directed O Intel VT d Objectives The key Intel VT d objectives are domain based isolation and hardware based virtualization A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated Virtualization allows for the creation of one or more partitions on a single system This could be multiple partitions in the same operating system or there can be multiple operating system instances running on the same system offering benefits such as system consolidation legacy migration activity partitioning or security 36 Datasheet Volume 1 Technologies 3 1 4 Intel Virtualization Technology Intel VT for Directed Intel VT d Features The processor supports the following Intel VT d features Memory controller and Processor Graphics comply with Intel VT d 1 2 specification Two VT d DMA remap engines iGraphics DM
83. ctive mode processor executing code Ci AutoHALT state CiE AutoHALT state with lowest frequency and voltage operating point C3 Execution cores in C3 flush their L1 instruction cache L1 data cache and L2 cache to the L3 shared cache Clocks are shut off to each core C6 Execution cores in this state save their architectural state before removing core voltage I ntegrated Memory Controller States Integrated Memory Controller States Power down State Description Power up CKE asserted Active mode Pre charge CKE de asserted not self refresh with all banks closed Active Power Down CKE de asserted not self refresh with minimum one bank active Self Refresh CKE de asserted using device self refresh PCI Express Link States PCI Express Link States State Description LO Full on Active transfer state LOS First Active Power Management low power state Low exit latency L1 Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency Datasheet Volume 1 Power Management 4 1 5 Direct Media Interface DMI States Table 4 5 Direct Media Interface DMI States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency Li Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit late
84. dards Datasheet Volume 1 Electrical Specifications 7 9 Table 7 4 intel Storage Conditions Specifications Environmental storage condition limits define the temperature and relative humidity that the device is exposed to while being stored in a moisture barrier bag The specified storage conditions are for component level prior to board attach Table 7 4 specifies absolute maximum and minimum storage temperature limits that represent the maximum or minimum device condition beyond which damage latent or otherwise may occur The table also specifies sustained storage temperature relative humidity and time duration limits These limits specify the maximum or minimum device storage conditions for a sustained period of time Failure to adhere to the following specifications can affect long term reliability of the processor Storage Condition Ratings Symbol Parameter Min Max Notes The non operating device storage temperature Damage latent or otherwise 8 Tabsolute storage may occur when exceeded for any length of 15e 1 2 3 4 time The ambient storage temperature in SES Tsustained storage shipping media for a sustained period of time 5 C 40 C 5 6 The ambient storage temperature in 6 Tshort term storage shipping media for a short period of time 20 C 85 C The maximum device storage relative 6 RH sustained storage humidity for a sustained period of time
85. e Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VSS AV11 GND VSS D20 GND VSS AV14 GND VSS D23 GND VSS AV17 GND VSS D26 GND VSS AV3 GND VSS D29 GND VSS AV35 GND VSS D32 GND VSS AV38 GND VSS D37 GND VSS AV6 GND VSS D39 GND VSS AW10 GND VSS D4 GND VSS AW11 GND VSS D5 GND VSS AW14 GND VSS D9 GND VSS AW16 GND VSS E11 GND VSS AW36 GND VSS E12 GND VSS AW6 GND VSS E17 GND VSS AY11 GND VSS E20 GND VSS AY14 GND VSS E23 GND VSS AY18 GND VSS E26 GND VSS AY35 GND VSS E29 GND VSS AY4 GND VSS E32 GND VSS AY6 GND VSS E36 GND VSS AY8 GND VSS E7 GND VSS 10 GND VSS E8 GND VSS B13 GND VSS Fi GND VSS B14 GND VSS F10 GND VSS B17 GND VSS F13 GND VSS B23 GND VSS F14 GND VSS B26 GND VSS F17 GND VSS B29 GND VSS F2 GND VSS B32 GND VSS F20 GND VSS B35 GND VSS F23 GND VSS B38 GND VSS F26 GND VSS 6 GND VSS F29 GND VSS C11 GND VSS F35 GND VSS C12 GND VSS F37 GND VSS C17 GND VSS F39 GND VSS C20 GND VSS F5 GND VSS C23 GND VSS F6 GND VSS C26 GND VSS F9 GND VSS C29 GND VSS Gil GND VSS C32 GND VSS G12 GND VSS C35 GND VSS G17 GND VSS C7 GND VSS G20 GND VSS C8 GND VSS G23 GND VSS D17 GND VSS G26 GND VSS D2 GND VSS G29 GND Datasheet Volume 1 105 m 8 n tel Processor Pin and Signal I nformation Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir P
86. easing the versatility of the 3D Engine The Gen 6 0 3D engine provides the following performance and power management enhancements Up to 12 Execution units EUs e Hierarchal Z e Video quality enhancements 3D Engine Execution Units e Supports up to 12 EUs The EUs perform 128 bit wide execution per clock e Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing 3D Pipeline Vertex Fetch VF Stage The VF stage executes 3DPRIMITIVE commands Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL Vertex Shader VS Stage The VS stage performs shading of vertices output by the VF function The VS unit produces an output vertex reference for every input vertex reference received from the VF unit in the order received Geometry Shader GS Stage The GS stage receives inputs from the VS stage Compiled application provided GS programs specifying an algorithm to convert the vertices of an input object into some output primitives For example a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges Clip Stage The Clip stage performs general processing on incoming 3D objects However it also includes specialized logic to perform a Clip Test
87. eceived or the Link is determined to have failed The Data Link Layer also generates and consumes packets that are used for Link management functions 2 2 1 3 Physical Layer The Physical Layer includes all circuitry for interface operation including driver and input buffers parallel to serial and serial to parallel conversion PLL s and impedance matching circuitry It also includes logical functions related to interface initialization and maintenance The Physical Layer exchanges data with the Data Link Layer in an implementation specific format and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device Datasheet Volume 1 25 intel Interfaces 2 2 2 Figure 2 4 2 2 3 26 PCI Express Configuration Mechanism The PCI Express external graphics link is mapped through a PCI to PCI bridge structure PCI Express Related Register Structures in the Processor PCI PCI Bridge PCI representing PCI Compatible Express PEGO root PCI Host Bridge Device Express ports Device Device 1 and Device 0 Device 6 DMI PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the Conventional PCI Specification PCI Express configuration space is divided into a PCI compatible region that consists
88. ed x16 unbuffered non ECC Raw Card B Single Ranked x8 unbuffered non ECC Raw Card C Single Ranked x16 unbuffered non ECC Raw Card F Dual Ranked x8 planar unbuffered non ECC Desktop platform DDR3 DIMM Modules Raw Card A Single Ranked x8 unbuffered non ECC Raw Card B Dual Ranked x8 unbuffered non ECC Raw Card C Single Ranked x16 unbuffered non ECC e Advanced Server Workstation PCH platforms DDR3 DIMM Modules Raw Card A Single Ranked x8 unbuffered non ECC Raw Card B Dual Ranked x8 unbuffered non ECC Raw Card C Single Ranked x16 unbuffered non ECC Raw Card D Single Ranked x8 unbuffered ECC Raw Card E Dual Ranked x8 unbuffered ECC e Essential Standard Server PCH platforms DDR3 DIMM Modules Raw Card D Single Ranked x8 unbuffered ECC Raw Card E Dual Ranked x8 unbuffered ECC DDR3 DRAM Device Technology 1 Gb 2 Gb and 4 Gb DDR3 DRAM Device technologies and addressing are supported Datasheet Volume 1 19 intel Interfaces Table 2 1 Supported UDIMM Module Configurations Raw DIMM DRAMDevice DRAM ent cw E EA Capacity Technology Organization E ics Device Address Inside Page Size Ranks Bits DRAM Unbuffered Non ECC Supported DIMM Module Configurations 1GB 1 Gb 128MX8 8 2 14 10 8 8K 2 GB 2 Gb 128 M X 16 8 2 14 10 8 16K 2 GB 1 G
89. efine the SRAM Commands DDR3 SB CAS CAS Control Signal This signal is used with SB_RAS and SB_WE O along with SB_CS to define the SRAM Commands DDR3 Data Strobes SB_DQS 8 0 and its complement signal group make SB_DQS 8 0 up a differential strobe pair The data is captured at the crossing point 1 0 SB_DQS 8 0 of SB_DQS 8 0 and its SB_DQS 8 0 during read and write DDR3 transactions SB DQ 63 0 Data Bus Channel B data signal interface to the SDRAM data bus I O DDR3 SB 15 0 Memory Address These signals are used to provide the multiplexed 15 0 row and column address to the SDRAM DDR3 SDRAM Differential Clock Channel B SDRAM Differential clock signal SB Ck 3 0 pair The crossing of the positive edge of SB CK and the negative edge g of its complement SB_CK are used to sample the command and DDR3 control signals on the SDRAM SB CK T3 0 SDRAM Inverted Differential Clock Channel B SDRAM Differential 3 0 clock signal pair complement DDR3 Clock Enable 1 per rank Used to Initialize the SDRAMs during power up SB_CKE 3 0 e Power down SDRAM ranks DDR3 Place all SDRAM ranks into and out of self refresh during STR Chip Select 1 per rank Used to select particular SDRAM SB_CS 3 0 components during the active state There is one Chip Select for each DDR3 SDRAM rank SB ODT 3 0 On Die Termination Active Termination Control 0 DDR3 6 2 Memory Reference and Compensation Signals Table 6
90. ents at a later date Each processor is programmed with a maximum valid voltage identification value VID that is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States The voltage specification requirements are measured across VCC SENSE and VSS SENSE lands at the socket with a 20 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe ICC MAX specification is based on the Vcc loadline at worst case highest tolerance and ripple The Vcc specifications represent static and transient limits The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC SENSE and VSS SENSE lands PSx refers to the voltage regulator power state as set by the SVID protocol 2011A processors with 35 W TDP loadline slope TOB and ripple specifications allow for a cost reduced voltage regulator for boards supporting only the 2011A
91. er Type Catastrophic Error This signal indicates that the system has experienced a catastrophic error and cannot continue to operate The processor will set this for non recoverable machine check errors or other unrecoverable internal errors CATERR On the processor CATERR is used for signaling the following types of o errors CMOS Legacy MCERRs CATERR is asserted for 16 BCLKs Legacy IERRs CATERR remains asserted until warm or cold reset PECI Platform Environment Control Interface A serial sideband 1 0 PECI interface to the processor it is used primarily for thermal power and A h error management Synchronols Processor Hot PROCHOT goes active when the processor temperature monitoring sensor s detects that the processor has CMOS Input PROCHOT reached its maximum safe operating temperature This indicates that o pu the processor Thermal Control Circuit TCC has been activated if pon Drain enabled This signal can also be driven to the processor to activate the P TCC Thermal Trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are TAERA TRIE no false trips The processor will stop all execution when the junction Ao IONS temperature exceeds approximately 130 C This is signaled to the system by the THERMTRIP pin 6 10 Power Sequencing Signals Table 6 12 Power Sequencing Signals i m Di
92. es and any such use of Intel s internal code names is at the sole risk of the user Intel Intel Core Celeron Pentium Speedstep and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2011 2013 Intel Corporation All rights reserved 2 Datasheet Volume 1 Contents 1 Introductions serr anann a a a ne ee 9 1 1 Processor Feature Details 5 iacu Ze cages deeds n asada nas 11 1 1 1 Supported Technologies eres rina ae a uc Fe 11 1 2 Interfaces TTA 11 1 2 1 System Memory SUpport esisiini opi Re een 11 1 2 2 uel D m 12 1 2 3 Direct Media Interface DM ussrunseasaunasananannannnnunn 13 1 2 4 Platform Environment Control Interface PECI nn 14 1 2 5 Processor Graphics iioii na een 14 1 2 6 Intel Flexible Display Interface Intel FDI uuueeesseseesesnennnnnnnnnnnnnennnnnen 14 1 3 Power Management Support uesansnnennnennennnnnnnnnnnnnnnnnnnnnn sese eene e nennen nnn 15 1 321 Processor COLO ee Quan Ne EEE 15 1 3 2 SYSE tee Nest 15 1 3 3 Memory Controller n 15 1 3 4 PCI a RARRE 15 1 3 5 Direct Media Interfa
93. es occur at the thread processor core and processor package level Thread level C states are available if Intel HT Technology is enabled Long term reliability cannot be assured unless all the Low Power Idle States are enabled Datasheet Volume 1 Power Management m Figure 4 2 Idle Power Management Breakdown of the Processor Cores Thread 0 Thread 1 Thread 0 Thread 1 Core 0 State Core 1 State Processor Package State Entry and exit of the C States at the thread and core level are shown in Figure 4 3 Figure 4 3 Thread and Core C State Entry and Exit Table 4 8 MWAIT CT HLT _ 7MWATT CS MWAIT C1 HLT x MWAIT C3 a Read CIE Enabled P_LV2 O Read N o ww While individual threads can request low power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from CO is required before entering any other C state Coordination of Thread Power States at the Core Level Thread 1 Processor Core estate co c3 c6 co co co co co Ci CO c cit ci Thread 0 C3 CO c 03 C3 C6 CO cit 03 C6 Note 1 If enabled the core C state will be C1E if all enabled cores have also resolved a core C1 state or higher Datasheet Volume 1 47 m 8 Power Management intel
94. et Volume 1 17 1 7 Table 1 3 18 intel Related Documents Refer to Table 1 3 for additional information Related Documents Introduction Document Document Number Location 2nd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family Desktop and Intel Celeron Processor Family Desktop Datasheet Volume 2 http download intel com design processor datashts 324642 pdf 2nd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family Desktop and Intel Celeron Processor Family Desktop Specification Update http download intel com design processor specupdt 324643 pdf 2nd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family Desktop and Intel Celeron Processor Family Desktop and LGA1155 Socket Thermal Mechanical Specifications and Design Guidelines Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet http download intel com design processor designex 324644 pdf www intel com Assets PDF datas heet 324645 pdf Intel 6 Series Chipset and Intel C200 Series Chipset Thermal Mechanical Specifications and Design Guidelines www intel com Assets PDF desig nguide 324647 pdf Advanced Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 http www pcisig com specifica tions Intel TXT Measured Launched
95. ffective with e Display images well suited to compression such as text windows slide shows and so on Poor examples are 3D games e Static screens such as screens with significant portions of the background showing 2D applications processor benchmarks and so on or conditions when the processor is idle Poor examples are full screen 3D games and benchmarks that flip the display image at or near display refresh rates Datasheet Volume 1 Power Management intel 4 6 5 4 7 Intel Graphics Dynamic Frequency Intel Graphics Dynamic Frequency Technology is the ability of the processor and graphics cores to opportunistically increase frequency and or voltage above the ensured processor and graphics frequency for the given part Intel Graphics Dynamic Frequency Technology is a performance feature that makes use of unused package power and thermals to increase application performance The increase in frequency is determined by how much power and thermal budget is available in the package and the application demand for additional processor or graphics performance The processor core control is maintained by an embedded controller The graphics driver dynamically adjusts between P States to maintain optimal performance power and thermals The graphics driver will always place the graphics engine in its lowest possible P State thereby acting in the same capacity as Intel GPMT Thermal Power Management See Section 4 6 for all grap
96. function on incoming objects The Clip Test optimizes generalized 3D Clipping The Clip unit examines the position of incoming vertices and accepts rejects 3D objects based on its Clip algorithm Strips and Fans SF Stage The SF stage performs setup operations required to rasterize 3D objects The outputs from the SF stage to the Windower stage contain implementation specific information required for the rasterization of objects and also supports clipping of primitives to some extent Datasheet Volume 1 29 intel Interfaces 2 4 1 2 6 2 4 1 3 2 4 1 4 2 4 1 4 1 2 4 1 4 2 30 Windower IZ WIZ Stage The WIZ unit performs an early depth test which removes failing pixels and eliminates unnecessary processing overhead The Windower uses the parameters provided by the SF unit in the object specific rasterization algorithms The WIZ unit rasterizes objects into the corresponding set of pixels The Windower is also capable of performing dithering whereby the illusion of a higher resolution when using low bpp channels in color buffers is possible Color dithering diffuses the sharp color bands seen on smooth shaded objects Video Engine The Video Engine handles the non 3D media video applications It includes support for VLD and MPEG2 decode in hardware 2D Engine The 2D Engine contains BLT Block Level Transfer functionality and an extensive set of 2D instructions To take advantage of the 3D during engine s functi
97. hat are RSVD and RSVD NCTF must be left No Connect RSVD NCTF unconnected on the board Non Critical to Function DDR3 DRAM Reset Reset signal from processor to DRAM devices One SM_DRAMRST common to all channels CMOS Notes 1 PCIe bifurcation support varies with the processor and PCH SKUs used 64 Datasheet Volume 1 Signal Description 6 4 Table 6 6 PCI Express Based Interface Signals PCI Express Graphics I nterface Signals ntel Signal Name Description Ber PEG_ICOMPI PCI Express Input Current Compensation t PEG ICOMPO PCI Express Current Compensation PEG_RCOMPO PCI Express Resistance Compensation PEG RX 15 0 PEG RX 15 0 PE RX 3 0 PE RX4 3 0 PCI Express Receive Differential Pair I PCI Express PEG TX 15 0 PEG TX 15 0 PE 3 011 PE TX4 3 0 PCI Express Transmit Differential Pair PCI Express Notes PE TX 3 0 and PE_RX 3 0 are only used for platforms that support 20 PCIe lanes 1 6 5 Table 6 7 Intel Flexible Display Interface Intel FDI Signals Intel Flexible Display Interface Intel FDI xi e Direction Signal Name Description Buffer Type 8 n FDIO FSYNC O Intel Flexible Display I nterface Frame Sync Pipe A I CMOS 8 n n LSYNC O Intel Flexible Display Interface Line Sync Pipe A I CMOS FDI TX 7 0 Intel Flexible Display Interface Transmi
98. he 250 MB s where quick calculations would imply 300 MB s The external graphics ports support Gen2 speed as well At 5 0 GT s Gen 2 operation results in twice as much bandwidth per lane as compared to Gen 1 operation When operating with two PCIe controllers each controller can be operating at either 2 5 GT s or 5 0 GT s The PCI Express architecture is specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries Refer to Figure 2 2 for the PCI Express Layering Diagram PCI Express Layering Diagram Transaction Transaction Data Link Data Link Physical Physical Logical Sub block Logical Sub block Electrical Sub block Electrical Sub block LLL RX TX RX TX LES J PCI Express uses packets to communicate information between components Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component As the transmitted packets flow through the other layers they are extended with additional information necessary to Datasheet Volume 1 Interfaces intel handle packets at those layers At the receiving side the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally for Transaction Layer Packets to the form that can be proce
99. hics thermal power management related features 88 Datasheet Volume 1 57 58 Power Management Datasheet Volume 1 Thermal Management 5 Thermal Management For thermal specifications and design guidelines refer to the 2nd Generation Intel Core Processor Family Desktop Intel Pentium Processor Family Desktop and Intel Celeron Processor Family Desktop and LGA1155 Socket Thermal and Mechanical Specifications and Design Guidelines 88 Datasheet Volume 1 59 60 Thermal Management Datasheet Volume 1 Signal Description 6 Signal Description This chapter describes the processor signals They are arranged in functional groups according to their associated interface or category The following notations are used to describe the signal type Notations Signal Type I Input Pin 0 Output Pin I O Bi directional Input Output Pin The signal description also includes the type of buffer used for the particular signal see Table 6 1 Table 6 1 Signal Description Buffer Types Signal Description PCI Express PCI Express interface signals These signals are compatible with PCI Express 2 0 Signalling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Refer to the PCIe specification Direct Media Interface signals These signals are based on PCI Express 2 0 Signaling DMI Environment AC Specifications 5 GT s but
100. ice versa however channel A size must be greater or equal to channel B size Datasheet Volume 1 21 intel Interfaces Figure 2 1 Intel Flex Memory Technology Operation 2 1 3 2 1 Note 2 1 4 Note 22 TOM Non interleaved access E Dual channel interleaved access CHA CHB B The largest physical memory amount of the smaller size memory module C The remaining physical memory amount of the larger size memory module Dual Channel Symmetric Mode Dual Channel Symmetric mode also known as interleaved mode provides maximum performance on real world applications Addresses are ping ponged between the channels after each cache line 64 byte boundary If there are two requests and the second request is to an address on the opposite channel from the first that request can be sent before data from the first request has returned If two consecutive cache lines are requested both may be retrieved simultaneously since they are ensured to be on opposite channels Use Dual Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being the same When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory IMC operates completely in Dual Channel Symmetric mode The DRAM device techn
101. in Name Pin Buffer Type Dir VSS G34 GND VSS L26 GND VSS G7 GND VSS L29 GND VSS G8 GND VSS L8 GND VSS H1 GND VSS M1 GND VSS H17 GND VSS M17 GND VSS H2 GND VSS M2 GND VSS H20 GND VSS M20 GND VSS H23 GND VSS M23 GND VSS H26 GND VSS M26 GND VSS H29 GND VSS M29 GND VSS H33 GND VSS M33 GND yss H35 GND vss M35 GND VSS H37 GND VSS M37 GND VSS H39 GND VSS M39 GND VSS H5 GND VSS M5 GND VSS H6 GND VSS M6 GND VSS H9 GND VSS M9 GND VSS Jii GND VSS N8 GND VSS J17 GND VSS P1 GND VSS 120 GND VSS P2 GND VSS 123 GND VSS P36 GND VSS 126 GND VSS P38 GND VSS 129 GND VSS P40 GND VSS 132 GND VSS P5 GND VSS K1 GND VSS P6 GND VSS K12 GND VSS R33 GND VSS K13 GND VSS R35 GND VSS K14 GND VSS R37 GND VSS K17 GND VSS R39 GND VSS K2 GND VSS R8 GND VSS K20 GND VSS GND VSS K23 GND VSS T5 GND VSS K26 GND VSS T6 GND VSS K29 GND VSS U8 GND VSS K33 GND VSS Vi GND VSS K35 GND VSS v2 GND VSS K37 GND VSS V33 GND VSS K39 GND VSS V34 GND VSS K5 GND 55 V35 GND VSS K6 GND VSS V36 GND VSS L10 GND VSS V37 GND vss u7 cv vss v38 GND VSS 120 GND VSS 39 GND VSS L23 GND VSS 40 GND 106 Datasheet Volume 1 8 Processor Pin and Signal Information n tel Table 8 1 Processor Pin List by Pin Name Pin Name Pin 4 Buffer Type Dir VSS V5 GND VSS W6 GND VSS Y5 GND VSS Y8 GND VSS_NCTF A4 GND VSS NCTF AV39 GND VSS_NCTF AY37 GND VSS_NCTF B3 GND VSS_SENS
102. ior to the link going down may be processed as normal No completions from downstream non posted transactions are returned upstream over the DMI link after a link down event Processor Graphics Controller GT New Graphics Engine Architecture includes 3D compute elements Multi format hardware assisted decode encode Pipeline and Mid Level Cache MLC for superior high definition playback video quality and improved 3D performance and Media Display Engine in the Uncore handles delivering the pixels to the screen GSA Graphics in System Agent is the primary Channel interface for display memory accesses and PCI like traffic in and out Figure 2 6 Processor Graphics Controller Unit Block Diagram 28 VS GS Setup Rasterize Hierachical Z Hardware Clipper Unified Execution Unit Array Texture Unit Pixel Backend Additional Post Processing Multi Format Decode Encode Full MPEG2 VC1 AVC Decode Fixed Function Post Processing Full AVC Encode Partial MPEG2 VC1 Encode Datasheet Volume 1 Interfaces 2 4 1 2 4 1 1 2 4 1 2 2 4 1 2 1 2 4 1 2 2 2 4 1 2 3 2 4 1 2 4 2 4 1 2 5 3D and Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive All the cores are fully programmable incr
103. isplayPort DTS Digital Thermal Sensor Enhanced Intel SpeedStep Technology Technology that provides power management capabilities to laptops EU Execution Unit Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and IA 32 Architectures Software Developer s Manuals for more detailed information IMC Integrated Memory Controller Intel 64 Technology 64 bit memory extensions to the IA 32 architecture Intel FDI Intel Flexible Display Interface Intel TXT Intel Trusted Execution Technology Intel Virtualization Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments Technology inside a single platform Intel virtualization Technology Intel VT for Directed I O Intel VT d is a hardware assist under system software Virtual Machine Manager or OS Intel VT d control for enabling I O device virtualization Intel VT d also brings robust security by providing protection from erran
104. l Turbo Boost Technology Intel Turbo Boost Technology is a feature that allows the processor core to opportunistically and automatically run faster than its rated operating frequency render clock if it is operating below power temperature and current limits The Intel Turbo Boost Technology feature is designed to increase performance of both multi threaded and single threaded workloads Maximum frequency is dependant on the SKU and number of active cores No special hardware support is necessary for Intel Turbo Boost Technology BIOS and the OS can enable or disable Intel Turbo Boost Technology Compared with previous generation products Intel Turbo Boost Technology will increase the ratio of application power to TDP Thus thermal solutions and platform cooling that are designed to less than thermal design guidance might experience thermal and performance issues since more applications will tend to run at the maximum power limit for significant periods of time Intel Turbo Boost Technology may not be available on all SKUs Intel Turbo Boost Technology Frequency The processor s rated frequency assumes that all execution cores are running an application at the thermal design power TDP However under typical operation not all cores are active Therefore most applications are consuming less than the TDP at the rated frequency To take advantage of the available thermal headroom the active cores can increase their operating frequency
105. l be dropped Re issues Configuration cycles that have been previously completed with the Configuration Retry status PCI Express reference clock is 100 MHz differential clock Power Management Event PME functions Dynamic width capability Message Signaled Interrupt MSI and MSI X messages Polarity inversion Note The processor does not support PCI Express Hot Plug 1 2 3 Direct Media Interface DMI Datasheet Volume 1 DMI 2 0 support Four lanes in each direction 5 GT s point to point DMI interface to is supported Raw bit rate on the data pins of 5 0 GB s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface Does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 2 GB s in each direction simultaneously for an aggregate of 4 GB s when DMI x4 Shares 100 MHz PCI Express reference clock 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Supports the following traffic types to or from the PCH DMI DRAM DMI gt processor core Virtual Legacy Wires
106. latform has not granted permission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in CO Package C1 CIE No additional power reduction actions are taken in the package C1 state However if the C1E sub state is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when At least one core is in the C1 state The other cores are in a C1 or lower power state The package enters the C1E state when All cores have directly requested C1E using MWAIT C1 with a C1E sub state hint All cores are in a power state lower that C1 C1E but the package low power state is limited to C1 C1E using the PMG CST CONFIG CONTROL MSR All cores have requested C1 using HLT or MWAIT C1 and C1E auto promotion is enabled in IA32 MISC ENABLES No notification to the system occurs upon entry to C1 C1E Datasheet Volume 1 51 4 2 5 3 4 2 5 4 4 3 4 3 1 52 Power Management Package C3 State A processor enters the package C3 low power state when At least one core is in the C3 state The other cores are in a C3 or lower power state and the processor has been granted permission by the platform The platform has not granted a request to a package C6 state but has allowed a package C6 state In package C3 state the L3 shared cache is valid
107. mV and edge Vin and Voy may experience excursions above Vppo However input signal drivers must comply with the Datasheet Volume 1 Electrical Specifications Table 7 9 Control Sideband and TAP Signal Group DC Specifications Symbol Parameter Min Max Units Notes Vit Input Low Voltage Vccio 0 3 2 VIH Input High Voltage Vecio 0 7 V 2 4 VoL Output Low Voltage Vecio 0 1 V 2 VoH Output High Voltage Vccio 0 9 V 2 4 Buffer on Resistance 23 73 Q I Input Leakage Current 200 uA 3 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vcc o referred to in these specifications refers to instantaneous Vcc o 3 For Vin between 0 V and Vcc o Measured when the driver is tristated 4 and Voy may experience excursions above Vec o However input signal drivers must comply with the signal quality specifications Table 7 10 PCI Express DC Specifications Symbol Parameter Min Typ Max Units Notes Low differential peak to peak Tx voltage Vrx DIFF p Low swing P P 9 04 0 5 0 6 3 Differential peak to peak Tx voltage swing 0 8 1 1 2 V 3 Tx AC Peak Common Mode Output VrX C AC p Voltage Gen1 only 20 my 12 8 Tx AC Peak Common Mode Output VTx_CM AC p p Voltage Gen2 only 100 mV 1 2 ZTX DIFF
108. mal Management 5 nce ater deny ek eaa RR E RRRRERARARE aan 59 SPI DENISE 61 6 1 System Memory Interface SignalS ccccccccccecesenceeesessaeceeeeeececeeeaeeneaeasarsaeceeaeeees 62 6 2 Memory Reference and Compensation Signals sss 63 6 Reset and Miscellaneous Signals ecciesie esee einsehen ehe nnns nau su na nen 64 6 4 PCI Express Based Interface Signals sss nnne enne 65 6 5 Intel Flexible Display Interface Intel FDI Signals eee 65 6 6 Direct Media Interface DMI 5 6 8 6 eee nun nenn nn nn aaia 66 6 7 Phase Lock Loop PLL Signals nu ee an 66 6 8 Test Access Points TAP Signals uususununenonanananannnnunnn Aa ann hann nnn nn 66 6 9 Error and Thermal Protection Signals 4s4ssHsnnnnnennnnn nn en nun emnes 67 6 10 Power Sequencing Signals altare eier 67 6 11 Processor Power Signals aces ori nada naa a ERR nn nn nn anna nn anne 68 SIGNAlS 68 6 13 Ground and Non Critical to Function NCTF Signals sss 68 6 14 Processor Internal Pull Up Pull Down Resistors ususserennnnnnnnnnnnnn nenn nun en en nn nn nn 69 7 Electrical Specifications eroe eni nn ERR RR TRA a 71 ZA Powerand Ground Lands rh iere ae Rana A
109. mory channel Clocks can be controlled on a per SO DIMM basis Exceptions are made for per SO DIMM control signals such as CS CKE and ODT for unpopulated SO DIMM slots The I O buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should be disabled and any DLL circuitry related ONLY to unused signals should be disabled The input path must be gated to prevent spurious results due to noise on the unused signals typically handled automatically when input receiver is disabled PCI Express Power Management e Active power management support using LOs and L1 states All inputs and outputs disabled in L2 L3 Ready state PEG interface does not support Hot Plug Power impact may be observed when PEG link disable power management state is used Direct Media Interface DMI Power Management Active power management support using LOs L1 state Datasheet Volume 1 55 4 6 4 6 1 4 6 2 4 6 3 4 6 4 56 Power Management Graphics Power Management Intel Rapid Memory Power Management Intel RMPM also known as CxSR The Intel Rapid Memory Power Management puts rows of memory into self refresh mode during C3 C6 to allow the system to remain in the lower power states longer Desktop processors routinely save power during runtime conditions by entering the C3 C6 state Intel RMPM is an indirect method of power saving that can have a significant effect
110. namic power down PCI Express LOs and L1 ASPM power management capability Direct Media Interface DMI LOs and L1 ASPM power management capability Processor Graphics Controller e Intel Rapid Memory Power Management Intel RMPM CxSR e Intel Graphics Performance Modulation Technology Intel GPMT Intel Smart 2D Display Technology Intel S2DDT e Graphics Render C State RC6 Thermal Management Support Digital Thermal Sensor Intel Adaptive Thermal Monitor e THERMTRIP and PROCHOT support On Demand Mode e Memory Thermal Throttling e External Thermal Sensor TS on DIMM and TS on Board Render Thermal Throttling Fan speed control with DTS Datasheet Volume 1 15 intel 1 5 Note 1 6 Table 1 2 16 Package Introduction The processor socket type is noted as LGA 1155 The package is a 37 5 x 37 5 mm Flip Chip Land Grid Array FCLGA 1155 See the 2nd Generation Intel Core Processor Intel Pentium Processor and Intel Celeron Processor and LGA1155 Socket Thermal Mechanical Specifications and Design Guidelines for complete details on package Terminology Terminology Sheet 1 of 2 Term Description ACPI Advanced Configuration and Power Interface AIO All In One BLT Block Level Transfer CRT Cathode Ray Tube DDR3 Third generation Double Data Rate SDRAM memory technology DMA Direct Memory Access DMI Direct Media Interface DP D
111. nce from APD mode is that when waking up all page buffers are empty 3 DLL off In this mode the data in DLLs on DDR are off Power saving in this mode is the best among all power modes Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP but also tXPDLL 10 20 according to DDR type cycles until first data transfer is allowed The processor supports 5 different types of power down The different modes are the power down modes supported by DDR3 and combinations of these The type of CKE power down is defined by the configuration The are options are 1 No power down 2 APD The rank enters power down as soon as idle timer expires no matter what is the bank status 3 PPD When idle timer expires the MC sends PRE all to rank and then enters power down 4 DLL off same as option 2 but DDR is configured to DLL off 5 APD change to PPD APD PPD Begins as option 1 and when all page close timers ofthe rank are expired it wakes the rank issues PRE all and returns to PPD APD change to DLL off APD_DLLoff Begins as option 1 and when all page close timers of the rank are expired it wakes the rank issues PRE all and returns to DLL off power down The CKE is determined per rank when it is inactive Each rank has an idle counter The idle counter starts counting as soon as the rank has no accesses and if it expires the rank may enter power down while no new transactions to the rank arrive to queues
112. ncorporates a DDR3 Data Scrambling feature to minimize the impact of excessive di dt on the platform DDR3 VRs due to successive 1s and 05 on the data bus Past experience has demonstrated that traffic on the data bus is not random and can have energy concentrated at specific spectral harmonics creating high di dt that is generally limited by data patterns that excite resonance between the package inductance and on die capacitances As a result the memory controller uses a data scrambling feature to create pseudo random patterns on the DDR3 data bus to reduce the impact of any excessive di dt Datasheet Volume 1 23 2 2 1 Figure 2 2 24 Interfaces PCI Express Interface This section describes the PCI Express interface capabilities of the processor See the PCI Express Base Specification for details of PCI Express The number of PCI Express controllers is dependent on the platform Refer to Chapter 1 for details PCI Express Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The initial recovered clock speed of 1 25 GHz results in 2 5 Gb s direction that provides a 250 MB s communications channel in each direction 500 MB s total That is close to twice the data rate of classic PCI The fact that 8b 10b encoding is used accounts for t
113. ncy 4 1 6 Processor Graphics Controller States Table 4 6 Processor Graphics Controller States State Description DO Full on display active D3 Cold Power off 4 1 7 Interface State Combinations Table 4 7 G S and C State Combinations Processor State System Clocks Description G State S State 6 State GO 50 co Full On On Full On GO so C1 C1E Auto Halt On Auto Halt GO 50 C3 Deep Sleep On Deep Sleep GO 50 C6 Deep Power down On Deep Power down G1 S3 Power off Off except RTC Suspend to RAM G1 S4 Power off Off except RTC Suspend to Disk G2 S5 Power off Off except RTC Soft Off G3 NA Power off Power off Hard off Datasheet Volume 1 45 m 8 Power Management intel 4 2 1 4 2 2 Caution 46 Processor Core Power Management While executing code Enhanced Intel SpeedStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P state When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C state In general lower power C states have longer entry and exit latencies Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology Multiple frequency and voltage points for optimal performance and power efficiency These operating points are k
114. nd vertically aligned at the destination If the destination for the BLT overlaps with the source memory location the BLT engine specifies which area in memory to begin the BLT transfer Hardware is included for all 256 raster operations source pattern and destination defined by Microsoft including transparent BLT The BLT engine has instructions to invoke BLT and stretch BLT operations permitting software to set up instruction buffers and use batch processing The BLT engine can perform hardware clipping during BLTs Datasheet Volume 1 Interfaces 2 4 2 Figure 2 7 2 4 2 1 2 4 2 1 1 2 4 2 1 2 2 4 2 1 3 intel Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components Display Planes e Display Pipes DisplayPort and Intel FDI Processor Display Block Diagram 5 T isplay ort o D Ea Pipe A Control im E 2 Display 4 Display A amp ra Arbi M Planes i ES rbiter En Sun L amp VGA Display a E Display Port 5 Ss Pipe B Control a o em B Display Planes A display plane is a single displayed surface in memory and contains one image desktop cursor overlay It is the portion of the display hardware logic that defines the format and location of a rectangular region of memory that can be displayed on display output de
115. nology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Intel Active Management Technology 7 0 Intel AMT 7 0 Intel Trusted Execution Technology Intel TXT Intel Streaming SIMD Extensions 4 1 Intel SSE4 1 Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 Intel Hyper Threading Technology Intel HT Technology Intel 64 Architecture Execute Disable Bit Intel Turbo Boost Technology Intel Advanced Vector Extensions Intel AVX Intel Advanced Encryption Standard New Instructions Intel AES NI PCLMULQDQ Instruction 1 2 I nterfaces 1 2 1 System Memory Support Datasheet Volume 1 Two channels of unbuffered DDR3 memory with a maximum of two UDIMMs or SO DIMMs for AIO per channel Single channel and dual channel memory organization modes Data burst length of eight for all memory organization modes Memory DDR3 data transfer rates of 1066 MT s and 1333 MT s 64 bit wide channels DDR3 I O Voltage of 1 5 V The type of memory supported by the processor is dependent on the PCH SKU in the target platform Desktop PCH platforms support non ECC un buffered DIMMs only All In One platforms AIO support SO DIMMs Maximum memory bandwidth of 10 6 GB s in single channel mode or 21 GB s in dual channel mode assuming DDR3 1333 MT s 1Gb 2Gb and 4Gb DDR3 DRAM technologies are supported Using 4Gb device technologies the largest memory capacity possible is 32 GB assuming Dual Ch
116. nown as P states Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on the selected frequency and the number of active processor cores If the target frequency is higher than the current frequency Vcc is ramped up in steps to an optimized voltage This voltage is signaled by the SVID bus to the voltage regulator Once the voltage is established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling the target voltage on SVID bus All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested amongst all active cores is selected Software requested transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition is completed The processor controls voltage ramp rates internally to ensure glitch free transitions Because there is low transition latency between P states a significant number of transitions per second are possible Low Power Idle States When the processor is idle low power idle states C states are used to save power More power Savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Resolution of C stat
117. nstructions are used MWAIT substates cannot be defined The MWAIT substate is always zero if I O MWAIT redirection is used By default P LVLx I O redirections enable the MWAIT break on EFLAGS IF feature that triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF Core C states The following are general rules for all core C states unless specified otherwise A core C State is determined by the lowest numerical thread state such as Thread 0 requests C1E while Thread 1 requests C3 resulting in a core C1E state See Table 4 7 e A core transitions to CO state when An interrupt occurs There is an access to the monitored address if the state was entered using an MWAIT instruction For core C1 C1E core C3 and core C6 an interrupt directed toward a single thread wakes only that thread However since both threads are no longer at the same core C state the core resolves to CO A system reset re initializes all processor cores Core CO State The normal operating state of a core where code is being executed Datasheet Volume 1 Power Management intel 4 2 4 2 4 2 4 3 4 2 4 4 4 2 4 5 Core C1 CIE State C1 C1E is a low power state entered when all threads within a core execute a HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 C1E state See the Intel 64 and 32 Architecture Software Develo
118. of the first 256 bytes of a logical device s configuration space and an extended PCI Express region that consists of the remaining configuration space The PCI compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section The PCI Express Host Bridge is required to translate the memory mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles To maintain compatibility with PCI configuration addressing mechanisms it is recommended that system software access the enhanced configuration space using 32 bit operations 32 bit aligned only See the PCI Express Base Specification for details of both the PCI compatible and PCI Express Enhanced configuration mechanisms and transaction rules PCI Express Port The PCI Express interface on the processor is a single 16 lane x16 port that can also be configured at narrower widths The PCI Express port is compliant with the PCI Express Base Specification Revision 2 0 Datasheet Volume 1 Interfaces intel 2 2 4 PCI Express Lanes Connection Figure 2 5 demonstrates the PCIe lanes mapping Figure 2 5 PCI Express Typical Operation 16 lanes Mapping
119. ok to set this register Customers who choose to change the value of this register can do it by changing the BIOS For experiments this register can be modified in real time if BIOS did not lock the MC registers Note In APD APD PPD and APD DLLoff there is no point in setting the idle counter in the same range of page close idle timer Another option associated with CKE power down is the 5 DLL off When this option is enabled the SBR I O slave DLLs go off when all channel ranks are in power down Do not confuse it with the DLL off mode in which the DDR DLLs are off This mode requires to define the I O slave DLL wakeup time 4 3 2 1 I nitialization Role of CKE During power up CKE is the only input to the SDRAM that has its level recognized other than the DDR3 reset pin once power is applied It must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during power up CKE signals remain LOW while any reset is active until the BIOS writes to a configuration register Using this method CKE is ensured to remain inactive for much longer than the specified 200 micro seconds after power and clocks to SDRAM devices are stable 4 3 2 2 Conditional Self Refresh Intel Rapid Memory Power Management Intel RMPM conditionally places memory into self refresh in the package C3 and C6 low power states Intel RMPM functionality depends on the graphics display state relevant only when processor graphics is being
120. ology and width may vary from one channel to the other Rules for Populating Memory Slots In all modes the frequency of system memory is the lowest frequency of all memory modules placed in the system as determined through the SPD registers on the memory modules The system memory controller supports one or two DIMM connectors per channel The usage of DIMM modules with different latencies is allowed but in that case the worst latency per channel will be used For dual channel modes both channels must have a DIMM connector populated and for single channel mode only a single channel may have one or both DIMM connectors populated In a 2 DIMM Per Channel 2DPC daisy chain layout memory configuration the furthest DIMM from the processor of any given channel must always be populated first Datasheet Volume 1 Interfaces 2 1 5 2 1 5 1 2 1 5 2 2 1 5 3 2 1 6 2 1 7 Technology Enhancements of Intel Fast Memory Access Intel FMA The following sections describe the Just in Time Scheduling Command Overlap and Out of Order Scheduling Intel FMA technology enhancements Just in Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next The most efficient request is picked from all pending requests and issued to system memory Just in Time to make optimal use of Command Overlapping Thus
121. olume 1 intel Processor Pin and Signal Information 94 Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir BCLK_ITP c40 Diff Clk I DMI TX 0 V6 DMI BCLK_ITP D40 Diff Clk I DMI_TX 1 ws DMI BCLK 0 w2 Diff Clk I DMI_TX 2 Y7 DMI BCLK 0 wi Diff Clk I DMI_TX 3 8 DMI BPM 0 H40 GTL 1 0 FC AH1 AH1 N A BPM 1 H38 GTL I O FC_AH4 AH4 N A BPM 2 G38 GTL I O FDI_COMPIO AE2 Analog I BPM 3 G40 GTL 1 0 FDI FSYNC 0 AC5 CMOS I BPM 4 G39 GTL 1 0 FDI FSYNC 1 AE5 CMOS I BPM 5 F38 GTL 1 0 FDI_ICOMPO AE1 Analog I BPM 6 E40 GTL 1 0 FDI_INT AG3 CMOS I BPM 7 F40 GTL 1 0 FDI_LSYNC 0 AC4 CMOS I CATERR E37 GTL FDI LSYNC 1 AE4 CMOS I CFG 0 H36 CMOS I FDI TX 0 AC8 FDI CFG 1 J36 CMOS I FDI TX 1 AC2 FDI CFG 10 M38 CMOS I FDI TX 2 AD2 FDI CFG 11 N36 CMOS I FDI TX 3 AD4 FDI CFG 12 N38 CMOS I FDI TX 4 AD7 FDI CFG 13 N39 CMOS I FDI TX 5 AE7 FDI CFG 14 N37 CMOS I FDI TX 6 AF3 FDI CFG 15 N40 CMOS I FDI TX 7 AG2 FDI CFG 16 G37 CMOS I FDI_TX 0 AC7 FDI CFG 17 G36 CMOS I FDI_TX 1 AC3 FDI CFG 2 137 CMOS I FDI_TX 2 AD1 FDI CFG 3 K36 CMOS I FDI_TX 3 AD3 FDI CFG 4 L36 CMOS I FDI_TX 4 AD6 FDI CFG 5 N35 CMOS I F
122. on Cpec 10pF Node Host Originator PECI Client Additional PECI Clients Datasheet Volume 1 Electrical Specifications 7 11 2 Table 7 11 7 11 3 Figure 7 2 intel DC Characteristics The PECI interface operates at a nominal voltage set by Vcc o The set of DC electrical specifications shown in Table 7 11 is used with devices normally operating from a Vcc o interface supply Vccro nominal levels will vary between processor families All PECI devices will operate at the Vcc o level determined by the processor installed in the system For specific nominal Vcc o levels refer to Table 7 6 PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes Rup Internal pull up resistance 15 45 Ohm 3 Vin Input Voltage Range 0 15 Vccio V Vhysteresis Hysteresis 0 1 Vec o N A V Vn Negative Edge Threshold Voltage 0 275 Vecro 0 500 Vecio V Vp Positive Edge Threshold Voltage 0 550 Vccro 0 725 Vecio V Cbus Bus Capacitance per Node N A 10 pF Cpad Pad Capacitance 0 7 1 8 pF Ileak000 leakage current at OV 0 6 mA 2 Ileak025 leakage current at 0 25 Vcc o E 0 4 mA 2 Ileak050 leakage current at 0 50 Vcc o x 0 2 mA 2 IleakO75 leakage current at 0 75 Vcc o 0 13 mA 2 Ileak100 leakage current at Vcc o 0 10 mA 2 Notes 1 Vccro supplies the PECI interface PECI behavior does not affect Vcc o
123. onality some BLT functions make use of the 3D renderer Processor Graphics VGA Registers The 2D registers consists of original VGA registers and others to support graphics modes that have color depths resolutions and hardware acceleration features that go beyond the original VGA standard Logical 128 Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows operating systems The 128 bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations The BLT engine can be used for the following Move rectangular blocks of data between memory locations Data alignment To perform logical operations raster ops The rectangular block of data does not change as it is transferred between memory locations The allowable memory transfers are between cacheable system memory and frame buffer memory frame buffer memory and frame buffer memory and within system memory Data to be transferred can consist of regions of memory patterns or solid color fills A pattern is always 8 x 8 pixels wide and may be 8 16 or 32 bits per pixel The BLT engine expands monochrome data into a color depth of 8 16 or 32 bits BLTs can be either opaque or transparent Opaque transfers move the data specified to the destination Transparent transfers compare destination color to source color and write according to the mode of transparency selected Data is horizontally a
124. ondition Ratings a nr ee 79 7 5 Processor Core Active and Idle Mode DC Voltage and Current Specifications 80 7 6 Processor System Agent I O Buffer Supply DC Voltage and Current Specifications 82 7 7 Processor Graphics VID based Vayg Supply DC Voltage and Current Specifications 83 7 8 DDR3 Signal Group DC Specifications eee eect eee ee eee eee anne nennen eee 84 7 9 Control Sideband and TAP Signal Group DC 5 85 7 10 PCI Express DC SpecifiCallOris iieri rd Pos petu ann 85 7 11 PECI DC Electrical Limits x kennen rre nera menn utin inen e FR nk eR e ERR a n a e OR E 87 8 1 Processor Pin List by Pin Name eek RARO U RECAP 94 9 1 DDR Data Swizzling Table Channel nn nun nenn nn ann ernennen nennen 110 9 2 DDR Data Swizzling Table Channel B nn nun nennen ann ernennen nennen 111 Datasheet Volume 1 7 intel Revision History Revision Description Revision Number Date T January 001 Initial release 2011 e Added Intel Core i5 2405S i5 2310 and i3 2105 processors 002 e Added Intel Pentium processor family desktop Intel May 2011 Pentium G850 G840 G620 and G620T processors e Added
125. patibility with future processors See Chapter 8 for a land listing of the processor and the location of all reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability For details see Table 7 9 Datasheet Volume 1 Electrical Specifications 7 7 Table 7 3 Signal Groups intel Signals are grouped by buffer type and similar characteristics as listed in Table 7 3 The buffer type indicates which signaling technology and specifications apply to the signals All the differential signals and selected DDR3 and Control Sideband signals have On Die Termination ODT resistors There are some signals that do not have ODT and need to be terminated on the board Signal Groups Sheet 1 of 2 Signal Group Type Signals System Reference Clock Differential CMOS Input BCLK 0 BCLK 0 DDR3 Reference Clocks Differential DDR3 Output DDR3 Command Signals SA CK 3 0 SA CK 3 0 SB CK 3 0 SB CK 3 0 Single Ended DDR3
126. per s Manual Volume 3A 3B System Programmer s Guide for more information While a core is in C1 C1E state it processes bus snoops and snoops from other threads For more information on C1E see Section 4 2 5 2 Core C3 State Individual threads of a core can enter the C3 state by initiating a P LVL2 I O read to the P BLK or an MWAIT C3 instruction A core in C3 state flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core s caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory Core C6 State Individual threads of a core can enter the C6 state by initiating a P LVL3 I O read or an MWAIT C6 instruction Before entering core C6 the core will save its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts During exit the core is powered on and its architectural state is restored C State Auto Demotion In general deeper C states such as C6 have long latencies and have higher energy entry exit costs The resulting performance and energy penalties become significant when the entry exit frequency of a deeper C state is high Therefore incorrect or inefficient usage of deeper C states have a negative impact on power To increase residency
127. pports a maximum of 2 displays connected to the PEG card in parallel with up to 2 displays connected to the PCH When supporting Multi Graphics controllers Multi Monitors drag and drop between monitors and the 2x8 PEG is not supported Datasheet Volume 1 Interfaces t 2 5 Platform Environment Control Interface PECI The PECI is a one wire interface that provides a communication channel between a PECI client processor and a PECI master The processor implements a PECI interface to Allow communication of processor thermal and other information to the PECI master Read averaged Digital Thermal Sensor DTS values for fan speed control 2 6 I nterface Clocking 2 6 1 I nternal Clocking Requirements Table 2 4 Reference Clock Reference Input Clock Input Frequency Associated PLL BCLK 0 BCLK 7 0 Datasheet Volume 1 100 MHz 88 Processor Memory Graphics PCIe DMI FDI 33 34 Interfaces Datasheet Volume 1 Technologies intel 3 Technologies This chapter provides a high level description of Intel technologies implemented in the processor The implementation of the features may vary between the processor SKUs Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site http www intel com technology 3 1 Intel virtualization Technology Intel VT Intel Virtualization Technology Intel VT m
128. press Output En PEG_TX 15 0 PE_TX 3 0 Single Ended Analog Input PEG_ICOMPO PEG_COMPI PEG_RCOMPO DMI Differential DMI Input DMI_RX 3 0 DMI_RX 3 0 Differential DMI Output DMI TX 3 0 DMI TX2 3 0 Intel FDI Single Ended FDI Input FDI FSYNC 1 0 FDI LSYNC 1 0 FDI INT Differential FDI Output FDI TX 7 0 FDI TX2 7 0 Single Ended Analog Input FDI COMPIO FDI ICOMPO Notes 1 Refer to Chapter 6 and Chapter 8 for signal description details 2 SAand SB refer to DDR3 Channel A and DDR3 Channel B 3 The maximum rise fall time for UNCOREPWRGOOD is 20 ns All Control Sideband Asynchronous signals are required to be asserted de asserted for at least 10 BCLKs with a maximum Trise Tfall of 6 ns for the processor to recognize the proper signal state See Section 7 10 for the DC specifications Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level The processor supports Boundary Scan JTAG IEEE 1149 1 2001 and IEEE 1149 6 2003 standards Some small portion of the I O pins may support only one of these stan
129. re 8 2 Socket Pinmap Top View Upper Right Quadrant 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 aS SB BS 2 21 SA DQ 30 puse pus Row Be nidi Mjeeiiel se ma Aereo VCCIO VCCIO Datasheet Volume 1 91 i L Processor Pin and Signal Information Figure 8 3 Socket Pinmap Top View Lower Left Quadrant VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VIDSOU UU 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Rom RSW raw O0 OO mmo r xr ZZ Dy aD Je lt SES KX 92 Datasheet Volume 1 Processor Pin and Signal Information m Figure 8 4 Socket Pinmap Top View Lower Right Quadrant M VCCIO x Ln 3 VCCIO VCCIO PE_RX 3 pe TX 1 PE RX 2 VCCIO PE TX 2 VCCIO VCCIO PE RXI1 re xor PE TX 0 PE RX4 0 PE RX 0 VCCIO VCCIO VCCIO VCCSA VCCSA VCCSA VCCSA VCCSA VCCIO VCCIO VCCSA VCCSA VCCIO VCCIO VCCSA VCCSA VCCSA RSD RSD VCCIO VCCIO PEG RX9 rcx VCCIO NCTF PEG 11 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ar Um I Datasheet V
130. rection Signal Name Description Buffer Type SM DRAMPWROK Processor Input Connects to PCH I SM DRAMPWROK DRAMPWROK Asynchronous CMOS The processor requires this input signal to be a clean indication that the Vccsa Vector Vaxg and Vppo power supplies are stable and within specifications This requirement applies regardless of the S I state of the processor Clean implies that the signal will remain low UNCORERWRGOOD capable of sinking leakage current without glitches from the time Asynchronous that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state This is connected to the PCH PROCPWRGD signal SKTOCC Socket Occupied Pulled down directly 0 Ohms on SKTOCC the processor package to ground There is no connection to the processor silicon for this signal System board designers may use this signal to determine if the processor is present Datasheet Volume 1 67 intel 6 11 Signal Description Processor Power Signals Table 6 13 Processor Power Signals Pr Direction Signal Name Description Buffer Type VCC Processor core power rail Ref VCCIO Processor power for I O Ref VDDQ Processor I O supply voltage for DDR3 Ref VCCAXG Graphics core power supply Ref VCCPLL VCCPLL provides isolated power for internal processor PLLs Ref VCCSA System Agent power suppl
131. regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself VID signals are CMOS push pull drivers Refer to Table 7 9 for the DC specifications for these signals The VID codes will change due to temperature and or current load changes in order to minimize the power of the part A voltage range is provided in Table 7 5 The specifications are set so that one voltage regulator can operate with all supported frequencies Individual processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings This is shown in the VID range values in Table 7 5 The processor provides the ability to operate while transitioning to an adjacent VID and its associated voltage This will represent a DC shift in the loadline See the VR12 IMVP7 SVID Protocol for further details Datasheet Volume 1 intel Electrical Specifications Sheet 1 of 3 VID VID VID VID VID VID VID VID inition VR 12 0 Voltage Identification Def Table 7 1 0 89000 0 97000 1 00000 1 00500 1 01000 1 01500 1 02000 1 02500 1 03000 1 03500 1 04000 1 04500 1 05000 1 05500 1 06000 1 06500 1 07000 1 07500 1 08000 1 08500 1 09000 1 09500 HEX wax 1 5 0 91000 E 0 95500 F 0 96000 1 3 0 98000 5 0 99000 E F 1 3 5 8 O 0 88500 8 8 2 0 89500 8 3 0 90000 8 4 0 90500
132. rity Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Active Management Technology requires the computer system to have an Intel R AMT enabled chipset network hardware and software as well as connection with a power source and a corporate network connection Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality It may also require modifications of implementation of new business processes With regard to notebooks Intel AMT may not be available or certain capabilities may be limited over a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see http www intel com technology platform technology intel amt Hyper Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use
133. ssability for both the logical and physical destination modes e Adds new features to enhance performance of interrupt delivery Reduces complexity of logical destination mode interrupt delivery on link based architectures The key enhancements provided by the x2APIC architecture over xAPIC are the following e Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations In xAPIC compatibility mode APIC registers are accessed through a memory mapped interface to a 4 KB page identical to the xAPIC architecture In x2APIC mode APIC registers are accessed through Model Specific Register MSR interfaces In this mode the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery e Increased range of processor addressability in x2APIC mode Physical xAPIC ID field increases from 8 bits to 32 bits allowing for interrupt processor addressability up to 4G 1 processors in physical destination mode A processor implementation of x2APIC architecture can support fewer than 32 bits in a software transparent fashion Logical xAPIC ID field increases from 8 bits to 32 bits The 32 bit logical x2APIC ID is partitioned into two sub fields a 16 bit cluster ID and a 16 bit logical ID within the cluster Consequently 2 20 16 processors can be addressed in logical destination mode Processor implementations
134. ssed by the Transaction Layer of the receiving device Figure 2 3 Packet Flow through the Layers mu uan p omo ae u a fae zw Sm OT a 5 Sequence I I Framing i Data ECRC LCRC Framing A J A Transaction Layer Data Link Layer M Physical Layer x 2 2 1 1 Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is the assembly and disassembly of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs 2 2 1 2 Data Link Layer The middle layer in the PCI Express stack the Data Link Layer serves as an intermediate stage between the Transaction Layer and the Physical Layer Responsibilities of Data Link Layer include link management error detection and error correction The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer calculates and applies data protection code and TLP sequence number and submits them to Physical Layer for transmission across the Link The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing On detection of TLP error s this layer is responsible for requesting retransmission of TLPs until information is correctly r
135. sssseseeemmme 52 4 3 2 DRAM Power Management and Initialization esses 53 4 3 2 1 Initialization Role of CKE iieri entree nex na pu xr ex 54 4 3 2 2 Conditional Self Refresh leise ener ttai anne 54 4 3 2 3 Dynamic Power down 55 4 3 2 4 DRAM I O Power Management euesensnsenannnnnnnnnnnn nennen nennen nennen 55 4 4 PCI Express Power Management ene nnne nnn nns 55 4 5 Direct Media Interface DMI Power Management ee 55 4 6 Graphics Power Management nn nn nennen 56 4 6 1 Intel Rapid Memory Power Management Intel RMPM also known s CXSR cu iine tenen terrre panna ana ana 56 4 6 2 Intel Graphics Performance Modulation Technology Intel 56 4 6 3 Graphics Render C State scende ette er 56 4 6 4 Intel Smart 2D Display Technology Intel 525 56 4 6 5 Intel Graphics Dynamic 4 nnns 57 4 7 Thermal Power Management sessseeseieee sanus nha aaa RA RR anna anna nenn anna nn nennen 57 5 Ther
136. t DMAs by using DMA remapping a key feature of Intel VT d IOV I O Virtualization ITPM Integrated Trusted Platform Module LCD Liquid Crystal Display LVDS Low Voltage Differential Signaling A high speed low power data transmission standard used for display connections to LCD panels Non Critical to Function NCTF locations are typically redundant ground or non NCTF critical reserved so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality Datasheet Volume 1 Introduction Table 1 2 intel Terminology Sheet 2 of 2 Term Description PCH Platform Controller Hub The new 2009 chipset with centralized platform capabilities including the main I O interfaces along with display connectivity audio features power management manageability security and storage features PECI Platform Environment Control Interface PEG PCI Express Graphics External Graphics using PCI Express Architecture A high speed serial interface whose configuration is software compatible with the existing PCI specifications Processor The 64 bit single core or multi core component package Processor Core Processor Graphics The term processor core refers to Si die itself which can contain multiple execution cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the L3 cache Intel
137. t Differential Pairs FDI_TX 7 0 FDI _p FDI1_FSYNC 1 Intel Flexible Display Interface Frame Sync Pipe B I CMOS _ pi FDI1 LSYNC 1 Intel Flexible Display I nterface Line Sync Pipe B I CMOS Intel Flexible Display Interface Hot Plug I nterrupt I FDI INT Asynchronous CMOS Datasheet Volume 1 65 Signal Description intel 6 6 Direct Media Interface DMI Signals Table 6 8 Direct Media Interface DMI Signals Processor to PCH Serial Interface Direction Signal Name Description Buffer Type DMI RX 3 0 DMI Input from PCH Direct Media Interface receive differential pair I DMI RX 3 0 DMI DMI TX 3 0 DMI Output to PCH Direct Media Interface transmit differential pair 0 DMI_TX 3 0 DMI 6 7 Phase Lock Loop PLL Signals Table 6 9 Phase Lock Loop PLL Signals Direction Signal Name Description Buffer Type BCLK Differential bus clock input to the processor I BCLK Diff Clk 6 8 Test Access Points TAP Signals Table 6 10 Test Access Points TAP Signals 5 Direction Signal Name Description Buffer Type Breakpoint and Performance Monitor Signals These signals are BPM 7 0 outputs from the processor that indicate the status of breakpoints I O and programmable counters used for monitoring processor CMOS performance BCLK_ITP These pins are connected in parallel to the top side debug probe to 1
138. t translations No support for advance fault reporting No support for super pages No support for Intel VT d translation bypass address range such usage models need to be resolved with VMM help in setting up the page tables correctly 37 intel Technologies 3 3 38 Intel Trusted Execution Technology Intel TXT Intel Trusted Execution Technology Intel TXT defines platform level enhancements that provide the building blocks for creating trusted platforms The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute These extensions enhance two areas The launching of the Measured Launched Environment MLE The protection of the MLE from potential corruption The enhanced pl
139. the processor is not required to enter CO before entering any other C state The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following If a core break event is received the target core is activated and the break event message is forwarded to the target core If the break event is not masked the target core enters the core CO state and the processor enters package CO If the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package remains in the higher power C state Table 4 10 Coordination of Core Power States at the Package Level Core 1 Package C State co c1 c3 C6 co co co co co C1 CO cit cit ci Core 0 C3 CO cit 03 03 C6 CO cit 03 C6 Note 1 If enabled the package C state will be C1E if all cores have resolved a core C1 state or higher 50 Datasheet Volume 1 Power Management intel Figure 4 4 Package C State Entry and Exit 4 2 5 1 4 2 5 2 Package CO This is the normal operating state for the processor The processor remains in the normal state when at least one of its cores is in the CO or C1 state or when the p
140. tsveedenerdn 36 3 1 4 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Features ci quada deca nee 37 3 1 5 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Features Not Supported ceceeee een 37 3 2 Intel Trusted Execution Technology Intel TXT 38 3 3 Intel Hyper Threading Technology Intel HT 38 3 4 Intel Turbo Boost Technalogyarsancucnansnunnannnn iaa dorada Quince caia nai addat 39 3 4 1 Intel Turbo Boost Technology Frequency cscsssccccscssscncceccesesesenececaunenenes 39 3 4 2 Intel Turbo Boost Technology Graphics 39 3 5 Intel Advanced Vector Extensions Intel AVX sss 40 3 6 Intel Advanced Encryption Standard New Instructions Intel AES NI 40 36 1 PELMULODO oi riii aae ey ke er aa an Dh 40 3 7 Intel 64 Architecture Rye ada Ne tU Dd n 40 Power Management essei seinen kn dann ak den hera adn hd nn a 43 4 1 Advanced Configuration and Power Interface ACPI States Supported 44 4 1 1 SYStEM StateSins ieu pex cage CORR 44 4 1 2 Processor Core Package Idle States sss 44 4 1 3 Integrated
141. updated with characterized data from silicon measurements at a later Vccsa must be provided using a separate voltage source and not be connected to Vcc This specification is measured at VCCSA SENSE Notes 1 date 2 3 5 total Minimum of 2 DC and 3 AC at the sense point di dt 50 A us with 150 ns step Datasheet Volume 1 Electrical Specifications Table 7 7 Datasheet Volume 1 intel Processor Graphics VID based Vaxc Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note VAXG GFX VID GFX VID Range for VccAxG hange 0 2500 1 5200 V 1 Vccaxc Loadline Slope 4 1 mt 3 4 Vcc Tolerance Band VaxcTOB PSO PS1 19 mV 3 4 5 PS2 11 5 Ripple PSO 10 VaxcRipple PS1 10 mV 3 4 5 PS2 10 15 Current for Processor Graphics I Sustained current for Processor m m 25 A Graphics core Notes 1 Vecaxg is VID based rail 2 Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurements at a later date 3 The Vaxc min and Vaxc max loadlines represent static and transient limits 4 The loadlines specify voltage limits at the die measured at the VAXG SENSE and VSSAXG SENSE lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VAXG
142. vice and delivers that data to a display pipe This is clocked by the Core Display Clock Planes A and B Planes A and B are the main display planes and are associated with Pipes A and B respectively The two display pipes are independent allowing for support of two independent display streams They are both double buffered which minimizes latency and improves visual quality Sprite A and B Sprite A and Sprite B are planes optimized for video decode and are associated with Planes A and B respectively Sprite A and B are also double buffered Cursors A and B Cursors A and B are small fixed sized planes dedicated for mouse cursor acceleration and are associated with Planes A and B respectively These planes support resolutions up to 256 x 256 each Datasheet Volume 1 31 2 4 2 1 4 2 4 2 2 2 4 2 3 2 4 3 2 4 4 Note 32 Interfaces Video Graphics Array VGA VGA is used for boot safe mode legacy games etc It can be changed by an application without OS driver notification due to legacy requirements Display Pipes The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed This is clocked by the Display Reference clock inputs The display pipes A and B operate independently of each other at the rate of 1 pixel per clock They can attach to any of the display ports Each pipe sends display d
143. y Ref VIDALERT VIDSCLK and VIDSCLK comprise a three signal serial 1 0 VIDSOUT synchronous interface used to transfer power management information VIDSCLK between the processor and the voltage regulator controllers This serial 1 VIDALERT VID interface replaces the parallel VID interface on previous CMOS processors VCCSA VID Voltage selection for VCCSA O 6 12 Sense Signals Table 6 14 Sense Signals Tm Direction Signal Name Description Buffer Type VCC SENSE VCC SENSE and VSS SENSE provide an isolated low impedance VSS SENSE connection to the processor core voltage and ground They can be Anal used to sense or measure voltage near the silicon nalog VAXG SENSE VAXG_SENSE and VSSAXG_SENSE provide an isolated low VSSAXG SENSE impedance connection to the Vayg voltage and ground They can Anal be used to sense or measure voltage near the silicon nalog VCCIO SENSE VCCIO_SENSE and VSS_SENSE_VCCIO provide an isolated low ie impedance connection to the processor Vcc o voltage and ground VSS_SENSE_VCCIO They can be used to sense or measure voltage near the silicon Analog VDDQ_SENSE VDDQ_SENSE and VSSD_SENSE provides an isolated low VSSD SENSE impedance connection to the Vppo voltage and ground They can Arial be used to sense or measure voltage near the silicon ngatog VCCSA_SENSE provide an isolated low impedance connection to o VCCSA_SENSE the processor system agent voltage It can be used to sense or Anal measure voltage

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