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Transcend 16GB 40-pin PATA SLC

1. DASPB PDIAGB RESET Transcend Information Inc 3 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Exceeding Your Expectations Absolute Maximum Ratings Symbol Parameter Min Max Unit VDD VSS DC Power Supply 0 6 6 V Ta Operating Temperature 0 70 C Tst Storage Temperature 40 85 C Recommended Operating Conditions Symbol Parameter Min Max Units VDD Power supply 3 0 5 5 V VIN Input voltage 0 VDD 0 3 V Ta Operating Temperature 0 70 C DC Characteristics Ta 0 C to 70 C Vcc 5 0V 10 Parameter Symbol Min Max Unit Remark Supply Voltage Voc 4 5 5 5 V High level output voltage Vou Voc 0 8 V Low level output voltage VoL 0 8 V 4 V Non schmitt tri High level input voltage Vin s a rigger 2 92 V Schmitt trigger V Non schmitt tri Low level input voltage Vit s d um F ngger 1 70 V Schmitt trigger Ta 0 C to 70 C Vcc 3 3V 5 Parameter Symbol Min Max Unit Remark Supply Voltage Voc 3 135 3 465 V High level output voltage Vou Voc 0 8 V Low level output voltage VoL 0 8 V 2 4 V Non schmitt trigger High level input voltage V ieee g H 2 05 V Schmitt trigger F V Non schmitt tri Low level input voltage Vit uh oe P 1 25 V Schmitt trigger Transcend Information Inc Ver 1 3 Transcend 40 Pin
2. d While operating in Ultra DMA modes 2 1 or 0 the host shall be prepared to receive zero one or two additional data words after negating HDMARDY While operating in Ultra DMA modes 4 or 3 the host shall be prepared to receive zero one two or three additional data words The additional data words are a result of cable round trip delay and tres timing for the device e The host shall resume an Ultra DMA data burst by asserting HDMARDY DMAR device DMAC host STOP host HDMARDY host DSTROBE device Data D 15 00 device ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM Notes 1 The host may assert STOP to request termination of the Ultra DMA data burst no sooner than tpp after HDMARDY is negated 2 After negating HDMARDY the host may receive zero one two or three more data words from the device 3 The bus polarity of the DMARQ and DMACK signals is dependent on the active interface mode Transcend Information Inc 19 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Exceeding Your Expectations Device Terminating an Ultra DMA Data In Burst The device terminates an Ultra DMA Data In burst by following the steps lettered below The timing diagram is shown in below Ultra DMA Data In Burst Device Termination Timing The timing parameters are spe
3. Ultra DMA Data Out Burst Host Termination Timing while timing parameters are specified in Page 12 Ultra DMA Data Burst Timing Requirements and timing parameters are described in Page 13 Ultra DMA Data Burst Timing Descriptions The following steps shall occur in the order they are listed unless otherwise specifically allowed a The host shall initiate termination of an Ultra DMA data burst by not generating HSTROBE edges b The host shall assert STOP no sooner than tss after it last generated an HSTROBE edge The host shall not negate STOP again until after the Ultra DMA data burst is terminated c The device shall negate DMARQ within t after the host asserts STOP The device shall not assert DMARQ again until after the Ultra DMA data burst is terminated d The device shall negate DDMARDY within t after the host has negated STOP The device shall not assert DDMARDY again until after the Ultra DMA data burst termination is complete e If HSTROBE is negated the host shall assert HSTROBE within t after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition on HSTROBE HSTROBE shall remain asserted until the Ultra DMA data burst is terminated f The host shall place the result of its CRC calculation on D 15 00 see ATA specification Ultra DMA CRC Calculation g The host shall negate DMACK no sooner than tmu after the host has asserted HSTROBE and STOP a
4. 0000h 2 Obsolete 21 0000h 2 Obsolete 22 0004h 2 Number of ECC bytes passed on Read Write Long Commands 23 26 aaaa 8 Firmware revision in ASCII Big Endian Byte Order in Word Model number in ASCII Left Justified Big Endian Byte Order in 27 46 aaaa 40 Word 47 XXXXh 2 Maximum number of sectors on Read Write Multiple command 48 0000h 2 Reserved 49 XX00h 2 Capabilities 50 0000h 2 Reserved Transcend Information Inc 31 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Exceeding Your Expectations Pian ae Ee Data Field Type Information 51 0200h 2 PIO data transfer cycle timing mode 52 0000h 2 Obsolete 53 000Xh 2 Field Validity 54 XXXXh 2 Current numbers of cylinders 55 XXXXh 2 Current numbers of heads 56 XXXXh 2 Current sectors per track 57 58 XXXXh 4 Current capacity in sectors LBAs Word 57 LSW Word 58 59 01XXh 2 Multiple sector setting 60 61 XXXXh 4 Total number of sectors addressable in LBA Mode 62 0000h 2 Reserved 63 0X0Xh 2 Multiword DMA transfer In PC Card modes this value shall be Oh 64 0003h 2 Advanced PIO modes supported Minimum Multiword DMA transfer cycle time per word In PC Card A AAR 2 modes this value shall be Oh i i 66 XXXXh 2 ira N e N a Pij transfer cycle time In PC Card 67 XXXXh 2 Minimum PIO transfer cycle time without flow control 68 XXXXh 2 Minimum PIO transfer
5. 02 00 CS0 CS1 IDE ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM Notes The definitions for the IORDY DDMARDY DSTROBE IORD HDMARDY HSTROBE and IOWR STOP signal lines are not in effect until DMARQ and DMACK are asserted A 02 00 CS0 amp CS1 are True IDE mode signal definitions Transcend Information Inc 17 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Sustaining an Ultra DMA Data In Burst An Ultra DMA Data In burst is sustained by following the steps lettered below The timing diagram is shown in below Sustained Ultra DMA Data In Burst Timing The timing parameters are specified in Page 12 Ultra DMA Data Burst Timing Requirements and are described in Page 13 Ultra DMA Data Burst Timing Descriptions The following steps shall occur in the order they are listed unless otherwise specifically allowed a The device shall drive a data word onto D 15 00 b The device shall generate a DSTROBE edge to latch the new word no sooner than tpvs after changing the state of D 15 00 The device shall generate a DSTROBE edge no more frequently than tcyc for the selected Ultra DMA mode The device shall not generate two rising or two falling DSTROBE edges more frequently than 2tcyc for the selected Ultra DMA mode c The device shall not change the state of D 15 00 until at least tov a
6. IDE Flash Module TS128M 16GDOM40V S Transcend Transcend Information Inc 5 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 146GDOM40V S Transcend True IDE PIO Mode Read Write Timing Mode Mode Mode Mode Mode Mode Mode Item 0 1 2 3 4 5 6 to Cycle time min 600 383 240 180 120 100 80 t Address Valid to IORD IOWR setup min 70 50 30 30 25 15 10 t2 IORD IOWR min 165 125 100 80 70 65 55 t IORD IOWR min Register 8 bit 290 290 290 80 70 65 55 to IORD IOWR recovery time min 70 25 25 20 t3 IOWR data setup min 60 45 30 30 20 20 15 t4 IOWR data hold min 30 20 15 10 10 5 5 ts IORD data setup min 50 35 20 20 20 15 10 te IORD data hold min 5 5 5 5 5 5 5 tez IORD data tristate max 30 30 30 30 30 20 20 ty Address valid to OCS16 assertion max 90 50 40 N A N A N A N A ts Address valid to OCS16 released max 60 45 30 N A N A N A N A tg IORD IOWR to address valid hold 20 15 10 10 10 10 10 tro Read Data Valid to IORDY active min if IORDY initially low after tA o i H 4 9 ta IORDY Setup time 35 35 35 35 35 N A N A tg IORDY Pulse Width max 1250 1250 1250 1250 1250 N A N A tc IORDY assertion to release max 5 5 5 5 5 N A N A Notes All timings are in nanoseconds The maximum load on IOCS16 is 1 LSTTL
7. Symbol Function HDO HD15 Data Bus Bi directional HAO HA2 Address Bus Input RESET Device Reset Input IORB Device I O Read Input IOWB Device I O Write Input IOIS16B Transfer Type 8 16 bit Output CE1B CE2B Chip Select Input PDIAGB Pass Diagnostic Bi directional DASPB Disk Active Slave Present Bi directional DMARQ DMA request DMACK DMA acknowledge IREQ Interrupt Request Output NC No Connection GND Ground VCC Vcc Power Input Input Power The 40 Pin IDE Flash Module offers 2 ways to get input power either via the small power cord or through Pin 20 of the IDE connector If Pin 20 of the IDE connector is defined as NC No Connect then the 40 Pin IDE Flash Module must be directly connected to your system s power supply If Pin 20 of the IDE connector is defined as VCC then the 40 Pin IDE Flash Module can get necessary power without use of the power cord Pin Layout Pint Bulge Pin39 Pin2 Pin40 Transcend Information Inc Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Block Diagram With 1 pcs of Flash Memory FDO FD 8 HD0 HD15 IREG 1018168 HAO HA2 CE1B CE2B ATA FLASH ORB CONTROLLER o S o w o oO wi Q w a t DASPB PDIAGB RESET With 2 pcs of Flash Memory FDO FD HDO HD15 lt e iREG iO1S16B HAQ HA2 iCE1B CE2B ATA FLASH gt ORB CONTROLLER 40 Pins IDE Connector
8. United Kingdom E mail sales transcend uk com www transcend uk com Transcend Information Inc 35 Ver 1 3
9. calculation If a miscompare error occurs during one or more Ultra DMA data burst for any one command at the end of the command the device shall report the first error that occurred see ATA specification Ultra DMA CRC Calculation n While operating in True IDE mode the device shall release DSTROBE within tiorpyz after the host negates DMACK o The host shall neither negate STOP nor assert HDMARDY until at least tacx after the host has negated DMACK Transcend Information Inc 21 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend p In True IDE mode the host shall not assert IORD CSO CS1 nor A 02 00 until at least tack after negating DMACK DMARQ device tu bai DMACK host tray STOP host HDMARDY host DSTROBE device tevu Data D 15 00 _ XXX KKK KKK KK ORE EEE A 02 00 tack CS0 CS1 IDE ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM Notes The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated A 02 00 CSO amp CS1 are True IDE mode signal definitions Transcend Information Inc 22 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 146GDOM40V S Transcend Initiating an Ultra DMA Data Out Burst An Ultra DMA Data out burst is initiated by following the steps l
10. 10 Read multiple C4H Y Y Y Y Y Y 11__Read long sector 22H 23H Y Y Y Y Y 12 Read sector s 20H 21H Y Y Y Y Y Y 13 Read verify sector s 40H 41H Y Y Y Y Y Y 14 Recalibrate 1XH E Y 15 Request sense 03H Y 16 Seek TXH Y Y Y Y Y 17_ Set features EFH Y Y 18 Set multiple mode C6H Y Y 19 Set sleep mode E6H or 99H _ 7 Y 20 Stand by E2Hor96H Y 21 Stand by immediate EOH or 94H Y 22 Translate sector 87H Y Y Y 23 Wear level F5H Y Y 24 Write buffer E8H a Y 25 Write long sector 32H or 33H Y Y Y Y Y 26 Write multiple C5H Y Y Y Y Y Y 27 Write multiple w o erase CDH Y Y Y Y Y Y 28 Write sector 30H or 3141H Y Y Y Y Y Y 29 Write sector w o erase 38H Y Y Y y Y Y 30 Write veri 3CH E Y Y Y Y Y Y Note FR Feature Register SC Sector Count register 00H to FFH SN Sector Number register 01H to 20H CY Cylinder Low High register DR Drive bit of Drive Head register HD Head No 0 to 3 of Drive Head register Transcend Information Inc 33 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Exceeding Your Expectations Capacity Specifications Transcend P N Capacity Cylinder C Head H Sector S TS128MDOM40V S 128MB 248 16 63 TS256MDOM40V S 256MB 496 16 63 TS512MDOM40V S 512MB 993 16 63 TS1GDOM40V S 1GB 1942 16 6
11. 3 TS2GDOM40V S 2GB 3884 16 63 TS4GDOM40V S 4GB 7769 16 63 TS8GDOM40V S 8GB 15538 16 63 TS16GDOM40V S 16GB 33149 15 63 Transcend Information Inc 34 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Ordering Information T Transcend Product o Type V Vertical H Horizontal Capacity 128M 512M 128 MB up to 512 MB 1G 16G 1 GB up to 16 GB Pin Count 40 40 pin 44 44 pin IDE Flash Module Disk On Module The above technical information is based on industry standard data and has been tested to be reliable However Transcend makes no warranty either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes to the specifications at any time without prior notice USA Los Angeles E mail sales transcendusa com Transcend 2 E mail sales_md transcendusa com E is www transcendusa com Exceeding Your Expectations cua E mail sales transcendchina com www transcendchina com TAIWAN GERMANY No 70 XingZhong Rd NeiHu Dist Taipei Taiwan R O C E mail vertriepb transcend de TEL 886 2 2792 8000 Fax 886 2 2793 2222 www transcend de E mail sales transcend com tw HONG KONG www transcend com tw E mail sales transcend com hk www transcendchina com JAPAN E mail sales transcend co jp www transcend jp THE NETHERLANDS E mail sales transcend nl www transcend nl
12. DMA or a WRITE DMA command requiring data transfer and 3 the device asserts DMARQ and 4 the host asserts DMACK These signal lines revert back to the definitions used for non Ultra DMA transfers upon the negation of DMACK by the host at the termination of an Ultra DMA data burst With the Ultra DMA protocol the STROBE signal that latches data from D 15 00 is generated by the Transcend Information Inc 10 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 146GDOM40V S Transcend same agent either host or device that drives the data onto the bus Ownership of D 15 00 and this data strobe signal are given either to the device during an Ultra DMA data in burst or to the host for an Ultra DMA data out burst During an Ultra DMA data burst a sender shall always drive data onto the bus and after a sufficient time to allow for propagation delay cable settling and setup time the sender shall generate a STROBE edge to latch the data Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes the device is capable of supporting The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA mode at which the system operates The Ultra DMA mode selected by a host shall be less than or equal to the fastest mode of w
13. IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM Notes 1 The device may negate DMARQ to request termination of the Ultra DMA data burst no sooner than trp after DDMARDY is negated 2 After negating DDMARDY the device may receive zero one two or three more data words from the host Transcend Information Inc 26 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 146GDOM40V S Transcend Device Terminating an Ultra DMA Data Out Burst The device terminates an Ultra DMA Data Out burst by following the steps lettered below The timing diagram for the operation is shown in below Ultra DMA Data Out Burst Device Termination Timing The timing parameters are specified in Page 12 Ultra DMA Data Burst Timing Requirements and are described in Page 13 Ultra DMA Data Burst Timing Descriptions The following steps shall occur in the order they are listed unless otherwise specifically allowed a The device shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra DMA data burst has been transferred b The device shall initiate Ultra DMA data burst termination by negating DDMARDY c The host shall stop generating an HSTROBE edges within tars of the device negating DDMARDY d While operating in Ultra DMA modes 2 1 or 0 the device shall be prepared to receive zero one or two additional data words after negating HD
14. MARDY While operating in Ultra DMA modes 4 or 3 the device shall be prepared to receive zero one two or three additional data words The additional data words are a result of cable round trip delay and trrs timing for the device e The device shall negate DMARQ no sooner than trp after negating DDMARDY The device shall not assert DMARQ again until after the Ultra DMA data burst is terminated f The host shall assert STOP within t after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA data burst is terminated g If HSTROBE is negated the host shall assert HSTROBE within t after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition of HSTROBE HSTROBE shall remain asserted until the Ultra DMA data burst is terminated h The host shall place the result of its CRC calculation on D 15 00 see ATA specification Ultra DMA CRC Calculation i The host shall negate DMACK no sooner than tw after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DDMARDY and no sooner than tpvs after placing the result of its CRC calculation on D 15 00 j The device shall latch the host s CRC data from D 15 00 on the negating edge of DMACK k The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA d
15. Read Write Timing Specification Ultra DMA is an optional data transfer protocol used with the READ DMA and WRITE DMA commands When this protocol is enabled the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host This protocol applies to the Ultra DMA data burst only When this protocol is used there are no changes to other elements of the ATA protocol TRUE IDE MODE UDMA Signal Type UDMA DMARQ Output DMARQ DMACK Input DMACK STOP Input STOP HDMARDY R fau TEMARO HSTROBE W HSTROBE W DDMARDY W Output DDMARDY W DSTROBE R DSTROBE R DATA Bidir D 15 00 ADDRESS Input A 02 00 CSEL input CSEL INTRQ Output INTRQ CS0 Card Select Input cst Notes 1 The UDMA interpretation of this signal is valid only during an Ultra DMA data burst The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA Read command The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write command 2 3 4 The HSTROBE and DSTROBE signals are active on both the rising and the falling edge 5 Address lines 03 through 10 are not used in True IDE mode Several signal lines are redefined to provide different functions during an Ultra DMA data burst These lines assume their UDMA definitions when 1 an Ultra DMA mode is selected and 2 a host issues a READ
16. Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Exceeding Your Expectations Description With an IDE interface and strong data retention ability 40 Pin IDE Flash Modules are ideal for use in the harsh environments where Industrial PCs Set Top Boxes etc are used Placement Features RoHS compliant products Storage Capacity 128MB 16GB Operating Voltage 3 3V 5 or 5V 10 Operating Temperature 0 C 70 C Operating Humidity Non condensation 0 to 95 Storage Humidity Non condensation 0 to 95 Endurance 2 000 000 Program Erase cycles MTBF 1 000 000 hours Durability of Connector 10 000 times Fully compatible with devices and OS that support the IDE standard pitch 2 54mm Built in ECC function assures high reliability of data transfer Supports up to Ultra DMA Mode 4 Supports PIO Mode 6 Support Wear Leveling to extend product life Dimensions Side Millimeters Inches A 61 00 0 40 2 402 0 016 B 27 10 0 50 1 067 0 020 C 7 10 0 20 0 280 0 008 Transcend Information Inc Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Exceeding Your Expectations Pin Assignments Pin Pin 31 IREQ 32 lOIS16B 33 HA1 34 PDIAGB 35 HAO 36 HA2 37 CE1B 38 CE2B 39 DASPB 40 GND No Name Pin Definition
17. Y low before ta wait generated The cycle completes after IORDY is reasserted For cycles where a wait is generated and IORD is asserted the device shall place read data on D15 D00 for tro before causing IORDY to be asserted Transcend Information Inc Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Exceeding Your Expectations True IDE Multiword DMA Mode Read Write Timing Specification iem Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 ns ns ns ns ns to Cycle time min 480 150 120 100 80 to IORD IOWR asserted width min 215 80 70 65 55 te IORD data access max 150 60 50 50 45 tf IORD data hold min 5 5 5 5 5 te IORD IOWR data setup min 100 30 20 15 10 tH IOWR data hold min 20 15 10 5 5 ti DMACK to IORD IOWR setup min 0 0 0 0 0 ty IORD IOWR to DMACK hold min 20 5 5 5 5 tkr IORD negated width min 50 50 25 25 20 tkw IOWR negated width min 215 50 25 25 20 ttr IORD to DMARQ delay max 120 40 35 35 35 tiw IOWR to DMARQ delay max 40 40 35 35 35 tm CS 1 0 valid to IORD IOWR 50 30 25 10 5 tn CS 1 0 hold 15 10 10 10 10 tz DMACK 20 25 25 25 25 Notes 1 to is the minimum total cycle time and tp is the minimum command active time while tke and tkw are the minimum command recovery time or command inactive time for input and output cycles respectively The actual cycl
18. an Ultra DMA data burst i The host shall release D 15 00 within taz after asserting DMACK j The device may assert DSTROBE tziorpy after the host has asserted DMACK While operating in True IDE mode once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK at the end of an Ultra DMA data burst k The host shall negate STOP and assert HDMARDY within tenv after asserting DMACK After negating STOP and asserting HDMARDY the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device i e after the first data word has been received ae ee I The device shall drive D 15 00 no sooner than tzan after the host has asserted DMACK negated STOP and asserted HDMARDY m The device shall drive the first word of the data transfer onto D 15 00 This step may occur when the device first drives D 15 00 in step j n To transfer the first word of data the device shall negate DSTROBE within trs after the host has negated STOP and asserted HDMARDYV The device shall negate DSTROBE no sooner than tpvs after driving the first word of data onto D 15 00 Transcend Information Inc 16 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 146GDOM40V S Transcend DMARQ device A DMACK host STOP host e St host DSTROBE device taz Data 7 D15 DU DOOOOOOOPOS gt tack A
19. anscend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Host Terminating an Ultra DMA Data In Burst The host terminates an Ultra DMA Data In burst by following the steps lettered below The timing diagram is shown in below Ultra DMA Data In Burst Host Termination Timing The timing parameters are specified in Page 12 Ultra DMA Data Burst Timing Requirements and are described in Page 13 Ultra DMA Data Burst Timing Descriptions The following steps shall occur in the order they are listed unless otherwise specifically allowed a The host shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra DMA data burst has been transferred b The host shall initiate Ultra DMA data burst termination by negating HDMARDY The host shall continue to negate HDMARDY until the Ultra DMA data burst is terminated c The device shall stop generating DSTROBE edges within tars of the host negating HDMARDY d While operating in Ultra DMA modes 2 1 or 0 the host shall be prepared to receive zero one or two additional data words after negating HDMARDY While operating in Ultra DMA modes 4 or 3 the host shall be prepared to receive zero one two or three additional data words The additional data words are a result of cable round trip delay and trrs timing for the device e The host shall assert STOP no sooner than trp after negating HDMARDY The host shall not negate STOP again until after the Ultra DMA
20. ata bursts for any one command the device shall report the first error that occurred see ATA specification Ultra DMA CRC Calculation I While operating in True IDE mode the device shall release DSTROBE within tiorpyz after the host negates DMACK m The host shall not negate STOP nor assert HDMARDY until at least tack after negating DMACK n In True IDE mode the host shall not assert IOWR CSO CS1 nor A 02 00 until at least tack after negating DMACK Transcend Information Inc 27 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend DMARQ device DMACK host ty tu _ tack STOP lt host LY tee tioroyz DDMARDY device a ee thes HSTROBE host tevs Data D 15 00 host _20OOX DOOOOOOOOOXODK_CRG tack A 02 00 CS0 CS1 ID ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated A00 A02 CS0 amp CS1 are True IDE mode signal definitions TOPENEREONE CCIE DIE IE LPR Transcend Information Inc 28 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Host Terminating an Ultra DMA Data Out Burst Termination of an Ultra DMA Data Out burst by the host is shown in below
21. cified in Page 12 Ultra DMA Data Burst Timing Requirements and are described in Page 13 Ultra DMA Data Burst Timing Descriptions The following steps shall occur in the order they are listed unless otherwise specifically allowed a The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data burst has been transferred b The device shall pause an Ultra DMA data burst by not generating DSTROBE edges c NOTE The host shall not immediately assert STOP to initiate Ultra DMA data burst termination when the device stops generating STROBE edges If the device does not negate DMARQ in order to initiate Ultra DMA data burst termination the host shall negate HDMARDY and wait trp before asserting STOP d The device shall resume an Ultra DMA data burst by generating a DSTROBE edge DMARQ device DMACK host STOP host XXX HDMARDY mat N I XXX Z tss e gt tiorpyz DSTROBE device C tzan taz tevs tevH Data D 15 00 A 02 00 lack CS0 CS1 IDE occa ME ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM Notes The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated A 02 00 CS0 amp CS1 are True IDE mode signal definitions Transcend Information Inc 20 Ver 1 3 Tr
22. cycle time with IORDY flow control 69 79 0000h 20 Reserved 80 81 0000h 4 Reserved CF cards do not return an ATA version 82 84 XXXXh 6 Features command sets supported 85 87 XXXXh 6 Features command sets enabled 88 001Fh 2 Ultra DMA Mode Supported and Selected UDMA mode 0 4 89 XXXXh 2 Time required for Security erase unit completion 90 XXXXh 2 Time required for Enhanced security erase unit completion 91 XXXXh 2 Current Advanced power management value 92 127 0000h 72 Reserved 128 XXXXh 2 Security status 129 159 0000h 64 Vendor unique bytes 160 XXXXh 2 Power requirement description 161 0000h 2 Reserved for assignment by the CFA 162 0000h 2 Key management schemes supported 163 XXXXh 2 CF Advanced True IDE Timing Mode Capability and Setting 164 XXXXh 2 CF Advanced PC Card I O and Memory Timing Mode Capability 165 167 0000h 6 Reserved for assignment by the CFA 168 255 0000h 158 Reserved Transcend Information Inc 32 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend ATA Command Set No Command set Code FR Sc SN CY DR HD LSB 1 Check power mode E5H or 98H Y 2 _ Execute drive diagnostic 90H Y 3 Erase sector s COH Y Y Y Y Y Y 4 Format track 50H Y Y Y Y Y 5 Identify Drive ECH Y 6 Idle E3H or97H Y Y E E 7 Idle immediate E1H or95H_ Y 8 Initialize drive parameters 91H Y Y Y 9 Read buffer E4H Y
23. data burst is terminated f The device shall negate DMARQ within t after the host has asserted STOP The device shall not assert DMARQ again until after the Ultra DMA data burst is terminated g If DSTROBE is negated the device shall assert DSTROBE within t after the host has asserted STOP No data shall be transferred during this assertion The host shall ignore this transition on DSTROBE DSTROBE shall remain asserted until the Ultra DMA data burst is terminated h The device shall release D 15 00 no later than taz after negating DMARQ i The host shall drive D 15 00 no sooner than tzan after the device has negated DMARQ For this step the host may first drive D 15 00 with the result of its CRC calculation see ATA specification Ultra DMA CRC Calculation j If the host has not placed the result of its CRC calculation on D 15 00 since first driving D 15 00 during 9 the host shall place the result of its CRC calculation on D 15 00 see ATA specification Ultra DMA CRC Calculation k The host shall negate DMACK no sooner than tu after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY and no sooner than tpvs after the host places the result of its CRC calculation on D 15 00 I The device shall latch the host s CRC data from D 15 00 on the negating edge of DMACK m The device shall compare the CRC data received from the host with the results of its own CRC
24. e first negation of HSTROBE by the host j The host shall drive the first word of the data transfer onto D 15 00 This step may occur any time during Ultra DMA data burst initiation k To transfer the first word of data the host shall negate HSTROBE no sooner than tu after the device has asserted DDMARDYV The host shall negate HSTROBE no sooner than tpvs after the driving the first word of data onto D 15 00 C d wis a N e Transcend Information Inc 23 Ver 1 3 Transcend 40 Pin IDE Flash Module Exceeding Your Expectations DMARQ device Jn tu omak OOO yo host tack teny STOP host tziorpy tu tur DDMARDY device HSTROBE host Data D 15 00 SZSZSZS ZZ oo eS HE JE JE IE aw E HEE D host Pee se a V a PSPS 2L Maadl 26 2S waa PIA tack D A 02 00 CS0 CS1 IDE MEA NMEN ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted A 02 00 CS0 amp CS1 are True IDE mode signal definitions Transcend Information Inc 24 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Sustaining an Ultra DMA Data Out Burst An Ultra DMA Data Out burst is sustained by following the st
25. e time equals the sum of the actual command active time and the actual command inactive time The three timing requirements of to tp tkr and tkw shall be met The minimum total cycle time requirement is greater than the sum of tp and tkr or tkw for input and output cycles respectively This means a host implementation can lengthen either or both of tp and either of tkr and tkw as needed to ensure that to is equal to or greater than the value reported in the device s identify device data Transcend Information Inc Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Exceeding Your Expectations True IDE Multiword DMA Mode Read Write Timing Diagram O CS0 CS1 St le sf DMARQ O See Note 1 t L DMACK See Note 2 IORD A IOWR tz Read Data D15 D00 Write Data D15 D00 Figure 2 True IDE Multiword DMA Mode Read Write Timing Diagram Notes 1 If the Card cannot sustain continuous minimum cycle time DMA transfers it may negate DMARQ within the time specified from the start of a DMA transfer cycle to suspend the DMA transfers in progress and reassert the signal at a later time to continue the DMA operation 2 This signal may be negated by the host to suspend the DMA transfer in progress Transcend Information Inc 9 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 146GDOM40V S Transcend Ultra DMA Mode
26. ecipient shall wait to pause after negating DMARDY toroyz Maximum time before releasing IORDY tziorvy _ Minimum time before driving IORDY 4 taox_ Setup and hold times for DMACK before assertion or negation tss Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst Notes 1 The parameters tui tui in Page 19 Ultra DMA Data In Burst Device Termination Timing and Page 20 Ultra DMA Data In Burst Host Termination Timing and t indicate sender to recipient or recipient to sender interlocks i e one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding ty is an unlimited interlock that has no maximum time value tml is a limited time out that has a defined minimum t is a limited time out that has a defined maximum 2 80 conductor cabling see see ATA specification Annex A shall be required in order to meet setup tps tcs and hold tpp tcn times in modes greater than 2 3 Timing for toys tpv tevs and tcyH shall be met for lumped capacitive loads of 15 and 40 pF at the connector where the Data and STROBE signals have the same capacitive load value Due to reflections on the cable these timing measurements are not valid in a normally functioning system 4 For all timing modes the parameter tziorpy May be greater than teny due to the fact that the host has a pull up on IORDY Transcend Informat
27. eps lettered below The timing diagram is shown in below Sustained Ultra DMA Data Out Burst Timing The associated timing parameters are specified in Page 12 Ultra DMA Data Burst Timing Requirements and are described in Page 13 Ultra DMA Data Burst Timing Descriptions The following steps shall occur in the order they are listed unless otherwise specifically allowed a The host shall drive a data word onto D 15 00 b The host shall generate an HSTROBE edge to latch the new word no sooner than tpvs after changing the state of D 15 00 The host shall generate an HSTROBE edge no more frequently than tcyc for the selected Ultra DMA mode The host shall not generate two rising or falling HSTROBE edges more frequently than 2teyc for the selected Ultra DMA mode c The host shall not change the state of D 15 00 until at least tov after generating an HSTROBE edge to latch the data d The host shall repeat steps a b and c until the data transfer is complete or an Ultra DMA data burst is paused whichever occurs first HSTROBE at host Data D 15 00 at host HSTROBE at device Data D 15 00 a at device KXKKKKK KKK KKK Note Data D 15 00 and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Transcend Info
28. ettered below The timing diagram is shown in below Ultra DMA Data Out Burst Initiation Timing The timing parameters are specified in Page 12 Ultra DMA Data Burst Timing Requirements and are described in Page 13 Ultra DMA Data Burst Timing Descriptions The following steps shall occur in the order they are listed unless otherwise specifically allowed a The host shall keep DMACK in the negated state before an Ultra DMA data burst is initiated b The device shall assert DMARQ to initiate an Ultra DMA data burst Steps c d and e may occur in any order or at the same time The host shall assert STOP The host shall assert HSTROBE In True IDE mode the host shall not assert CSO CS1 nor A 02 00 f Steps c d and e shall have occurred at least tack before the host asserts DMACK The host shall keep DMACK asserted until the end of an Ultra DMA data burst g The device may negate DDMARDY tziorpy after the host has asserted DMACK While operating in True IDE mode once the device has negated DDMARDY the device shall not release DDMARDY until after the host has negated DMACK at the end of an Ultra DMA data burst h The host shall negate STOP within teny after asserting DMACK The host shall not assert STOP until after the first negation of HSTROBE i The device shall assert DDMARDY within t after the host has negated STOP After asserting DMARQ and DDMARDY the device shall not negate either signal until after th
29. finitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated A 02 00 CSO amp CS1 are True IDE mode signal definitions Transcend Information Inc 30 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 146GDOM40V S Transcend IDENTIFY DEVICE information The Identify Device command enables the host to receive parameter information from the device This command has the same protocol as the Read Sector s command The parameter words in the buffer have the arrangement and meanings defined in Table as below All reserved bits or words are zero Hosts should not depend on Obsolete words in Identify Device containing 0 Table below specifies each field in the data returned by the Identify Device Command In Table as below X indicates a numeric nibble value specific to the card and aaaa indicates an ASCII string specific to the particular drive Word Default Total Data Field Type Information Address Value Bytes 0 044Ah 2 General configuration Bit Significant with ATA 4 definitions 1 XXXXh 2 Default number of cylinders 2 0000h 2 Reserved 3 00XXh 2 Default number of heads 4 0000h 2 Obsolete 5 0000h 2 Obsolete 6 XXXXh 2 Default number of sectors per track 7 8 XXXXh 4 Number of sectors per card Word 7 MSW Word 8 LSW 9 XXXXh 2 Obsolete 10 19 aaaa 20 Serial number in ASCII Right Justified 20
30. fter generating a DSTROBE edge to latch the data d The device shall repeat steps a b and c until the data transfer is complete or an Ultra DMA data burst is paused whichever occurs first DSTROBE at device Data D 15 00 at device DSTROBE at host Data D 15 00 at host 22O QOQA OOOO XX OOX Notes D 15 00 and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Transcend Information Inc 18 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 146GDOM40V S Transcend Host Pausing an Ultra DMA Data In Burst The host pauses a Data In burst by following the steps lettered below A timing diagram is shown in below Ultra DMA Data In Burst Host Pause Timing The timing parameters are specified in Page 12 Ultra DMA Data Burst Timing Requirements and are described in Page 13 Ultra DMA Data Burst Timing Descriptions The following steps shall occur in the order they are listed unless otherwise specifically allowed a The host shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data burst has been transferred b The host shall pause an Ultra DMA data burst by negating HDMARDY c The device shall stop generating DSTROBE edges within tars of the host negating HDMARDY
31. hich the device is capable Only one Ultra DMA mode shall be selected at any given time All timing requirements for a selected Ultra DMA mode shall be satisfied Devices supporting any Ultra DMA mode shall also support all slower Ultra DMA modes An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a software reset sequence or the sequence caused by receipt of a DEVICE RESET command if a SET FEATURES disable reverting to defaults command has been issued The device may revert to a Multiword DMA mode if a SET FEATURES enable reverting to default has been issued An Ultra DMA capable device shall clear any previously selected Ultra DMA mode and revert to the default non Ultra DMA modes after executing a power on or hardware reset Both the host and device perform a CRC function during an Ultra DMA data burst At the end of an Ultra DMA data burst the host sends its CRC data to the device The device compares its CRC data to the data sent from the host If the two values do not match the device reports an error in the error register If an error occurs during one or more Ultra DMA data bursts for any one command the device shall report the first error that occurred If the device detects that a CRC error has occurred before data transfer for the command is complete the device may complete the transfer and report the error or abort the command and report the error NOTE Ifa data transfer is terminated before c
32. ime at recipient from data valid until STROBE edge tox Data hold time at recipient from STROBE edge until data may become invalid tovs Data valid setup time at sender from data valid until STROBE edge tov Data valid hold time at sender from STROBE edge until data may become invalid tcs CRC word setup time at device tou CRC word hold time device tevs __ CRC word valid setup time at host from CRC valid until DMACK negation 9 09 PO PO CO CO PO PO tovy CRC word valid hold time at sender from DMACK negation until CRC may become invalid tzFs Time from STROBE output released to driving until the first transition of critical timing tozrs Time from data output released to driving until the first transition of critical timing tes First STROBE time for device to first negate DSTROBE from STOP during a data in burst tu Limited interlock time 1 tut Interlock time with minimum 1 tui Unlimited interlock time 1 taz Maximum time allowed for output drivers to release from asserted or negated tran Minimum delay time required for output tzan drivers to assert or negate from released tenv Envelope time from DMACK to STOP and HDMARDY during data in burst initiation and from DMACK to STOP during data out burst initiation tres Ready to final STROBE time no STROBE edges shall be sent this long after negation of DMARDY trp Ready to pause time that r
33. imings in ns 1 All timing measurement switching points low to high and high to low shall be taken at 1 5 V 2 All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column For example in the case of tars both STROBE and DMARDY transitions are measured at the sender connector 3 The parameter tcyc shall be measured at the recipient s connector farthest from the sender 4 The parameter t shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively Both the incoming signal and the outgoing response shall be measured at the same connector 5 The parameter taz shall be measured at the connector of the sender or recipient that is driving the bus but must release the bus to allow for a bus turnaround 6 See Page 14 the AC Timing requirements in Ultra DMA AC Signal Requirements Transcend Information Inc 12 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Ultra DMA Data Burst Timing Descriptions Name Comment Notes tocyctyp Typical sustained average two cycle time tcye Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE edge tecyc Two cycle time allowing for clock variations from rising edge to next rising edge or from falling edge to next falling edge of STROBE tos Data setup t
34. ion Inc 13 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend giving it a known state when released Ultra DMA Sender and Recipient IC Timing Requirements Nanie UDMA Mode 0 ns UDMA Mode 1 ns UDMA Mode 2 ns UDMA Mode 3 ns UDMA Mode 4 ns Min Max Min Max Min Max Min Max Min Max tosic 14 7 9 7 6 8 6 8 4 8 toHic 4 8 4 8 4 8 4 8 4 8 tovsic 72 9 50 9 33 9 22 6 9 5 tovHic 9 0 9 0 9 0 9 0 9 0 tosic Recipient IC data setup time from data valid until STROBE edge see note 2 toHic Recipient IC data hold time from STROBE edge until data may become invalid see note 2 tpvsic Sender IC data valid setup time from data valid until STROBE edge see note 3 tpvHic Sender IC data valid hold time from STROBE edge until data may become invalid see note 3 Notes 1 All timing measurement switching points low to high and high to low shall be taken at 1 5 V 2 The correct data value shall be captured by the recipient given input data with a slew rate of 0 4 V ns rising and falling and the input STROBE with a slew rate of 0 4 V ns rising and falling at tosic and tpnic timing as measured through 1 5 V 3 The parameters tpvsic and tpvuic shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all signals have the same capacitive load value Noise that may couple onto the output signals from external sources ha
35. nd the device has negated DMARQ and DDMARDY and no sooner than tpvs after placing the result of its CRC calculation on D 15 00 h The device shall latch the host s CRC data from D 15 00 on the negating edge of DMACK i The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA data bursts for any one command at the end of the command the device shall report the first error that occurred see ATA specification Ultra DMA CRC Calculation j While operating in True IDE mode the device shall release DDMARDY within tiorpyz after the host has negated DMACK k The host shall neither negate STOP nor negate HSTROBE until at least tack after negating DMACK I In True IDE mode the host shall not assert IOWR CSO CS1 nor A 02 00 until at least tack after negating DMACK Transcend Information Inc 29 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 146GDOM40V S Transcend t DMARQ device tu DMACK host tu tack STOP toroyz DDMARDY device UUO lice HSTROB host lt r Y NXXX X tevs tevu Data D15 D00 a TAVAN ANAVATAN A KXXX XXXIX KKK KKK KX AOA TATATATA TAN host A 02 00 tack CS0 CS1 IDE CE1 CE2 ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM Notes The de
36. ompletion the assertion of INTRQ should be passed through to the host software driver regardless of whether all data requested by the command has been transferred Transcend Information Inc 11 Ver 1 3 Transcend 40 Pin IDE Flash Module Transcend TS1 28M rs 1 6G DOM40V S Exceeding Your Expectations Ultra DMA Data Burst Timing Requirements Name UDMA Mode 0 UDMA Mode 1 UDMA Mode 2 UDMA Mode 3 UDMA Mode 4 Wieasureilocation Min Max Min Max Min Max Min Max Min Max See Note 2 tocyctyp 240 160 120 90 60 Sender teyc 112 73 54 39 25 Note 3 tecyc 230 153 115 86 57 Sender tos 15 0 10 0 7 0 7 0 5 0 Recipient toy 5 0 5 0 5 0 5 0 5 0 Recipient tovs 70 0 48 0 31 0 20 0 6 7 Sender tovh 6 2 6 2 6 2 6 2 6 2 Sender tcs 15 0 10 0 7 0 7 0 5 0 Device tcH 5 0 5 0 5 0 5 0 5 0 Device tevs 70 0 48 0 31 0 20 0 6 7 Host tcvH 6 2 6 2 6 2 6 2 6 2 Host tzFs 0 0 0 0 0 Device tozrs 70 0 48 0 31 0 20 0 6 7 Sender tes 230 200 170 130 120 Device tu 0 150 0 150 0 150 0 100 0 100 Note 4 tu 20 20 20 20 20 Host tui 0 0 0 0 0 Host taz 10 10 10 10 10 Note 5 tzaH 20 20 20 20 20 Host tzan 0 0 0 0 0 Device tenv 20 70 20 70 20 70 20 55 20 55 Host tars 75 70 60 60 60 Sender tre 160 125 100 100 100 Recipient tiorDYz 20 20 20 20 20 Device tzioRDY 0 0 0 0 0 Device tack 20 20 20 20 20 Host tss 50 50 50 50 50 Sender Notes All T
37. rmation Inc 25 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Device Pausing an Ultra DMA Data Out Burst The device pauses an Ultra DMA Data Out burst by following the steps lettered below The timing diagram is shown in below Ultra DMA Data Out Burst Device Pause Timing The timing parameters are specified in Page 12 Ultra DMA Data Burst Timing Requirements and are described in Page 13 Ultra DMA Data Burst Timing Descriptions The following steps shall occur in the order they are listed unless otherwise specifically allowed a The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data burst has been transferred b The device shall pause an Ultra DMA data burst by negating DDMARDY c The host shall stop generating HSTROBE edges within trrs of the device negating DDMARDY d While operating in Ultra DMA modes 2 1 or 0 the device shall be prepared to receive zero one or two additional data words after negating HDMARDY While operating in Ultra DMA modes 4 or 3 the device shall be prepared to receive zero one two or three additional data words The additional data words are a result of cable round trip delay and trrs timing for the device e The device shall resume an Ultra DMA data burst by asserting DDMARDY DMARQ device DMACK host STOP host DDMARDY device HSTROBE host Data D 15 00 host ALL WAVEFORMS
38. s not been included in these values Ultra DMA AC Signal Requirements Name Comment Min V ns Max V ns Note SRISE Rising Edge Slew Rate for any signal 1 25 1 SFALL Falling Edge Slew Rate for any signal 1 25 1 Note 1 The sender shall be tested while driving an 18 inch long 80 conductor cable with PVC insulation material The signal under test shall be cut at a test point so that it has not trace cable or recipient loading after the test point All other signals should remain connected through to the recipient The test point may be located at any point between the sender s series termination resistor and one half inch or less of conductor exiting the connector If the test point is on a cable conductor rather than the PCB an adjacent ground conductor shall also be cut within one half inch of the connector The test load and test points should then be soldered directly to the exposed source side connectors The test loads consist of a 15 pF or a 40 pF 5 0 08 inch by 0 05 inch surface mount or smaller size capacitor from the test point to ground Slew rates shall be met for both capacitor values Measurements shall be taken at the test point using a lt 1 pF gt 100 Kohm 1 Ghz or faster probe and a 500 MHz or faster oscilloscope The average rate shall be measured from 20 to 80 of the settled VOH level with data transitions at least 120 nsec apart The settled VOH level shall be measured as the average ou
39. t supported in this mode Transcend Information Inc 6 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S True IDE PIO Mode Timing Diagram Transcend Exceeding Your Expectations ao Notes See note 4 4 3 i i ADDR valid A02 A01 A00 CS0 CS1 See note 1 t 1 IORD IOWR N_ Write Data DIS DOO Ansni R RR aE See note 2 Read Data D15 D00 Aqasn tien aa sees See note 2 DE IOCS16 See note 3 4 TORDY _ FP SSS SS SSS SS SS SSS SSS SS SS SSS SS SS SSS SSS SSS SSS eS SSS SSS SSS See note 4 4 1 j a IORDY 77777 T e aaa creas See note 4 4 2 e ae NXXXXXXXXXXXXXXN Figure 1 True IDE PIO Mode Timing Diagram 1 Device address consists of CSO CS1 and A 02 00 Data consists of D 15 00 16 bit or D O7 00 8 bit IOCS16 is shown for PIO modes 0 1 and 2 For other modes this signal is ignored The negation of IORDY by the device is used to extend the PIO cycle The determination of whether the cycle is to be extended is made by the host after ta from the assertion of IORD or IOWR The assertion and negation of IORDY is described in the following three cases 4 1 Device never negates IORDY No wait is generated 4 2 Device starts to drive IORDY low before ta but causes IORDY to be asserted before ta No wait generated 4 3 Device drives IORD
40. tput Transcend Information Inc 14 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend high level under the defined testing conditions from 100 nsec after 80 of a rising edge until 20 of the subsequent falling edge Transcend Information Inc 15 Ver 1 3 Transcend 40 Pin IDE Flash Module TS128M 16GDOM40V S Transcend Initiating an Ultra DMA Data In Burst a An Ultra DMA Data In burst is initiated by following the steps lettered below The timing diagram is shown in below Ultra DMA Data In Burst Initiation Timing The associated timing parameters are specified in Page 12 Ultra DMA Data Burst Timing Requirements and are described in Page 13 Ultra DMA Data Burst Timing Descriptions b The following steps shall occur in the order they are listed unless otherwise specifically allowed c The host shall keep DMACK in the negated state before an Ultra DMA data burst is initiated d The device shall assert DMARQ to initiate an Ultra DMA data burst After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE e Steps c d and e may occur in any order or at the same time The host shall assert STOP f The host shall negate HDMARDY g In True IDE mode the host shall not assert CSO CS1 and A 02 00 h Steps c d and e shall have occurred at least tack before the host asserts DMACK The host shall keep DMACK asserted until the end of
41. with a 50 pF 40pF below 120nsec Cycle Time total load All times are in nanoseconds Minimum time from IORDY high to IORD high is 0 nsec but minimum IORD width shall still be met 1 to is the minimum total cycle time t is the minimum command active time and tz is the minimum command recovery time or command inactive time The actual cycle time equals the sum of the actual command active time and the actual command inactive time The three timing requirements of tO t2 and ti shall be met The minimum total cycle time requirement is greater than the sum of tz and ta This means a host implementation can lengthen either or both tz or tz to ensure that to is equal to or greater than the value reported in the device s identify device data 2 This parameter specifies the time from the negation edge of IORD to the time that the data bus is released by the device 3 The delay from the activation of IORD or IOWR until the state of IORDY is first sampled If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle can be completed If the device is not driving IORDY negated at ta after the activation of IORD or IOWR then ts shall be met and trp is not applicable If the device is driving IORDY negated at the time ta after the activation of IORD or IOWR then trp shall be met and t5 is not applicable 4 tz and ts apply only to modes 0 1 and 2 For other modes this signal is not valid 5 IORDY is no

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