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Intel Celeron Mobile 1.50 GHz

1. 298517 006 Socketable Micro FCPGA Package Specification Symbol Parameter Min Max Unit A Overall height top of die to package seating plane 1 81 2 03 mm Overall height top of die to PCB surface including socket 1 4 69 5 15 mm A1 Pin length 1 95 2 11 mm A2 Die height 0 854 mm B Pin diameter 0 28 0 36 mm D Package substrate length 34 9 35 1 mm E Package substrate width 34 9 35 1 mm D1 Die length 11 18 mm 10 82 E1 Die width 7 20 mm 6 85 e Pin pitch 1 27 mm Package edge keep out 5 mm K1 Package corner keep out 7 mm K3 Pin side capacitor boundary 14 mm Pin tip radial true position lt 0 254 mm N Pin count 478 each Pdie Allowable pressure on the die for thermal solution 689 kPa W Package weight 4 5 g O Package surface Flatness 0 286 mm NOTES 1 All dimensions are subject to change 2 Overall height with socket is based on design dimensions of the Micro FCPGA package and socket with no thermal solution attached Values were based on design specifications and tolerances This dimension is subject to change based on socket design OEM motherboard design or OEM SMT process 3 Dimension for CPUID 0x06B1 4 Dimension for CPUID 0x06B4 Datasheet 65 Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages Datasheet intal Figure 25 Socketable Micro FCPGA Package Top and Bottom Isometric Views DIE LABEL TOP VIEW PACKAGE
2. O Al4 VSS VSS VCC VSS vec vss vcc vss o e A15 VCCT VCC VSS vcc O A8 VSS VSS VCC vss 6 e A11 VCCT VCC vss vec O A6 VSS VSS VCC vss vss O e REGI VCCT NC VSS vec vecT O e O vec vss vss o e vss vec vecT O e O O nc VCC vss vss o e vss vec vecT vec vss vss o e vss vec vecT O O vec vss vss o O vss vec vecT vec vss vss 6060606060606060 vss Sit VCCT vss vec vss VCC vss VCC VSS VCC VSS VCC VSS VCC vec VSS VCCT O O Apoy PUR vec vss VCC vss VCC vss vss vcc VSS GOOD o o BCLK VIDI A20M VCCT vss vcc vss vcc vss vec vec VSS VCCT O O O O O O O SMI NC cmos vect TDO vccT NC VCCT PICDO BPM1 BPMO NC lt gO 05050505050 0 0 O 620 lt A a O 0O O O gt E lt PA a g 8 g S O O lt A a ojo 0 m o 3 E o lt a a g R Z O O O O 00 lt E m 5 2 E R lt A a z 6 lt PA a g z 6 vss O NC O O NC O O O O E m 2 S w K 2 E lt A a OS 00 O O O a g lt 2 a f M 5 m 2 Z a Z g amp L g O O O O E m 2 E FA 3 a a 2 lt A a lt G a O O O E 2 lt PA a E o lo a S lt 6 a 2 O O O 00 03030 s 3 g gt 2 o R Z 2 lt 2 am
3. 1001 1301 1 42 a w X ala w oj 3 1 1 wo Oo al 295 5 7 EF ala w w NS MEN 298517 006 Datasheet 31 Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages Datasheet intal Table 17 Vcc Tolerances for the Mobile Intel Celeron Processor in the Deep Sleep State VID 1 40 V Icc A EIA 32 LC eT Vee V CI EN EJE Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 18 Vcc Tolerances for the Mobile Intel Celeron Processor VID 1 45 V Icc W sae Transient are ete Pos 100 pars 10 108 Tas Pes pam 1401 vast Ts Tan Pos are re 16 D Tas Pos rare rae 169 199 Tas 298517 006 Datasheet 33 Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages Datasheet intal Table 19 Vcc Tolerances for the Mobile Intel Celeron Processor in the Deep Sleep State VID 1 45 V Icc A KAKI 34 Ea aT Vcc V e EN EIC 14 14 109 1 401 D Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 20 Vcc Tolerances for the Mobile Intel Celeron Processor VID 1 50 V lec W sate Transient S s pars les s Tas Pes are La 190 Ta T os ass ras 1405 De 150 Poo rs 1400 1400 1
4. 5 000000 000000 000000 000000 000000 000000 000000 00000000000000000000000000 000000 000000 000000 000000 000000 000000 000000 To 9 N 6 8 10 e gt 25X 1 27 e 1 625 S 4 places 4 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 1 625 S 0000000000000 4 places 000000 000000 2000000 000000 000000 000000 000000 000000 000000 000000 2000000 oo00000 000000 2000000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 15 17 19 21 23 25 14 16 18 20 22 24 26 NOTE All dimensions in millimeters Values shown are for reference only See Table 37 for specific details Datasheet 298517 006 intel E Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet 5 3 Signal Listings Figure 31 is a top side view of the ball or pin map of the Mobile Intel Celeron Processor with the voltage balls pins called out Table 45 lists the signals in ball pin number order Table 46 lists the signals in signal name order Figure 31 Pin Ball Map Top View G 0 0 0 0 0 O NC A10 VREF NC A3t BREQO A33 A32H DOR VREF O O 0 000 O VSS A25 VSS AI7T VSS Ap VSS RESET VSS D17 O O O O A16 A28 NC VCCT A19 VCCT BERR VCCT D6 vecT O o VSS A13 VSS VCCT VCC VSS vcc vss vcc vss e o O e TestH VTT vcct vcc vcecT vcc vss vcc VSS vec PWRGD O
5. Bus Error signal is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by either system bus agent and must be connected to the appropriate pins balls of both agents if used However the Mobile Intel Celeron Processors do not observe assertions of the BERR signal BERR assertion conditions are defined by the system configuration Configuration options enable the BERR driver as follows e Enabled or disabled e Asserted optionally for internal errors along with IERR e Asserted optionally by the request initiator of a bus transaction after it observes an error e Asserted by any bus agent when it observes an error in a bus transaction BINIT I O AGTL The BINIT Bus Initialization signal may be observed and driven by both system bus agents and must be connected to the appropriate pins balls of both agents if used If the BINIT driver is enabled during the power on configuration BINIT is asserted to signal any bus condition that prevents reliable future information If BINIT is enabled during power on configuration and BINIT is sampled asserted all bus state machines are reset and any data which was in transit is lost All agents reset their rotating ID for bus arbitration to the state after reset and internal count information is lost The L1 and L2 caches are not affected If BINIT is disabled during power on configuration a central agent may handle an assertion of BINIT as ap
6. Recommended 1 2 Resistor Value Q Mobile Intel Celeron Processor Signal Additional Pullup Pulldown Resistor Recommendations 270 pull up SMI 680 pull up STPCLK 1 5k pull up A20M DPSLP INIT IGNNE LINTO INTR LINT1 NMI NOTES 1 The recommendations above are only for signals that are being used These recommendations are maximum values only stronger pull ups may be used Pull ups for the signals driven by the chipset should not violate the chipset specification Refer to Section 3 1 4 for the required pull up or pull down resistors for signals that are not being used 2 Open drain signals must never violate the undershoot specification in Section 4 3 Use stronger pull ups if there is too much undershoot A pull down on BREQO is an alternative to having the central agent to drive BREQO low at reset A 56 2 Q 1 terminating resistor connected to Vecr is required The following signals are actively driven high by the ICH3 M component and do not need external pull up resistors on ICH3 M based platforms A2ZOM DPSLP INIT IGNNE LINTO INTR LINT1 NMI SMI STPCLK 6 These pull up recommendations apply to systems on which these signals are not actively pulled high such as those utilizing the 82443MX chipset a Power Sequencing Requirements Unlike the Mobile Intel Celeron Processor 0 18 u the Mobile Intel Celeron Processor 0 13 u does have specific power sequencing requirements The power on sequenc
7. 60 Datasheet 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 38 133 MHz AGTL Signal Group Overshoot Undershoot Tolerance at the Processor Core Max Vccrt Overshoot Undershoot Allowed Pulse Duration ns Tj 100C see Note 7 Magnitude volts S Activity Factor 0 01 Activity Factor Activity Factor 1 0 1 4 NOTES 1 2 3 Under no circumstances should the sum of the Max Vccr and absolute value of the Overshoot Undershoot voltage exceed 1 78 V Activity factor of 1 represents the same toggle rate as the 133 MHz clock Ringbacks below Vccr cannot be subtracted from overshoots Lesser undershoot does not allocate longer or larger overshoot Ringbacks above ground cannot be subtracted from undershoots Lesser overshoot does not allocate longer or larger undershoot System designers are encouraged to follow Intel provided AGTL layout guidelines All values are specified by design characterization and are not tested Tj 85 C for 1 33 GHz Table 39 100 MHz AGTL Signal Group Overshoot Undershoot Tolerance at the Processor Core Allowed Pulse Duration ns Tj 100C see Note 7 Max Vccr Overshoot Undershoot Magnitude volts S Activity Factor 0 01 Activity Factor 0 1 Activity Factor 1 On Under no circumstances should the sum of the Max Vccr and absolute value of the Overshoot Undershoot voltage exceed 1 78 V Activity fa
8. 7 Note7 Note7 7 Pa mama ee L 11H e ne NOTES 1 2 3 4 00 30 All AC timings for AGTL and CMOS signals are referenced to the BCLK and BCLK crossing point Measured on differential waveform defined as BCLK BCLK Not 100 tested Specified by design characterization Due to the difficulty of accurately measuring clock jitter in a system it is recommended that the clock driver be designed to meet a period stability specification into a test load of 10 pF to 20 pF This should be measured on the rising edge of adjacent BCLKs at the BCLK BCLK crossing point The jitter present must be accounted for as a component of BCLK skew between devices Period difference is measured around 0 V crossing points Measurement taken from common mode waveform measure rise fall time from 0 41 to 0 86 V Rise fall time matching is defined as the instantaneous difference between maximum BCLK rise fall and minimum BCLK fall rise time or minimum BCLK rise fall and maximum BCLK fall rise time This parameter is designed to guard waveform symmetry Rise time is measured from 0 35 V to 0 35 V and fall time is measured from 0 35 V to 0 35 V Measured on common mode waveform includes every rise fall crossing Measured at the package ball for the Micro FCBGA package Measured at the socket pin for the Micro FCPGA package Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA
9. All inputs required valid after PWRGOOD low 298517 006 Datasheet 53 Mobile Intel Celeron Processor 0 13 u in l ntel o Micro FCBGA and Micro FCPGA Packages Datasheet Figure 17 Power Down Sequencing and Timings Vcc Leading 0045 00 T T20A Time from VCCT 12 to VTTPWRGD low T T20B All outputs valid after VTTPWRGD low T T20C All inputs required valid after VTTPWRGD low Ta T20D VID BSEL signals valid after VTTPWRGD low 54 Datasheet 29851 7 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Figure 18 Test Timings Boundary Scan TDI TMS Input Signals Output Signals D0008 01 NOTES Tr T43 All Non Test Inputs Setup Time Ts T44 All Non Test Inputs Hold Time Tu T40 TDO Float Delay Ty T37 TDI TMS Setup Time Tw T38 TDI TMS Hold Time Tx T39 TDO Valid Delay Ty T41 All Non Test Outputs Valid Delay Tz T42 All Non Test Outputs Float Delay Figure 19 Test Reset Timings D0009 01 Tg T36 TRST Pulse Width 298517 006 Datasheet 55 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Figure 20 Quick Start Deep Sleep Timing BCLK Stopping Method Normal Quick Start Deep Sleep Quick Start Normal ANN Ty STPCLK CPU bus DPSLP Compatibility Frozen Signals V00102 00 Ty T45 Stop Grant Acknowledge Bu
10. e Added note 5 CMOSREF resistor divider recommendations to Table 24 e Updated references June 2002 298517 003 Updates include e Targeted processor frequencies updated e Updated Tables 3 9 12 19 29 and 44 e Updated corrected Tables 39 and 40 e Updated Figure 5 Figure 7 e Updated Section 5 e Updated CMOSREF description in Section 8 1 e Added Section 3 2 4 August 2002 29851 7 004 Updates include e Added new processor frequencies e Updated Table 11 and Table 48 December 2002 298517 005 Updates include e Added new processor frequencies e Updated Table 11 and Table 48 April 2003 298517 006 Updates include e Added new processor frequencies 1 26 GHz e Updated Table 11 and Table 48 Datasheet 29851 7 006 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages Product Features Mobile Intel Celeron Processor with the following Processor core bus speeds 1 333 GHz 133 MHz at 1 50 V 1 200 GHz 133 MHz at 1 45 V 1 133 GHz 133 MHz at 1 45 V 1 066 GHz 133 MHz at 1 45 V 1 266 GHz 133 MHz at 1 40 V 1 000 GHz 133 MHz at 1 40 V Low Voltage Mobile Intel Celeron Processor 0 13 u with the following Processor core bus speeds 866 133 MHz at 1 15 V 733 133 MHz at 1 15 V 650 100 MHz at
11. scan operation REQ 4 0 I O AGTL The REQ 4 0 Request Command signals must be connected to the appropriate pins balls on both agents on the system bus They are asserted by the current bus owner when it drives A 35 3 to define the currently active transaction type RESET I AGTL Asserting the RESET signal resets the processor to a known state and invalidates the L1 and L2 caches without writing back Modified M state lines For a power on type reset RESET must stay active for at least 1 ms after Vcc and BCLK BCLK have reached their proper DC and AC specifications and after PWRGOOD has been asserted When observing active RESET all bus agents will deassert their outputs within two clocks RESET is the only AGTL signal that does not have on die AGTL termination A 56 2 Q 1 terminating resistor connected to Vccr is required Datasheet 298517 006 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet A number of bus signals are sampled at the active to inactive transition of RESET for the power on configuration The configuration options are described in Section 4 and in the P6 Family of Processors Developer s Manual Unless its outputs are tri stated during power on configuration after an active to inactive transition of RESET the processor optionally executes its built in self test BIST and begins program execution at reset vector OOOFFFFOH or FFFFFFFOH RES
12. the VTTPWRGD signal should have reasonable transition time through the transition region A sharp edge on the signal transition will minimize the chance of noise causing a glitch on this signal Intel recommends the following transition time for the VTTPWRGD signal Datasheet 29851 7 006 intel 4 3 1 2 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet VTTPWRGD Transition Parameter Recommendation Table 42 VTTPWRGD Transition Parameter Recommendation 4 3 1 2 1 4 3 1 2 2 4 3 1 2 3 298517 006 Parameter Recommendation Transition time 300 mV to 900 mV Less than or equal to 100 us In addition the VTT_PWRGD signal should have reasonable transition time through the transition region A sharp edge on the signal transition will minimize the chance of noise causing a glitch on this signal Intel recommends the following transition time for the VTT_PWRGD signal Transition Region The transition region covered by this requirement is 300 mV to 900 mV Once the VITTPWRGD signal is in that voltage range the processor is more sensitive to noise which may be present on the signal The transition region when the signal first crosses the 300 mV voltage level and continues until the last time it is below 900 mV Transition Time The transition time is defined as the time the signal takes to move through the transition region A 100 us transition time will ensure that the p
13. 1 15 V Ultra Low Voltage Mobile Intel Celeron processor 0 13 u with the following Processor core bus speeds 800 133 MHz at 1 10V 733 133 MHz at 1 10V 700 100 MHz at 1 10V 650 100 MHz at 1 10 V Supports the Intel Architecture with Dynamic Execution m On die primary 16 Kbyte instruction cache and 16 Kbyte write back data cache m On die second level cache 256 Kbyte with Advanced Transfer Cache Architecture Datasheet Data Prefetch Logic Integrated AGTL termination Integrated math co processor Micro FCPGA and Micro FCBGA packaging technologies Supports thin form factor notebook designs Exposed die enables more efficient heat dissipation Mobile ULV and LV Celeron processor 0 13 u are available only in Micro FCBGA package Mobile Intel Celeron processors at 1 45 V and 1 50 V are available only in Micro FCPGA package Fully compatible with previous Intel microprocessors Binary compatible with all applications Support for MMX technology Support for Streaming SIMD Extensions Power Management Features Quick Start and Deep Sleep modes provide low power dissipation On die thermal diode Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet k Introduction 1 1 10 Using Intel s advanced 0 13 micron process technology with copper interconnect the Mobile Intel Celeron Processor offers high pe
14. BCLK Single Ended 1 0V for PICCLK 1 0V for TCK V 0 5V for BCLK Single Ended 0 4V for PICCLK Vemosres 0 2V for TCK Vy 2 0V for BCLK Single Ended 1 6V for PICCLK Vemosrer 0 2V for TCK Figure 10 Differential BCLK BCLK Waveform Common Mode 298517 006 V2 V3 max Veross BCLK V1 V3 min Datasheet 49 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Figure 11 BCLK BCLK Waveform Differential Mode Tl lt gt Vin pir V4 OV V5 Vi pier gt T6 T5 Figure 12 Valid Delay Timings Tx T7 T11 T29 Valid Delay Tpw T14 T14B Pulse Width N VREF for AGTL signal group 1 0V Tor CMOS Open drain APIC and TAP signal groups Ve Crossing point of BCLK rising edge and BCLK falling edge for BCLK references Differential Clock 1 25V Single Ended Clock 50 Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Ts T8 T27 Setup Time Th T9 T28 Hold Time V VREF for AGTL signals 1 0V for CMOS APIC and TAP signals Vc Crossing point of BCLK rising edge and BCLK falling edge for BCLK references Differential Clock 1 25V Single Ended Clock Figure 14 Cold Warm Reset and Configuration Timings BCLK RESET Configuration HRA III va NN vere aer Ah E a us III III
15. L2 cache runs at the processor core speed and the increased cache size provides superior processing power Data Prefetch Logic The Mobile Intel Celeron Processor features Data Prefetch Logic that speculatively fetches data to the L2 cache before an L1 cache request occurs This reduces transactions between the cache and system memory reducing or eliminating bus cycle penalties resulting in improved performance The processor also includes extensions to memory order and reorder buffers that boost performance Differential Clocking Differential clocking requires the use of two complementary clocks BCLK and BCLK Benefits of differential clocking include easier scaling to lower voltages reduced EMI and less jitter All references to BCLK in this document apply to BCLK also even if not explicitly stated The Mobile Intel Celeron Processor will also support Single Ended Clocking The processor will configure itself for Differential or Single Ended Clocking based on the waveforms detected on the BCLK and BCLK CLKREF signal lines Datasheet 13 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 2 1 5 Signal Differences Between the Mobile Intel Celeron Processor 0 18 u in BGA2 and Micro PGA2 Packages and the Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages A list of new and changed signals is shown in Table 1 Table 1 New and Revised Mobile Intel
16. N6 N22 N25 P2 P21 P23 R4 R6 R22 R25 T2 T5 T21 T23 U4 U6 U22 U25 V2 V5 V21 V23 W4 W6 W22 W25 Y2 Y5 Y21 Y23 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25 AB2 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AC25 AD2 AE1 AE5 AE7 AE9 AE11 AE13 AE15 AE17 AE19 AE21 AE23 AE26 AF25 AF26 NOTE A2 pin is de populated on the Micro FCPGA package Datasheet 79 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 6 Vcc Thermal Specifications 80 In order to achieve proper cooling of the processor a thermal solution e g heat spreader heat pipe or other heat transfer system must make firm contact to the exposed processor die The processor die must be clean before the thermal solution is attached or the processor may be damaged Table 48 provides the Thermal Design Power TDP dissipation and the minimum and maximum T temperatures for the Mobile Intel Celeron Processor The thermal solution should be designed to ensure the junction temperature never exceeds the specified value while operating at the Thermal Design Power Additionally a secondary failsafe mechanism in hardware should be provided to shutdown the processor at 101 C to prevent permanent damage as described in Section 3 1 3 TDP is a thermal design power specification based on the worst case power dissipation of t
17. Out signal transfers serial test data from the processor TDO provides the serial output needed for JTAG support TESTHI 2 1 I 1 25 V Tolerant The TESTHI 2 1 Test input High signals are used during processor test and need to be pulled high during normal operation TESTLO 2 1 I 1 5 V Tolerant The TESTLO 2 1 Test input Low signals are used during processor test and needs to be pulled to ground during normal operation THERMDA THERMDC Analog The THERMDA Thermal Diode Anode and THERMDC Thermal Diode Cathode signals connect to the anode and cathode of the on die thermal diode TMS I 1 5 V Tolerant The TMS Test Mode Select signal is a JTAG support signal used by debug tools TRDY I O AGTL The TRDY Target Ready signal is asserted by the target to indicate that the target is ready to receive write or implicit write back data transfer TRD Y must be connected to the appropriate pins balls on both agents on the system bus TRST I 1 5 V Tolerant The TRST Test Reset signal resets the Test Access Port TAP logic The Mobile Intel Celeron Processors do not self reset during power on therefore it is necessary to drive this signal low during power on reset Datasheet 298517 006 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet VID 4 0 O Open drain The VID 4 0 Voltage ID pins balls can be used to support automatic selection
18. PLL2 Analog The PLL1 and PLL2 signals provide isolated analog decoupling is required for the internal PLL See Section 3 2 2 for a description of the analog decoupling circuit PRDY O AGTL The PRDY Probe Ready signal is a processor output used by debug tools to determine processor debug readiness PREQ I 1 5 V Tolerant The PREQ Probe Request signal is used by debug tools to request debug operation of the processor PWRGOOD I 1 8 V Tolerant PWRGOOD Power Good is a 1 8 V tolerant input The processor requires this signal to be a clean indication that clocks and the power supplies Vcc Vecr etc are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current and without glitches from the time that the power supplies are turned on until they come within specification The signal will then transition monotonically to a high 1 8 V state Figure 15 through Figure 17 illustrate the relationship of PWRGOOD to other system signals PWRGOOD can be driven inactive at any time but clocks and power must again be stable before the rising edge of PWRGOOD It must also meet the minimum pulse width specified in Table 30 Section 3 6 and be followed by a 1 ms RESET pulse The PWRGOOD signal which must be supplied to the processor is used to protect internal circuits against voltage sequencing issues The PWRGOOD signal should be driven high throughout boundary
19. Processor CPUID sees 17 Electrical Specifications raaa naen aaa aana naa aaa NENEK NANA E Na Kana a nn nn EEEE EEEE aana eaaa nee 19 3 1 Processor System Signals saa eee 19 3 1 1 Power Sequencing Reguirements aaa eee ee eee 20 3 1 2 Test Access Port TAP Connection saa eee 20 3 1 3 Catastrophic Thermal Protection a eee 21 3 1 4 Unused Signals sss 21 3 1 5 Signal State in Low power States see 21 3 1 5 1 System BUS Signals sese eee eee 21 3 1 5 2 CMOS and Open drain Signals sese 21 3 1 5 3 Other SIQMALS viii 22 3 2 Power Supply Redguirements eee eee ee eee 22 3 2 1 Decoupling Guidelines sana eee 22 3 2 2 Voltage Planes sse esse sese a essere anaa nen nenen nnn nnn nene nnn 22 32 9 Voltage Identification ios ti n 23 3 2 4 VTTPWRGD Signal Quality Specification eee eee ee 24 3 2 4 1 Transition REGION cocinera 24 3 2 4 2 Transition TT 24 3 2 4 3 N eT 25 3 3 System Bus Clock and Processor Clocking sese eee eee 25 3 4 Maximum RAUMOS lt a it ita 26 3 5 DG Specifications aaa aga aaa Aan BENE aan Aa nai a KA Ta a BAG Na Na KI a aj Ka Ba E al a aa naa ae gaene 26 Datasheet 3 Mobile Intel Celeron Processor 0 13 u in intel a Micro FCBGA and Micro FCPGA Packages Datasheet 3 6 LAST eiee el ata at TA Ad 41 3 6 1 System Bus Clock APIC TAP CMOS and Open drain AC Specifications 41 4
20. Timings sese eee eee 51 Figure 14 Cold Warm Reset and Configuration Timings sss sees eee eee eee eee 51 Figure 15 Power on Sequence and Reset Timings eee eee ee eee eee 52 Figure 16 Power Down Sequencing and Timings VCC Leading sese sese eee eee 53 Figure 17 Power Down Sequencing and Timings Vect Leading sese ee eee eaaa eee 54 Figure 18 Test Timings Boundary Scan eessesssssrsseernesssnnantennannannnntennaaanannantennaanannaneenndanan 55 Figure 19 Test Reset TIMINGS T 55 Figure 20 Quick Start Deep Sleep Timing BCLK Stopping Method sese sese 56 Figure 21 Quick Start Deep Sleep Timing DPSLP Assertion Method sss esse eee 57 Figure 22 BCLK Single Ended PICCLK Generic Clock Waveform eee eee eee 59 Figure 23 Maximum Acceptable Overshoot Undershoot Waveform sss eee ee eee ee e an 60 Figure 24 VTTPWRGD Noise Specification ooononnincnnnnnicinnnnncoccnnnncannnnnnnannnnrnna nn rrnnnr nn 64 Figure 25 Socketable Micro FCPGA Package Top and Bottom Isometric Views 66 Figure 26 Socketable Micro FCPGA Package Top and Side View sese eee eee ee 67 Figure 27 Socketable Micro FCPGA Package Bottom View eee eee eee ee 68 Figure 28 Micro FCBGA Package Top and Bottom Isometric Views eee 70 Figure 29 Micro FCBGA Package Top and Side Views eee eee eee 71 Figure 30 Micro FCBGA Package Bottom View sese eee eee eee 72 Figu
21. and Micro FCPGA Packages Datasheet Table 26 System Bus Clock AC Specifications 133 MHz Single Ended oo System Bus Frequency 133 T1Sabs BCLK Period Instantaneous Minimum aa ee H HE pa Notes 2 3 4 s ectkwiontine E fe e arzov SN ESTO H fe E HS Pres BOUKRisoTine oa ne re 6 noes Cros scikrartme oa ns os 6 Noes NOTES 1 All AC timings for AGTL and CMOS signals are referenced to the BCLK rising edge at 1 25 V 2 Period jitter skew and offset measured at 1 25 V 3 Not 100 tested Specified by design characterization 4 Measured on the rising edge of adjacent BCLKs at 1 25 V The jitter present must be accounted for as a component of BCLK skew between devices 5 Measured between 0 5 V and 2 0 V Table 27 System Bus Clock AC Specifications 100 MHz Single Ended MI jeh System Bus Frequency System Bus Frequency Frequency A T msi BCLK Period Period Je Notez 2 KEH E Period Instantaneous 75 CIN TEC 2 Minimum eja LC VES ERG jer C C japana KRE G e e aos Fresr_ ecikRsetime foa re ns 6 nes Presr_ ecikrartime Jos De ns 6 nes NOTES 1 All AC timings for AGTL and CMOS signals are referenced to the BCLK rising edge at 1 25 V 2 Period jitter skew and offset measured at 1 25 V 3 Not 100 tested Specified by design characterization 4 Measured on the rising edge of adjacent BCLKs at 1 25 V The jitter present must be a
22. gain in pass band e lt 0 5 dB attenuation in pass band lt 1 Hz see DC drop in next set of requirements e 34 dB attenuation from 1 MHz to 66 MHz e 28 dB attenuation from 66 MHZ to core frequency e The filter specification AC is graphically shown in Figure 32 Other requirements e Usea shielded type inductor to minimize magnetic pickup e The filter should support a DC current of at least 30 mA e The DC voltage drop from Vccr to PLL1 should be less than 60 mV which in practice implies series resistance of less than 2 Q This also means that the pass band from DC to 1 Hz attenuation below 0 43 dB for Vcct 1 25 V Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Figure 32 PLL Filter Specifications Forbidden zone Forbidden DC 1 Hz fpeak 1MHz 66 MHz fcore N gt 1 Passband High Frequency Band x 20 log Vcct 60 mV Vcct NOTES Diagram is not to scale No specification for frequencies beyond fcore Fpeak if existent should be less than 0 05 MHz A3 Recommendation for Mobile Systems The following LC components are recommended The tables will be updated as other suitable components and specifications are identified Table 56 PLL Filter Inductor Recommendations inductor Part Number Rated Min Damping R Needed max Murata LQG21N4R7K10 10 47 MHz 0 7 Q 50 Murata LQG21C4R7N00 30 35 MHz 0 2 Q assumed NOTE Minim
23. of power supply voltages Please refer to Section 3 2 3 for details VREF Analog The VREF AGTL Reference Voltage signal provides a DC level reference voltage for the AGTL input buffers A voltage divider should be used to divide Vccr by 2 Resistor values of 1 00 kQ and 2 00 kQ are recommended Decouple the VREF signal with three 0 1 uF high frequency capacitors close to the processor VTTPWRGD I 1 25 V The VITPWRGBD signal informs the processor to output the VID signals During power up the VID signals will be in an indeterminate state for a small period of time The voltage regulator should not sample and or latch the VID signals until the VTTPWRGD signal is asserted The assertion of the VTTPWRGBD signal indicates that the VID signals are stable and are driven to the final state by the processor Please refer to Figure 15 for the power up sequence Also see Section 4 3 1 Datasheet 93 Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages Datasheet 8 2 Signal Summaries Table 52 Input Signals Name Active Level Signal Group Qualified BCLK BCLK Low BPRI Low DEFER Low FLUSH IGNNE Low INIT Low INTR LINT 1 0 NMI NCTRL PICCLK PREQ PWRGOOD RESET Low RSP Low SMI Low STPCLK Low E H TH Table 53 Output Signals 94 E Fer gt Datasheet 298517 006 intel A Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packa
24. should be inserted between VCCT and the inductor e Any discrete resistor should be inserted between Vccr and the inductor Comments e A magnetically shielded inductor protects the circuit from picking up external flux noise This should provide better timing margins than with an unshielded inductor e A discrete or routed resistor is required because the LC filter by nature has an under damped response which can cause resonance at the LC pole Noise amplification at this band although not in the PLL sensitive spectrum could cause a fatal headroom reduction for analog circuitry The resistor serves to dampen the response Systems with tight space constraints should consider a discrete resistor to provide the required damping resistance Too large of a damping resistance can cause a large IR drop which means less analog headroom and lower frequency e Ceramic capacitors have very high self resonance frequencies but they are not available in large capacitance values A high self resonant frequency coupled with low ESL ESR is crucial for sufficient rejection in the PLL and high frequency band The recommended tantalum capacitors have acceptably low ESR and ESL e The capacitor must be close to the PLL1 and PLL2 pins otherwise the value of the low ESR tantalum capacitor is wasted Note the distance constraint should be translated from the 0 1 Q requirement Datasheet 29851 7 006
25. the priority agent causes the processor to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed and then releases the bus by deasserting BPRI BREQO I O AGTL The BREQO Bus Request signal is a processor Arbitration Bus signal The processor indicates that it wants ownership of the system bus by asserting the BREQO signal During power up configuration the central agent must assert the BREQO bus signal The processor samples BREQO on the active to inactive transition of RESET Optionally this signal may be grounded with a 10 ohm resistor BSEL 1 0 O 3 3V Tolerant The BSEL 1 0 Select Processor System Bus Speed signal is used to configure the processor for the system bus frequency The chipset and system clock generator also uses the BSEL signals The VTTPWRGD signal informs the processor to output the BSEL signals During power up the BSEL signals will be indeterminate for a small period of time The chipset and clock generator should not sample the BSEL signals until the VTTPWRGD signal is asserted The assertion of the VTTPWRGD signal indicates that the BSEL signals are stable and driven to a final state by the processor Please refer to Figure 15 for the timing relationship between the BSEL and VITPWRGBD signals Table 51 shows the encoding scheme for BSEL 1 0 The only supported system bus frequency for t
26. 0 signals can be enabled for ECC checking or disabled for no checking DRDY I O AGTL The DRDY Data Ready signal is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi cycle data transfer DRDY can be deasserted to insert idle clocks This signal must be connected to the appropriate pins balls on both agents on the system bus DPSLP I 1 5 V Tolerant The DPSLP Deep Sleep signal when asserted in the Quick Start state causes the processor to enter the Deep Sleep state In order to return to the Quick Start state BCLK BCLK must be running and the DPSLP pin must be deasserted Datasheet 87 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 88 EDGCTRLP I Analog The EDGCTRLP Edge Rate Control signal is used to configure the edge rate of the AGTL output buffers Connect the signal to Vss with a 110 Q 1 resistor FERRY O 1 5 V Tolerant Open drain The FERR Floating point Error signal is asserted when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and it is included for compatibility with systems using DOS type floating point error reporting FLUSH I 1 5 V Tolerant When the FLUSH Flush input signal is asserted the processor writes back all internal cache lines in the Modified state and invalidates all internal cache line
27. 00 1509 298517 006 Datasheet 35 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Table 21 Vcc Tolerances for the Mobile Intel Celeron Processor in the Deep Sleep State VID 1 50 V a Wa Aik 36 Datasheet 298517 006 intel E Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Figure 5 Illustration of Vcc Static and Transient Tolerances VID 1 15 V 1 250 Transient Maximum Static Maximum 1 200 Static Typical 1 150 1 100 4 10 lt Static Minimum 1 050 Transient Minimum 1 000 0 950 ICC Figure 6 Illustration of Deep Sleep Vcc Static and Transient Tolerances VID Setting 1 15 V 1 180 Transient Maximum 1 160 Static Maximum Static Typical 1 140 1 120 4 1 100 1 080 10 lt 1 060 Static Minimum 1 040 1 020 Transient Minimum 1 000 0 980 ICC 298517 006 Datasheet 37 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Figure 7 Illustration of Vcc Static and Transient Tolerances VID 1 40 V 1 500 Transient Maximum 1 450 Static Maximum 1 400 Static Typical 1 350 Vcc V 1 300 Static Minimum Transient Minimum 1 250 1 200 SEEE EEEE oF oP Pa oP e pp Icc A 38 Datasheet 298517 006 intel Mobile Intel Celeron Proc
28. 06 Datasheet 27 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 28 4 5 8 9 10 11 lccxmax Specifications are specified at Vcc static typical derived from the tolerances in Table 12 through Table 19 Vectimax Tjmax and under maximum signal loading conditions Based on simulations and averaged over the duration of any change in current Use to compute the maximum inductance and reaction time of the voltage regulator This parameter is not tested Maximum values specified by design characterization at nominal Vcc and Vecr Vecx must be within this range under all operating conditions including maximum current transients Vcc must return to within the static voltage specification Vecx nc within 100 us after a transient event VID leakage current is lt 100 pA for VID voltages under 3 0 V Typical Vcc indicates the VID encoded voltage Voltage supplied must conform to the load line specification shown in Table 12 through Table 19 Voltages are measured at the processor socket pin for the Micro FCPGA part and at the package ball on the Micro FCBGA part This specification applies only to the Ultra Low Voltage Mobile Intel Celeron Processor Table 12 Vcc Tolerances for the Low Voltage Mobile Intel Celeron Processor VID 1 15 V EE Paso as re o wo REC rar o are REA EC o ee RECO E over 00 es o see 05 es o fee or frer LAL 1 118 1 093 1 1 1
29. 114 1 089 1 1 co Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 13 Vcc Tolerances for the Low Voltage Mobile Intel Celeron Processor in the Deep Sleep State VID 1 V a 1 114 1 089 1 139 1 069 1 159 1 110 1 085 1 135 1 065 1 155 1 069 1 119 1 139 Eso 1000 1 065 1 115 1 135 Table 14 Vcc Tolerances for the Ultra Low Voltage Mobile Intel Celeron Processor VID 1 1 V sene Transient T a 1 067 1 117 1 04 1 137 1 088 1 063 1 113 1 04 1 133 1 084 1 059 1 109 1 03 1 129 al a D al 1 080 1 055 1 105 1 03 1 125 1 047 1 02 1 117 1 043 1 093 1 023 1 113 1 035 1 015 1 105 1 027 1 007 1 121 Y E o o wo al Al Qm lO lG ll o 298517 006 Datasheet 29 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Table 15 Vcc Tolerances for the Ultra Low Voltage Mobile Intel Celeron Processor in the Deep Sleep State VID 1 1 V Vee V Transient 4 0 1 052 1 027 1 077 1 007 1 097 5 0 1 048 1 023 1 073 1 003 1 093 1 056 1 031 1 081 1 011 1 101 30 Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 16 Vcc Tolerances for the Mobile Intel Celeron Processor VID 1 40 V Vcc V e statie Transient Typ 60 rore 1361
30. 3 u in Micro FCBGA and Micro FCPGA Packages Datasheet 76 Signal Name No Signal Name EME Signal Name No Signal Name vss ass ves rove veer PEAN CT foe e KENA CCOO E ote Junto 9 e APS FLUSH Ar JM Are FERR CI forrest foe ns Teer Ts vee fez BPMO AF11 TESTHI JHE JE ERERRRERBBE GO llO Om G lM A lO S ECO veo ara os nn ves aci vos Tes vecer Ts frc E acis vec aea srece ario Prea Aes _ es lt Q O A wl lt m lt lt D o D m 616 R m m SIE ela aj LT 4 4 vss picas es faen Tee es Jae vss Ter Tes ar Taa pwrcooo Acie vec Tes vo aras Tann vss aea vos jara vos aras Tea vo er vee fuero uo puras pss lso vss es oer aer vss zen vss acze oer asis vs S por T ermapror er vs es voor CCOO COM CI ves laos omosrer Tass Taar gt gt ns es Ts T pr fro ae Iag T ns veer aes ws T ns pani jaan IGNNE AE24 DEPO AD10 rek AE25 DEP2 Datasheet 29851 7 006 intel A Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 46 Signal Listing in Order by Signal Name No Signal Name Signal Buffer Type No Signal Name Signal Buffer Type KA A30 AGTL I O AF23 BINIT AGTL I O J A4 AGTL I O BNR AGTL I O 2 as AGTL I O AF22 BP2 AGTL I O AGH AGTL I O AE20 BP3 AGTL I O AT AGTL I O AD22 BPMO AGTL I O A8 AGTL I O AD21 BPM1 AGTL I O AQ AGTL I O BPRI AGTL In
31. 75 V with respect to ground Parameter applies to CLKREF TESTHI VTTPWRGD signals Parameter applies to CMOS Open drain APIC TESTLO and TAP bus signal groups only Parameter applies to PWRGOOD signal Parameter applies to PICCLK signal Parameter applies to each VID pin ball individually Parameter applies to BCLK signal in Single Ended Clocking Mode OO NOY 91 e O DC Specifications Table 11 through Table 24 list the DC specifications for the Mobile Intel Celeron Processor Specifications are valid only while meeting specifications for the junction temperature clock frequency and input voltages The junction temperature range for all DC specifications is 0 C to 100 C unless otherwise noted Care should be taken to read all notes associated with each parameter Unlike the Mobile Intel Pentium III Processor the Ve tolerances for the Mobile Intel Celeron Processor are not specified as a percentage of nominal The tolerances are instead specified in the form of load lines for the static and transient cases in Table 12 through Table 21 Illustration of the load lines is shown in Figure 5 through Figure 8 Datasheet 29851 7 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 11 Power Specifications for Mobile Intel Celeron Processor V cc Transient Vcc for core logic Static Vcc for core logic Vcc for System Bus Buffers Transient tolerance 1 138 Vcc for System Bus Bu
32. BGA and Micro FCPGA Packages Datasheet Processor Initialization and Configuration 7 1 7 1 1 7 2 298517 006 Description The Mobile Intel Celeron Processor has some configuration options that are determined by hardware and some that are determined by software The processor samples its hardware configuration at reset on the active to inactive transition of RESET The P6 Family of Processors Developer s Manual describes these configuration options Some of the configuration options for the Mobile Intel Celeron Processor are described in the remainder of this section Quick Start Enable Quick Start enabling is mandatory on the Mobile Intel Celeron Processor by strapping A15 low When the STPCLK signal is asserted it will enter the Quick Start state when A15 is sampled active on the RESET signal s active to inactive transition The Quick Start state supports snoops from the bus priority device but it does not support symmetric master snoops nor is the latching of interrupts supported A 1 in bit position 5 of the Power on Configuration register indicates that the Quick Start state has been enabled System Bus Frequency The current generation Mobile Intel Celeron Processor will only function with a system bus frequency of 133 MHz The Low Voltage and Ultra Low Voltage Mobile Intel Celeron Processors will support both 100 MHz and 133 MHz bus frequencies Bit positions 18 to 19 of the Power on Configuration register indica
33. Buffer Type F25 AF6 1 5 V Open Drain Output U26 AF4 1 5 V Open Drain Output V26 AGTL I O AGTL I O AGTL I O AGTL I O AGTL I O Datasheet 29851 7 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet No stgnainame signalButter Tyre No signainame signat Buter Type E2 Table 47 Voltage and No Connect Pin Ball Locations 298517 006 Signal Pin Ball Numbers Name A2 A5 A11 B1 C1 C4 C22 D1 D26 El F1 L5 N4 N24 P1 P4 P5 P26 AD4 AD13 AD23 AE8 AE10 AF17 AF18 D6 D8 D10 D12 D14 D16 D18 D20 D22 E5 E7 E9 E11 E13 E15 E17 E19 E21 F6 F8 F10 F12 F14 F16 F18 F20 F22 G5 G21 H6 H22 J5 J21 K6 K22 L21 M6 M22 N5 N21 P6 P22 R5 R21 T6 T22 U5 U21 V6 V22 W5 W21 Y6 Y22 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC5 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 A26 C5 C7 C9 C11 C13 C15 C17 C19 C21 D5 E4 E6 G4 G23 J4 J23 L4 L23 N23 R23 U23 V4 W23 AA4 AA23 AC4 AC23 AD6 AD8 AD12 AD14 AD18 AD20 AE3 AE18 AF1 AF2 A25 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B26 C23 C25 D2 D4 D7 D9 D11 D13 D15 D17 D19 D21 E8 E10 E12 E14 E16 E18 E20 E22 E25 F2 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 G6 G22 G25 H2 H4 H5 H21 H23 J6 J22 J25 K2 K4 K5 K21 K23 L6 L22 L25 M2 M3 M4 M21 M23
34. Celeron Processor 0 13 u Signals 2 2 2 2 1 2 2 2 2 2 3 14 BCLK BCLK Differential host clk signals CLKREF Host Clock reference signal in Single Ended Clocking mode BSEL 1 0 Signals are output only instead of I O Please refer to the Appendix for details DPSLP Deep Sleep pin replaces SLP pin on the mobile Celeron processor 0 18 u NCTRL AGTL output buffer pull down impedance control VID 4 0 Voltage Identification different implementation from mobile Celeron processor 0 18 u Please refer to Section 3 2 3 for details VTTPWRGD Power Good signal for VCCT which indicates that the VID signals are stable Please refer to Figure 3 for VTTPWRGD system level connections Power Management Clock Control Architecture The Mobile Intel Celeron Processor clock control architecture Figure 1 has been optimized for leading edge mobile computer designs The clock control architecture consists of six different clock states Normal Auto Halt Quick Start HALT Grant Snoop and Deep Sleep states The Auto Halt state provides a low power clock state that can be controlled through the software execution of the HLT instruction The Quick Start state provides a very low power and low exit latency clock state that can be used for hardware controlled idle computer states The Deep Sleep state provides extremely low power states that can be used for Power On Suspend computer states which is an alternative to shutti
35. Contents 298517 006 VMOU CHO A TTT 10 1 1 SU A E A 10 1 2 SECA TTT TTT 11 1 3 TEMO O iii adi dadas 11 1 4 Retenes 12 Mobile Intel Celeron Processor Features 13 2 1 New Features in the Mobile Intel Celeron Processor 13 2 1 1 133 MHz PSB With AGTL Signaling eee eee 13 2 1 2 256 K On die Integrated L2 Cache cooconcccccnnoccccnonconcccnononccnnnnnnccnnnnnncncnnannnccnnnnna 13 2 1 3 Data Prefetch Log Co aas aaa Ka aaa A aaa tala indicada 13 2 1 4 Differential CloOCKINO c0coomiioriicd n nice retar di era 13 2 1 5 Signal Differences Between the Mobile Intel Celeron Processor 0 18 p in BGA2 and Micro PGA2 Packages and the Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages ccccicoccccnocococcnnonnnnnnos 14 2 2 Power Management sasana aan ia ag KING KAEN BETAWI EA NANA KE canada cola ceci creada 14 2 2 1 Clock Control Architecture a ee eee 14 2 2 2 Normal Stat aana anaa ne dia Na Cia 14 2 235 Auto Halt States aaa aa aa na aa saa dan aaa di Ng ga a aa maneng a aga 14 2 24 QUICK Start State aana a aaa aa a daa aaa tna 15 2 2 5 HAET Grant SNOOP State vicios ie aaa 16 2 2 0 Deep Sleep Sale ia saa aa GENE aa aa thease tada 16 2 2 7 Operating System Implications of Low power States seaeaeeraranan een aeene 17 2 3 AGT Le SIQMAIS rak naa aa Saban at aaa di E KA AA NGA EA au KA ENEH NANA DANA GA KANE GETEN EEN 17 2 4 Mobile Intel Celeron
36. ET must be connected to the appropriate pins balls on both agents on the system bus RP I O AGTL The RP Request Parity signal is driven by the request initiator and provides parity protection on ADS and REQ 4 0 RP should be connected to the appropriate pins balls on both agents on the system bus A correct parity signal is high if an even number of covered signals is low and low if an odd number of covered signals are low This definition allows parity to be high when all covered signals are high RS 2 0 UO AGTL The RS 2 0 Response Status signals are driven by the response agent the agent responsible for completion of the current transaction and must be connected to the appropriate pins balls on both agents on the system bus RSP I AGTL The RSP Response Parity signal is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 RSP provides parity protection for RS 2 0 RSP should be connected to the appropriate pins balls on both agents on the system bus A correct parity signal is high if an even number of covered signals are low and it is low if an odd number of covered signals are low During Idle state of RS 2 0 RS 2 0 000 RSP is also high since it is not driven by any agent guaranteeing correct parity RTTIMPEDP I Analog The RTTIMPEDP Rrr Impedance PMOS signal is used to configure the on die AGTL termination Conne
37. H CT CONEA COS wan 11100 USC REE Vin Absolute Voltage Range Undershoot Overshoot Note 2 PICCLK Rising Edge Ringback 1 6 v 20 Absolute Value Note 3 PICCLK Falling Edge Ringback 104 v 20 Absolute Value Note 3 NOTES 1 The clock must rise fall monotonically between ViL20 and V H20 2 These specifications apply only when PICCLK is running See the DC specifications for when PICCLK is stopped PICCLK may not be above VjH20 max Or below ViL20 min for more than 50 of the clock cycle 3 The rising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the PICCLK signal can go to after passing the V x20 rising or V L20 falling voltage limits Figure 22 BCLK Single Ended PICCLK Generic Clock Waveform V0012 01 298517 006 Datasheet 59 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 4 2 AGTL AC Signal Quality Specifications Ringback specifications for the AGTL signals are as follows Ringback below Vrer max 200 mV is not authorized during low to high transitions Ringback above VrgF min 200 mV is not authorized during high to low transitions Overshoot and undershoot specifications are documented in Table 38 and Table 39 and illustrated in Figure 23 Figure 23 Maximum Acceptable Overshoot Undershoot Waveform Time Dependant Overshoot 7 Po Time Dependant Undershoot
38. III II II OI II aee D0006 02 T9 AGTL Input Hold Time T8 AGTL Input Setup Time Tv T10 RESET Pulse Width Tw T16 Reset Configuration Signals A 15 5 BREQO FLUSH INIT PICDO Setup Time Tx T17 Reset Configuration Signals A 15 5 BREQO FLUSH INIT PICDO Hold Time Ty T18D RESET inactive to Valid Outputs Tz T18E RESET inactive to Drive Signals Vc Crossing point of BCLK rising edge and BCLK falling edge Differential Clock 1 25 V Single Ended Clock 298517 006 Datasheet 51 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Figure 15 Power on Sequence and Reset Timings VTTPWRGD VIHVTTPWR min VID 4 0 BSEL 1 0 CMOSREF CLKREF V REF PWRGOOD nare Tp RESET V0040 00 T T15 PWRGOOD Inactive Pulse Width T T18 RESET PWRGOOD Setup Time Te T18B Setup time from VCC valid until PWRGOOD assertion Ty TIBA Setup time from VCCT valid to VTTPWRGD assertion Te T18C VID BSEL valid time before VTTPWRGD assertion 52 Datasheet 298517 006 ntel a Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Figure 16 Power Down Sequencing and Timings VCC Leading VCC 12 PICD 1 0 AGTL OUTPUTS OTHER CMOS OUTPUTS ALL INPUTS T T19A Time from VCC nominal 12 to PWRGOOD low T T19B All outputs valid after PWRGOOD low T T19C
39. ISTPCLK and HS is equivalent to the active low signal STPCLK is unasserted i e it is at 1 5V and the HS condition is true Electrical low signal levels Electrical high signal levels Logical low For example BD 3 0 1010 HLHL refers to a hexadecimal A and D 3 0 1010 LHLP also refers to a hexadecimal A Logical high For example BD 3 0 1010 HLHL refers to a hexadecimal A and D 3 0 1010 LHLP also refers to a hexadecimal A Specifications that are yet to be determined and will be updated in future revisions of the document Don t care condition Datasheet 11 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 1 4 12 References P6 Family of Processors Hardware Developer s Manual Order Number 244001 001 Intel Architecture Optimization Reference Manual Order Number 245127 001 Intel Architecture Software Developer s Manual Volume I Basic Architecture Order Number 245470 Volume II Instruction Set Reference Order Number 245471 Volume III System Programming Guide Order Number 245472 CK 408 CK Titan Clock Synthesizer Driver Specification Contact your Intel Field Sales Representative Mobile Intel Pentium III Processor M I O Buffer Models IBIS Format Contact your Intel Field Sales Representative Intel 830 Chipset Family 82830 Graphics
40. KEEPOUT CAPACITOR AREA BOTTOM VIEW 66 Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Figure 26 Socketable Micro FCPGA Package Top and Side View 7 K1 SUBSTRATE KEEPOUT ZONE DO NOT CONTACT PACKAGE 8 places INSIDE THIS LINE 5 K 4 places gt MA K d 1 25 MAK A A2 gt gt 2 03 0 08 PIN A1 CORNER A1 NOTE All dimensions in millimeters Values shown are for reference only See Table 36 for specific details 298517 006 Datasheet 67 Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages Datasheet Figure 27 Socketable Micro FCPGA Package Bottom View AF AE AD AC AB AA EN EAN A 9000 OE y e 25X 1 27 e 25X 1 27 2 4 6 8 10 12 14 16 18 20 22 24 26 NOTE All dimensions in millimeters Values shown are for reference only See Table 36 for specific details 68 Datasheet 298517 006 intel 5 2 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Surface Mount Micro FCBGA Package The Mobile Intel Celeron Processor will also be available in a surface mount 479 ball Micro FCBGA package The Low Voltage and Ultra Low Voltage processors will be available only in this package The Mobile Intel Celeron processors at 1 45V and 1 5V will not be av
41. Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages At 1 33 GHz 1 26 GHz 1 20 GHz 1 13 GHz 1 06 GHz 1 00 GHz Low Voltage 866 MHz 733 MHz 650 MHz and Ultra Low Voltage 800 MHz 733 MHz 700 MHz and 650 MHz Datasheet April 2003 Order Number 298517 006 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications The information provided in this report and related materials and presentations are intended to illustrate the effects of certain design variables as determined by modeling and are neither a recommendation nor endorsement of any specific system level design practices or targets The model results are based on a simulated notebook configuration and do not describe or characteri
42. Overall height as delivered Values were based on design specifications and tolerances Final height after surface mount depends on OEM motherboard design and SMT process 3 Dimension for CPUID 0x06B1 4 Dimension for CPUID 0x06B4 Datasheet 69 Mobile Intel Celeron Processor 0 13 u in In Micro FCBGA and Micro FCPGA Packages Datasheet Figure 28 Micro FCBGA Package Top and Bottom Isometric Views PACKAGE KEEPOUT CAPACITOR AREA LABEL DIE TOP VIEW BOTTOM VIEW 70 Datasheet 298517 006 intel Figure 29 Micro FCBGA Package Top and Side Views 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet 7 K1 SUBSTRATE KEEPOUT ZONE DO NOT CONTACT PACKAGE 8 places 0 20 P INSIDE THIS LINE 5 K 4 places A 2 a 35 D gt 0 78 b O A I 5 4 479 places A O El 35 E NOTE All dimensions in millimeters Values shown are for reference only See Table 37 for specific details Kab a PIN A1 CORNER Datasheet 71 Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages Datasheet 72 Figure 30 Micro FCBGA Package Bottom View intel AF AE AD AC AB D TU 0000000000000000000000000 00000000000000000000000000 00000000000000000000000000O E 3 25X 1 27 2 00000000000000000000000000O 4 0000000000000 000000000000O0O
43. Processor These signals can be used to support automatic selection of Vcc voltages They are needed to cleanly support voltage specification variations on current and future processors VID 4 0 are defined in Table 7 The voltages specified in the VID table are the Battery Optimized Mode Vcc voltages The VID 4 0 signals are open drain on the processor and need pull up resistors to 3 3 V on the motherboard Please refer to the mobile VR guidelines provided by Intel for additional information Table 7 Mobile Intel Celeron Processor VID Values VID 4 0 VID 4 0 VID 4 0 VID 4 0 00000 00001 00010 Figure 3 shows the system level connections for the VTTPWRGD signal Please refer to the appropriate VR and system level guidelines provided by Intel for more details 298517 006 Datasheet 23 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Figure 3 VTTPWRGD System Level Connections 3 2 4 Vcct Vect Processor Voltage Regulator Vect Vttpwrgd Vttpwrgd output input Clock Generator Vttpwrgd input 1 2V to 3 3V Level Shifter VTTPWRGD Signal Quality Specification The VITPWRGBD signal is an input to the processor used to determine that the VTT power is stable and the VID and BSEL signals should be driven to their final state by the processor To ensure the processor correctly reads this signal it must meet the following requirement whi
44. Referenced to TCK falling edge Valid delay timing for this signal is specified into 150 Q terminated to 1 5 V and 0 pF of external load For real system timings these specifications must be derated for external capacitance at 105 ps pF Non Test Outputs and Inputs are the normal output or input signals except TCK TRST TDI TDO and TMS These timings correspond to the response of these signals due to boundary scan operations During Debug Port operation use the normal specified timings rather than the TAP signal timings Table 34 Quick Start Deep Sleep AC Specifications el pan p wan roar A Quick Start Cycle Completion to Clock Stop or 100 BCLKs 17 18 DPSLP assertion eee 187 Deep Siep PLL LockLateney o foo fis re roe ms steen Hol Tmetom H e re 7 ao input Sianal Hold Time nom res nest Je ear re NOTES 1 2 48 Input signals other than RESET and BPRI must be held constant in the Quick Start state The BCLK BCLK Settling Time specification T60 applies to Deep Sleep state exit under all conditions Datasheet 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Figure 9 BCLK Single Ended PICCLK TCK Generic Clock Timing Waveform D0003 01 Tr T5S T5S1 T34 T25 Rise Time Ti T6S T6S1 T35 T26 Fall Time Th T3S T3S1 T32 T23 High Time T T4S T4S1 T33 T24 Low Time Tp T1S T1S1 T31 T22 Period Vrrip 1 25V for
45. SLP Ka fees ANANA 4 State 0 2 V gila The clock must rise fall monotonically between VIL BCLK and VIH BCLK E These specifications apply only when BCLK BCLK are running 3 Therising and falling edge ringback voltage specified is the minimum rising or maximum falling voltage the differential waveform can go to after passing the VIH_DIFF rising or VIL_DIFF falling levels VIL_DIFF max 0 57 V VIH_DIFF min 0 57 V 4 Applies when BCLK and BCLK are stopped in Deep Sleep State Table 36 BCLK Single Ended DC Specifications and AC Signal Quality Specifications 58 II CECI CN CIN era FCI EIA CTC IZAN ON CA NA ESTA CTC va cti Rising rage 1 HH 20 abone Vale noes vs BCU Faning Esge Ringback jos v 20 absolute vale Note NOTES 1 The clock must rise fall monotonically between Vi_pcix and Vinu acu BCLK must be stopped in the low state 2 These specifications apply only when BCLK is running BCLK may not be above Vinpcikmax Or below VIL BcLK min for more than 50 of the clock cycle 3 The rising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the BCLK signal can go to after passing the Vi scix rising or Vit sctk falling voltage limits Datasheet 29851 7 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 37 PICCLK DC Specifications and AC Signal Quality Specifications I E AOS
46. SREFmin V 300 mV Vins Input High Voltage 1 5 V CMOS WeMOSREFmax 2 0 V Note 10 250 mV ViH15PICD Input High Voltage 15V PICD 1 0 WeMOSREFmax 2 0 V Note 11 200 mV Vas Oupa towvotege 33V saras CH H Jos v e E E Vase COSREFVotage loo ana v ne Varen input tow votege VHPARGO Joa Vv ner Varrar input Hian Votage vITAWRGO 0 Wer 0000 IS MESAS E TT CO CTI CI E NAN Leakage Current for Inputs Outputs 100 Note 5 and l Os psi Parameter applies to the PWRGOOD signal only 2 V ix min ANd Vinx max only apply when BCLK BCLK and PICCLK are stopped PICCLK should be stopped in the low state See Table 33 and Table 34 for DC levels when BCLK and BCLK are stopped 3 Measured at 9 mA 4 Vcmosrer should be created from a stable 1 5 V supply using a voltage divider It must track the voltage supply to maintain noise immunity The same 1 5 V supply should be used to power the chipset CMOS 1 O buffers that drive these signals 5 0 lt vinout lt Vins mas 6 Specified as the minimum amount of current that the output buffer must be able to sink However Vo max cannot be guaranteed if this specification is exceeded 7 Parameter applies to VTTPWRGD signal only 8 Applies to non AGTL signals except BCLK PWRGOOD PICCLK BSEL 1 0 VID 4 0 9 5 DC tolerance CLKREF must be generated from the 2 5 V supply used to generate the BCLK signal AC Tolerance must be less than 40 dB 1 MHz 10 Applies to a
47. Systm Sigid Simulations cuca E EA 58 4 1 System Bus Clock BCLK and PICCLK DC Specifications and AC Signal Quality Specification Spree an ee daa A t 58 4 2 AGTL AC Signal Quality Specifications see eee eee ee 60 4 3 Non AGTL Signal Quality Specifications 2 0 eee eee eaaa aana eaaa aana nean nean nana 61 4 3 1 PWRGOOD VTTPWRGD Signal Quality Specifications ss eee 62 4 3 1 1 VTTPWRGD Noise Parameter Specification eee eee 62 4 3 1 2 VTTPWRGD Transition Parameter Recommendation 63 4 3 1 2 1 Transition Region sse sees ee eree ereer ereer nenen reenn 63 4 3 1 2 2 Transition TIMe a kabina dud adah nada daga bana a Na a ma TUN a daa 63 4 3 1 2 3 IG Tal 63 5 Mechanical SpeciTicaiong sees eee eee eee ee eee 65 5 1 Socketable Micro FCPGA Package ooononocccnnoccccncocononcnonononcnnnnnn sana nano nenen nenn 65 5 2 Surface Mount Micro FCBGA Package eee eee 69 5 3 Signal LISUNGS aaa aana a aa dadas 73 6 Vee Thermal SpecificatlO0nNs a a anaa eds Activin teste eee ida 80 6 1 Thermal Diode sika aka ag cat bee eel eee 82 7 Processor Initialization and Confnguration sees eee eee eee eee 83 7 1 DESCHIPUON anaa an inab Na ded edie ER a eee rd eA are O La 83 T11 Quick Start Enable sn it a nes Sain eee eee 83 71 2 System Bus Frequency coli dt 83 as APIC Ema Ble saca tein TT 83 7 2 Clock Frequencies and Ratios sese seer eee eee 83 8 Processor Interface TTT 84 8 1 Alphabetical Signal Refer
48. a Micro FCBGA and Micro FCPGA Packages Datasheet 2 2 5 2 2 6 16 A transition to the Deep Sleep state can be made by stopping the clock input to the processor or asserting the DPSLP signal A transition back to the Normal state from the Quick Start state is made only if the STPCLK signal is deasserted While in this state the processor is limited in its ability to respond to input It is incapable of latching any interrupts servicing snoop transactions from symmetric bus masters or responding to FLUSH or BINIT assertions While the processor is in the Quick Start state it will not respond properly to any input signal other than STPCLK RESET or BPRI If any other input signal changes then the behavior of the processor will be unpredictable No serial interrupt messages may begin or be in progress while the processor is in the Quick Start state RESET assertion will cause the processor to immediately initialize itself but the processor will stay in the Quick Start state after initialization until STPCLK is deasserted HALT Grant Snoop State The processor will respond to snoop transactions on the system bus while in the Auto Halt or Quick Start state When a snoop transaction is presented on the system bus the processor will enter the HALT Grant Snoop state The processor will remain in this state until the snoop has been serviced and the system bus is quiet After the snoop has been serviced the processor will return to its
49. ailable in this package Mechanical specifications are shown in Table 44 Figure 28 through Figure 30 illustrate different views of the package The Micro FCBGA package may have capacitors placed in the area surrounding the die Because the die side capacitors are electrically conductive and only slightly shorter than the die height care should be taken to avoid contacting the capacitors with electrically conductive materials Doing so may short the capacitors and possibly damage the device or render it inactive The use of an insulating material between the capacitors and any thermal solution should be considered to prevent capacitor shorting Table 44 Micro FCBGA Package Mechanical Specifications 298517 006 Symbol Parameter Min Max Unit A Overall height as delivered 1 2 27 2 77 mm A2 Die height 0 854 mm b Ball diameter 0 78 mm D Package substrate length 34 9 35 1 mm E Package substrate width 34 9 35 1 mm D1 Die length 11 18 mm 10 82 E1 Die width 7 20 mm 6 85 e Ball pitch 1 27 mm Ball count 479 each K Keep out outline from edge of package 5 mm K1 Keep out outline at corner of package 7 mm K2 Capacitor keep out height 0 7 mm S Package edge to first ball center 1 625 mm Solder ball coplanarity 0 2 mm Pdie Allowable pressure on the die for thermal solution 689 kPa W Package weight 4 5 g NOTES 1 All dimensions are subject to change 2
50. and Memory Controller Hub GMCH M Datasheet Order Number 298338 003 Intel 830 Chipset Family Intel 830 Chipset Platform Design Guide Order Number 298339 003 Intel 830 Chipset Family Intel 82801CAM I O Controller Hub 3 ICH3 M Datasheet Order Number 290716 001 Intel Mobile Voltage Positioning II IMVP II Design Guide Contact your Intel Field Sales Representative Mobile Intel Pentium 111 Processor M 440MX Platform Design Guide Contact your Intel Field Sales Representative Intel Processor Identification and the CPUID Instruction Application Note AP 485 Order Number 241618 020 Datasheet 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Mobile Intel Celeron Processor Features 2 1 2 1 1 298517 006 New Features in the Mobile Intel Celeron Processor 133 MHz PSB With AGTL Signaling The Mobile Intel Celeron Processor uses Assisted GTL AGTL signaling on the PSB interface The main difference between AGTL and GTL used on previous Intel processors is Vecer 1 25 V for AGTL versus 1 5 V for GTL The lower voltage swing enables high performance at lower power The Low Voltage and Ultra Low Voltage Mobile Celeron Processors will also support a 100 MHz PSB 256 K On die Integrated L2 Cache The 256 K on die integrated L2 cache on the Mobile Intel Celeron Processor is double the L2 cache size on the Mobile Intel Celeron Processor 0 18 u The
51. bled and the LINT1 or LINTO signal is configured as an edge triggered interrupt with fixed delivery otherwise specification T14 applies When driven inactive or after Vcc Vecr and BCLK BCLK become stable PWRGOOD must remain below ViL1s max Until all the voltage planes meet the voltage tolerance specifications in Table 12 through Table 21 and BCLK BCLK have met the BCLK BCLK AC specifications in Table 35 and Table 36 for at least 2 us PWRGOOD must rise error free and monotonically to 1 8 V If the BCLK Settling Time specification T60 can be guaranteed at power on reset then the PVRGOOD Inactive Pulse Width specification T15 is waived and BCLK may start after PWRGOOD is asserted PWRGOOD must still remain below VjL25 max until all the voltage planes meet the voltage tolerance specifications Datasheet 45 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Table 31 Reset Configuration AC Specifications and Power On Power Down ba smn lel io Reset Configuration Signals A 15 5 BCLKs Before deassertion of BREQO FLUSH INIT PICDO Setup RESET Time Reset Configuration Signals A 15 5 20 BCLKs 11 After clock that BREQO FLUSH INIT PICDO Hold Time deasserts RESET RESET PWRGOOD Setup Time ms Before deassertion of o k HS H H H e fa TT D I KA fs pe o 7 T18C BSEL VID valid time before VTTPWRGD ps 12 assertion eek CI SS CONOCES KNA T19A Time f
52. ccounted for as a component of BCLK skew between devices 5 Measured between 0 5 V and 2 0 V 298517 006 Datasheet 43 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Table 28 Valid Mobile Intel Celeron Processor Frequencies BCLK Frequency Frequency Multiplier Core Frequency Power on Configuration MHz MHz bits 27 25 22 6 5 650 100 0 1111 133 5 5 733 0 0100 133 7 5 1000 0 1101 133 8 1066 0 1010 133 8 5 1133 1 0110 133 9 1200 1 0000 133 10 1333 1 1011 NOTE While other combinations of bus and core frequencies are defined operation at frequencies other than those listed above will not be validated by Intel and are not guaranteed The frequency multiplier is programmed into the processor when it is manufactured and it cannot be changed 44 Datasheet 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 29 AGTL Signal Groups AC Specifications Rrr 560 internally terminated to Vecer Vrer IN cer load 50 ohms ama mee JJ Jn e rer oupa vaid oaa ECO EXEC fo T T9 GTC mpu oa HH e o Nowe PREseT Puse wan me a Notes TB AGTL Input Setup Time 0 95 ns 10 Notes 2 3 6 1 30 Note 7 NOTES 1 dR 30 All AC timings for AGTL signals are referenced to the crossing point of the BCLK rising edge and the BCLK falling edge for Differentia
53. ckage Mechanical Specifications sa eee 69 Signal Listing in Order by Pin Ball Number sees eee eee 74 Signal Listing in Order by Signal Name eee eee eee 77 Voltage and No Connect Pin Ball Locations sese eee eee eee 79 Power Specifications for Mobile Intel Celeron Process0r see eee eee ee 81 Thermal Diode Interface eee eree 82 Thermal Diode SpecificatiOMS oooooooccncnnccnnnnococcccncncconnnononccnnnnnnnnnnonn nn cnn cnn nana nee 82 BSEL 1 0 EMCOGING aaa a a aa Ng Ka a a Da TT 86 Tus eis TTT 94 Output Sinala aeae RE EE AEAEE al di 94 Input Output Signals Single Driver sese sese eee eee 95 Input Output Signals Multiple Driver sees ee eee eee 95 PLL Filter Inductor Recommendations eee ee eee eee 97 PLL Filter Capacitor Recommendations sss eee eee ee 97 PLL Filter Resistor Recommendations esse 98 Datasheet 7 Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages Datasheet Revision History Date Revision Updates October 2001 298517 001 Initial release January 2002 298517 002 Updates include e Added new processor speeds 1 2 GHz 1 13 GHz and 1 06 GHz at 1 45V e Added new Low Voltage 667 MHz e Added new Ultra Low Voltage 650 MHz e Updated Processor Specifications Tables 9 12 15 40 e Added Specification Clarification for VTTPWRGD in Table 25 Figure 21 and Section 4 3 1
54. ct the RTTIMPEDP signal to Vss with a 56 2 Q 1 resistor SMI I 1 5 V Tolerant The SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enters System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler STPCLK I 1 5 V Tolerant The STPCLK Stop Clock signal when asserted causes the processor to enter a low power Quick Start state The processor issues a Stop Grant Acknowledge special transaction and stops providing internal clock signals to all units except the bus and APIC units The processor continues to snoop bus transactions and service interrupts while in the Quick Start state When STPCLK is deasserted and Datasheet 91 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 92 other conditions in are met the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no affect on the bus clock TCK I 1 5 V Tolerant The TCK Test Clock signal provides the clock input for the test bus also known as the test access port TDI I 1 5 V Tolerant The TDI Test Data In signal transfers serial test data to the processor TDI provides the serial input needed for JTAG support TDO O 1 5 V Tolerant Open drain The TDO Test Data
55. ctor of 1 represents the same toggle rate as the 100 MHz clock Ringbacks below Vccr cannot be subtracted from overshoots Lesser undershoot does not allocate longer or larger overshoot Ringbacks above ground cannot be subtracted from undershoots Lesser overshoot does not allocate longer or larger undershoot System designers are encouraged to follow Intel provided AGTL layout guidelines All values are specified by design characterization and are not tested Tj 85 C for 1 33 GHz 4 3 Non AGTL Signal Quality Specifications Signals driven to the Mobile Intel Celeron Processor should meet signal quality specifications to ensure that the processor reads data properly and that incoming signals do not affect the long term reliability of the processor The overshoot and undershoot specifications for non AGTL signals are shown in Table 40 Ringback must not exceed the CMOS Vy and Vi specification levels in Table 24 298517 006 Datasheet 61 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Table 40 Non AGTL Signal Group Overshoot Undershoot Tolerance at the Processor Core 4 3 1 4 3 1 1 Allowed Pulse Duration ns Tj 100C see note 6 Max Vemos Overshoot Undershoot Magnitude volts A Activity Factor 0 01 Activity Factor 0 1 Activity Factor 1 1 Vemos nominal 1 5 V 2 Under no circumstances should the sum of the Max Vemos and absolute value of the Over
56. d the chipset and the bus traces are short It is possible to change the layout and termination of the system bus to take advantage of the mobile environment using the same AGTL I O buffers This termination is provided on the processor core except for the RESET signal 2 4 Mobile Intel Celeron Processor CPUID When the CPUID version information is loaded with EAX 01H the EAX and EBX registers contain the values shown in Table 3 After a power on RESET the EDX register contains the processor version information type family model stepping Table 4 shows the CPUID Cache and TLB descriptor values after the L2 cache is initialized See the Intel Processor Identification and the CPUID Instruction Application Note AP 485 for further information 29851 7 006 Datasheet 17 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Table 3 Mobile Intel Celeron Processor CPUID EAX 31 0 EBX 7 0 Reserved 31 14 Type 13 12 Family 11 8 Model 7 4 Stepping 3 0 Brand ID o jes d e x Jo Table 4 Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors Cache and TLB Descriptors 01H 02H 03H 04H 08H OCH 83H 18 Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet KA Electrical Specifications 3 1 Processor System Signals Table 5 lists the processor system signals by type All AGTL signals ar
57. e The signal quality of the VTTPWRGD signal is critical to the correct operation of the processor Every effort should be made to ensure this signal is monotonic in the transition region If noise or glitches are present on this signal it must be kept to less than 100 mV of a voltage drop from the highest voltage level received to that point This glitch must remain less than 100 mV until the excursion ends by the voltage returning to the highest voltage previously received Please see Figure 4 for an example graph of this situation and requirements Figure 4 Noise Estimation 3 3 298517 006 Transistion Region PN 0 7 Highest voltage S 0 6 received Excursion 0 1 i end 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 Micro Seconds System Bus Clock and Processor Clocking The BCLK and BCLK clock inputs directly control the operating speed of the system bus interface All system bus timing parameters are specified with respect to the crossing point of the rising edge of the BCLK input and falling edge of the BCLK input The Mobile Intel Celeron Processor core frequency is a multiple of the BCLK frequency The processor core frequency is configured during manufacturing The configured bus ratio is visible to software in the Power on configuration register See Section 7 2 for details Multiplying the bus clock frequency is necessary to increase performance while allowing for easier distribution of s
58. e ceramic capacitors should be placed around the package periphery near the balls Trace lengths to the vias should be designed to minimize inductance Avoid bending traces to minimize ESL e High and Mid Frequency Vccr decoupling Place ten 1 uF X7R 0603 ceramic capacitors close to the package Via and trace guidelines are the same as above e Bulk Vcc decoupling Minimum of 1200 uF capacitance with Equivalent Series Resistance ESR less than or equal to 3 5 mQ s Bulk Vccr decoupling Platform dependent but recommendation is minimum of 660 uF with ESR less than or equal to 7 mQ Please refer to the appropriate platform design guidelines for bulk decoupling recommendations Voltage Planes All Vcc and Vss pins balls must be connected to the appropriate voltage plane All Vecr and Vref pins balls must be connected to the appropriate traces on the system electronics In addition to the main Vcc Vecr and Vss power supply signals PLL1 and PLL2 provide analog decoupling to the PLL Datasheet 29851 7 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet section PLL1 and PLL2 should be connected according to Figure 2 Do not connect PLL2 directly to Vss Appendix A contains the RLC filter specification Figure 2 PLL RLC Filter C1 0027 01 PLL2 3 2 3 Voltage Identification There are five voltage identification balls pins on the Mobile Intel Celeron
59. e synchronous with the BCLK and BCLK signals All TAP signals are synchronous with the TCK signal except TRST All CMOS input signals can be applied asynchronously Table 5 System Signal Groups AGTL Input BPRI DEFER RESET RSP AGTL Output PRDY AGTL I O A 35 3 ADSH AERR AP 1 0 BERR BINIT BNR BP 3 2 BPM 1 0 BREQO D 63 0 DBSY DEP 7 0 DRDY HIT HITM LOCK REQ 4 0 RP RS 2 0 TRDY 1 5 V CMOS Input A20M DPSLP FLUSH IGNNE INIT LINTO INTR LINT1 NMI PREQ SMI STPCLK APIC I O PICD 1 0 Power Other CLKREF CMOSREF EDGECTRLP NC NCTRL PLL1 PLL2 RTTIMPEDP Vcc Vecr Veer Vss 1 VCC is the power supply for the core logic 2 PLL1 and PLL2 are power ground for the PLL analog section See Section 3 2 2 for details 3 VCCT is the power supply for the system bus buffers 4 VREF is the voltage reference for the AGTL input buffers 5 VSS is system ground The APIC data and TAP outputs are Open drain and should be pulled up to 1 5 V using resistors with the values shown in Table 6 If Open drain drivers are used for input signals then they should also be pulled up to the appropriate voltage using resistors with the values shown in Table 6 29851 7 006 Datasheet 19 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Table 6 Recommended Resistors for Mobile Intel Celeron Processor Signals 3 1 1 3 1 2 20
60. ecommends that the software clears or masks any floating point error condition before putting the processor into the Deep Sleep state Other Signals The system bus clocks BCLK BCLK must be driven in all of the low power states except the Deep Sleep state The APIC clock PICCLK must be driven whenever BCLK and BCLK are driven Otherwise it is permitted to turn off PICCLK by holding it at Vss BCLK and BCLK should be obey the DC levels in Table 38 for Differential Clocking and Table 39 for Single Ended Clocking In the Auto Halt state the APIC bus data signals PICD 1 0 may toggle due to APIC bus messages These signals are required to be tri stated and pulled up when the processor is in the Quick Start or Deep Sleep states Power Supply Requirements Decoupling Guidelines The Mobile Intel Celeron Processor in Micro FCPGA package has twelve 0805IDC 1 uF surface mount decoupling capacitors Eight capacitors are on the Vcc supply and four capacitors are on Vccr For the Micro FCBGA package there are six 0 68 uF capacitors on Vcc and two 0 68 uF capacitors on Vecr In addition to the package capacitors sufficient board level capacitors are also necessary for power supply decoupling The guidelines are as follows e High and Mid Frequency Vcc decoupling Place twenty four 0 22 uF 0603 capacitors directly under the package on the solder side of the motherboard using at least two vias per capacitor node Ten 10 uF X7 6 3V 1206 siz
61. ee eee eee 45 Table 31 Reset Configuration AC Specifications and Power On Power Down Timings 46 Table 32 APIC Bus Signal AC Specifications eee eee eee 47 Table 33 TAP Signal AC SpecificatiONS oooonnnniininninicinnnncocnnnnococnnnnnnonnnrnnnnn nn KARANA RAKA NAN AGAR ANAA 48 Table 34 Quick Start Deep Sleep AC Specifications see eee 48 Table 35 BCLK Differential DC Specifications and AC Signal Quality Specifications 58 Table 36 BCLK Single Ended DC Specifications and AC Signal Quality Specifications 58 Table 37 PICCLK DC Specifications and AC Signal Quality Specifications 59 Table 38 133 MHz AGTL Signal Group Overshoot Undershoot Tolerance at the Processor COP AT 61 Table 39 100 MHz AGTL Signal Group Overshoot Undershoot Tolerance at the Processor COG castor ainia ini naaa ide 61 Table 40 Non AGTL Signal Group Overshoot Undershoot Tolerance at the Processor 6 lt T O 62 Table 41 VTTPWRGD Noise Parameter Specification eee eee ee 62 Datasheet 298517 006 298517 006 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet VTTPWRGD Transition Parameter Recommendation eee eee eee ani 63 Socketable Micro FCPGA Package Specification sese eee eee 65 Micro FCBGA Pa
62. ence iconos dicta EAO TAT 4 KA KASARE 84 8 2 Signal SUMMANES v 22 nee hee KANA s eee eee 94 Appendix A PLL RLC Filter Specification eee eee eee 96 Al Introductions 00 Aga a aaa NE tas TTT 96 A2 Filter SDECMICAION ia pais 96 A3 Recommendation for Mobile Systems sese eee eee eee 97 A4 COMMENTS asas aaa eect ee e A eee eee eee cet teen ge 98 4 Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Figures Figure 1 Clock Control RTT 15 Figure 2 PLE REC Fleitas adria 23 Figure 3 VTTPWRGD System Level Connechiong ssssssssss esse es nana en aaa anan anna ae nnn nnn 24 Figure 4 Noise EStimation asas hana h aana A sad Ag kna a KA KANA SA AG AKA AN GA NA BAN KAPAN ada 25 Figure 5 Illustration of Vcc Static and Transient Tolerances VID 1 15 V 37 Figure 6 Illustration of Deep Sleep Vcc Static and Transient Tolerances VID Setting 1 15 VI neee 37 Figure 7 Illustration of Vcc Static and Transient Tolerances VID 1 40 VI 38 Figure 8 Illustration of Deep Sleep Vcc Static and Transient Tolerances VID Setting 1 40 VT 39 Figure 9 BCLK Single Ended PICCLK TCK Generic Clock Timing WaveforM 49 Figure 10 Differential BCLK BCLK Waveform Common Mode sese sese eee 49 Figure 11 BCLK BCLK Waveform Differential Mode sss sese 50 Figure 12 Valid Delay Timings sese eee ee eee 50 Figure 13 Setup and Hold
63. essor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Figure 8 Illustration of Deep Sleep Vcc Static and Transient Tolerances VID Setting 1 40 V 298517 006 Vcc V 1 430 1 380 1 330 1 280 1 230 1 180 Transient Maximum Transient Minimum Static Maxim um Static Typical Static Minimum Datasheet 39 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Table 22 AGTL Signal Group DC Specifications omo TA Input High Voltage See Vectmax in Table 11 Output High Voltage lV See Vectimax in Table 11 NOTES 1 Specification applies to leakage high only for pins with on die R 0 lt Vin ouT lt VccT 2 Refer to IBIS models for I V characteristics Table 23 AGTL Bus DC Specifications A E Input Reference Voltage 2 L2 leer 2 N 2 Note 2 NOTES 1 Please refer to Table 11 for minimum and maximum values 2 Vaer should be created from Vcct by a voltage divider 3 The RESET signal does not have an on die Rrr It requires an off die 56 2 Q 1 terminating resistor connected to Vecr 40 Datasheet 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 24 CLKREF APIC TAP CMOS and Open drain Signal Group DC Specifications 3 6 3 6 1 298517 006 Symbol Parameter Min Max Unit Notes Vilas Input Low Voltage 1 5 V CMOS 0 15 N CMO
64. ferenced at 1 0 V The minimum frequency is 2 MHz when PICDO is at 1 5 V at reset Referenced to PICCLK Rising Edge For Open drain signals Valid Delay is synonymous with Float Delay Valid delay timings for these signals are specified into 150 Q to 1 5 V and 0 pF of external load For real system timings these specifications must be derated for external capacitance at 105 ps pF Datasheet 47 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Table 33 TAP Signal AC Specifications CI E T30 TCK Frequency Frequency IET E KETA LT NAN O ji Ma T paso fe e vasom fa3 rextow Time fo fe fo o Var 02 Nate T34 TCK Rise Time 5 0 ns Vemosrer 0 2V Vemosrer 0 2V Notes 2 3 TCK Fall Time Vemosrer 0 2V Venosrer 0 2V Notes 2 3 T __ TRST Puee wen foo es fie asoma Note rar rors sous feo fe tee E AE fao e CN CT o 100 rossi H o re 156 noss rra2 AN Non Test Outputs Float Delay 280 re 16 Notes 2 5 7 8 a3 AlNon Testinpus Sep O fps fis Notes zo s AlNon Test inputs Hoa time Jw90 re 16 noes zo NOTES 1 DARON N All AC timings for TAP signals are referenced to the TCK rising edge at 1 0 V All TAP and CMOS signals are referenced at 1 0 V Not 100 tested Specified by design characterization 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHZ Referenced to TCK rising edge
65. ffers Static tolerance 1 188 lec Current for Vcc at core frequency 800 MHz amp 1 10V 733 MHz 8 1 10 V 700 MHz amp 1 10 V 650 MHz amp 1 10 V 650 MHz amp 1 15 V 667 MHz amp 1 15 V 733 MHz amp 1 15 V 866 MHz amp 1 15 V 1 00 GHz amp 1 40 V 1 26 GHz amp 1 40V 1 06 GHz amp 1 45 V 1 13 GHz 8 1 45 V 1 20 GHz amp 1 45 V 1 33 GHz 8 1 50 V Current for Vect ff A Notes 3 4 lcc an Processor Auto Halt current at Note 4 1 10 V Notes 4 11 1 15V 1 40 V 1 45 V 1 50 V lcc as Processor Quick Start current at 1 10 V 1 15V 1 40 V 1 45 V 1 50 V lec psLp Processor Deep Sleep Leakage current at 1 10V 1 15V 1 40 V 1 45 V 1 50 V dlec dt Vcc power supply current slew rate Alus Notes 5 6 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies Processors will comply with the Iccx max Specification for the current mode of operation 2 Static voltage regulation includes DC output initial voltage set point adjust output ripple and noise temperature and warm up 3 lccr is the current supply for the system bus buffers including the on die termination Note 11 Notes 9 10 Notes 9 10 Notes 9 10 Notes 9 10 Note 11 Notes 9 10 Notes 9 10 Notes 9 10 Notes 9 10 9 Notes 7 10 5 Notes 2 10 Notes 4 11 Notes 4 11 Notes 4 11 Notes 4 11 Note 4 Note 4 Note 4 Note 4 Veet gt Note 4 Notes 4 11 Note 4 Notes 4 11 29851 7 0
66. g to the Auto Halt state from the System Management Mode SMM The FLUSH signal is serviced in the Auto Halt state After the on chip and off chip caches have been flushed the processor will return to the Auto Halt state without issuing a Halt bus cycle Transitions in the A20M and PREQ signals are recognized while in the Auto Halt state Figure 1 Clock Control States STPCLK BCLK stopped N or DPSLP orma HS false STPCLK and HS Deep Sleep 2 or RESET BCLK on and DPSLP STPCLK HiT snoop serviced SNOOP instruction pra occurs an occurs Auto Halt HALT Grant HS true Snoop snoop serviced 0001 022 NOTES 1 State transition does not occur until the Stop Grant or Auto Halt acknowledge bus cycle completes Halt break A20M BINIT FLUSH INIT INTR NMI PREQ RESET SMI or APIC interrupt HLT HLT instruction executed HS Processor Halt State 2 Restrictions apply to the use of both methods of entering Deep Sleep See Deep Sleep state description for details 2 2 4 Quick Start State The processor is required to be configured for the Quick Start state by strapping the A15 signal low In the Quick Start state the processor is only capable of acting on snoop transactions generated by the system bus priority device Because of its snooping behavior Quick Start can only be used in a uniprocessor UP configuration 29851 7 006 Datasheet 15 Mobile Intel Celeron Processor 0 13 u in l ntel
67. ge Mobile Intel Celeron Processor MID Sl Uri ita tibias 29 Table 15 Vcc Tolerances for the Ultra Low Voltage Mobile Intel Celeron Processor in the Deep Sleep State VID 1 1 V 30 Table 16 Vcc Tolerances for the Mobile Intel Celeron Processor VID 1 40 V 31 Table 17 Vcc Tolerances for the Mobile Intel Celeron Processor in the Deep Sleep State VID SAO UM A A anaa a ak 32 Table 18 Vcc Tolerances for the Mobile Intel Celeron Processor VID 1 45 V 33 Table 19 Vcc Tolerances for the Mobile Intel Celeron Processor in the Deep Sleep State VID A A A 34 Table 20 Vcc Tolerances for the Mobile Intel Celeron Processor VID 1 50 V 35 Table 21 Vcc Tolerances for the Mobile Intel Celeron Processor in the Deep Sleep State VIDAS B deb 36 Table 22 AGTL Signal Group DC Specifications eee eee eee eee 40 Table 23 AGTL Bus DC Specifications eee eee eee 40 Table 24 CLKREF APIC TAP CMOS and Open drain Signal Group DC Specifications 41 Table 25 System Bus Clock AC Specifications Diferential eee 42 Table 26 System Bus Clock AC Specifications 133 MHz Single Ended sese 43 Table 27 System Bus Clock AC Specifications 100 MHz Single Ended sese 43 Table 28 Valid Mobile Intel Celeron Processor Frequencies oooooooccccccccocococcnccocccocnnanenccnncnnnns 44 Table 29 AGTL Signal Groups AC Specihnicaiong see eee eee 45 Table 30 CMOS and Open drain Signal Groups AC Specifications e
68. ges Datasheet Table 54 Input Output Signals Single Driver Name Active Level Signal Group Qualified Table 55 Input Output Signals Multiple Driver Name Active Level Signal Group Qualified AERR Low BCLK System Bus ADS 3 BERR Low BCLK System Bus BINIT Low BCLK System Bus 298517 006 Datasheet 95 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Appendix A PLL RLC Filter Specification A1 A2 96 Introduction All Mobile Intel Celeron Processors have internal PLL clock generators which are analog in nature and require quiet power supplies for minimum jitter Jitter is detrimental to a system it degrades external VO timings as well as internal core timings i e maximum frequency The PLL RLC filter specifications for the Mobile Intel Celeron Processor are the same as those for the mobile Intel Pentium IIl Processor M The general desired topology is shown in Figure 2 Excluded from the external circuitry are parasitics associated with each component Filter Specification The function of the filter is two fold It protects the PLL from external noise through low pass attenuation It also protects the PLL from internal noise through high pass filtering In general the low pass description forms an adequate description for the filter The AC low pass specification with input at Vccr and output measured across the capacitor is as follows e lt 0 2 dB
69. he Mobile Intel Celeron Processor is 133 MHz The Low Voltage and Ultra Low Voltage Mobile Intel Celeron Processors will support both 100 MHz and 133 MHz bus frequencies If another frequency is used then the processor is not guaranteed to function properly Table 51 BSEL 1 0 Encoding BSEL 1 0 System Bus Frequency CLKREF Analog The CLKREF System Bus Clock Reference signal provides a reference voltage to define the trip point for the BCLK signal on platforms supporting Single Ended Clocking This signal should be connected to Datasheet 29851 7 006 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet a resistor divider to generate 1 25 V from the 2 5 V supply A minimum of 1 uF decoupling capacitance is recommended on CLKREF On systems with Differential Clocking the CLKREF pin functions as the BCLK input CMOSREF Analog The CMOSREF CMOS Reference Voltage signal provides a DC level reference voltage for the CMOS input buffers CMOSREF must be generated from a stable 1 5V supply 830 chipset family 2 5 V 440MX chipset family and must meet the VCMOSREF specification The same 1 5 V 830 chipset family or 2 5 V 440MX chipset family supply should be used to power the chipset CMOS I O buffers that drive the CMOS signals The Thevenin equivalent impedance of the VCMOSREF generation circuits must be less than 0 5 KQ 1 KQ i e top resistor 500 Q bottom resistor 1 KQ for
70. he Debug Port There are no requirements for placing the Mobile Intel Celeron Processor in the JTAG chain except for those that are dictated by voltage requirements of the TAP signals Catastrophic Thermal Protection The Mobile Intel Celeron Processor does not support catastrophic thermal protection or the THERMTRIP signal An external thermal sensor must be used to protect the processor and the system against excessive temperatures If the external thermal sensor detects a processor junction temperature of 101 C maximum both the Vcc and Vccr supplies to the processor must be reduced to at least 50 of the nominal values within 500 ms and are recommended to be turned off completely within 1 second to prevent damage to the processor Processor temperature must be monitored in all states including low power states Unused Signals All signals named NC must be unconnected Unused AGTL inputs outputs and bi directional signals should be unconnected Unused CMOS active low inputs should be connected to 1 5 V and unused active high inputs should be connected to Vss Unused Open drain outputs should be unconnected When tying any signal to power or ground a resistor will allow for system testability For unused signals Intel suggests that 1 5 kQ resistors are used for pull ups and 1 0 kQ resistors are used for pull downs PICCLK must be driven with a clock that meets specification and the PICD 1 0 signals must be pulled up separately to 1 5 V w
71. he hottest location on the die and time based variations in the die temperature measurement Time based variations can occur when the sampling rate of the thermal diode by the thermal sensor is slower than the rate at which the T temperature can change Table 49 Thermal Diode Interface Signal Name Pin Ball Number Signal Description THERMDA AF13 Thermal diode anode THERMDC AF14 Thermal diode cathode Table 50 Thermal Diode Specifications l en E E EC CI n Diode Ideality Factor 5 150uA 1 0011 1 0067 1 0122 Notes 1 2 3 4 6 n Diode Ideality Factor 5 300uA 1 0003 1 0091 1 0178 Notes 1 2 3 5 6 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range Characterized at 100 C Not 100 tested Specified by design characterization Specified for Forward Bias Current 5 uA min and 150 pA max Specified for Forward Bias Current 5 uA min and 300 uA max The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation Where saturation current q electronic charge V4 voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin Lew ls Gia 1 DURUR 82 Datasheet 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FC
72. he processor while executing publicly available software under normal operating conditions at nominal voltages Contact your Intel Field Sales Representative for further information Datasheet 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 48 Power Specifications for Mobile Intel Celeron Processor 298517 006 At 100 C Note 1 650 MHz amp 1 10 V 700 MHz amp 1 10 V 733 MHz amp 1 10 V 800 MHz amp 1 10V 650 MHz amp 1 15 V 733 MHz amp 1 15 V 866 MHz amp 1 15 V 1 000 GHz amp 1 40 V 1 266 GHz amp 1 40 V 1 066 GHz amp 1 45 V At 85 C Note 4 1 133 GHz 8 1 45 V 1 200 GHz amp 1 45 V 1 333 GHz amp 1 50 V ee oa e Auto Halt power at WW At 50 C Note 2 1 10 V c 1 15V 1 40 V 7 1 45 V 1 50 V E Quick Start power at W_ At 50 C Note 2 1 10 V 1 15V E 1 40 V 1 45V 2 1 50 V Deep Sleep power at W At 35 C Note 2 1 10 V 1 15 V y 1 40 V 1 45 V i 1 50 V Junction Temperature C Note 3 For all processors except 1 33 GHz For 1 33 GHz processor only Note 4 NOTES 1 TDP is defined as the worst case power dissipated by the processor while executing publicly available software under normal operating conditions at nominal voltages that meet the load line specifications The TDP number shown is a specification based on Icc maximum and indirectly tested by Icc maximum testing TDP definition is synonymous with the Ther
73. ignals within the system Clock multiplication within the processor is provided by the internal Phase Lock Loop PLL which requires constant frequency BCLK and BCLK inputs During Reset or on exit from the Deep Sleep state the PLL requires some amount of time to acquire the phase of BCLK and BCLK This time is called the PLL lock latency which is specified in Section 3 6 AC timing parameters T18 and T47 Datasheet 25 Mobile Intel Celeron Processor 0 13 u in l ntel 2 Micro FCBGA and Micro FCPGA Packages Datasheet 3 4 Maximum Ratings Table 10 contains the Mobile Intel Celeron Processor stress ratings Functional operation at the absolute maximum and minimum is neither implied nor guaranteed The processor should not receive a clock while subjected to these conditions Functional operating conditions are provided in the AC and DC tables Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circuitry to resist damage from static electric discharge one should always take precautions to avoid high static voltages or electric fields Table 10 Mobile Intel Celeron Processor Absolute Maximum Ratings 3 5 26 lI HE H 9 NOTES 1 The shipping container is only rated for 65 C Parameter applies to the AGTL signal groups only Compliance with both Vin cr specifications is required The voltage on the AGTL signals must never be below 0 3 V or above 1
74. ing and timings are shown in Figure 15 and Table 31 Power down timing requirements are shown in Figure 16 Figure 17 and Table 31 The Vcc power plane must not rise too fast At least 200 usec Tr must pass from the time that Vcc is at 10 of its nominal value until the time that Vcc is at 90 of its nominal value For more details please refer to the Intel Mobile Voltage Positioning II IMVP II Design Guide contact your Field Sales Representative Test Access Port TAP Connection The TAP interface is an implementation of the IEEE 1149 1 JTAG standard Due to the voltage levels supported by the TAP interface Intel recommends that the Mobile Intel Celeron Processor and the Datasheet 29851 7 006 3 1 5 3 1 5 1 3 1 5 2 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet other 1 5 V JTAG specification compliant devices be last in the JTAG chain after any devices with 3 3 V or 5 0 V JTAG interfaces within the system A translation buffer should be used to reduce the TDO output voltage of the last 3 3 5 0 V device down to the 1 5 V range that the Mobile Intel Celeron Processor can tolerate Multiple copies of TMS and TRST must be provided one for each voltage level A Debug Port and connector may be placed at the start and end of the JTAG chain containing the processor with TDI to the first component coming from the Debug Port and TDO from the last component going to t
75. ith 150 Q resistors even if the local APIC is not used If the TAP signals are not used then the inputs should be pulled to ground with 1 kQ resistors and TDO should be left unconnected Signal State in Low power States System Bus Signals All of the system bus signals have AGTL input output or input output drivers Except when servicing snoops the system bus signals are tri stated and pulled up by the termination resistors Snoops are not permitted in the Deep Sleep state CMOS and Open drain Signals The CMOS input signals are allowed to be in either the logic high or low state when the processor is in a low power state In the Auto Halt state these signals are allowed to toggle These input buffers have no internal pull up or pull down resistors and system logic can use CMOS or Open drain drivers to drive them Datasheet 21 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 3 1 5 3 3 2 3 2 1 3 2 2 22 The Open drain output signals have open drain drivers and external pull up resistors are required One of the two output signals IERR is a catastrophic error indicator and is tri stated and pulled up when the processor is functioning normally The FERR output can be either tri stated or driven to Vss when the processor is in a low power state depending on the condition of the floating point unit Since this signal is a DC current path when it is driven to Vss Intel r
76. l Clocking and to the BCLK rising edge at 1 25 V for Single Ended Clocking All AGTL signals are referenced at Vref Unless other specified all timings apply to both 100 MHz and 133 MHz bus frequencies RESET can be asserted active asynchronously but must be deasserted synchronously Specification is for a minimum 0 40 V swing from Vref 200 mV to Vref 200 mV Specification is for a maximum 0 8 V swing from Vcct 0 8 V to Vcct After Vcc Vect and BCLK BCLK become stable and PWRGOOD is asserted Applies to all processors supporting 133 MHz bus clock frequency except Ultra Low Voltage processors Applies to all processors supporting 100 MHz bus clock frequency and Ultra Low Voltage processors supporting 133 MHz bus clock frequency Table 30 CMOS and Open drain Signal Groups AC Specifications sn r COC E ICI 298517 006 T14 T15 NOTE 1 1 5V Input Pulse Width except PWRGOOD and 2 BCLKs Active and inactive LINT 1 0 states T14B LINT 1 0 Input Pulse Width je eciks 9 Noes PWRGOOD Inactive Pulse Width 2 lus 12 Note 4 5 S All AC timings for CMOS and Open drain signals are referenced to the crossing point of the BCLK rising edge and BCLK falling edge for Differential Clocking and to the rising edge of BCLK at 1 25 V for Single Ended Clocking All CMOS and Open drain signals are referenced at 1 0 V Minimum output pulse width on CMOS outputs is 2 BCLKs This specification only applies when the APIC is ena
77. le registers Datasheet 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet On die second level L2 cache 8 way set associative 32 byte line size 1 line per sector Operates at full core speed 256 Kbyte ECC protected cache data array AGTL system bus interface 64 bit data bus 100 MHz and 133 MHz operation Uniprocessor two loads only processor and chipset Integrated termination Processor clock control Quick Start for low power low exit latency clock throttling Deep Sleep mode for lower power dissipation Thermal diode for measuring processor temperature 1 2 State of the Data All information in this document is the best available information at the time of publication Revisions of this document will be provided on an as required basis until the Mobile Intel Celeron Processor is released for production orders 1 3 Terminology Term TBD 298517 006 Definition A symbol following a signal name indicates that the signal is active low This means that when the signal is asserted based on the name of the signal it is in an electrical low state Otherwise signals are driven in an electrical high state when they are asserted In state machine diagrams a signal name in a condition indicates the condition of that signal being asserted Indicates the condition of that signal not being asserted For example the condition
78. le the signal is in its transition region of 300 mV to 900 mV Also VTTPWRGD should only enter the transition region once after VTT is at nominal values for the assertion of the signal Table 8 VTTPWRGD Noise Specification Parameter Specification Amount of noise glitch Less than 100 mV In addition the VTTPWRGD signal should have reasonable transition time through the transition region A sharp edge on the signal transition will minimize the chance of noise causing a glitch on this signal Intel recommends the following transition time for the VTTPWRGD signal Table 9 VTTPWRGD Transition Time Specification 3 2 4 1 3 2 4 2 24 Parameter Recommendation Transition time 300 mV to 900 mV Less than or equal to 100 us Transition Region The transition region covered by this requirement is 300 mV to 900 mV Once the VTTPWRGD signal is in that voltage range the processor is more sensitive to noise which may be present on the signal The transition region when the signal first crosses the 300 mV voltage level and continues until the last time it is below 900 mV Transition Time The transition time is defined as the time the signal takes to move through the transition region A 100 us transition time will ensure that the processor receives a good transition edge Datasheet 29851 7 006 3 2 4 3 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Nois
79. led during power on configuration a central agent may handle an assertion of AERR as appropriate to the error handling architecture of the system AP 1 0 I O AGTL The AP 1 0 Address Parity signals are driven by the request initiator along with ADS A 35 3 REQ 4 0 and RP AP1 covers A 35 24 APO covers A 23 3 A correct parity signal is high if an even number of covered signals is low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should be connected to the appropriate pins balls on both agents on the system bus Datasheet 29851 7 006 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet BCLK BCLK I The BCLK and BCLK signals determines the system bus frequency On systems with Differential Clocking both system bus agents must receive these signals to drive their outputs and latch their inputs on the BCLK rising edge and BCLK falling edge All external timing parameters are specified with respect to the crossing point of the BCLK rising edge and BCLK falling edge On systems with Single Ended Clocking both system bus agents must receive the BCLK signal to drive their outputs and latch their inputs on the BCLK rising edge All external timing parameters are specified with respect to the BCLK signal The BCLK signal functions as the CLKREF input BERR I O AGTL The BERR
80. ll TAP and CMOS signals not to APIC signals 11 Applies to PICD 1 0 AC Specifications System Bus Clock APIC TAP CMOS and Open drain AC Specifications All system bus AC specifications for the AGTL signal group are relative to the crossing point of the rising edge of the BCLK input and falling edge of the BCLK input All AGTL timings are referenced to Veer for both 0 and 1 logic levels unless otherwise specified All APIC TAP CMOS and Open drain signals except PWRGOOD are referenced to 1 0 V All minimum and maximum specifications are at points within the power supply ranges shown in Table 12 through Table 21 and junction temperatures Datasheet 41 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 42 Tj in the range 0 C to 100 C unless otherwise noted Tj must be less than or equal to 100 C or the otherwise noted given value for all functional processor states Table 25 System Bus Clock AC Specifications Differential E NAN AAN KN KA LI KN KETA NAN System System Bus Frequency Frequency System Bus Frequency 183 Mel P R e par iabe BOLK Pers instantaneous minimum 73 w 6 noe T2 BCLK Cycle to Cycle Jitter 200 ps 8 Motes2 34 BCLK Rise Time 175 467 ps Notes 2 6 8 o CR L BCLK Fall Time 175 467 ps Notes 2 6 8 NA OOOO E AO EI ee Verossfori Vswing for 1 V Veross for 1 V swing os 076 v
81. m bus provides a glue less point to point interface for a memory controller hub This document covers the electrical mechanical and thermal specifications for the following e The Mobile Intel Celeron Processor at the following frequencies and voltages 1 33 GHz at 1 50 V 1 2 GHz 1 13 GHz 1 06 GHz at 1 45 V and 1 266GHz 1 GHz at 1 40 V e The Low Voltage Mobile Intel Celeron Processor at the following frequencies and voltages 866 MHz 733 MHz and 650 MHz at 1 15 V e The Ultra Low Voltage Mobile Intel Celeron Processor at the following frequencies and voltages 800 MHz 733 MHz 700 MHz and 650 MHz at 1 10 V e Unless explicitly stated all references to the Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA packages in this document also apply to the Low Voltage and Ultra Low Voltage Mobile Intel Celeron Processor 0 13 1 in the Micro FCBGA package Overview e Performance features Supports the Intel Architecture with Dynamic Execution Supports the Intel Architecture MMX technology Supports Streaming SIMD Extensions for enhanced video sound and 3D performance Integrated Intel Floating Point Unit compatible with the IEEE 754 standard Data Prefetch Logic e On die primary L1 instruction and data caches 4 way set associative 32 byte line size 1 line per sector 16 Kbyte instruction cache and 16 Kbyte write back data cache Cacheable range controlled by processor programmab
82. mal Design Power typical specification referred to in previous Intel datasheets The Intel TDP specification is a recommended design point and is not representative of the absolute maximum power the processor may dissipate under worst case conditions Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated T is measured with the on die thermal diode Ty at 85 C only applies to 1 33 GHz processor Intel recommends that the notebook thermal management system include full speed fan activation at no higher than 55 C to provide adequate cooling Datasheet 81 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 6 1 Thermal Diode The Mobile Intel Celeron Processor has an on die thermal diode that should be used to monitor the die temperature T A thermal sensor located on the motherboard or a stand alone measurement kit should monitor the die temperature of the processor for thermal management or instrumentation purposes Table 49 and Table 50 provide the diode interface and specifications Note The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the temperature of the hottest location on the die This is due to inaccuracies in the thermal sensor on die temperature gradients between the location of the thermal diode and t
83. mentation details NMI I 1 5 V Tolerant The NMI Non Maskable Interrupt indicates that an external interrupt has been generated NMI becomes the LINTI signal when the APIC is disabled Asserting NMI causes an interrupt with an internally supplied vector value of 2 An external interrupt acknowledge transaction is not generated If NMI is asserted during the execution of an NMI service routine it remains pending and is recognized after the IRET is executed by the NMI service routine At most one assertion of NMI is held pending NMI is rising edge sensitive PICCLK I 2 0 V Tolerant The PICCLK APIC Clock signal is an input clock to the processor and system logic or I O APIC that is required for operation of the processor system logic and I O APIC components on the APIC bus Datasheet 89 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 90 PICD 1 0 I O 1 5 V Tolerant Open drain The PICD 1 0 APIC Data signals are used for bi directional serial message passing on the APIC bus They must be connected to the appropriate pins balls of all APIC bus agents including the processor and the system logic or I O APIC components If the PICDO signal is sampled low on the active to inactive transition of the RESET signal then the APIC is hardware disabled For the Mobile Intel Celeron Processor the APIC is required to be hardware enabled as described in Section 7 1 3 PLL1
84. ng off the processor s power The exit latency of the Deep Sleep state is 30 msec in the Mobile Intel Celeron Processor Performing state transitions not shown in Figure 1 is neither recommended nor supported Figure 2 provides the clock state characteristics which are described in detail in the following sections Normal State The Normal state of the processor is the normal operating mode where the processor s core clock is running and the processor is actively executing instructions Auto Halt State This is a low power mode entered by the processor through the execution of the HLT instruction A transition to the Normal state is made by a halt break event one of the following signals going active NMI INTR BINIT INIT RESET FLUSH or SMI Datasheet 29851 7 006 intel E Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Asserting the STPCLK signal while in the Auto Halt state will cause the processor to transition to the Quick Start state Deasserting STPCLK will cause the processor to return to the Auto Halt state without issuing a new Halt bus cycle The SMI interrupt is recognized in the Auto Halt state The return from the System Management Interrupt SMI handler can be to either the Normal state or the Auto Halt state See the Intel Architecture Software Developer s Manual Volume III System Programmer s Guide for more information No Halt bus cycle is issued when returnin
85. ocessor and the system logic or I O APIC component When APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a non maskable interrupt INTR and NMI are backward compatible with the same signals for the Pentium processor Both signals are asynchronous inputs Both of these signals must be software configured by programming the APIC register space to be used either as NMI INTR or LINT 1 0 in the BIOS If the APIC is enabled at reset then LINT 1 0 is the default configuration LOCK I O AGTL The LOCK Lock signal indicates to the system that a sequence of transactions must occur atomically This signal must be connected to the appropriate pins balls on both agents on the system bus For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction through the end of the last transaction When the priority agent asserts BPRI to arbitrate for bus ownership it waits until it observes LOCK deasserted This enables the processor to retain bus ownership throughout the bus locked operation and guarantee the atomicity of lock NCTRL I Analog The NCTRL signal provides the AGTL pull down impedance control The processor samples this input to determine the N channel pull down device strength when it is the driving agent An external 14 ohm 1 tolerance pull up resistor to Vecr is required for this signal Please refer to platform design guide for imple
86. p R O O a amp z lt PA a a a S 4 m 2 d o O O lt El 5 z 3 13 050 VCCT STPCLK VSS INITH VSS BSELO VSS LINTI VSS VSS BP3 VSS PRDY VSS OO 0 O O O00 90 0 O O O 0 0 0 VCCT VCCT VID3 IERR FLUSH FERR DPSLP VREF BSEL1 TESTHI Era THRMDATHRMDC TRST eae NC PREQ PICCLK VREF BP2 BINIT Oo e O vec VSS CCT Other Note A2 pin is de populated on Micro FCPGA package 29851 7 006 Datasheet 73 Mobile Intel Celeron Processor 0 13 u in Micro FCBGA and Micro FCPGA Packages Datasheet Table 45 Signal Listing in Order by Pin Ball Number E3 Signal Name Ea Signal Name a eee et oe CO CC E AA NAN je CSIC CA CM rec ezz vss lon ws oo o fea or fo fys mo a 525 o oa fve S CI CC forse D jajawi or CCOO CC CI Ino ore vs ate oor os er CC Ive mr oa es wo EZ me pise fer veer Joz fve ao fow fos pe CE raa foe en oor 026 Iv m p foe jen CI Signal Name VCC VSS TESTHI VTTPWRGD VCCT VCCT fro vss os rect jes ves E e ow foe vec Tem 74 Datasheet VCC E22 7 co lt Q O A G23 G24 Signal Name VSS D16 D23 D19 Zz O VCCT D25 298517 006 Mobile Intel Celeron Processor 0 13 u e Micro FCBGA and Micro FCPGA Packages Datasheet Signal Name Signal Name ASH m e vss f 2 vec m resno e 3 298517 006 Datasheet ve VCC V26 75 Mobile Intel Celeron Processor 0 1
87. parity signal and the A 23 3 signals are protected with the APO parity signal On the active to inactive transition of RESET each processor bus agent samples A 35 3 signals to determine its power on configuration See P6 Family of Processors Developer s Manual for details A20M I 1 5V Tolerant If the A20M Address 20 Mask input signal is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of A20M is only supported in Real mode ADS I O AGTL The ADS Address Strobe signal is asserted to indicate the validity of a transaction address on the A 35 3 signals Both bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must be connected to the appropriate pins balls on both agents on the system bus AERR I O AGTL The AERR Address Parity Error signal is observed and driven by both system bus agents and if used must be connected to the appropriate pins balls of both agents on the system bus AERR observation is optionally enabled during power on configuration if enabled a valid assertion of AERR aborts the current transaction If AERR observation is disab
88. previous state If the HALT Grant Snoop state is entered from the Quick Start state then the input signal restrictions of the Quick Start state still apply in the HALT Grant Snoop state except for those signal transitions that are required to perform the snoop Deep Sleep State The Deep Sleep state is a very low power state that the processor can enter while maintaining its context The Deep Sleep state is entered by stopping the BCLK and BCLK inputs to the processor or by asserting the DPSLP signal while it is in the Quick Start state Note that either one of the methods can be used to enter Deep Sleep but not both at the same time When BCLK and BCLK are stopped they must obey the DC levels specified in Table 38 and Table 39 The processor will return to the Quick Start state from the Deep Sleep state when the BCLK and BCLK inputs are restarted or the DPSLP signal is deasserted Due to the PLL lock latency there is a delay of up to 30 usec after the clocks have started before this state transition happens PICCLK may be removed in the Deep Sleep state PICCLK should be designed to turn on when BCLK and BCLK turn on or DPSLP is deasserted when transitioning out of the Deep Sleep state Datasheet 29851 7 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 2 Clock State Characteristics Clock State Exit Latency System Uses Normal Normal program execution Auto Halt S W cont
89. propriate to the Machine Check Architecture MCA of the system BNR I O AGTL The BNR Block Next Request signal is used to assert a bus stall by any bus agent that is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents may need to request a bus stall simultaneously BNR is a wired OR signal that must be connected to the appropriate pins balls of both agents on the system bus In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges Datasheet 85 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 86 BP 3 2 I O AGTL The BP 3 2 Breakpoint signals are the System Support group Breakpoint signals They are outputs from the processor that indicate the status of breakpoints BPM 1 0 I O AGTL The BPM 1 0 Breakpoint Monitor signals are breakpoint and performance monitor signals They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance BPRI I AGTL The BPRI Bus Priority Request signal is used to arbitrate for ownership of the system bus It must be connected to the appropriate pins balls on both agents on the system bus Observing BPRI active as asserted by
90. put A10 AGTL 1 0 BREQO AGTL 1 0 A11 AGTL I O AE12 BSELO 3 3 V CMOS Output A12 AGTL 1 0 AF10 BSEL1 3 3 V CMOS Output A13 AGTL I O ADS CMOSREF CMOS Reference Voltage A14 AGTL I O AF12 CMOSREF CMOS Reference Voltage A15 AGTL 1 0 Do AGTL I O A16 AGTL 1 0 D1 AGTL I O 5 A17 AGTL I O D2 AGTL 1 0 B11 A18 AGTL I O 23 D3 AGTL W O 6 A19 AGTL I O D4 AGTL 1 0 A20 AGTL I O 20 D5 AGTL I O A21 AGTL I O D6 AGTL 1 0 A22 AGTL I O 20 D7 AGTL I O A23 AGTL I O 22 ps AGTL I O A10 A24 AGTL I O D9 AGTL 1 0 A25 AGTL I O A23 D10 AGTL I O A13 A26 AGTL I O A24 D11 AGTL I O A27 AGTL I O D12 AGTL I O 3 A28 AGTL 1 0 D24 D13 AGTL I O c12 TA298 AGTL 1 0 24 D14 AGTL I O c10 A30 AGTL 1 0 D15 AGTL I O 6 A31 AGTL 1 0 E23 D16 AGTL I O A15 A32 AGTL 1 0 B21 D17 AGTL I O A14 A33 AGTL 1 0 B23 D18 AGTL I O B13 A34 AGTL 1 0 E26 D19 AGTL I O A12 A35 AGTL I O c24 D20 AGTL I O AC3 A20M 1 5V CMOS Input F24 D21 AGTL I O AA3 ADS AGTL I O D25 D22 AGTL I O w2 AERR AGTL I O E24 p23 AGTL I O AB3 APO AGTL I O B25 D24 AGTL I O P3 AP1 AGTL I O G24 p25 AGTL I O Act BCLK Clock Input H24 D26 AGTL I O AD1 BCLK CLKREF Clock Input F26 D27 AGTL I O BERR AGTL 1 0 L24 D28 AGTL I O 298517 006 Datasheet 77 Mobile Intel Celeron Processor 0 13 u in intel a Micro FCBGA and Micro FCPGA Packages Datasheet 78 No Signal Name Signal Buffer Type No Signal Name Signal
91. r IGNNE has no affect when the NE bit in control register 0 CRO is set INIT I 1 5 V Tolerant The INIT Initialization signal is asserted to reset integer registers inside the processor without affecting the internal L1 or L2 caches or the floating point registers The processor begins execution at the power on reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous input If INIT is sampled active on RESET s active to inactive transition then the processor executes its built in self test BIST Datasheet 29851 7 006 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet INTR I 1 5 V Tolerant The INTR Interrupt signal indicates that an external interrupt has been generated INTR becomes the LINTO signal when the APIC is enabled The interrupt is maskable using the IF bit in the EFLAGS register If the IF bit is set the processor vectors to the interrupt handler after completing the current instruction execution Upon recognizing the interrupt request the processor issues a single Interrupt Acknowledge INTA bus transaction INTR must remain active until the INTA bus transaction to guarantee its recognition LINT 1 0 I 1 5 V Tolerant The LINT 1 0 Local APIC Interrupt signals must be connected to the appropriate pins balls of all APIC bus agents including the pr
92. re 31 Pin Ball Map Top View sa eee eee ee eee eee 73 Figure 32 PLL Filter Specifications aaa 97 298517 006 Datasheet 5 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Tables Table 1 New and Revised Mobile Intel Celeron Processor 0 13 U SIgnals sse cee 14 Table 2 Clock State Characteristics eee 17 Table 3 Mobile Intel Celeron Processor CWUID aaa eaaa aa anae naen a nana a naa aana a neran anae 18 Table 4 Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors 18 Table 5 System Signal Group aana eny AKA r oo aa a KANA Aan O AA ANANA KAKA KANAN D KANAAN aa KA A KA 19 Table 6 Recommended Resistors for Mobile Intel Celeron Processor Signals 20 Table 7 Mobile Intel Celeron Processor VID Values eee eee 23 Table 8 VTTPWRGD Noise Specification eee eee eee 24 Table 9 VTTPWRGD Transition Time Specification see eee eee eee ee 24 Table 10 Mobile Intel Celeron Processor Absolute Maximum Ratings sese eee eee 26 Table 11 Power Specifications for Mobile Intel Celeron PrOCESSOM aaa aaa aee aee aaa eaaa 27 Table 12 Vcc Tolerances for the Low Voltage Mobile Intel Celeron Processor E Ban aa ei al aa an aa a aceite lon ag aan 28 Table 13 Vcc Tolerances for the Low Voltage Mobile Intel Celeron Processor in the Deep Sleep State VID HVS si Aa 29 Table 14 Vcc Tolerances for the Ultra Low Volta
93. rformance and low power consumption The Mobile Intel Celeron Processor 0 131 in Micro FCBGA and Micro FCPGA packages hereafter referred to as the Mobile Intel Celeron Processor is based on the same core as existing mobile Intel Pentium II Processor M Key performance features include Internet Streaming SIMD instructions an Advanced Transfer Cache architecture and a processor system bus speed of 133 MHz The Low Voltage and Ultra Low Voltage Mobile Intel Celeron Processors will support both a 133 MHz and 100 MHz bus speed These features are offered in Micro FCPGA packages for socketable boards and Micro FCBGA packages for surface mount boards The Low Voltage and Ultra Low Voltage Mobile processors will be available only in the Micro FCBGA package The Mobile Intel Celeron processors at 1 45 V and at 1 50 V are available only in the Micro FCPGA package All of these technologies make outstanding performance possible for mobile PCs in a variety of shapes and sizes The 256 KB integrated L2 cache based on the Advanced Transfer Cache architecture runs at full speed and is designed to help improve performance It complements the system bus by providing critical data faster and reducing total system power consumption The processor also features Data Prefetch Logic that speculatively fetches data to the L2 cache resulting in improved performance The Mobile Intel Celeron Processor s 64 bit wide Assisted Gunning Transceiver Logic AGTL syste
94. rocessor receives a good transition edge Noise The signal quality of the VTTPWRGD signal is critical to the correct operation of the processor Every effort should be made to ensure this signal is monotonic in the transition region If noise or glitches are present on this signal the noise or glitches must be kept to less than 100 mV of a voltage drop from the highest voltage level received to that point This glitch must remain less than 100 mV until the excursion ends by the voltage returning to the highest voltage previously received Please see Figure 24 for an example graph of this situation and requirements Datasheet 63 Mobile Intel Celeron Processor 0 13 u in l ntel o Micro FCBGA and Micro FCPGA Packages Datasheet Figure 24 VTTPWRGD Noise Specification Highest voltage Excursion end 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 Micro Seconds 64 Datasheet 298517 006 Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Mechanical Specifications 5 1 Table 43 Socketable Micro FCPGA Package The Mobile Intel Celeron Processor is packaged in a 478 pin Micro FCPGA package The Low Voltage and Ultra Low Voltage processors will not be available in this package The mechanical specifications for the socketable package are provided in Table 43 Figure 25 through Figure 27 illustrate different views of the package
95. rolled entry idle mode Quick Start Through snoop to HAL T Grani Snoop state H W controlled entry exit mobile throttling immediate Through STPCLK to Normal state 10 usec Yes Yes Yes es HALT Grant A few bus clocks after Y Supports snooping in the low power states Snoop snoop completion Deep Sleep 30 usec H W controlled entry exit mobile powered on suspend support 2 2 7 Operating System Implications of Low power States The time stamp counter and the performance monitor counters are not guaranteed to count in the Quick Start state The local APIC timer and performance monitor counter interrupts should be disabled before entering the Deep Sleep state or the resulting behavior will be unpredictable 2 3 AGTL Signals The Mobile Intel Celeron Processor system bus signals use a variation of the low voltage swing GTL signaling technology The AGTL system bus depends on incident wave switching and uses flight time for timing calculations of the AGTL signals as opposed to capacitive derating Intel recommends analog signal simulation of the system bus including trace lengths Contact your field sales representative to receive the IBIS models for the Mobile Intel Celeron Processor The AGTL system bus of the Mobile Intel Celeron Processor is designed to support high speed data transfers with multiple loads on a long bus that behaves like a transmission line However in mobile systems the system bus only has two loads the processor an
96. rom VCC nominal 12 to PWRGOOD 13 La is the VID low a setting oe i ia S O AR TAL pea Fan Time tom vocr VITPWRGD Iw lo rs ja REE vato ater VTTPWRGD iow H rs T20C All inputs required valid after VTTPWRGD low T20D VID BSEL signals valid after VITPWRGD fo deo he low T20E VTTPWRGD Transition Time Measurement from 300 mV to 900 mV Amount of noise glitch less than 100 mV See Section 4 3 1 for details NOTE Atleast 1 ms must pass after PWRGOOD rises above V H18min and BCLK BCLK meet their AC timing specification until RESET may be deasserted ns ta 46 Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Table 32 APIC Bus Signal AC Specifications 298517 006 Symbol Parameter Min Max Unit Figure Notes T21 PICCLK Frequency 2 33 3 MHz Note 2 T22 PICCLK Period 30 500 ns 6 T23 PICCLK High Time 10 5 ns 6 at gt 1 6 V T24 PICCLK Low Time 10 5 ns 6 at lt 0 4 V T25 PICCLK Rise Time 0 25 3 0 ns 6 0 4 V 1 6 V T26 PICCLK Fall Time 0 25 3 0 ns 6 1 6 V 0 4 V T27 PICD 1 0 Setup Time 8 0 ns 9 Note 3 T28 PICD 1 0 Hold Time 2 5 ns 9 Note 3 T29 PICD 1 0 Valid Delay Rising 1 5 8 7 ns 8 Notes 3 4 Edge Lo Valid Delay Falling 15 12 0 NOTES 1 2 3 4 All AC timings for APIC signals are referenced to the PICCLK rising edge at 1 0 V All CMOS signals are re
97. s At the completion of a flush operation the processor issues a Flush Acknowledge transaction The processor stops caching any new data while the FLUSH signal remains asserted On the active to inactive transition of RESET each processor bus agent samples FLUSH to determine its power on configuration HIT I O AGTL HITM I O AGTL The HIT Snoop Hit and HITM Hit Modified signals convey transaction snoop operation results and must be connected to the appropriate pins balls on both agents on the system bus Either bus agent can assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR O 1 5 V Tolerant Open drain The IERR Internal Error signal is asserted by the processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the system bus This transaction may optionally be converted to an external error signal e g NMI by system logic The processor will keep IERR asserted until it is handled in software or with the assertion of RESET BINIT or INIT IGNNE I 1 5 V Tolerant The IGNNE Ignore Numeric Error signal is asserted to force the processor to ignore a numeric error and continue to execute non control floating point instructions If IGNNE is deasserted the processor freezes on a non control floating point instruction if a previous instruction caused an erro
98. s Cycle Completion to Clock Shut Off Delay Tw 146 Setup Time to Input Signal Hold Requirement Tx T47 Deep Sleep PLL Lock Latency Ty T48 PLL lock to STPCLK Hold Time Tz T49 Input Signal Hold Time 56 Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet Figure 21 Quick Start Deep Sleep Timing DPSLP Assertion Method Normal Quick Start Deep Sleep Quick Start Normal SNG NF NSS STPCLK DPSLP Compatibility 7 Frozen Signals 7 V00103 00 Ty T45 Stop Grant Acknowledge Bus Cycle Completion to DPSLP assertion Tw 146 Setup Time to Input Signal Hold Requirement Tx T47 Deep Sleep PLL Lock Latency Ty T48 PLL lock to STPCLK Hold Time Tz T49 Input Signal Hold Time 298517 006 Datasheet 57 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 4 System Signal Simulations 4 1 Systems must be simulated using IBIS models to determine if they are compliant with this specification All references to BCLK signal quality also apply to BCLK for Differential Clocking System Bus Clock BCLK and PICCLK DC Specifications and AC Signal Quality Specifications Table 35 BCLK Differential DC Specifications and AC Signal Quality Specifications omo room Jm me Imel ae BCLK Voltage in Deep Sleep Statel0 4 145 v Notes Gass DPSLP BCLK Voltage i In Deep Sleep C DP
99. shoot Undershoot voltage exceed 2 38 V 3 Activity factor of 1 represents a toggle rate of 33 MHz 4 System designers are encouraged to follow Intel provided non AGTL layout guidelines 5 All values are specified by design characterization and are not tested 6 Tj 85 C for 1 33 GHz PWRGOOD VTTPWRGD Signal Quality Specifications The processor requires PWRGOOD to be a clean indication that clocks and the power supplies Vcc Vcecr etc are stable and within their specifications Clean implies that the signal will remain below Vitig and without errors from the time that the power supplies are turned on until they come within specification The signal will then transition monotonically to a high 1 8 V state The VTTPWRGD signal must also transition monotonically The VITPWRGBD signal is an input to the processor used to determine that the VTT power is stable and the VID and BSEL signals should be driven to their final state by the processor To ensure the processor correctly reads this signal the processor must meet the requirement shown in Table 41 while the signal is in its transition region of 300 mV to 900 mV Also VTTPWRGD should only enter the transition region once after VTT is at nominal values for the assertion of the signal VTTPWRGD Noise Parameter Specification Table 41 VITPWRGD Noise Parameter Specification 62 Parameter Specification Amount of noise glitch Less than 100 mV In addition
100. tes at which speed a processor will run APIC Enable The processor APIC must be hardware enabled by pulling the PICD 1 0 signals separately up to 1 5 V and supplying an active PICCLK to the processor Software can be used to disable the APIC if it is not being used after PICD 1 0 are sampled high when RESET is deasserted and the processor has started executing instructions Clock Frequencies and Ratios The Mobile Intel Celeron Processor uses a clock design in which the bus clock is multiplied by a ratio to produce the processor s internal or core clock The ratio used is programmed into the processor during manufacturing The bus ratio programmed into the processor is visible in bit positions 22 to 25 and 27 of the Power on Configuration register Table 28 shows the 5 bit codes in the Power on Configuration register and their corresponding bus ratios Datasheet 83 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet 8 Processor Interface 8 1 84 Alphabetical Signal Reference A 35 3 I O AGTL The A 35 3 Address signals define a 2 byte physical memory address space When ADS is active these signals transmit the address of a transaction when ADS is inactive these signals transmit transaction information These signals must be connected to the appropriate pins balls of both agents on the system bus The A 35 24 signals are protected with the AP1
101. the Intel 830 Chipset family The Thevenin equivalent impedance of the VCMOSREF generation circuits must be less than 0 75 KQ 0 5 KQ i e top resistor 750 Q bottom resistor 500 Q for the Intel 440MX chipset family D 63 0 I O AGTL The D 63 0 Data signals are the data signals These signals provide a 64 bit data path between both system bus agents and must be connected to the appropriate pins balls on both agents The data driver asserts DRDY to indicate a valid data transfer DBSY I O AGTL The DBSY Data Bus Busy signal is asserted by the agent responsible for driving data on the system bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must be connected to the appropriate pins balls on both agents on the system bus DEFER I AGTL The DEFER Defer signal is asserted by an agent to indicate that the transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory agent or I O agent This signal must be connected to the appropriate pins balls on both agents on the system bus DEP 7 0 I O AGTL The DEP 7 0 Data Bus ECC Protection signals provide optional ECC protection for the data bus They are driven by the agent responsible for driving D 63 0 and must be connected to the appropriate pins balls on both agents on the system bus if they are used During power on configuration DEP 7
102. um damping resistance is calculated from 0 35 Q DCRmin From vendor provided data L1 and L2 DCRmin is 0 4Q and 0 502 respectively qualifying them for zero required trace resistance DCRin for L3 is not known and is assumed to be 0 15Q Products with equivalent specifications may also be used Table 57 PLL Filter Capacitor Recommendations 298517 006 Datasheet 97 Mobile Intel Celeron Processor 0 13 u in l ntel a Micro FCBGA and Micro FCPGA Packages Datasheet Table 58 PLL Filter Resistor Recommendations A4 98 Rs H jian HIE To satisfy damping requirements total series resistance in the filter from Vecr to the top plate of the capacitor must be at least 0 35 Q This resistor can be in the form of a discrete component or routing or both For example if the picked inductor has minimum DCR of 0 25 2 then a routing resistance of at least 0 10 Q is required Be careful not to exceed the maximum resistance rule 2 Q For example if using discrete R1 the maximum DCR of the L should be less than 2 0 1 1 0 9 Q which precludes using L2 and possibly L1 Other routing requirements include e The capacitor should be close to the PLL1 and PLL2 pins with less than 0 1 Q per route These routes do not count towards the minimum damping resistance requirement e The PLL2 route should be parallel and next to the PLL1 route minimize loop area e The inductor should be close to the capacitor any routing resistance
103. ze the properties of any specific existing system design A detailed description of the simulated notebook configuration is available upon request Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Mobile Intel Celeron Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation www intel com or call 1 800 548 4725 Intel Celeron Pentium and MMX are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright O Intel Corporation 2000 2002 2 Datasheet 298517 006 intel Mobile Intel Celeron Processor 0 13 u Micro FCBGA and Micro FCPGA Packages Datasheet

Intel Celeron Mobile 1.50 GHz

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