Dataram DTM64330A memory module
Contents
1. Gye DTM64330A as Blue fed A Optimizing Value and Performance Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5V 0 075 I O Type SSTL_15 On board temperature sensor with integrated Serial Presence Detect SPD EEPROM Data Transfer Rate 8 5 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 and 8 Bi directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 15 10 3 Fully ROHS Compliant Pin Configuration 8GB 240 Pin 4Rx8 Registered ECC DDR3 DIMM Identification DTM64330A 1Gx72 8GB 4Rx8 PC3 8500R 7 10 HO Performance range Clock Module Speed CL trco 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64330A is a registered 1Gx72 memory module which conforms to JEDEC s DDR3 PC3 8500 standard The assembly is Quad Rank Each Rank is comprised of nine 256Mx8 DDR3 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monit2. 240 Pin 4Rx8 Registered ECC DDR3 DIMM 144 Module Part Number O oo 145 Module Part Number 146147 Module Revision Code Document 06588 Revision 15 May 10 Dataram Corporation 2010 Page 11 Tweet DTM64330A SGB 240 pin 4Rx8 Registered ECC DDR3 DIMM TNIDATARAM MA A Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06588 Revision A 15 May 10 Dataram Corporation 2010 Page 12
3. 1 Vrer 0 1 Vpop V Logical Low Logic 0 Vss Vrer 0 1 V AC Input Logic Levels Single Ended O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH AC Vrer 0 175 V Logical Low Logic 0 ViL AC Vrer 0 175 V VEL CI r UI H m Document 06588 Revision A 15 May 10 Dataram Corporation 2010 Page 4 EygDATARAM Optimizing Value and Performance DTM64330A 8GB 240 Pin 4Rx8 Registered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High ViH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low ViL DIFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative VDD 2 Vix 0190 0150 M Capacitance T4 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO Cck 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control S 3 0 CKE 1 0 ODT 1 0 1 5 2 5 pF DQ 63 0 CB 7 0 DQS 8 0 DQS 8 0 Input Output Capacitance DM 8 0 TDQS 17 9 Cio 6 10 pF DC Characteristics 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol
4. Bank Addresses 14 Vos 44 Vss 74 ICAS 104Vss 134 DM1 164 CB6 194 Voo 224 DQ54 ODT 1 0 On Die Termination Inputs 15 DQS1 45 CB2 75 Vp 105 DQ50 135 TDQS10 165 CB7 195 ODTO 225 DQ55 SA 2 0 SPD Address 16 DQS1 46 CB3 76 51 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss SCL SPD Clock Input 17 Vss 47 Vss 77 1 107Vss 137 0014 167 NC TEST 197 Vo 227 0060 SDA SPD Data Input Output 18 DQ10 48 Vr 78 Von 108 DQ56 380015 168 RESET 198 S3 228 DQ61 Vss Ground 19 DQ11 M49 79 S2 109 DQ57 139 Vss 169 CKE1 199 Vss 229 Vss Voo Power 20 Vss 50 CKEO 80 Vss 110Vss 4oDa20 170Voo 200 DQ36 230 DM7 Vonsro SPD EEPROM Power 21 DQ16 51 81 DQ32 111 DQs7 141DQ21 171A15 201 DQ37 231 TDQS16 Reference Voltage for DQ 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172 A14 202 Vss 232 Vss VREFCA Reference Voltage for CA 23 Vss 53 Err_Our 83 Vss 113Vss 143 DM2 173 Voo 203 DM4 033 DQ62 Var Termination Voltage 24 DQS2 54 84 DQS4 114 DQ58 144 TDQS11474 A12 BC 204 TDQS13 234 DQ63 Event Temperature Sensing 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 A9 205 Vss 235 Vss NC No Connection 26 Vss 56 A7 86 Vss 116Vss 1460022 176Voo 206 DQ38 236 27 DQ18 57 87 DQ34 117SA0 147 0023 177A8 207 DQ39 237 SA1 28 DQ19 58 A5 88 DQ35 118SCL 148 Vos 178 A6 208 Vss 238 SDA 29 Vss 59 A4 89 Vss 119SA2 149DQ28 179 Vp 209 DQ44 239 Vss 30 DQ24 60 Vp 90 DQ40 120v 1500029 180A3 210 DQ45 240 Va Not used Document 06588 Revi
5. Minimum Maximum Unit Note Input Leakage Current li 18 18 pA 1 2 Any input 0 V VIN VDD Output Leakage Current lo 10 10 pA 2 3 OV VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled AEREA CC KNIT SP O AAA A E Document 06588 Revision A 15 May 10 Dataram Corporation O 2010 Page 5 DTM64330A 8GB 240 Pin 4Rx8 Registered ECC DDR3 DIMM lbo Specifications and Conditions 0 to 70 C Voltage referenced to Vss 0 V i Max PARAMETER Symbol Test Condition Value Unit Operating One Bank Active IppO Operating current One bank ACTIVATE to PRECHARGE 999 mA Precharge Current Operating One 3 Bank Active Read loo1 One bank ACTIVATE to READ to 1089 mA Precharge Current Precharge Power Down Current Ipp2P Precharge power down current Slow exit 432 mA Precharge Power Down Current Ipp2P Precharge power down current Fast exit 1080 mA Precharge Standby Current Ipp2N Precharge standby current 1620 mA Active Power Down Ipp3P Active power down current 1260 mA Active Standby m Current Ipp3N Active standby current 1980 mA Operating Burst Write Current Ipp4W Burst write operating current 1629 mA Operating Burst E Read Currant Ipp4R Burst read operating current 1584 mA Burst Refresh m Current Ipp5B Refresh current 7560 mA Self Refresh M
6. pem Current Ipp6 Self refresh temperature current MAX Tc 85 C 432 mA Operating Bank Interleave Read Ipp7 All bank interleaved read current 2214 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation Document 06588 Revision A 15 May 10 Dataram Corporation 2010 Page 6 DTM64330A 8GB 240 Pin 4Rx8 Registered ECC DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay teco 4 Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 875 2 500 ns Clock Low Level Width avg 0 47 0 53 Data Input Hold Time after DQS Strobe 100 ps DQ Input Pulse Width toipw 490 ps DQS Output Access Time from Clock tpasck 300 300 ps Write DQS High Level Width 0 45 0 55 tck avg Write DQS Low Level Width toast 0 45 0 55 tck avo DQS Out Edge to Data Out Edge Skew toasa 150 ps Data Input Setup Time Before DQS Strobe tos 25 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tek avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Address and Command Hold Time after Clock tin 200 ps Address and Command Setup Time before Clock tis 125 ps Load Mode Command Cycle Time 4 DQ to DQS Hold 0 38
7. I SDRAMs EVENT TEMPERATURE MONITOR SERIAL PD SCL SDA SAO SA1 SA2 Document 06588 Revision A 15 May 10 Dataram Corporation 2010 Page 3 DTM64330A 8GB 240 Pin 4Rx8 Registered ECC DDR3 DIMM IN2DATARAM Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsroRAGE 55 100 C Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TcasE 0 95 C Voltage on Vpp relative to Vss 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage 1 425 1 5 1 575 V Reference Voltage VREFDQ 0 49 Vpp 0 50 Vpp 0 51 Vpp V 1 1 O Reference Voltage VREFCA 0 49 Vpp 0 50 Vpp 0 51 V 1 Notes 1 The value of Vrer is expected to equal one half Voo and to track variations in the Voo DC level Peak to peak noise on Veer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic
8. O 1 0 7 0 DQR 47 40 DQSR20 DQSR6 O IDQSR2 IDQSR6 DMR2O DMR6O TDQSR110 TDQSR15O DQR 23 16 DQR 55 48 DQSR3O DQSR7 O DQSR3 O DQSR7 O DMR3O DMR7 O TDQSR120 TDQSR16O0 DQR 31 24 DQSR8O DQR 56 63 O DQSR8 O DMR8O TDQSR17O CBR 7 0 All 15 OHMS O O CB Z0 O O DQ 63 0 DQR 63 0 CBR 7 0 005 8 0 O O 1005 8 0 O O OM O Oo M O DQSR 8 0 DQSR 8 0 DM 8 0 DMR 8 0 TDQS 17 9 TDQSR 17 9 GLOBAL SDRAM CONNECTS All 22 OHMS BA 2 0 R A 15 0 R RASR ICASR IWER All 22 OHMS CKE 1 0 R ODT 1 0 R a VTT RS 1 0 TO SDRAMS All 22 OHMS 19 3 0 VWW H RS 3 0 LCLK S LCLK 3 BA 2 0 WA BA 2 0 R A 15 0 WWw A 15 0 R IRAS AN E RASR CAS AN CASR CKEO VW CKEOR RANK 0 amp 2 CKE1 AWY 25 CKE1R RANK 1 amp 3 wv ODTOR RANKO ODT1 c ODT1R RANK 2 PAR IN WA ERR_OUT E L R CLK 3 0 120 2 OHMS I L R CLK 3 0 RESET SDRAMS All 240 OHMS Vss VDD VDD All 39 OHMS 10 0 nF RCLK 3 0 t RCLK 3 0 All39 OHMS 100 nF oo 0 DECOUPLING VDDSPD 4 Serial PD VDD All Devices VREF DQ All SDRAMs Vss All Devices VREF CA All SDRAMs VTT 32 A
9. ck avg Active to Precharge Time tras 37 5 9 tnEri ns Active to Active Auto Refresh Time tre 50 625 ns RAS to CAS Delay terco 13 125 ns Average Periodic Refresh Interval 0 lt Tcase lt 85 C treri 7 8 us Average Periodic Refresh Interval 85 lt Tcase lt 95 3 9 us Auto Refresh Row Cycle Time trec 160 ns Row Precharge Time tre 13 125 ns Read DQS Preamble Time tRPRE 0 9 Note1 tck avg Read DQS Postamble Time tRPsT 0 3 Note2 tck avg Row Active to Row Active Delay Max 4nCK 7 5ns ns Internal Read to Precharge Command Delay trtp Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twPsT 0 3 tck avg Write Recovery Time 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06588 Revision A 15 May 10 Dataram Corporation 2010 Page 7 Ey DTM64330A WWW SGB 240 Pin 4Rx8 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 Key Byte DRAM Device Type DDR3 0x0B SDRAM Key Byte Module Type 0x01 Bit 3 Bit 0 Module Type RDIMM Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks 0x03 Bit 3 Bit 0 Tota
10. e Nominal Height Bit 4 Bit 0 Module Nominal Height max in mm 30 lt h lt 31 Bit 7 Bits Reserved 0 Module Maximum Thickness Bit 3 Bit 0 Front in mm baseline thickness 1 mm 2 lt th lt 3 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 2 lt th lt 3 Reference Raw Card Used Bit 4 Bit O Reference Raw Card Bit 6 Bit 5 Reference Raw Card Revision Bit 7 Reserved O N O Co DIMM Module Attributes Bit 1 Bit O of Registers used on RDIMM Bit 3 Bit 2 of Rows of DRAMs on RDIMM Bit 7 Bit 1 Reserved 64 Module Specific Section 0x00 0x22 0x07 0x09 NE ES E 65 Moiule Specifo Seation 68 ModieSpeicSedon TC 67 Module Speciic Section o 0x00 70 MekeSpedicSedon 7 Module Specife Seaton OB 0x00 0x00 17 Module Manufacturer ID Code Least Significant Byte ow 118 Module Manufacturer ID Code Most Significant Byte 0x00 120421 Module Manufacturing Date __ foz 122425 Module Serial Number 9 128 137 Module Part Number 182 Module Part Number 0x54 186 Module Part Number O O R 02 0x4D 189 Module Part Number O 140 Module Part Number O O o 034 Document 06588 Revision A 15 May 10 Dataram Corporation 2010 Page 10 Ey DTM64330A EE
11. l SDRAM capacity in megabits 2Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved SDRAM Addressing 0x19 Bit 2 Bit 0 Column Address Bits Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved UNUSED Module Organization Bit 2 Bit 0 SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved Module Memory Bus Width 0x0B Bit 2 Bit O Primary bus width in bits Bit 4 Bit 3 Bus width extension in bits Bit 7 Bit 5 Reserved Fine Timebase FTB Dividend Divisor 0x52 Bit 3 Bit O Fine Timebase FTB Divisor Bit 7 Bit 4 Fine Timebase FTB Dividend 5 Medium Timebase MTB Dividend 0 125ns Medium Timebase MTB Divisor 0x08 0 125ns SDRAM Minimum Cycle Time tCKmin 1 875ns OxOF UNUSED 14 CAS Latencies Supported Least Significant Byte 0x1C Bit 0 CL 4 Bit 1 5 Bit 2 CL 6 X Bit 3 CL 7 X Bit 4 8 X Document 06588 Revision A 15 May 10 Dataram Corporation 2010 Page 8 DTM64330A WWW SGB 240 Pin 4Rx8 Registered ECC DDR3 DIMM Bit 5 CL 9 Bit 6 CL 10 Bit 7 CL 11 CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved Minimum CAS Latency Time tAAmin 13 125ns Minimum Write Recove
12. ors the DIMM module and can prevent exceeding the maximum operating temperature of 95C A Heat Spreader is attached to improve the thermal characteristics of the module Pin Description Front Side Back Side Name Function 1 31 DQ25 61 A2 91 DQ41 121 Vss 151 Vss 181A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32 Vss 62 Voo 92 Vs 122 4 152 DM3 182 Voo 212 DM5 DQ 63 0 Data Bits DQO 33 DQS3 63 DQss 123 005 153 TDQS12 183 Vo 213 TDQS14 DAS 8 0 DQS 8 0 Differential Data Strobes 4 34 DQs3 64 CK1 94 DQS5 124 Vss 154 Vss 184 CKO 214 Vss DM 8 0 Data Mask 5 35 Vss 65 Voo 95 Vss 125 DMO 155 DQ30 185 CKO 215 DQ46 TDQS 17 9 Termination Data Strobes 6 DQS0 36 DQ26 66 Vp 96 pQ42 i26 TDQS9 156 0031 186 Vop 216 DQ47 CK 1 0 CK 1 0 Differential Clock Inputs 37 DQ27 67 Vrerca DQ43 127 Vss 157 Vss 187 Event 217 Vss CKE 1 0 Clock Enables 8 Vss 38 Vss 68 ly 98 Vss 128 Da6 158 CB4 188 A0 218 DQ52 CAS Column Address Strobe 9 DQ2 39 69 VDD 99 DQ48 129 DAZ 159 CB5 189 Voo 219 DQ53 RAS Row Address Strobe 10 CBI 70 A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss IS 3 0 Chip Selects 11 Vos 41 Vss 71 BAO 101Vss i131DQ12 161DM8 191 Vp 221 DM6 Write Enable 12 H2 DQS8 72 102 DQse 132DQ13 162 700517 192 RAS 222 TDQS15 A 15 0 Address Inputs 13 DQ9 43 Dass 73 103 base 133 Vss 163 Vss 193 S0 223 Vss BA 2 0
13. ry Time tWRmin Minimum RAS to CASA Delay Time tRCDmin 13 125ns Minimum Row Active to Row Active Delay Time tRRDmin Minimum Row Precharge Delay Time tRPmin 13 125ns 2 Upper Nibbles for tRAS and tRC 0x11 Bit 3 Bit 0 tRAS Most Significant Nibble 1 Bit 7 Bit 4 tRC Most Significant Nibble 1 Minimum Active to Precharge Delay Time tRASmin Least 37 5ns 0x2C Significant Byte Minimum Active to Active Refresh Delay Time tRCmin Least Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Most Significant Byte tWTRmin tRTPmin 8 2 Upper Nibble for tFAW Bit 3 Bit 0 tFAW Most Significant Nibble Bit 7 Bit 4 Reserved 29 Minimum Four Activate Window Delay Time tFAWmin Least Significant Byte 30 SDRAM Optional Features Bit 0 RZQ 6 Bit 1 RZQ 7 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support 31 SDRAM Drivers Supported 0x05 Extended Temperature Range X Extended Temperature Refresh Rate with standard 1X refresh rate Auto Self Refresh ASR X On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Document 06588 Revision A 15 May 10 Dataram Corporation 2010 Page 9 rE DTM64330A WWW SGB 240 Pin 4Rx8 Registered ECC DDR3 DIMM Reserved x Renee A 35 56 UNUSED Modul
14. sion A 15 May 10 Dataram Corporation 2010 Page 1 Pct DTM64330A EE 240 Pin 4Rx8 Registered ECC DDR3 DIMM Front view 133 35 5 250 E L 9 50 0 374 30 00 21 1 181 L1 17 30 Q 0 681 O 5 175 47 00 71 00 0 204 1 850 2 795 123 00 4 843 Back view Side view 7 493 Max 0 295 Max w heatspreader 4 00 Min 0 157 Min DAMAAAANAAAAA AMARA AAA NNNMNN EBD i 1 27 10 4 ic 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches IPC C a G G M A 2 Page 2 Document 06588 Revision A 15 May 10 Dataram Corporation 2010 DTM64330A Optimizing Value and Performance 8GB 240 Pin 4Rx8 Registered ECC DDR3 DIMM IRS3 IRS2O mS m o 7 1 De n DasR4 DQSRO DQSR4 TDQSRYO TDQSR13O DOA 900 ZO GU GQ a a a E E Bn RANK 1 RANK 2 DQR 7 0 O V O 7 0 RANK 0 DQR 39 32 OJ o 7 0 RANK 0 DQSR1 DQSR5 DMR1O E DMR5O O O TDQSR10 le TDQSR14 DQR 15 8
Download Pdf Manuals
Related Search