Dataram DTM63393B memory module
Contents
1. PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 400 400 ps CAS io CAS Command Delay tceco 2 tck Clock High Level Width tou 0 45 0 55 tck Clock Cycle Time tck 2 5 ps Clock Low Level Width teL 0 45 0 55 tck Data Input Hold Time after DQS Strobe toH 125 ps DQ Input Pulse Width toipw 0 35 tck DQS Output Access Time from Clock toasck 350 350 ps Write DQS High Level Width toasH 0 35 tox Write DQS Low Level Width toas 0 35 tck DQS Out Edge to Data Out Edge Skew toasa 200 ps Data Input Setup Time Before DQS Strobe tos 50 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck DQS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tup minimum of tcy or teL ns Address and Command Hold Time after Clock tin 250 ps Address and Command Setup Time before Clock tis 175 ps Load Mode Command Cycle Time tmRD 2 tck DQ to DQS Hold Lon thp tans Data Hold Skew Factor tans 300 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 57 25 ns RAS to CAS Delay trep 12 5 ns Average Periodic Refresh Interval tREFI 7 8 US Auto Refresh Row Cycle Time force 105 ns Row Precharge Time trp 12 5 ns Read DQS Preamble Time RPRE 0 9 1 1 tck Read DQS Postamble Time trest 0 4 0 6 tck Row Active to Row Active Delay trrp 7 5 ns Internal Read to Precharge Command Delay trtp 7 5 ns Write DQS Preamble Setup Time twP2. PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Ve Vrer 0 125 Voo 0 300 V Logical Low Logic 0 Vioc 0 300 Vrer 0 125 V AC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 250 V Logical Low Logic 0 Viac Vreer 0 250 V D a a eS eet Document 06511 Revision A 04 Mar 09 Dataram Corporation 2009 Page 4 DTM63393B DATARAM 1GB 240 Pin Unbuffered ECC DDR2 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note DC Input Signal Voltage Vinc 0 300 Vop 0 300 V 1 DC Differential Input Voltage Vipioc 0 250 Von 0 600 V 2 AC Differential Input Voltage Vinac 0 500 Von 0 600 V 3 AC Differential Cross Point Voltage Vixac 0 50 VoD 0 175 0 50 Vpop 0 175 V 4 Notes 1 Vinoc specifies the allowable DC excursion of each input of a differential pair 2 Vipo specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Viac Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 Voo and is expected to track variations in Vor Capacitance T 25 C f 100 MHz PARAMETER Pi
3. 3 x 200 OHMS CKO SDRAM X 3 CKO 3x1 pF 3 x 200 OHMS CKI SDRAM X 3 ICK1 3x1 pF 3 x 200 OHMS ie SDRAM X 3 ICK2 3x1 pF DECOUPLING Vppspp ___ gt Serial PD VDD All Devices VREF All SDRAMs Vss Ss All Devices SCL SERIAL PD SDA SAO SA1 SA2 Page 3 DTM63393B 1GB 240 Pin Unbuffered ECC DDR2 DIMM DATARAM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TstoRAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tease 0 95 C Voltage on Vpp relative to Vss Vpp 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Notes Temperature above 85C requires doubling the refresh rate i e 3 9us instead of 7 8us Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Von 1 7 1 8 1 9 V UO Reference Voltage VREF 0 49 Mon 0 50 Von 0 51 Von V 1 Bus Termination Voltage Ver Vrer 0 04 VREF Vrer 0 04 V Notes 1 The value of Vor is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Veer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V
4. Dataram Corporation 2009 Page 12
5. 0 204 lt 2 480 2 165 la 123 00 4 843 Back view Side view BS 2 72Max 0 105 Max C C 4 00 Min 0 157 Min O SH 1 27 10 lle 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Document 06511 Revision A 04 Mar 09 Dataram Corporation 2009 Page 2 DQS DOS DQRI7 0 OF 1 0 7 0 DMR1 Q DQSR1 O DQSR1 DQS DOS DQR 15 8 O 1 0 7 0 DQSR2 DQSR2 DMR3 DQSR3 DQSR3 DQS DOS DQR 31 24 OF 1 017 0 DQSR8 DQSR8 DOS DOS CBRI7 0 VO 7 0 22 OHMS CB 7 0 O WA O _CBRI7 0 DQ 63 0 O VWA O DQR 63 0 DQS 8 0 O VW O DQRS 8 0 DQS 8 0 O VVy O O DQRS 8 0 DM 8 0 O VW O DMR 8 0 GLOBAL SDRAM CONNECTS 10 OHMS BA 2 0 O VWA O BA 2 0 R A 13 0 CNN A 13 0 R IRAS O A A O RASR ICAS O AA O CASR WE O WA O IWER CKEO m CKEO 22 pF ODTO ODTO 22 pF SO e w S0 Document 06511 Revision A 04 Mar 09 Dataram Corporation 2009 DTM63393B 1GB 240 Pin Unbuffered ECC DDR2 DIMM DQSR4 DQS DOS CS DM DQR 39 32 OJ 0 7 0 DMRS O DQSR5 DQSR5 DQS DOS CS DM DQR 47 40 DMR6 DQSR6 DQSR6 HH DQS DQS CS DM VO 7 0 DQR 55 48 VO 7 0 iDQS DAS CS DM DQR 63 56 VO 7 0
6. ms CKE is HIGH CS is HIGH between valid commands 1413 mA Address bus inputs are switching Data bus inputs are switching All banks open Continuous burst reads lout 0 mA BL 4 Operating Burst 4R CL 5 tck AL 0 tras 70 ms CKE is HIGH CS is HIGH 1368 mA Read Current pp between valid commands Address bus inputs are switching Data bus inputs are switching Burst Refresh Refresh command at every 75 ns CKE is HIGH CS is HIGH c Ipp5 between valid commands Other control and address bus inputs are 2052 mA urrent te ee switching Data bus inputs are switching Self Refresh loo6 CK and CK at 0 V CKE lt 0 2 V Other control and address bus 44 mA Current Be inputs are floating Data bus inputs are floating All bank interleaving reads lout 0 mA BL 4 CL 5 tex ee SC loo AL tRCD IDD 1 x tCK IDD treo 7 5 ns CKE is HIGH CS 2259 ma Current HIGH between valid commands Address bus inputs are stable during deselects Data bus inputs are switching Note For all Jonk measurements tek 2 5 ns tre 57 25 ns tacp 12 5 ns tras 45 ns and trp 12 5 ns unless otherwise specified All currents are based on DRAM absolute maximum values a aa a a a a a ENEESNENSENSH Document 06511 Revision A 04 Mar 09 Dataram Corporation 2009 Page 6 DTM63393B DATARAM 1GB 240 Pin Unbuffered ECC DDR2 DIMM AC Operating Conditions
7. 8 TBD TBD TBD TBD 18 SDRAM Device Attributes CAS Latency 0x30 TBD TBD Document 06511 Revision A 04 Mar 09 Dataram Corporation 2009 DTM63393B DATARAM 1GB 240 Pin Unbuffered ECC DDR2 DIMM Latency 2 Latency 3 Latency 4 Latency 5 Latency 6 TBD a DIMM Mechanical Characteristics Max module thickness x lt 4 10 0x01 mm DIMM type information 0x02 Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UDIMM 82 0mm TBD TBD SDRAM Module Attributes Refer to Byte20 for DIMM type information 0x00 Number of active registers on the DIMM N A for UDIMM 1 Number of PLL on the DIMM N A for UDIMM 0 x lt gt lt FET Switch External Enable No TBD Analysis probe installed No TBD SDRAM Device Attributes General 0x02 Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Self Refresh TBD TBD TBD TBD TBD a Clock Cycle Time at Reduced CAS Latency CL Ge Data Access Time DAC from Clock at CL X 1 Minimum Clock Minimum Clock Cycle Time at CL X 2 ns Time at CL X 2 ns a Data Access Time SE eee Te ae from Clock at CL X 2 UNUSED de Row Precharge Time tRP ns Minimum Row Active to Row Active Ke tRRD Minimu
8. Bank Active bei inputs are switching Data bus inputs are switchin 792 mA Precharge Current H 9 H 9 Oparating One lour 0 mA BL 4 CL 5 ns AL 0 CKE is HIGH CS is HIGH Bank Active Read oi between valid commands Address bus inputs are switchin 846 mA Precharge Current H 9 Precharge Power Ibn 2P All banks idle CKE is LOW Other control and address bus inputs 117 mA Down Current RD are stable Data bus inputs are floating Precharge Quiet Ibo2Q All banks idle CKE is HIGH CS is HIGH Other control and 513 mA Standby Current PR address bus inputs are stable Data bus inputs are floating Precharge Standby 1 2N All banks idle CKE is HIGH CS is HIGH Other control and 531 e Current BD address bus inputs are switching Data bus inputs are switching S All banks open CKE is LOW Other control and address bus inputs RE lbb3P_ are stable Data bus inputs are floating Fast Power down exit 378 mA Mode Register bit 12 0 Active Power Down All banks open CKE is LOW Other control and address bus inputs c lbo3P are stable Data bus inputs are floating Slow Power down exit 180 mA urrent 8 f z Mode Register bit 12 1 All banks open tras 70 ms CKE is HIGH CS is HIGH between see Standby Joh valid commands Other control and address bus inputs are 603 mA urrent ieee SE switching Data bus inputs are switching Operating Burst All banks open Continuous burst writes BL 4 CL z 5 tck AL 0 Write Current Ipp4W_ tras 70
9. DTM63393B Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 8 V 0 1 VO Type SSTL_18 Data Transfer Rate 6 4 Gigabytes sec Data Bursts 4 or 8 bits Sequential or Interleaved ordering Programmable I O driver strength OCD Programmable On Die Termination ODT Programmable CAS Latency 4 or 5 Differential Redundant Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully ROHS Compliant Pin Configuration 1GB 240 Pin Unbuffered ECC DDR2 DIMM Identification DTM63393B 128Mx72 1GB 1Rx8 PC2 6400E 555 12 F0 Performance range Clock Module Speed CL trep trp 400MHZz PC2 6400 5 5 5 333MHz PC2 5300 5 5 5 266MHz PC2 4200 4 4 4 Description DTM63393B is an Unbuffered 128Mx72 memory module which conforms to JEDEC s PC2 6400 standard The DIMM has one Rank comprised of nine 128Mx8 DDR2 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals The Data Strobe signals may be used either as differential pairs or as single ended strobes with the DQS signals disabled Data Mask inputs are provided to selectively prevent data from being written to an 8 bit byte Alternatively these may be used as Redundant Data Strobes for use in systems with a mix of x4 and x8 DRAMs Pin Descri
10. N DT2Q Degree CH DRAM Case Temperature Rise from Ambient due to 0x60 Precharge Power Down DT2P Degree C 9 6 5 1 44 2 DRAM Case Temperature Rise from Ambient due to Active 7 35 0x31 Standby DT3N Degree CH 65 2 2 O DN ol DRAM Case temperature Rise from Ambient due to Active 4 0x5D Power Down with Fast PDN Exit DT3Pfast Degree C 4 DRAM Case temperature Rise from Ambient due to Active 0x58 Power Down with Slow PDN Exit DT3Pslow Degree C DRAM Case Temperature Rise from Ambient due to Page Open Burst 0x54 Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree C Bit 0 0 if DT4W is greater than DT4R DTAR Bits 1 7 56 DRAM Case Temperature Rise from Ambient due to Burst 25 0x32 Refresh DT5B Degree C Document 06511 Revision A 04 Mar 09 Dataram Corporation 2009 Page 10 E o DTM63393B DATARAM 1GB 240 Pin Unbuffered ECC DDR2 DIMM 57 DRAM Case Temperature Rise from Ambient due to Bank 27 5 0x37 Interleave Reads with Auto Precharge DT7 Degree C 58 Thermal Resistance of PLL Package from Top to Ambient UNUSED 0x00 Psi T A PLL C Watt 59 Thermal Resistance of Register Package from Top to UNUSED 0x00 Ambient Psi T A Register C Watt PLL Case Temperature Rise from Ambient due to PLL UNUSED 0x00 Active DT PLL Active Degree C Register Case Temperature Rise from Ambient due to Register Active Mode 0x00 Bit DT Regis
11. RES 0 35 ps Write DQS Postamble Time twest 0 4 0 6 tck Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr trec min 10 ns Exit Self Refresh to Read Command txsrp 200 tck Document 06511 Revision A 04 Mar 09 Dataram Corporation 2009 Page 7 DTM63393B DATARAM 1GB 240 Pin Unbuffered ECC DDR2 DIMM SERIAL PRESENCE DETECT MATRIX Byt Function e Number of Bytes Utilized by Module Manufacturer 128 bytes Total number of Bytes in Serial PD device 256 bytes Memory Type DDR2 SDRAM 1 2 3 4 7 Number of Row Addresses 0 4 Number of Column Addresses Module Attributes Number of Ranks Package and Height of Ranks Card on Card DRAM Package Planar Module Height 30mm o meae Daa WAT roa last rs 8 Voltage Interface Level of this assembly SSTL 1 8V SDRAM Cycle time Max Supported CAS Latency CL X tCK ns 0 4 SDRAM Access from Clock Highest CAS latency tAC ns 04 0x40 11 DIMM configuration type Non parity Parity or ECC 0x02 Data Parity Data ECC Address Command Parity TBD TBD TBD TBD TBD Refresh Rate Type us 7 8 SR 0x82 Primary SDRAM Width 8 0x08 Error Checking SDRAM Width 8 TI 0x08 PRUSED 0x08 SDRAM Device Attributes Burst Lengths Supported TBD TBD Burst Length 4 Burst Length
12. m Active to SECH Time ns Data Input Hold Time After Strobe ne SC Document 06511 Revision A 04 Mar 09 Dataram Corporation 2009 Page 9 DTM63393B DATARAM 1GB 240 Pin Unbuffered ECC DDR2 DIMM Write Recovery Time tWR ns Internal write to read command delay tWTR ns Internal read to precharge command delay tRTP ns 0x00 Extension of Byte 41 tRC and Byte 42 tRFC ns 0x36 Add this value to byte 41 Add this value to byte 42 0 5 41 SDRAM Device Minimum Active to Active Auto Refresh 57 5 0x39 Time tRC ns SDRAM Device Minimum Auto Refresh to Active Auto 127 5 Ox7F Refresh Command Period tRFC ns SDRAM Device Maximum Cycle Time tCK max ns x80 SDRAM Dev DQS DQ Skew for DOS amp DQ signals t DQSQ 0 2 0x14 ns A AJ oa DDR SDRAM Device Read Data Hold Skew Factor tQHS Ox1E ns PLL Relock Time us 0x00 DRAM maximun Case Temperature Delta Degree C DT4R4W Delta Bits 0 3 Tcasemax delta Bits 7 4 8 Thermal Resistance of DRAM Package from Top Case to Ambient Psi T A DRAM C Watt DRAM Case Temperature Rise from Ambient due to Activate Precharge Mode Bits DTO Mode Bits Degree C Bit 0 If 0 DRAM does not support high temperature self 1 refresh entry Bit 1 If 0 Do not need double refresh rate for the proper 1 operation DTO Bits 2 7 6 50 DRAM Case Temperature Rise from Ambient due to 0x41 Precharge Quiet Standby DT2
13. n Symbol Minimum Maximum Unit Input Capacitance Clock CK 2 0 CK 2 0 CIN1 3 6 pF mea SC EE Address GE o SO RAS CAS WE CIN2 9 36 pF Input Output Capacitance Geer CB 7 0 DQS 8 0 DQSI8 0 CIO 3 4 pF DC Characteristics T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address lu 80 80 yA 1 Input Leakage Current S0 CKE0 ODTO lu 40 40 yA 1 Input Leakage Current CK 2 0 CK 2 0 lu 30 30 yA 1 Input Leakage Current DM lu 10 10 yA 1 Output Leakage Current DQS DQ loz 10 10 yA 2 Output Minimum Source DC Current loH 13 4 mA 3 Output Minimum Sink DC Current Jo 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 DQx and ODT are disabled and 0 V lt Vout lt Mon 2 Voo 1 7 V Vout 1420 mV Dour Voo lon must be less than 21 Ohms for values of Vout between Von and Vopn 280 mV A Vpp 1 7 V Vout 280 mV Moullo must be less than 21 Ohms for values of Vout between 0 V and 280 mV a a a Fh E Document 06511 Revision A 04 Mar 09 Dataram Corporation 2009 Page 5 DATARAM DTM63393B 1GB 240 Pin Unbuffered ECC DDR2 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V Max PARAMETER Symbol Test Condition Value Unit Operating One CKE is HIGH CS is HIGH between valid commands Address bus
14. ption Front Side Back Side Name Function 1 VREF 31DQ19 GA o vss baves 151 vss 181 VDD 211 DM5 CBI7 0 Data Check Bits 2 vss 32 vss 62 VDD 92 ooesbhaaoou 152 DQ28 182 A3 212 NC DQ 63 0 Data Bits 3 DQO 33 DQ24 6 amp 3a2 o DaSS 123 Da5 usa DQ29 Maa A1 213 VSS DQS 8 0 DQS 8 0 Differential Data Strobes 4 pat 34 DQ25 64vDD D vss hauves 154 VSS 184 VDD 214 Dade DM 8 0 Data Mask 5 VSS 35 VSS 65 vss oe DQ42 125 pmo 155 DM3 f85 CKO 215 DQ47 CK 2 0 CK 2 0 Differential Clock Inputs 6 DQSO 36 Das3 66 vss ge Da43 126 NC 156 NC 486 CKO 216 VSS CKEO Clock Enables 7 paso 37 DQs3 Supp 97 vss 127 vss 157 vss 187 VDD 217 Das2 ICAS Column Address Strobe 8 VSS 38 VSS 68NC oe DQ48 128 pae h58 Doan 188 AO 218 DQ53 IRAS Row Address Strobe 9 DQ2 39 DQ26 eovpop o Doug 129 pa7 159 DQa31 W gvpp 219 vss ISO Chip Selects 10DQ3 40DQ27 70A10 foo vss 130 vss feo vss 190 BA1 220 CK2 MWE Write Enable 11VSS 41 vss 71 BAO o SA2 131 DQ12 161 CB4 s 191 VDD 221 ck2 A 15 0 Address Inputs 12DQ8 42 CBO 72 VDD 102 NC 132 DQ13 162 cB5 192 RAS 222 VSS BA 2 0 Bank Addresses 13 DQ9 43 CB1 73 WE 103 vss 133 vss 163 VSS Wan SO 223 DM6 ODTO On Die Termination Inputs 14VSS WA VSS 74 CAS 104 Dase 134 DM1 s 164 Dm8 194 VDD 224 NC SAI2 0 SPD Address 15 DQS1 45 DAS8 75 VDD os pase 135 NC 165 NC 195 ODTO 225 VSS SCL SPD Clock Input 16 DQs1 Wepoen 76NC oe vss 136 vss fes vss 196 A13 226 DQ54 SDA SPD Data In
15. put Output 417 vss Wi VSS NG oz DQ50 bas cu 167 CB6 197 VDD 227 DQ55 vss Ground 18 NC 48 CB2 78 VDD 108 DQ51 138 CK1 ven CB7 198 VSS 228 VSS VDD Power 19 NC 49 CB3 7z9vss 109 vss 139 vss h69 vss 199 Da36 229 DQ60 VDDSPD SPD EEPROM Power 20 vss 50 Vss 80 DQ32 110 pose ban DQ14 up VDD pop poar 230 DQ61 VREF Reference Voltage 21 DQ10 51 VDD ai DQ33 Wu Da57 ai pop Wm NC 201 vss 231 VSS NC No Connection 22 DQ11 52CKEO s2vss f112 vss 142 vss 172 VDD j202 DM4 232 DM7 23 VSS 53 VDD 83 DQS4 113 DQS7 143 DQ20 aan 203 NC 233 NC 24 DQ16 54 BA2 84 Das4 114 Das7 144 DQa21 f174 a14 204 vss 234 vss 25 DQ17 55 NC 85 vss Wusves 145 vss 175 VDD 205 DQ38 235 DQ62 26VSS 56 VDD 86 DQ34 116 Da58 146 DM2 ue A12 206 DQ39 236 DQ63 27 IDQS2 57 A11 87 DQ35 117 DQ59 147 NC 177 A9 207 vss 237 VSS 28 DQS2 58 A7 88 vss 118 vss 148 vss f178 VDD 208 DQ44 238 VDDSPD 29 VSS 59 VDD 89 DQ40 119 SDA 149 DQ22 f179 AB 209 DQ45 239 SAO 30 DQ18 60 A5 90 DQ41 120 SCL Weg Da23 Wan A6 210 VSS ban SA1 Connected but not used Document 06511 Revision A 04 Mar 09 Dataram Corporation 2009 Page 1 DTM63393B DATARAM 1GB 240 Pin Unbuffered ECC DDR2 DIMM Front view 133 35 i 5 250 P 10 00 4 00 0 394 30 00 se C 1 181 S gt Lk 17 80 0 700 o o NANNAN T 2 54 Min 5 18 LL 63 00 55 00 0 100 Min
16. ter Active Mode Bit Bit OH O Unit for Bits 2 7 is 0 75C 0 75 Bit 1 RFU Default 0 0 Register Active Bits 2 7 0 Checksum forByies O62 TOA Module Manufacturer s JEDEC ID Code Dataram ID Module Manufacturer s JEDEC ID Code Dataram ID Module Manufacturer s JEDEC ID Code UNUSED Module Manufacturing Location UNUSED Module Revision Code UNUSED Module Manufacturing Date UNUSED Module Serial Number Module Serial Number N 66 71 N QIN oa o o Ojo Ojo AOIN 21 7 Module Serial Number Module Serial Number 99 Manufacturer s Specific Data UNUSED 127 Document 06511 Revision A 04 Mar 09 Dataram Corporation 2009 Page 11 DTM63393B DATARAM 1GB 240 Pin Unbuffered ECC DDR2 DIMM DATARAM DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06511 Revision A 04 Mar 09
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