Dataram 2GB DDR2
Contents
1. Data Hold Skew Factor toHs 300 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 57 5 ns RAS to CAS Delay trep 12 5 ns Average Periodic Refresh Interval REFI 7 8 us Auto Refresh Row Cycle Time trrc 127 5 ns Row Precharge Time tre 12 5 ns Read DQS Preamble Time RPRE 0 9 1 1 tox Read DQS Postamble Time test 0 4 0 6 tck Row Active to Row Active Delay RRD 7 5 ns Internal Read to Precharge Command Delay tRTP 7 5 ns Write DQS Preamble Time twPRE 0 35 ps Write DQS Postamble Time twest 0 4 0 6 tex Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr trec min 10 ns Exit Self Refresh to Read Command txsrD 200 tck Document 06989 Revision A 06 FEB 08 Dataram Corporation 2008 Page 7 DTM63368 JAVA VISA WN 268 256mx72 240 Pin Unbuffered ECC DDR2 DIMM SERIAL PRESENCE DETECT MATRIX sa Module Attributes Number of Ranks Package and Height of Ranks 2 Card on Card No DRAM Package Planar Module Height 30mm Module Data Width 72 7 UNUSED Voltage Interface Level of this assembly SSTL 1 8V 72 SDRAM Cycle time Max Supported CAS Latency CL X tCK ns 10 SDRAM Access from Clock Highest CAS latency tAC ns DIMM configuration type Non parity Parity or ECC Data Parity Data ECC Address Command Parity TBD TBD TBD TBD2. Primary SDRAM Width O R rror Checking SDRAM Width UNUSED SDRAM Device Attributes Burst Lengths Supported 12 14 15 TBD TBD Burst Length 4 Burst Length 8 TBD TBD TBD TBD 17 SDRAM Device Attributes Number of Banks on SDRAM Device 8 18 SDRAM Device Attributes CAS Latency TBD TBD Latency 2 Latency 3 Hex 0x80 x08 x08 x0E x0A 0x61 x48 0x00 0x05 j O Oo o o jo o o o o ol o x x x lt Q N O a x40 0x02 0x30 Document 06989 Revision A 06 FEB 08 Dataram Corporation O 2008 Page 8 DTM63368 DATARAM 2 GB 256Mx72 240 Pin Unbuffered ECC DDR2 DIMM Latency 4 X Latency 5 X Latency 6 TBD DIMM Mechanical Characteristics Max module thickness mm x lt 4 10 0x01 DIMM type information 0x02 Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm ye y Micro DIMM 45 5mm Mini RDIMM Mini UDIMM 82 Omm TBD TBD SDRAM Module Attributes Refer to Byte20 for DIMM type information Number of active registers on the DIMM N A for RIA Number of PLL on the DIMM N A for UDIMM FET Switch External Enable TBD Analysis probe installed TBD SDRAM Device Attributes General Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Sel
3. em M gy WE A Woy Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high DTM63368 DA ARAM 2 GB 256Mx72 240 Pin Unbuffered ECC DDR2 DIMM Operating Voltage 1 8 V 0 1 VO Type SSTL_18 Data Transfer Rate 6 4 Gigabytes sec Bursts Length 4 and 8 Programmable l O driver strength OCD Programmable On Die Termination ODT Programmable CAS Latency 4 or 5 Differential Redundant Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully ROHS Compliant Pin Configuration Identification DTM63368 256Mx72 Performance range Clock Module Speed CL trco trp 400 MHz PC2 6400 5 5 5 266 MHz PC2 4200 4 4 4 Description DTM63368 is an Unbuffered ECC 256Mx72 memory module which conforms to JEDEC s DDR2 PC2 6400 standard The assembly is consisting two Ranks Each Rank is comprised of nine 128Mx8 DDR2 SDRAMs One 2K bit EEPROM is used for Serial Presence Detect Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals Pin Description Front Side Back Side Name Function 1 VREF 31DQ19 61A4 or vss 121VSS 151 vss 181 VDD 211 DM5 CBI7 0 Data Check Bits 2 VSS 32 vss 62 VDD 92 DQs5 fi22DQ04 152 DQ28 182 A3 212 NC DQ 63 0 Data Bits 3 DQO 33DQ24 63A2 93 DQs5 123 Da5 153 DQ29 183 A1 213 VSS DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34DQ
4. to Burst 19 5 0x27 Refresh DT5B Degree C Document 06989 Revision A 06 FEB 08 Dataram Corporation O 2008 Page 10 4 kl ll DTM63368 DATARAM 2 GB 256Mx72 240 Pin Unbuffered ECC DDR2 DIMM Thermal Resistance of PLL Package from Top to Ambient UNUSED DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto Precharge DT7 Degree C Psi T A PLL C Watt Thermal Resistance of Register Package from Top to UNUSED 0x00 Ambient Psi T A Register C Watt PLL Case Temperature Rise from Ambient due to PLL UNUSED 0x00 Active DT PLL Active Degree C Register Case Temperature Rise from Ambient due to Register Active Mode Bit 0x00 DT Register Active Mode Bit Bit 0 If O Unit for Bits 2 7 is 0 75C 0 75 Bit 1 RFU Default O 0 5 5 5 6 Register Active Bits 2 7 0 5 a edeme EE E 5 5 7s Mode Pat Number 36 Module Serial Number os 97 Module Serial Number 0 38 Module Serial Number o O oa Manufacturer s Specific Data 7 8 9 1 2 3 4 5 2 5 7 Document 06989 Revision A 06 FEB 08 Dataram Corporation O 2008 Page 11 DTM63368 DATARAM 2 GB 256Mx72 240 Pin Unbuffered ECC DDR2 DIMM DATARAM DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been careful
5. 00 Min E 0 157 Min N_N mm O f 1 27 10 p 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Document 06989 Revision A 06 FEB 08 Dataram Corporation 2008 Page 2 DTM63368 DATARAM 2 GB 256Mx72 240 Pin Unbuffered ECC DDR2 DIMM Isto SO Sn DMRO DQRSO O DQSRO O DQS DAS CS DM DQS DAR 7 0 O 1O 7 0 VO 7 0 DQs DMR1 DQSR1 O DQSR1 O DQS DAS CS DM 1DQS DAS CS DM DQR 15 8 O 1 0 7 0 1 0 7 0 DMR2 o DQSR2 O DQSR2 O DQS DQS CS DM IDQS DQS CS DM DAQR 23 16 O 10 7 0 1 0 7 0 DMR3 O e DQSR3 O DQSR3 O t DQS Das CS DM iDAS DAS CS DM DQRI31 24 O VO 7 0 1 0 7 0 DMR8 O DQSR8 O o DQSR8 O DQS Das CS DM IDQS DQS CS DM CBR 7 0 O V O 7 0 1 0 7 0 22 OHMS DQ 3 0 O WA O DQR 63 0 CB 7 0 O VWW O CBR 7 0 DAQS 8 0 O VVWY O DQSR 8 0 DQS 8 0 O VW O DQRS 8 0 DM 8 0 O VVWY O DMR 8 0 GLOBAL SDRAM CONNECTS 7 5 OHMS BA 2 0 O VW O BA 2 0 R A 13 0 O VWAN O A 13 0 R IRAS O A O RASR ICAS O WA O CASR WE O VW O WER CKEO gt CKEO Z 22pF CKE1 CKE1 22 pF ODTO ODTO I 22 p
6. 25 64 vDD 94 vss f24vss 154 vss 184 VDD 214 DQ46 DM 8 0 Data Mask 5 VSS 35 VSS 65 VSS les DQ42 125DMO 155DM3 185 CKO 215 DQ47 CK 2 0 CK 2 0 Differential Clock Inputs 6 DQSO 36 DQS3 66 VSS 96 DQ43 126 NC 156 NC 186 CKO 216 VSS CKE 1 0 Clock Enables 7 Daso 37DQS3 67 VDD 97 vss 127 vss 157 VSS 187 VDD 217 DQ52 ICAS Column Address Strobe 8 vss 38 VSS 68NC es DQ48 f28 pae 158 DQ30 188 AO 218 DQ53 IRAS Row Address Strobe 9 DQ2 39DQ26 69 VDD DQ49 f129 Da7 159 Da31 189 VDD 219 vss S 1 0 Chip Selects 10DQ3 40 DQ27 7roAato 100 vSS 130 VSS jiso vss 190BA1 220 CK2 MWNE Write Enable 11 VSS 41 VSS 71 BAO 101 SA2 131 DQ12 161 cB4 191 VDD 221 CK2 A 15 0 Address Inputs 12DQ8 42 CBO 72 VDD 102NC i32DQ13 t62CB5 192 RAS 222 vss BA 2 0 Bank Addresses 13DQ9 43 CB1 73 WE 103 vss 133 VSS 163Vvss 193 SO 223 DM6 ODT 1 0 On Die Termination Inputs 14 Vss 44 VSS 74 CAS 104 DOS6 134 DM1 164 Doma 194 VDD 224 NC SA 2 0 SPD Address 15 DQS1 45 DQS8 75 VDD 105 pase 135 NC 165 NC 195 ODTO 225 vss SCL SPD Clock Input 16 DQS1 46 Dasa 76 si foe vss 136 vss fiee vss 196 A13 226 DQ54 SDA SPD Data Input Output 17 VSS 47 VSS 77 ODT1 107 DQ50 137 CK1 167 cBe f197vDD 227 DQ55 VSS Ground 18 NC 48 CB2 78 VDD 108 DQ51 138 CK1 168 cB7 198 VSS 228 vss VDD Power 19 NC 49 CB3 79vss 109 vss i3ovss eg vss 199 DQ36 229 DQ60 VDDSPD SPD EEPROM Power 20 VSS 50 VSS 80 DQ32 110 Da56 fi40 DQ14 1
7. 70 VDD 200 DQ37 230 DQ61 VREF Reference Voltage 21 DQ10 51 VDD 81 DQ33 111 DQ57 i41 Da15 171 CKE1 201 vss 231 vss NC No Connection 22 DQ11 52 CKE0 82 vss 112 vss 142 vss 172 VDD 202 DM4 232 DM7 23 VSS 53 VDD 83 DQS4 113 DQS7 143 Da20 173 A15 203 NC 233 NC 24 DQ16 54 BA2 84 Das4 114 Das7 144 DQ21 174 A14 204 vss 234 vss 25 DQ17 55 NC 85 vss 1145 VSS 145 VSS 175 VDD 205 DQ38 235 DQ62 26VSS 56 VDD 86 DQ34 116 DQ58 146 DM2 176 A12 206 DQ39 236 DQ63 27 IDQS2 57 A11 87 DQ35 117 Da59 147 NC 177 A9 207 VSS 237 VSS 28 DQS2 58 A7 88 vss 118 vss 48s vss 178 VDD 208 DQ44 238 VDDSPD 29VSS 59VDD 89 DQ40 119 sDA 149 DQ22 179 AB 209 DQ45 239 SAO 30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1 Connected but not used Document 06989 Revision A 06 FEB 08 Dataram Corporation 2008 Page 1 DTM63368 DATA 2 GB 256Mx72 240 Pin Unbuffered ECC DDR2 DIMM Front view la 133 35 5 250 10 00 da 0 394 30 00 3 E 1 181 _ G A 17 80 Tt 0 700 O ON o t 5 00 2 54 Min 0 197 0 100 5 18 63 00 55 00 Min 0 204 k 2 480 a ie 2 165 g 123 00 el 4 843 Back view Side view 4 00Max 0 157 Max A C Ll LU Ll Ll LU LU 4
8. F opT1 ODT1 Z 22 pF SO S0 22 pF S4 S1 15 22 pF DMR4 DQRS4 DQSR4 000 DQAS DAS DAR 39 32 O 1 0 7 0 ICS DM DAS DAS CS DM VO 7 0 DMRS DQRS5 o 00 DQSR5 t DQAS DAS DQR 47 40 O44 1 0 7 0 ICS DM IDQS DAS CS DM VO 7 0 DMR6 DQRS6 DQSR6 DQAS DAS DAR 55 48 O 1 0 7 0 ICS DM iDQS DAS CS DM 1 0 7 0 DMR7 O DQRS7 O DQSR7 DQS DAS DAR 63 46 O 1 0 7 0 Das CS DM ICS DQS DDSPD VDD VREF Vss SCL WP VO 7 0 3 X 200 OHMS oh SDRAM X 6 ICKO 3 X 200 OHMS cki SDRAM X 6 ICK1 3 X 200 OHMS ce SDRAM X 6 ICK2 DECOUPLING A Serial PD e EN All Devices 2 All SDRAMs F l l All Devices SERIALPD e spa SA0 SA1 SA2 A NO a A AAA E Document 06989 Revision A 06 FEB 08 Dataram Corporation O 2008 Page 3 DTM63368 2 GB 256Mx72 240 Pin Unbuffered ECC DDR2 DIMM DATARAM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TSTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tcase 0 85 C Voltage on Vpp relative to Vss Vop 0 5 2 3 V Voltage on Any Pin relative t
9. Fast Power down 450 mA exit Mode Register bit 12 0 a All banks open tras 70 ms CKE is HIGH CS is HIGH between Active Standby Ipbp3N valid commands Other control and address bus inputs are 990 mA Current EOS gt ae switching Data bus inputs are switching All banks open Continuous burst writes BL 4 CL 5 tcx Operating Burst lop4W AL 0 tras 70 ms CKE is HIGH CS is HIGH between valid 1620 mA Write Current Dp commands Address bus inputs are switching Data bus inputs are switching All banks open Continuous burst reads lout 0 mA BL 4 Operating Burst Io 4R CL 5 tck AL 0 tras 70 ms CKE is HIGH CS is HIGH 1620 mA Read Current Dp between valid commands Address bus inputs are switching Data bus inputs are switching Burst Refresh Refresh command at every 75 ns CKE is HIGH CS is HIGH Ipp5 between valid commands Other control and address bus inputs 3150 mA Current ats arte are switching Data bus inputs are switching Self Refresh lon6 CK and CK at 0 V CKE lt 0 2 V Other control and address bus 180 m Current pD inputs are floating Data bus inputs are floating A All bank interleaving reads loyr 0 mA BL 4 CL 5 tex Operating Bank AL 70ns taro 7 5 ns CKE is HIGH CS is HIGH between Interleave Read loo7 q a 3330 mA valid commands Address bus inputs are stable during deselects Current y EN Data bus inputs are switching One module rank in this operation
10. f Refresh TBD TBD TBD TBD TB He Cycle Time at Reduced CAS Latency CL X 1 arman Data Access Time tAC from Clock at CL X 0x40 pi Clock Minimum Clock Cycle Time at CL X 2 ns Time at CL X 2 ns UNUSED 0x00 Rr aes Te AG on COTTA Data Access Time tAC from Clock at CL X UNUSED 0x00 Minium Row Precharge Time tRP ns apn Row Active to Row Active Minimum Row Active to Row Active Delay tRRD ns tRRD ns Minimum RAS to CAS Delay tRCD ns FT IRON Minimum Active to Precharge Time tRAS ns MEM Rank Module Rank Density fetal and Command Setup Time Before Clock A E E ius Ok 0x3D S o x lt m EEE ea Loa Address and Command Hold Time After Clock tIH ns _ Data Input Setup Time Before Strobe Ea i s EEE Data Input Hold Time After Strobe tDH 36 wrie Recovery Time WR ns Document 06989 Revision A 06 FEB 08 Dataram Corporation 2008 Page 9 DTM63368 DATARAM 2 GB 256Mx72 240 Pin Unbuffered ECC DDR2 DIMM ae nternal write to read command delay tWTR Internal read to precharge command delay Tah _ 2 Ox1E a Memory Analysis Probe Characteristics UNUSED Extension of Byte 41 tRC and Byte 42 tRFC ns 0x36 Add this value to byte 41 Add this value to byte 42 0 5 Ms o Minimum Active to Active Auto Refresh ES tRC ns SDRAM Bovine Minimum Auto Refresh to Active Auto 127 5 Ox7F Command Period tRFC n
11. ly checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06989 Revision A 06 FEB 08 Dataram Corporation 2008 Page 12
12. o Vss Vin Vout 0 5 2 3 V Recommended DC Operating Conditions T O to 70 C Voltage referenced to Vss 0 V PARAMETER ia Minimum Tvpical Maximum Unit Note Power Supply Voltage 1 O Reference Voltage Bus Termination Voltage Notes Vrer 0 04 VREF Vrer 0 04 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Veer may not exceed 1 of its DC value DC Input Logic Levels Single Ended Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Svmbol Minimum Maximum Unit Logical High Logic 1 ViH DC Vrer 0 125 Voo 0 300 V Logical Low Logic 0 ViL Dc 0 300 Vrer 0 125 V AC Input Logic Levels Single Ended T O to 70 C Voltage referenced to Vss 0 V PARAMETER Svmbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 250 V Logical Low Logic 0 Vilac Vrer 0 250 V a a a a a a AAA A A Document 06989 Revision A 06 FEB 08 Dataram Corporation 2008 Page 4 DTM63368 DATARAM 2 GB 256Mx72 240 Pin Unbuffered ECC DDR2 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Svmbol Minimum Maximum Unit Note DC Input Signal Voltage Vin oc 0 300 Voo 0 300 V 1 DC Differential Input Voltage Vipioc 0 250 Voo 0 600 V 2 AC Differential Input Voltage Vinac 0 500 Vpp 0 600 V 3 AC Differential Cros
13. rest in IDD2P All module ranks in this operation Notes 1 For all IppX measurements tex 2 5 ns tre 57 5 ns tren 12 5 ns tras 45 ns and tre 12 5 ns unless otherwise specified 2 All IppX values shown are worst case maximums considering all DRAMs A a A a a ea Document 06989 Revision A 06 FEB 08 Dataram Corporation 2008 Page 6 DTM63368 DATARAM 2 GB 256Mx72 240 Pin Unbuffered ECC DDR2 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 400 400 ps CAS to CAS Command Delay teco 2 tck Clock High Level Width tcH 0 45 0 55 tck Clock Cycle Time tck 2 5 8000 ps Clock Low Level Width teL 0 45 0 55 tck Data Input Hold Time after DQS Strobe ton 125 ps DQ Input Pulse Width toipw 0 35 tck DQS Output Access Time from Clock toasck 400 400 ps Write DQS High Level Width toasH 0 35 tex Write DQS Low Level Width toast 0 35 tck DQS Out Edge to Data Out Edge Skew toasa 200 ps Data Input Setup Time Before DQS Strobe tos 50 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck DQS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tue minimum of tcy or teL ns Address and Command Hold Time after Clock tu 250 ps Address and Command Setup Time before Clock tis 175 ps Load Mode Command Cycle Time turD 2 tck DQ to DQS Hold ton tup tons
14. s SDRAM Device Maximum Cycle Time tCK max as ae ee SDRAM es DQS DQ Skew for DQS amp DQ 0x14 tDQSQ DDR SDR Device Read Data Hold Skew Factor 0 3 Ox1E tQHS PLL SLS Time us UNUSED 0x00 DRAM maximun Case Temperature Delta Degree C 0x50 DT4R4W Delta Bits 0 3 a Tcasemax delta Bits 7 4 Thermal Resistance of DRAM Package from Top Case Ss 0x74 to Ambient Psi T A DRAM C Watt DRAM Case Temperature Rise from Ambient due to Activate Precharge 0x4B Mode Bits DTO Mode Bits Degree C Bit 0 If 0 DRAM does not support high temperature self refresh entry Bit 1 If 0 Do not need double refresh rate for the proper operation DTO Bits 2 7 DRAM Case Temperature Rise from Ambient due to 0x32 Precharge Quiet Standby DT2N DT2Q Degree C DRAM Case Temperature Rise from Ambient due to 1 095 0x49 Precharge Power Down DT2P Degree C DRAM Case Temperature Rise from Ambient due to 0x28 Active Standby DT3N Degree C 53 DRAM Case temperature Rise from Ambient due to Active A 0x37 Power Down with Fast PDN Exit DT3Pfast Degree C DRAM Case temperature Rise from Ambient due to Active 1 325 0x35 Power Down with Slow PDN Exit DT3Pslow Degree C DRAM Case Temperature Rise from Ambient due to Page Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree C Bit 0 0 if DT4W is greater than DT4R DTAR Bits 1 7 DRAM Case Temperature Rise from Ambient due
15. s Point Voltage Vix Ac 0 50 VDD 0 175 0 50 VDD 0 175 V 4 Notes 1 Vinoc specifies the allowable DC excursion of each input of a differential pair 2 Vipco specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Viac Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 Voo and is expected to track variations in Vpp Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO CK1 CK1 CK2 CK2 CIN1 6 12 pF Input Capacitance Address BA 2 0 A 13 0 SO S1 RAS CAS CIN2 18 36 pF and Control WE CKEO CKE1 ODTO ODT1 Input Capacitance Control SO S1 CKEO CKE1 ODTO ODT1 CIN3 9 18 pF Input Output Capacitance De e DQS 8 0 CIO 6 8 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address lu 80 80 yA 1 Input Leakage Current S 1 0 CKE 1 0 lu 40 40 pA 1 ODT 1 0 Input Leakage Current CK 2 0 CK 2 0 lu 30 30 pA 1 Input Leakage Current DM lu 10 10 pA 1 Output Leakage Current DQS DQ loz 10 10 pA 2 Output Minimum Source DC Current loH 13 4 mA 3 Output Minimum Sink DC Current lot 13 4 mA 4 Notes 1 These values are guaranteed by design and are te
16. sted on a sample basis only 2 DQx and ODT are disabled and 0 V lt Vout Voo 3 Voo 1 7 V Vour 1420 mV Vour Voo lon must be less than 21 Ohms for values of Vout between Von and Vpp 280 mV 4 Vpp 1 7 V Vout 280 mV Vour lo must be less than 21 Ohms for values of Vout between 0 V and 280 mV Document 06989 Revision A 06 FEB 08 Dataram Corporation O 2008 Page 5 DATARAM DTM63368 2 GB 256Mx72 240 Pin Unbuffered ECC DDR2 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V wa Max PARAMETER Symbol Test Condition Value Unit Operating One CKE is HIGH CS is HIGH between valid commands Address Bank Active lop0 bus inputs are switching Data bus inputs are switchin 765 mA Precharge Current p 9 P 9 Operating One lout 0 mA BL 4 CL 5 ns AL 0 CKE is HIGH CS is Bank Active Read loo1 HIGH between valid commands Address bus inputs are 855 mA Precharge Current switching Precharge Power lon2P All banks idle CKE is LOW Other control and address bus inputs 180 mA Down Current 25 are stable Data bus inputs are floating Precharge Standby lon 2N All banks idle CKE is HIGH CS is HIGH Other control and 810 mA Current pe address bus inputs are switching Data bus inputs are switching r All banks open CKE is LOW Other control and address bus e r al loo3P inputs are stable Data bus inputs are floating
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