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Dataram 2GB DDR2

1. EN i ji 5 00 om m 518 63 00 gt 55 00 N 0 0 204 2 480 2 165 In 123 00 4 843 Back view Side view 4 00Max 0 157 Max 4 00 Min 0 157 Min 127240 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches a ae Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 2 51 O DTM63363 2 256 64 240 Pin Unbuffered DDR2 DIMM DQS DQS CS DM DAS DAS CS DM I O 7 0 VO 7 0 H i DQS DAS CS DM DQS DAS CS DM VO 7 0 VO 7 0 180 rT DMRO O 22 pF 22 DMR4 DQSRO UE S pasr40 DQSRO DQSR4 DQRI 7 0 O VO 7 0 DQR 39 32 O DMR1 O poe DMR5 DQSR1 DQSR5 O EE HE ms Er ICS DM Das DQS CS D DQR 15 8 O l O 7 0 VO 7 0 DQR 47 40 0 DMR2 poi DMR6 DQSR2 O DQSR6 O DQSR2 DQSR6 DQS DAS CS DM DQS DAS CS DM DQR 23 16 VO 7 0 VO 7 0 DQR 55 48 0 DMR3 O DMR7 DQSR3 O DQSR7 O DQSR3 IDQSR7 7DQS DAS CS DM DQR 31 24 O 1 017 0 VO 7 0 DQR 63 56 O All 22 OHMS D
2. 1420 mV Vpp lou must be less than 21 Ohms for values of Vout between Von and Vpp 280 mV 4 Vpp 1 7 V Vout 280 mV must be less than 21 Ohms for values of Vout between 0 V and 280 mV a 232 22 22 22 22 1 222 o mra Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 5 DTM63363 DATARAM 2 GB 256Mx64 240 Pin Unbuffered DDR2 DIMM lbo Specifications and Conditions 0 to 70 C Voltage referenced to Vss 0 V Max PARAMETER Symbol Test Condition Value Unit Operating One CKE is HIGH CS is HIGH between valid commands Address Bank Active 1000 bus inputs are switching Data bus inputs are switching 640 mA Precharge Current Operating One lout 0 mA BL 4 CL 5 ns AL 0 is HIGH CS is Bank Active Read Ipp1 HIGH between valid commands Address bus inputs are 720 mA Precharge Current switching Precharge Power lo 2p All banks idle CKE is LOW Other control and address bus inputs 160 mA Down Current us are stable Data bus inputs are floating Precharge Quiet lpp2Q All banks idle CKE is HIGH CS is HIGH Other control and 480 mA Standby Current address bus inputs stable Data bus inputs are floating Precharge Standby Io 2N All banks idle is HIGH CS is HIGH Other control and 640 mA Current 09 address bus inputs are switching Data bus inputs switching banks open C
3. Pin Configuration Pin Description Front Side Back Side Function 1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDD 211 DM5 7 0 Data Check Bits 2 VSS 32 VSS 62 VDD 92 DQS5 122 DQ4 152 DQ28 182 A3 212 NC DQ 63 0 Data Bits 3 DQO 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 183 A1 213 VSS DQS 8 0 DQS 8 0 Differential Data Strobes 4 091 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VDD 214 0046 DM 8 0 Data Mask 5 VSS 35 VSS 65 VSS 95 DQ42 125 DMO 155 DM3 185 CKO 215 DQ47 CK 2 0 CK 2 0 Differential Clock Inputs 6 DQSO 36 DQS3 66 VSS 96 DQ43 126 NC 156 NC 186 CKO 216 VSS CKE 1 0 Clock Enables 7 DQSO 37 DQS3 67 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52 ICAS Column Address Strobe 8 VSS 38 55 68 98 DQ48 128 DQ6 158 DQ30 188 A0 218 DQ53 RAS Row Address Strobe 9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 VSS IS 1 0 Chip Selects 10 DQ3 40 DQ27 70 A10 100 VSS 130 VSS 160 VSS 190 BA1 220 CK2 ANE Write Enable 11 VSS 41 VSS 71 BAO 101 SA2 131 DQ12 161 CB4 191 VDD 221 CK2 A 15 0 Address Inputs 12 DQ8 42 CBO 72 VDD 102 NC 132 DQ13 162 CB5 192 RAS 222 VSS BA 2 0 Bank Addresses 13 DQ9 43 CB1 73 WE 103 VSS 133 VSS 163 VSS 193 50 223 DM6 ODT 1 0 On Die Termination Inputs 14 VSS 44 VSS 74 CAS 104 DQS6 134 DM1 164 DM8 194 VDD 224 NC SA 2 0 SPD Address 15 DQS1 45 DQS8 75 VDD 105 DQS6 135 165 NC 195 ODTO 225 VSS SCL SPD Clock Input 16 DQS1 46 0958 76 S1 106 VSS 136 VSS 166 55 196 1
4. 0 V PARAMETER m Minimum Tvpical Maximum Unit Note Power Supply Voltage Reference Voltage Bus Termination Voltage Notes Veer 0 04 VREF Vrer 0 04 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Veer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to 0 V PARAMETER Svmbol Minimum Maximum Unit Logical High Logic 1 Vrer 0 125 Vpp 0 300 V Logical Low Logic 0 ViL DC 0 300 Vrer 0 125 V AC Input Logic Levels Single Ended 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Svmbol Minimum Maximum Unit Logical High Logic 1 ViH AC Vrer 0 250 V Logical Low Logic 0 ViL AC Vrer 0 250 V Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 4 DTM63363 DATARAM 2 GB 256Mx64 240 Pin Unbuffered DDR2 DIMM Differential Input Logic Levels 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Svmbol Minimum Maximum Unit Note DC Input Signal Voltage ViN DC 0 300 Vpp 0 300 V 1 DC Differential Input Voltage 0 250 Vpp 0 600 V 2 AC Differential Input Voltage Vip AC 0 500 Vpp 0 600 V 3 AC Differential Cross Point Voltage Vix AC 0 50 Vpp 0 175 0 50 Vpp 0 175 V 4 Notes 1 specifies the allowable DC exc
5. DTM63363 DA ARAM 2 GB 256Mx64 240 Pin Unbuffered DDR2 DIMM Identification DTM63363 256Mx64 Performance range Clock Module Speed CL tncp 333 MHz PC2 5300 5 5 5 266 MHz PC2 4200 4 4 4 200 MHz PC2 3200 3 3 3 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high DTM63363 is an Unbuffered 256Mx64 memory module which conforms to JEDEC s Operating Voltage 1 8 V 10 1 DDR2 PC2 5300 standard The assembly is Type SSTL 18 comprised of two Ranks Each Rank is Dala Transfer Rate comprised of eight 128Mx8 DDR2 SDRAMs One 2K bit EEPROM is used for Serial Data Bursts 4 or 8 bits Sequential or Interleaved ordering Presence Detect Both output driver strength Programmable I O driver strength OCD and input termination impedance ET programmable to maintain signal integrity on Programmable On Die Termination ODT the I O signals The Data Strobe signals may Programmable CAS Latency 3 4 or 5 be used either as differential pairs or as single ended strobes with the DQS signals Differential Redundant Data Strobe signals disabled Data Mask inputs are provided to SDRAM Addressing Row Col Bank 14 10 3 selectively prevent data from being written to ne U Oo an 8 bit byte Alternatively these may be used Fully RoHS Compliant as Redundant Data Strobes for use in systems with a mix of x4 and x8 DRAMs
6. if DTAW is greater than DTAR Bits 1 7 56 DRAM Case Temperature Rise from Ambient due to Burst 23 5 Ox2F Refresh DT5B Degree C Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 10 DTM63363 2 256 64 240 Pin Unbuffered DDR2 Dimm 57 DRAM Case Temperature Rise from Ambient due to Bank 31 Ox3E Interleave Reads with Auto Precharge DT7 Degree C 5 Thermal Resistance of PLL Package from Top to Ambient UNUSED 0x00 Psi T A PLL C Watt 7 8 59 2 Thermal Resistance of Register Package from Top to Ambient UNUSED 0x00 Psi T A Register C Watt PLL Case Temperature Rise from Ambient due to PLL Active UNUSED 0x00 DT PLL Active Degree C fern Case Temperature Rise from Ambient due to Register Active Mode Bit 0x00 DT Register Active Mode Bit Bit O Unit for Bits 2 7 is 0 75C 0 75 Bit 1 RFU Default O 0 Register Active Bits 2 7 0 62 SPD Revision Revision 1 2 63 Checksum for Bytes 0 62 ataram ID 0x00 7590ModWePatNumr Poa 1 92 0x00 796 Module SerialNumber J E 797 Module 798 Module SerialNumber Da 99 Manufacturer s Specific Data UNUSED 0x00 127 Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 11 DTM63363 2GB 256Mx64 240 Pin Unbuffered DDR2DIMM _ DATARAM DATARAM COR
7. Address and Command Hold Time after Clock 275 ps Address and Command Setup Time before Clock tis 200 ps Load Mode Command Cycle Time 2 DQ to DQS Hold ton tup tous Data Hold Skew Factor tous 340 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 60 ns RAS to CAS Delay trop 15 ns Average Periodic Refresh Interval 1 7 8 Hus Auto Refresh Row Cycle Time 127 5 ns Row Precharge Time tre 15 ns Read DQS Preamble Time tRPRE 0 9 1 1 tck Read DQS Postamble Time test 0 4 0 6 Row Active to Row Active Delay tRRD 7 5 ns Internal Read to Precharge Command Delay 7 5 ns Write DQS Preamble Setup Time twPRE 0 35 ps Write DQS Postamble Time twPsT 0 4 0 6 tck Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr trec min 10 ns Exit Self Refresh to Read Command txsrp 200 Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 7 DTM63363 JAVA MANI 2 256 64 240 Pin Unbuffered DDR2 Dimm SERIAL PRESENCE DETECT MATRIX 0_ Number of Byles Utizedby Module Manufacturer 128 bytes 080 DDR SDRAM 056 00 5 Module Attributes Number of Ranks Package and Height of Ranks 2 Card on Card No DRAM Package Planar Module Height 30mm 6 Module Data Width UNUSED Voltage Interface Level of this
8. assembly SSTL 1 8V 0x05 SDRAM Cycle time Max Supported CAS Latency CL X tCK ns 3 10 SDRAM Access from Clock Highest CAS latency ns DIMM configuration type Non parity Parity or ECC Data Parity Data ECC Address Command Parity TBD TBD TBD TBD TBD efresh Rate Type us 7 8 SR rimary SDRAM Width rror Checking SDRAM Width eserved UNUSED 0x00 1 SDRAM Device Attributes Burst Lengths Supported TBD TBD Burst Length 4 Burst Length 8 TBD TBD TBD TBD Device Attributes Number of Banks on SDRAM S ees Device 18 SDRAM Device Attributes CAS Latency 0x38 TBD TBD Latency 2 Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 8 DTM63363 2 256 64 240 Pin Unbuffered DDR2 DIMM Latency 3 X Latency 4 X Latency 5 X Latency 6 TBD DIMM Mechanical Characteristics Max module thickness x lt 4 10 0x01 mm 20 DIMM type information 0x02 Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UDIMM 82 0mm TBD TBD 22 24 25 Number of PLL on the DIMM N A for UDIMM FET Switch External Enable TBD Analysis probe installed TBD SDRAM Device Attribu
9. 3 226 DQ54 SDA SPD Data Input Output 17 VSS 47 VSS 77 ODT1 107 DQ50 137 CK1 167 CB6 197 VDD 227 DQ55 VSS Ground 18 NC 48 CB2 78 VDD 108 DQ51 138 CK1 168 CB7 198 VSS 228 VSS VDD Power 19 NC 49 CB3 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ36 229 DQ60 VDDSPD SPD EEPROM Power 20 VSS 50 VSS 80 DQ32 110 0056 140 DQ14 170 VDD 200 DQ37 230 DQ61 VREF Reference Voltage 21 DQ10 51 VDD 81 DQ33 111 DQ57 141 DQ15 171 CKE1 201 VSS 231 VSS NC No Connection 22 DQ11 52 CKEO 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4 232 DM7 23 VSS 53 VDD 83 DQS4 113 DQS7 143 DQ20 173 A15 203 NC 233 NC 24 DQ16 54 BA2 84 DQS4 114 DQS7 144 DQ21 174 A14 204 VSS 234 VSS 25 DQ17 55 NC 85 VSS 115 VSS 145 VSS 175 VDD 205 DQ38 235 DQ62 26 VSS 56 VDD 86 DQ34 116 DQ58 146 DM2 176 A12 206 DQ39 236 DQ63 27 DQS2 57 A11 87 DQ35 117 DQ59 147 NC 177 A9 207 VSS 237 VSS 28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD 29 VSS 59 VDD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SAO 30 DQ18 60 A5 90 0041 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1 Connected but not used Not used Non ECC DIMM Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 1 DTM63363 2GB 256Mx64 240 Pin Unbuffered DDR2DIMM 0 Front view 133 35 5 250 0 394 00 10 00 0 157 30 00 1 181 t
10. KE is LOW Other control and address bus iid Re Ipp3P inputs are stable Data bus inputs are floating Fast Power down 400 mA exit Mode Register bit 12 0 All banks open tras 70 ms is HIGH CS is HIGH between 2 Ipp3N valid commands Other control and address bus inputs 800 mA switching Data bus inputs are switching All banks open Continuous burst writes BL 4 CL 5 AL 0 Operating Burst tras 70 ms is HIGH CS is HIGH between valid Write Current Ipp4W commands Address bus inputs are switching Data bus inputs 1280 mA are switching All banks open Continuous burst reads loyr 0 mA BL 4 Operating Burst Ipp4R CL 5 AL 0 tras 70 ms is HIGH CS is HIGH between 1280 Read Current valid commands Address bus inputs are switching Data bus inputs are switching Refresh command at every 75 ns CKE is HIGH CS is HIGH Burst Refresh Ipp5 between valid commands Other control and address bus inputs 2800 mA Current EUR hohe are switching Data bus inputs are switching Self Refresh loo6 CK and CK at 0 V CKE lt 0 2 V Other control and address bus 160 mA Current nsi inputs are floating Data bus inputs are floating bank interleaving reads 0 mA BL 4 CL 5 AL 70 Operating Bank _ _ Do 1525 Interleave Read Ipp7 ns tarp 7 5 ns is HIGH CS is HIGH between valid 2880 mA commands Address bus inputs are stabl
11. PORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 12
12. Q 63 0 O A O DQR 63 0 DQS 7 0 O O DQRSI7 0 1005 7 0 O O DQRS 7 0 7 0 O O DMR 7 0 GLOBAL SDRAM CONNECTS 5 1 OHMS 2 0 O A AA O BA 2 0 R 13 0 O AA O A 13 0 R IRAS O ANA O RASR ICAS O AN O O AN O CKEO CKEO 22 CKE1 CKE1 22 pF 4 m ODTO zp22pF ODT1 L w ODT T 22 pF DQS DQS CS DM DQS DQS CS DM VO 7 0 V O 7 0 3 X 200 OHMS SDRAM X4 CKO 1 5 pF 3 X 200 OHMS SDRAM X 6 1 3 X 200 OHMS SDRAM X 6 2 V DECOUPLING DDSPD 34 Serial PD All Devices VREF All SDRAMs Vss All Devices SCL SERIAL PD SDA SA0 SA1 SA2 Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 3 DTM63363 2 GB 256Mx64 240 Pin Unbuffered DDR2 DIMM DATARAM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsroRAGE 55 100 Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TcasE 0 85 Voltage on Vpp relative to Vss 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Recommended DC Operating Conditions 0 to 70 C Voltage referenced to
13. e during deselects Data bus inputs are switching One module rank in this operation rest in IDD2P All module ranks in this operation Current Note For all measurements 3 0 ns tac 60 ns treo 15 ns tras 45 ns and tpp 15 ns unless otherwise specified All currents are based on DRAM absolute maximum values H enn S ore Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 6 DTM63363 DATARAM 2 GB 256Mx64 240 Pin Unbuffered DDR2 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 450 450 ps 5 5 Command Delay tccp 2 tck Clock High Level Width 0 45 0 55 Clock Cycle Time tck 3000 8000 ps Clock Low Level Width 0 45 0 55 Data Input Hold Time after DQS Strobe 175 ps DQ Input Pulse Width 0 35 DQS Output Access Time from Clock tpasck 400 400 ps Write DQS High Level Width 0 35 tck Write DQS Low Level Width toast 0 35 DQS Out Edge to Data Out Edge Skew toasa 240 ps Data Input Setup Time Before DQS Strobe tos 100 ps DQS Falling Edge from Clock Hold Time 0 2 DGS Falling Edge to Clock Setup Time toss 0 2 Clock Period tup minimum of tcy or tci ns
14. resh to Active Auto 127 5 Ox7F Refresh Command Period tRFC ns 43 SDRAM Device Maximum Cycle Time tCK max 0228 0x80 44 TA Dev DQS DQ Skew for DQS amp DQ ka DDR SDRAM Device Read Data Hold Skew Factor tQHS 0x22 6 8 UNUSED 0x00 x00 47 DRAM maximun Case Temperature Delta Degree C 0 DT4R4W Delta Bits 0 3 0 Tcasemax delta Bits 7 4 48 Thermal Resistance of DRAM Package from Top Case to Ambient Psi T A DRAM C Watt 9 DRAM Case Temperature Rise from Ambient due to Activate Precharge Mode Bits DTO Mode Bits Degree C Bit 0 If 0 DRAM does not support high temperature self refresh entry Bit 1 If 0 Do not need double refresh rate for the proper operation Bits 2 7 50 DRAM Case Temperature Rise from Ambient due to 4 4 0 2 Precharge Quiet Standby DT2N DT2Q Degree C DRAM Case Temperature Rise from Ambient due to 0 765 0x33 Precharge Power Down DT2P Degree C 52 DRAM Case Temperature Rise from Ambient due to Active 0x28 Standby DT3N Degree C 53 DRAM Case temperature Rise from Ambient due to Active 0x42 Power Down with Fast PDN Exit DT3Pfast Degree C 54 DRAM Case temperature Rise from Ambient due to Active 1 1 0 2 Power Down with Slow PDN Exit DT3Pslow Degree C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree Bit 0
15. tes General 0x03 Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Self Refresh TBD TBD TBD TBD TBD 25 Clock Cycle TimeatCL X 2 ns SDRAM Module Attributes Refer to Byte20 for DIMM type information 0x00 Number of active registers on the DIMM N A for UDIMM 5 Clock Cycle Time at Reduced CAS Latency CL X Hain Data Access Time tAC from Clock at CL X 1 NE x45 MATT Clock Cycle Time at CL X 2 n Minimum Clock Cycle Time atCL X 2 ns Data Access Time tAC from Clock at CL 2 Row Precharge Time tRP ns 28 Minimum Row Active to Row Active Delay tRRD 29 Minimum RAS to CAS Delay tRCD ns 30 Minimum Active to Precharge Time tRAS ns 45 34 Data Input Setup Time Before strobe 08 0 5 36 Write Recovery Time tWR ns Document 06977 Revision D 10 Jun 08 Dataram Corporation 2008 Page 9 DTM63363 PYAN VAN VAN UI 2 256 64 240 Pin Unbuffered DDR2 DIMM Internal write to read command delay tWTR ns Internal read to precharge command delay ns Memory Analysis Probe Characteristics UNUSED 40 Extension of Byte 41 tRC and Byte 42 tRFC ns 0x06 Add this value to byte 41 Add this value to byte 42 0 5 ii Minimum Active to Active Auto Refresh Time B s 42 SDRAM Minimum Auto Ref
16. ursion of each input of a differential pair 2 specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 and is expected to track variations in Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO CK1 CK1 CK2 CK2 CIN1 6 12 pF Input Capacitance Address and Control BA 2 0 A 13 0 RAS CAS WE CIN2 16 32 pF Input Capacitance Control CKE 1 0 ODT 1 0 S 1 0 CIN3 8 16 pF Input Output Capacitance uL DESI DAN CIO 5 7 pF DC Characteristics 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address lu 160 160 pA 1 Input Leakage Current S 1 0 CKE 1 0 80 80 pA 1 ODT 1 0 Input Leakage Current CK 1 0 CK 1 0 lu 4 4 pA 1 Input Leakage Current DM lu 20 20 1 Output Leakage Current 005 DQ loz 20 20 2 Output Minimum Source DC Current 13 4 3 Output Minimum Sink DC Current lot 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 ODT are disabled and 0 V lt 3 Voo 1 7 V

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