Dataram DTM65517 memory module
Contents
1. C X Bit 1 Bit 0 Reserved Bit 7 Bit 2 DTO SDRAM Case Temperature Rise from Ambient due to Precharge Quiet Standby DT2N DT2Q f Average Refresh Interval tREFI Double Refresh mode bit High Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 15 DTM65517 JAVA VITAE 6 68 16372 240 Pin FB DIMM SDRAM Case Temperature Rise from Ambient due to Precharge Power Down DT2P C ie SDRAM Temperature Rise from Ambient due to Active Standby DT3N SDRAM Case Temperature Rise from Ambient due to Page Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Bit 0 DTARAW Mode Bit Subfield B 0 4 C 0 Bit 7 Bit 1 DT4R Subfield A 0 4 C 17 6 SDRAM Case Temperature Rise from Ambient due to Burst Refresh DT5B C SDRAM Case Temperature Rise from Ambient due to Bank Interleave 10 5 Reads with Auto Precharge DT7 UNUSED 5 QR Control EE QR ODT control for rank 0 and rank 1 reads and writes EE QR ODT1 and ODT2 control for reads ODT definition for rank 2 and 3 EE FBD ODT Definition Bit 1 Bit 0 Rank 0 ODT 150 Ohms Bit 3 Bit 2 TBD TBD Bit 5 Bit 4 Rank 1 ODT 150 Ohms Bit 7 Bit 6 TBD 0 UNUSED Channel Protocols Supported Least Significant Byte Bit 0 DDR2 Base Non ECC Protocol 0 10 Supported 02 Bit 1 DDR2 Base ECC Protocol 1 Supported Bit 7 Bit 2 TBD 0 Channel Pro2. DTM65517 DATARAM Differential Receiver Input Specification 8 GB 1Gx72 240 Pin FB DIMM Parameter Symbol MIN MAX Units Differential peak to peak input voltage VRX DIFFp p L 1 170 1300 mV VRX DIFFp p 2 VRX D VRX D Maximum single ended voltage for El condition DC AC VRX IDLE SE 2 3 4 65 mV y 7 VRX IDLE SE 35 mV Maximum single ended voltage for El condition DC only DC 2 3 4 5 Single ended voltage w r t VSS on D D VRX SE 4 300 900 Single pulse peak differential input voltage VRX DIFF PULSE 4 6 85 Amplitude ratio between adjacent symbols VRX DIFF ADJ E 3 1100mV lt VRX DIFFp p 7 RATIO HI 4 7 Amplitude ratio between adjacent symbols VRX DIFF ADJ 8 4 VRX DIFFp p 1100mV RATIO 4 7 Maximum RX inherent timing error 3 2 and 4 Gb s TRX TJ MAX 4 8 9 0 4 Maximum RX inherent deterministic timing error 3 2 and 4 TRX DJ DD 4 8 9 10 0 3 35 5 Single pulse width at zero voltage crossing TRX PW ZC 4 6 0 55 Single pulse width at minimum level crossing TRX PW ML 4 6 0 2 Differential RX input rise fall time given by 20 80 voltage TRX RISE TRX FALL 50 ps levels Common mode of the input voltage VRX CM 1 11 120 400 mV Defined as VRX CM DC avg of VRX D VRX D 2 AC peak to peak common mode of input voltage VRX CM VRX CM ACp p 1 270 m
3. DTM65517 P AVA TTA 6 GB 16372 240 Pin FB DIMM Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 35 mm high Data Transfer Rate 5 3 Gigabytes sec Operating Voltage VDD 1 8 V 0 1 VCC 1 5V 0 1 SMBus interface to AMB for configuration register access MBIST and IBIST test functions Transparent mode for DDR2 SDRAM test support Full DIMM Heat Spreader High speed differential point to point link Fully ROHS Compliant Identification DTM65517 1Gx72 8GB 4Rx4 PC2 5300F 555 11 AA0 Performance range Clock Module Speed CL tncp trp 333MHz DDR2 667 5 5 5 Description The DTM65517 is a Quad Rank PC2 5300 Fully Buffered 1Gx72 ECC DIMM that conforms to the JEDEC FB DIMM standard Twin sets of two ranks each are comprised of eighteen 512 DDR2 SDRAMs using Dual Die Packaging each die being 256Mx4 One IDT Rev L4 Advanced Memory Buffer AMB is used as the interface between the system memory bus and DIMM DRAMs One 2K bit EEPROM is used for Serial Presence Detect For improved thermal performance a Full DIMM Heat Spreader with thermal interface material TIM is attached to the front and back of the DIMM Pin Configurations Pin Names Front side Back side Pin Names Function 1 VDD 31 PN3 61 PN9 91 PS9 121 VDD 151 SN3 181 SN9 211 SS9 SCK SCK System Clock Input 2 VDD 32 3 62 VSS 92 VSS 122 VDD 152 SN3 182 VSS 212 VSS PN PN 13 0 Prima
4. 005 All dimensions are expressed millimeters inches Eee Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 2 DTM65517 poo yoo0 001 fO 1 32 DO3 DOSS9 Bass DOs 095 56 Da7 Das pos ach pas m Data 0 11 o1 0 353 0 10 Lp 00106 DO12 0 0 uoo DG13 0 0 0 01 5314 5 DQ15 DOS Das DQ16 07 0018 DA19 01 past pas 0 3 0 1 322 WO 2 0023 C 04 D925 DQ26 07 2 58513 325 Do28 330 001 pase Bass CBO CB1 VO 1 CB2 2 CBS Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 3 DTM65517 vss 31 53 50 52 354 Bast 5332 5 33 05534 D 35 6553 52213 DQ36 5357 DQ38 5559 Dass Doss peso DO41 D042 D443 04 4 ey 004 11 8 es tS 00s DO44 0 0 D045 1 D12 D046 0 2 5347 c 355 Bass DO48 Do49 0 0 post posts Doss om DOGO oo DOG I 0 008623 0 2 363 3 00517 D951 C84 0 cos vot 02 vo CB7 3 003 B0 x Motes Sms All adaress command control dock We 8 550559 vee Am tnn 22 di saa i EBT DOOTI 7 7 1 E SRT Notes
5. Row Address Bits A N Module Physical Attributes Bit 3 Bit 0 Module Thickness 7 lt x lt 8 0 Bit 4 Bit 2 Module Height mm 30 lt x lt 35 Bit 7 6 Reserved 0 N Module Type e N Bit 3 Bit 0 Module Type FB DIMM Bit 7 Bit 4 Reserved Reserved Module Organization Bit 3 Bit 0 SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved N eo Fine Timebase Dividend Divisor Bit 3 Bit 0 Fine Timebase FTB Dividend Bit 7 Bit 4 Fine Timebase FTB Divisor EE Medium Timebase Dividend D 25ns 4 MTB Medium Timebase Divisor A 25ns SDRAM Minimum Cycle Time tCKmin SDRAM Maximum Cycle Time tCKmax SDRAM CAS Latencies Supported 3 Bit 3 Bit 0 Minimum CL clocks 24 Bit 7 Bit 4 CL Range clocks 14 SDRAM Minimum CAS Latency Time tAAmin 6 SDRAM Write Recovery Times Supported 5 Bit 3 Bit 0 Minimum WR clocks 42 Bit 7 Bit 4 WR Range clocks 16 SDRAM Write Recovery Time tWR 30 SDRAM Write Latencies Supported Bit 3 Bit 0 Minimum WL clocks 2 Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 14 DTM65517 ral ai 6 68 16372 240 Pin FB DIMM Bit 7 Bit 4 WL Range clocks 4 SDRAM Additive Latencies Supported Bit 3 Bit 0 Minimum AL clocks Bit 7 Bit 4 AL Range clock
6. ini n meet gt q n i hk T ES ChE pieca osoro 1 DO to l O wiring may be changed within a nibble 7 er DADDA at SCRAM 2 There are two physical copies of each address command control excluding CS TEWT Pee ECCAE NC 3 There are four physical copies of each clock 4 ECCA2 and ECCAS does not use NC ee 5 ODT pin D0 D35 is connected to VSS Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 4 DTM65517 8 GB 1Gx72 240 Pin FB DIMM DATARAM Absolute Maximum Ratings Parameter Symbol Rating Unit Note Temperature DDR2 DRAM Case Tcase 0 to 95 1 2 Temperature Storage Tere 55 to 100 1 Voltage on any pin relative to Vss Vin Vout 0 3 to 1 75 1 Voltage on Vcc relative to Vss Vcc 0 3 to 1 75 V 1 Voltage on Vpp relative to Vss VoD 0 5 to 2 3 1 Voltage on Vrr relative to Vss Vit 0 5 to 2 3 1 Power Dissipation Pp 21 1 Notes 1 Operation at or above absolute maximum rating can adversely affect device reliability 2 For 85C lt Tease lt 95 C treri 3 9 US max DC Operating Conditions Ta 0 to 70 C Voltage referenced to Vss OV Parameter Symbol Minimum Typical Maximum Unit Note AMB Supply Voltage Voc 1 455 1 5 1 575 V DDR2 Supply Voltage Vpp 1 7 1 8 1 9 V Termination Voltage Vit 0 48 x VDD 0 50 x VDD 0 52 x VDD EEPROM Supply Voltage SPD VppsPD 3 0 3 3 3
7. Cyclical Redundancy Code CRC 127 Cyclical Redundancy Code CRC 28 131 Module Part Number 132 Module Part Number 133 Module Part Number 47 3A 5F 4F 93 94 97 98 99 100 101 102 103 104 105 106 107 108 109 _ 110 EM 112 M3 114 115 M6 11 118 19 126 127 132 133 EE 135 136 94 97 o 100 101 102 103 104 N O oe 134 Module Part Number 135 Module Part Number 136 Module Part Number ojl 2 o o 24 94 20 44 41 54 41 52 Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 17 DTM65517 JAVA VITAE 6 GB 16372 240 Pin FB DIMM 137 1465 ModuePatNumper ooo ool 146 147 Module Revision Gedo UNUSED 00 148 149 SDRAM Manufacturers JEDECID Code UNUSED 00 150 MamfaduersSpedfcDaa To 151 Manufacturers Specie Daa To 152 175 Manufacturer s Specific Daa UNUSED 00 176 255 Open for customeruse_______ UNUSED 00 prm P OERERERERBRB M M a Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 18 DTM65517 DJAUAUAUI 6 GB 16372 240 Pin FB DIMM DATARAM DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princet
8. tRESAMPLE AMB 58 the measured delay at AMB balls between the center of the first UI of a frame on primary southbound lane 8 AMB balls U29 and U28 and the center of the first UI of the same frame on secondary southbound lane 8 AMB balls Y26 and W26 4 tRESYNC AMB NBis the measured delay at AMB balls between the center of the first Ul of a frame on secondary northbound lane AMB balls V4 and V5 and the center of the first UI of the same frame on primary northbound lane 0 AMB balls U1 and U2 5 tREsYNC AMB SB is the measured delay at AMB balls between the center of the first UI of a frame on primary southbound lane 8 AMB balls U29 and U28 and the center of the first UI of the same frame on secondary southbound lane 8 AMB balls 6 and W26 eee Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 10 DTM65517 0 1 8 GB 1Gx72 240 011 FB DIMM AMB Power Specification Ta 0 to 70 C Voltage referenced to Vss OV Parameter Symbol Test Condition E ower Value Unit upply Idle Single or last FBDIMM LO state idle 0 BW primary channel 1 5V 2200 Current IDD IDLE O enabled secondary channel disabled CKE high command and mA address lines stable DDR2 SDRAM clock active 1 8V 900 Idle First FBDIMM LO state idle 0 BW primary and secondary 1 5V 3000 Current IDD IDLE 1 channels enabled CKE high command and address lines mA stable DDR2 SDRAM clock active 1
9. 19 RFU2 49 PN12 79 PS3 109 VDD 139 RFU2 169 SN12 1199 553 229 ISCK M_TEST Margin Test 20 RFU2 50 VSS 80 PS3 110 VSS 140 RFU2 170 VSS 200 SS3 230 VSS SA 2 0 Serial Address EEPROM 21 VSS 51 PN6 81 VSS 111 VDD 141 VSS 171 SN6 201 VSS 231 VDD 22 PNO 52 6 82 PS4 112 VDD 142 SNO 172 ISN6 202 554 232 VDD 23 PNO 53 VSS 83 4 113 VDD 143 SNO 173 VSS 203 4 233 VDD 24 VSS 54 PN7 84 VSS 114 VSS 144 VSS 174 7 204 VSS 234 VSS 25 55 7 85 VSS 115 VDD 145 1 175 ISN7 205 VSS 235 VDD 26 PN1 56 VSS 86 RFU1 116 VDD 146 SN1 176 VSS 206 RFU1 236 VDD 27 VSS 57 PN8 amp 87 RFU1 117 VTT 147 VSS 177 SN8 207 RFU1 237 VTT 28 PN2 58 8 88 VSS 118 SA2 148 SN2 178 SN8 208 VSS 238 VDDSPD 29 PN2 59 VSS 89 VSS 119 SDA 149 SN2 179 VSS 209 VSS 239 SAO 30 VSS 60 9 90 PS9 120 SCL 150 VSS 180 SN9 210 SS9 240 SA1 NOTE M TEST is not used Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 1 DTM65517 2 6 GB 16372 240 Pin FB DIMM Front view B 133 35 5 250 9 50 3 00 0 118 0 374 30 35 1 191 17 30 A 0 681 Y 0 197 2 50 Min 5 18 67 00 51 00 0 098 Min 0 204 2 638 2 008 gt 123 00 4 843 Back view Side view 7 49 Max 0 295 Max w heatspearder 4 00 Min 0 157 Min 1 27 0 de 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 2 13
10. 6 V Input High Voltage SPD 1 Input Low Voltage SPD ViL DC 1 0 0 8 V 1 Input High Voltage RESET BFUNC V H DC 1 0 2 Input Low Voltage RESET BFUNC 0 5 2 Leakage Curent RESET BFUNC IL 90 90 2 Leakage Curent Link 8 5 5 Notes 1 Applies to SMB and SPD bus signals 2 Applies to AMB CMOS signal RESET Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 5 DTM65517 DATARAM Differential Transmitter Output Specification 8 GB 1Gx72 240 Pin FB DIMM Parameter Symbol MIN MAX Units Differential peak to peak output voltage for large voltage VTX DIFFp p L 1 900 1300 mV swing VTX DIFFp p 2 VTX D VTX D Differential peak to peak output voltage for regular voltage VTX DIFFp p R 1 800 mV swing VTX DIFFp p 2 VTX D VTX D Differential peak to peak output voltage for small voltage VTIX DIFFp p S 1 520 us mV swing VTX DIFFp p 2 VTX D VTX D DC common code output voltage for large voltage swing VTX CM L 1 m 375 mV Defined as VTX CM DC avg of VTX D VTX D 2 DC common mode output voltage for small voltage swing VTX CM 1 135 280 mV Defined as VTX CM DC avg of VTX D VTX D 2 De emphasized differential output voltage ratio for 3 5 dB VTX DE 3 5 3 4 dB de emphasis Ratio 1 2 3 De emphasized differentia
11. 8V 900 TDP BW Single or Last DIMM LO State TDP Channel 45V 2600 Active 30 TDP 0 BW 2 4GB s 667 67 READ 33 WRITE primary channel A Power enabled secondary channel disabled CKE high command and 48V 1600 m address lines stable DDR2 SDRAM clock active i TDP BW First DIMM LO State TDP Channel 15 3300 Active IDD_TDP_1 BW 2 4GB s 667 DIMM BW 1 6GB s 667 67 READ 33 Power WRITE primary channel enabled secondary channel enabled mA CKE high command and address lines stable DDR2 SDRAM 1 8V 1400 clock active IDD TRAINING Primary and secondary channels enabled 100 toggle on all 1 5V 3500 Training z channel lanes DDR2 SDRAM devices idle 0 BW CKE HIGH mA command and address lines stable DDR2 SDRAM clock active 1 8 V 900 EE Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 11 DTM65517 0 1 8 GB 1Gx72 240 011 FB DIMM DRAM AC Characteristics AC operating conditions unless otherwise noted Min Max Parameter Symbol Unit Note Value Value Row Cycle Time 60 5 Auto Refresh Row Cycle Time 127 5 8 Row Active Time tras 45 70K ns Row Address to Column Address Delay treco 15 ns Row Active to row Active Delay 586 7 5 ns Column Address to Column Address Delay 660 2 CLK Row Precharge time trp 15 ns Write Recovery Time twn 15 ns Auto Prech
12. T AMB Active 1 C oz o o WwW o 3 c E o EX 5 gt o gt 5 gt Q lt AMB Case Temperature Rise from Ambient due to AMB in Active_2 92 State DT AMB Active 2 C AMB Case Temperature Rise from Ambient due to AMB in LOs State UNUSED DT AMB LOs C Reserved MB Junction Temperature Maximum Tjmax C Reserved Reserved MB Personality Bytes Pre initialization MB Personality Bytes Pre initialization MB Personality Bytes Pre initialization MB Personality Bytes Pre initialization 105 MB Personality Bytes Pre initialization 106 MB Personality Bytes Pre initialization 107 AMB Personality Bytes Post initialization 108 MB Personality Bytes Post initialization 109 AMB Personality Bytes Post initialization 110 MB Personality Bytes Post initialization 111 45 Personality Bytes Post initialization 112 MB Personality Bytes Post initialization 113 AMB Personality Bytes Post initialization 114 MB Personality Bytes Post initialization 115 AMB Manufacturer s JEDEC ID Code 116 AMB Manufacturer s JEDEC ID Code 117 Module ID Module Manufacturer s JEDEC ID Code 118 Module ID Module Manufacturer s JEDEC ID Code 119 Module ID Module Manufacturing Location 20 121 Module ID Module Manufacturing Date 22 125 Module ID Module Serial Number serial number 126
13. V AC Max VRX D VRX D 2 Min VRX D VRX D 2 Ratio of VRX CM ACp p to minimum VRX DIFFp p VRX CM EH Ratio 12 45 96 Differential return loss RLRX DIFF 9 E dB Measured over 0 1 GHz to 2 4GHz Common mode return loss RLRX CM 6 m dB Measured over 0 1 GHz to 2 4GHz RX termination resistance RRX 13 41 55 Q D D RX resistance difference RRX Match DC 4 RRX Match DC 2 RRX D RRX D RRX D RRX D Lane to lane PCB skew at RX LRX PCB SKEW 14 6 Lane to Lane PCB skew at the Receiver that must be tolerated Minimum RX Drift Tolerance TRX DRIFT 15 400 0 5 Minimum data tracking 348 bandwidth FTRK 16 0 2 E MHz um TEI ENTRY 60 is Electrical idle entry detect time DETECT 17 Electrical idle exit detect time TEI EXIT DETECT 30 ns Bit Error Ratio BER 18 10 Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 8 DTM65517 2 6 68 16372 240 Pin FB DIMM NOTES FOR RECEIVER INPUT SPECIFICATIONS 1 Specified at the package pins into a timing and voltage compliant test setup Note that signal levels at the pad are lower than at the pin 2 Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition Worst case margins are determined by comparing El levels with common mode levels during normal operation for the case with transmitter usi
14. arge Write Recovery Precharge Time pA twn M inl ns System Clock Cycle Time tck 3000 8000 ps Clock High Level Width tcu 0 45 0 55 CLK Clock Low Level Width teL 0 45 0 55 CLK DQ output access time from CK 8 CK tac 0 500 0 500 ns DQS Out edge to Clock Edge skew toasck 0 450 0 450 ns DQS Out edge to Data out edge skew 15656 0 300 8 Data Out hold time from DQS tou tup tous ns 1 Data hold skew factor 985 0 400 5 1 Clock Half Period tup min teL 6 ns 1 Input Setup Time fast slew rate tis 0 250 ns 2 3 5 6 Input Hold Time fast slew rate 0 375 ns 2 3 5 6 Input Pulse Width tipw 0 6 CLK 6 Write DQS High Level Width 15088 0 35 CLK Write DQS Low Level Width toast 0 35 CLK CLK to First Rising edge to DQS In 10655 WL 0 25 WL 0 25 CLK Data In Setup Time to DQS In DQ amp DM tos 0 100 ns 7 Data In Hold Time to DQS In DQ amp DM tou 0 225 ns 7 Notes 1 This calculation accounts for tposo max the pulse width distortion of on chip and jitter 2 Data sampled at the rising edges of the clock 13 BAO BA2 CKE S 1 0 RAS CAS WWE 3 For command address input slew rate gt 1 0 V ns 4 For command address input slew rate gt 0 5 V ns and 1 0 V ns 5 CK CK slew rates are gt 1 0V ns 6 These Parameters guarantee device timing but they are not necessarily tested on each device and they may be guaranteed by design or tester correlation 7 Data latched at both risi
15. atch DC 4 RTX Match DC 2 RTX D RTX D RTX D RTX D Bounds are applied separately to high and low output voltage states Lane to lane skew at TX LTX SKEW 1 14 16 100 3UI ps Lane to lane skew at TX LTX SKEW 2 15 16 100 2UI ps TTX DRIFT 240 5 Maximum TX Drift resync mode RESYNC 17 Maximum TX Drift resample mode only TTX DRIFT n 120 ps RESAMPLE 17 Bit Error Ratio 558 18 10 Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 6 0 1 7 NOTES FOR TRANSMITTER OUTPUT SPECIFICATIONS 1 Specified at the package pins into a timing and voltage compliance test load Common mode measurements are performed using a 101010 pattern 2 This is the ratio of the VTx DIFFp p of the second and following bits after a transition divided by the VTx DIFFp p of the first bit after a transition De emphasis is disabled in the calibration state Includes all sources of AC common mode noise Single ended voltages below that value that are simultaneously detected 0 and D are interpreted as the Electrical Idle condition 6 Specified at the package pins into a voltage compliance test load Transmitters meet both single ended and differential output E1 specifications 7 This specification considered with VRx iDLE sE pc implies a maximum 15mV single ended DC offset between Tx and Rx pins during the electrical idle condition This in turn allows a grou
16. fset between transmit and receive devices 12 The received differential signal satisfies both this ratio as well as the absolute maximum AC peak to peak common mode specification For example if VRX DIFFp p is 200mV the maximum AC peak to peak common mode is the lesser of 200 mV 0 45 90mV and VRX CM ACp p 13 The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 5Q with regard to the average of the values measured at 100mV and at 400mvV for that pin 14 This number represents the lane to lane skew between TX and RX pins and does not include the transmitter output skew from the component driving the signal to the receiver This is one component of the end to end channel skew in the AMB specification 15 Measured from the reference clock edge to the center of the input eye This specification is met across specified voltage and temperature ranges Drift rate of change is significantly below the tracking capability of the receiver 16 This bandwidth number assumes the specified minimum data transition density Maximum jitter at 0 2MHz is 0 05UI 17 The specified time includes the time required to forward the El entry condition 18 BER per differential lane Or Boo zo Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 9 DTM6551 7 Advanced Memory Buffer FBD Timing Electrical Parameter Symbol MIN MAX Units El Assertion Pass Through Timin
17. g tEl PROPAGATE 4 CLKs El Deassertion Pass Through Timing tEID tBitlock CLKs El Assertion Duration 100 CLKs Bit Lock Interval tBITLOCK 119 Frames Frame Lock Interval tFRAMELOCK 154 Frames Advanced Memory Buffer Latency Parameters Parameter Symbol MIN MAX Units CMD to Data Latency Data Rate 533 tC2D AMB 20 3 25 1 ns tRESAMPLE AMB NB 0 9 22 Hs Resample Delay RESAMPLE AMB SB tRESYNC AMB NB 23 3 9 ns Resync Delay tRESYNC AMB SB Notes 1 tc2D_AmB is the measured delay at AMB balls between the center of the first Ul command frame on primary southbound lane 8 AMB balls U29 and U28 and the center of the first UI of return on primary northbound lane 0 AMB balls U1 and U2 CL DRAM CAS latency value frame clock period AL DRAM additional latency value frame clock period This definition assumes that SB lane 8 is the latest lane to arrive at the AMB balls This will typically be the case since SB lane 8 is the longest SB lane on FBDIMMs If due to large lane to lane skew at the DIMM gold finger another lane is the latest lane to arrive at the AMB balls this other lane must be used instead for the 1 2 AMB measurement 2 tRESAMPLE AMB 8 the measured delay at AMB balls between the center of the first UI of a frame on secondary northbound lane 0 AMB balls V4 and V5 and the center of the first UI of the same frame on primary northbound lane 0 AMB balls U1 and U2 3
18. l output voltage ratio for 6 dB de VTX DE 6 Ratio 1 2 3 _5 7 dB emphasis AC peak to peak common mode output voltage for large VTX CM ACp p L 1 4 ES 90 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX D VTX D 2 AC peak to peak common mode output voltage for regular VTX CM ACp p R 1 4 8 80 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX D VTX D 2 AC peak to peak common mode output voltage for small VTX CM ACp p S 1 4 70 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX D VTX D 2 Maximum single ended voltage in El condition DC AC VTX IDLE SE 5 6 die 50 mV Maximum single ended voltage in El condition DC only E nus 20 mV Maximum peak to peak differential voltage in El condition VTX IDLE DIFFp p 6 m 40 mV Single ended voltage w r t VSS on D D VTX SE 1 7 75 750 Minimum TX eye width 3 2 and 4 Gb s TTX Eye MIN 1 9 10 0 7 ES UI Maximum TX deterministic jitter 3 2 and 4 Gb s TTX DJ DD 1 9 10 11 E 0 2 Ul Instantaneous pulse width TTX PULSE 12 0 85 I Ul Differential TX output rise fall time TTX RISE TTX 30 90 ps Given by 2076 8096 voltage levels FALL 1 Mismatch between rise and fall times TTX RF MISMATCH 20 ps Differential return loss RLTX DIFF 8 Be dB Measured over 0 1 GHz to 2 4GHz Common mode return loss RLTX CM 6 EN dB Measured over 0 1 GHz to 2 4GHz Transmitter termination resistance RTX 13 41 55 Q D D TX resistance difference RTX M
19. nd offset between adjacent FB DIMM agents of 26mV when worst case termination resistance matching is considered 8 The maximum value is specified to be at least VTX DIFFp p L 4 VTX CM VTX CM ACp p 2 9 This number does not include the effects of SSC or reference clock jitter 10 These timing specifications apply to resync mode only 11 Defined as the dual dirac deterministic jitter as described in Section 4 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8 12 Pulse width measured at OV differential 13 The termination small signal resistance tolerance across voltages from 100mV to 40011 shall not exceed 5 with regard to the average of the values measured at 100mV and at 400mvV for that pin 14 Lane to Lane skew at the Transmitter pins for an end component 15 Lane to Lane skew at the Transmitter pins for an intermediate component assuming zero Lane to Lane skew at the Receiver pins of the incoming PORT 16 This is a static skew A FB DIMM component is not allowed to change its lane to lane phase relationship after initialization 17 Measured from the reference clock edge to the center of the output eye This specification is met across specified voltage and temperature ranges for a single component Drift rate of change is significantly below the tracking capability of the receiver 18 BER per differential lane ako Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 7
20. ng and falling edges of Data Strobes DQS Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 12 DTM65517 0 1 8 GB 1Gx72 240 011 FB DIMM AC Operating Conditions AC operating conditions unless otherwise noted Min Max 2 Parameter Symbol Unit Note Value Value DQ Input Pulse Width toipw 0 35 CLK Read DQS Preamble Time tRPRE 0 9 1 1 CLK Read DQS Postamble Time trest 0 4 0 6 CLK Write DQS Preamble Hold Time twPRE 0 35 CLK Write DQS Postamble Time twPsT 0 4 0 6 CLK Mode Register Set Delay trp 2 CLK Exit Self Refresh to Non Read Command txsnr tRFC 10 ns Exit Self Refresh to Read Command 586 200 CLK m E 7 8 Hs 1 Average Periodic Refresh Interval 3 9 us 2 Notes 1 For0C lt Tease 85 C 2 For 85C lt Tease 95 C Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 13 DTM65517 P AVA VITAE 6 GB 16372 240 Pin FB DIMM SERIAL PRESENCE DETECT MATRIX Number of SPD Bytes Written SPD Device Size CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 D DDR2 Byte DRAM Device Type FBDIMM Voltage Levels of this Assembly Bit 3 Bit 0 Power Supply 1 1 5V Bit 7 Bit 4 Power Supply 2 1 8V SDRAM Addressing Bit 1 0 Number of Banks Bit 5 Bit 3 Column Address Bits Bit 7 Bit 5
21. ng small voltage swing see RX Single ended Electrical Idle Levels and RX Common Mode Levels Multiple lanes need to detect the El condition before the device can act upon the detection Specified at the package pins into a timing and voltage compliance test setup This specification considered with VTx IDLE SE Dc implies a maximum 15mV single ended DC offset between TX and RX pins during the elecrical idle condition This in turn allows a ground offset between adjacent FB DIMM of 26mV when worstcase termination resistance matching is considered 6 The single pulse mask provides sufficient symbol energy for reliable RX reception Each symbol complies with both the single pulse mask and the cumulative eye mask see RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Early and RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Late 7 The relative amplitude ratio limit between adjacent symbols prevents excessive inter symbol interference in the Rx Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols see RX Maximum Adjacent Symbol Amplitude This number does not include the effects of SSC or reference clock jitter This number includes setup and hold of the RX sampling flop 0 Defined as the dual dirac deterministic timing error as described in Section 4 2 2 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8 11 Allows for 15mV DC of
22. on NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 19
23. ry Northbound Data 3 VDD 33 VSS 63 PN10 93 PS5 123 VDD 153 VSS 183 SN10 213 SS5 PS PS 9 0 Primary Southbound Data 4 VSS 34 PN4 64 PN10 94 PS5 124 VSS 154 4 184 SN10 214 SS5 SN SN 13 0 Secondary Northbound Data 5 VDD 35 65 VSS 95 VSS 125 VDD 155 SN4 185 VSS 215 VSS SS SS 9 0 Secondary Southbound Data 6 VDD 36 VSS 66 PN11 96 PS6 126 VDD 156 VSS 186 SN11 216 556 SCL Serial Clock EEPROM 7 VDD 37 PN5 67 PN11 97 PS6 127 VDD 157 SN5 187 SN11 217 SS6 SDA Serial Data EEPROM 8 VSS 38 68 VSS 98 VSS 128 VSS 158 5 188 VSS 218 VSS RESET AMB Reset Signal 9 VCC 39 VSS 69 VSS 99 129 VCC 159 VSS 189 VSS 219 SS7 VCC AMB Core Power and AMB Channel 10 VCC 40 PN13 70 PSO 100 PS7 130 VCC 160 SN13 190 SSO 220 SS7 Interface Power 1 5 V 11 VSS 41 PN13 71 0 101 VSS 131 VSS 161 SN13 1191 0 221 VSS VDD DRAM Power and AMB DRAM 12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 VSS 192 VSS 222 SS8 Power 1 8 V 13 VCC 43 VSS 73 1 103 PS8 133 VCC 163 VSS 193 SS1 223 SS8 VTT DRAM Address Command Clock 14 VSS 44 RFU 74 51 104 VSS 134 VSS 164 RFU1 194 SS1 224 VSS Termination Power VDD 2 15 VTT 45 RFU 75 VSS 105 RFU2 135 VTT 165 8 1 195 VSS 225 RFU2 VDDSPD SPD Power 16 VID1 46 VSS 76 PS2 106 RFU2 136 VIDO 166 VSS 196 SS2 226 RFU2 VSS Ground 17 RESET 47 VSS 77 52 107 VSS 137 M_TEST 167 VSS 197 SS2 227 VSS RFU Reserved For Future Use 18 VSS 48 PN12 78 VSS 108 VDD 138 VSS 168 SN12 198 VSS 228 SCK DNU Do Not Use
24. s 19 SDRAM Minimum RAS to CAS Delay tRCD E mE 20 S SDRAM Minimum Row Active to Row Active Delay tRRD 21 SDRAM Minimum Row Precharge Time tRP SDRAM Upper Nibbles for tRAS and tRC Bit 3 Bit 0 tRAS Most Significant Nibble Bit 7 Bit 4 tRC Most Significant Nibble 7 SORA Minimum Ave 7 RC m f Fo 25 S SDRAM Minimum Refresh Recovery Time Delay tRFC LSB 127585 FE 26 15 SDRAM Minimum Refresh Recovery Time Delay tRFC MSB 127585 01 E LD 989189 SDRAM Minimum Internal Read to Precharge Command Delay IRTP 7 5ns SDRAM Burst Lengths Supported Bit 0 BL 4 Bit 1 BL 8 Bit 6 Bit 2 8 Bit 7 Burst Chop o SDRAM Terminations Supported Bit 0 150 ohms ODT Bit 1 75 ohms ODT Bit 2 50 ohms ODT Bit 6 Bit 3 TBD eo N SDRAM Drivers Supported Bit 0 Weak Driver Bit 7 Bit 1 TBD Temperature self refresh rate support indication Bit 0 Bit 3 Average Refresh Interval tREFI uS 7 8 Bit 5 Bit 4 TBD 0 Bit 6 High Temperature Self Refresh _1 Required Bit 7 Double Refresh Requirement 1 5006 0 Tcasemax Delta Bit 3 8 0 DT4R4W Delta Subfield 6 0 4 C Bit 7 Bit 4 Tcasemax Subfield A 2 C Thermal Resistance of SDRAM Package C W SDRAM Case Temperature Rise from Ambient due to Activate Precharge minus 2 8 C offset temperature DTO
25. tocols Supported Most Significant Byte UNUSED 0 Bit 1 Bit 0 Rank Read to Read 0 add l clock Bit 3 Bit 2 Write to Read 0 add l clock Bit 5 Bit 4 Read to Write 1 add l clock Bit 7 Bit 6 TBD 0 AMB Read Access Time for DDR2 800 AMB LINKPARNXT 1 0 11 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK AMB Read Access Time for DDR2 667 AMB LINKPARNXT 1 0 10 46 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity AMB Read Access Time for 00852 533 AMB LINKPARNXT 1 0 01 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK Thermal Resistance of AMB Package from Top Case to Ambient Psi T A AMB C W AMB Case Temperature Rise from Ambient due to AMB in Idle O State DT AMB Idle 0 538 76 EUM g 80 82 E to back Turnaround Cycles 10 Document 06051 Revision A 24 Jul 08 Dataram Corporation 2008 Page 16 DTM65517 JAVA TTA 6 68 16372 240 Pin FB DIMM AMB Case Temperature Rise from Ambient due to AMB in Idle_1 71 DT AMB Idle_1 C 58 95 79 CD cet D oz n 4o c ZU o ut 9 3 gt 3 c 2 o o gt 5 a DT AMB Idle_2 C D
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