Dataram 8GB, 240-Pin, DDR3
Contents
1. Bit 1 Bit 0 RC2 DA3 4 Value RESERVED Bit 3 Bit 2 RC2 DBAO 1 Value RESERVED Bit 5 Bit 4 RC3 DA4 3 value Command Address A Outputs Moderate Bit 7 Bit 6 RC3 DBAO 1 value Command Address B Outputs Moderate SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Control and Clock 71 Bit 1 Bit 0 RC4 DA3 4 Control Signals A Outputs Moderate 0x55 Bit 3 Bit 2 RC4 DBAO 1 Control Signals B Outputs Moderate Bit 5 Bit 4 RC5 DA4 3 value Y1 Y1 and Y3 Y3 Clock Outputs Moderate Bit 7 Bit 6 RC5 DBAO 1 value YO YO and Y2 Y2 Clock Outputs Moderate 72 SSTE32882 RC7 MS Nibble RC6 LS Nibble Reserved UNUSED 0x00 73 SSTE32882 RC9 MS Nibble RC8 LS Nibble Reserved UNUSED 0x00 74 SSTE32882 RC11 MS Nibble RC10 LS Nibble Reserved UNUSED 0x00 75 SSTE32882 RC13 MS Nibble RC12 LS Nibble Reserved UNUSED 0x00 76 SSTE32882 RC15 MS Nibble RC14 LS Nibble Reserved UNUSED 0x00 77 116 Module Specific Section UNUSED 0x00 117 Module Manufacturer ID Code Least Significant Byte 0x80 118 Module Manufacturer ID Code Most Significant Byte OxCE 119 Module Manufacturing Location 0x01 120 Module Manufacturing Date 0x10 121 Module Manufacturing Date 0x22 122 Module Serial Number 0x08 123 Module Serial Number 0x16 124 Module Serial Number OxCC 125 Module Serial Number OxEE 126 Cyclical Redundancy Code CRC 0x69 127 Cyclical Redundancy Code CRC2. Divisor 9 Bit 3 Bit 0 Fine Timebase FTB Divisor 2 0x52 Bit 7 Bit 4 Fine Timebase FTB Dividend 5 1 MTB 10 Medium Timebase MTB Dividend 0 125ns Oxo 8 MTB 11 Medium Timebase MTB Divisor 0 125ns Vage 12 SDRAM Minimum Cycle Time tCKmin 1 5ns 0x0C 13 Reserved UNUSED 0x00 14 CAS Latencies Supported Least Significant Byte 0x3C Bit 0 CL 4 Bit 1 CL 5 Bit 2 Always 1 CL 6 X Document 06015 Revision A 10 Sep 10 Dataram Corporation 2010 Page 8 DTM64316E IZRRATARAM ptimizing Value and Performance 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Bit 3 CL 7 X Bit 4 CL 8 X Bit 5 CL 9 X Bit6 CL 10 Bit 7 CL 11 CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 15 Bit 3 CL 15 0x00 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 13 125ns 0x69 17 Minimum Write Recovery Time tWRmin 15 0ns 0x78 18 Minimum RAS to CAS Delay Time tRCDmin 13 125ns 0x69 19 Minimum Row Active to Row Active Delay Time tRRDmin 6 0ns 0x30 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x69 Upper Nibbles for tRAS and tRC 21 Bit 3 Bit 0 tRAS Most Significant Nibble 1 0x11 Bit 7 Bit 4 tRC Most Significant Nibble 1 22 val Active to Precharge
3. DQ 63 0 O VAW O DQR 63 0 Ki Voospo __ Serial PD CB 7 0 O WW O CBRI T 0 a 22 OHMS _ VDD All Devices ee VREF_DQ All SDRAMs DQS 17 0 O VWA O__DASRI17 0 181 AM IRS V All Devi BA 2 0 WM BA 2 0 R ss evices DQS 17 0 O VA O DQSR 17 0 A 15 0 Ww A I5 0 R VREF_CA All SDRAMs IRAS WA IRASR Vi alll SDRAMs GLOBAL SDRAM CONNECTS Mec en Te ee All 36 OHMS CKE 1 0 y n a 36 OHMS ena i CKERT1 0 LCLK 1 0 O VWW O LCLK 1 0 2 0 R A 15 0 R ODT 1 0 Vw 2 ODTR 1 0 RCLK 1 0 O VA O_ RCLK 1 0 RASR x PARIN AA 4 ERR_OUT CASR ki ERCH EVENT IWER VTT 150 i OHMS All 240 OHMS ICKO J ILR CLK 1 0 TEMPERATURE MONITOR ung al 2 SDA SA0 SA1 SA2 CKE 1 0 R ODT 1 0 R owd IRS 1 0 VIT ie Ol ec SDRAMS ZQ a Vss Document 06015 Revision A 10 Sep 10 Dataram Corporation 2010 Page 3 DTM64316E 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM IN2DATARAM Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TSTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tcase 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 9
4. 09 DQ44 239 Vss 30 DQ24 60 Vop 90 DQ40 120 Vr 150 DQ29 180 A3 210 DQ45 240 Vz Not used Document 06015 Revision A 10 Sep 10 Dataram Corporation 2010 Page 1 ye DIM64316E EE GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Front view 133 35 i 5 250 M A oso 0 374 30 00 I il E 0 681 Nnnn nnnm NNNnnn nnnm Y 5 00 4 pee 19 098 5 175 47 00 10 204 AA 1 850 or Ena gt 123 00 i 4 843 g Back view Side view 3 94 Max 0 155 Max M 0 L _ 0 157 Min O MAMMAM nnnm 4 Annman nnmnnn O 1 27 10 ml 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches A A A A A Page 2 Document 06015 Revision A 10 Sep 10 Dataram Corporation O 2010 aa DTM64316E Op
5. 0x1D 128 Module Part Number M 0x4D 129 Module Part Number 3 0x33 130 Module Part Number 9 0x39 131 Module Part Number 3 0x33 132 Module Part Number B 0x42 133 Module Part Number 1 0x31 134 Module Part Number K 0x4B 135 Module Part Number 7 0x37 136 Module Part Number 0 0x30 137 Module Part Number C 0x43 138 Module Part Number H 0x48 139 Module Part Number 0 0x30 Document 06015 Revision A 10 Sep 10 Dataram Corporation 2010 Page 11 Tag DTM64316E EE SGB 240 Pin 2Rx4 Registered ECC DDR3 DIMM 140 Module Part Number 0x2D 141 Module Part Number C 0x43 142 Module Part Number H 0x48 143 Module Part Number 9 0x39 144 Module Part Number 0x20 145 Module Part Number 0x20 146 Module Revision Code UNUSED 0x00 147 Module Revision Code UNUSED 0x00 148 DRAM Manufacturer ID Code Least Significant Byte 0x80 149 DRAM Manufacturer ID Code Most Significant Byte OxCE 150 175 Manufacturer s Specific Data UNUSED 0x00 176 255 Open for customer use UNUSED 0x00 Document 06015 Revision A 10 Sep 10 Dataram Corporation 2010 Page 12 eye DTM64316E GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM IN2DATARAM Zd Wa Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has
6. 75 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions Ta O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V 1 0 Reference Voltage VREFDQ 0 49 Vpp 0 50 Vpop 0 51 Voo V 1 1 O Reference Voltage VREFCA 0 49 Voo 0 50 Vpp 0 51 Voo V 1 Notes 1 The value of Vrer is expected to equal one half Voo and to track variations in the Voo DC level Peak to peak noise on Vrer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH DC Vrer 0 1 Vpop V Logical Low Logic 0 Vic Vss Vrer 0 1 V AC Input Logic Levels Single Ended T O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 175 V Logical Low Logic 0 ViL ac Vrer 0 175 V A a AA AER A AAA A A Document 06015 Revision A 10 Sep 10 Dataram Corporation O 2010 Page 4 IN2IDATARAM Optimizing Value and Performance DTM64316E 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential I
7. AM Device Type Std Mono 0x00 34 59 Reserved UNUSED 0x00 Module Nominal Height 60 Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 Ox0F Bit 7 Bits Reserved 0 Module Maximum Thickness 61 Bit3 BitO Front inmm baseline thickness 1mm 1 lt th lt 2 0x11 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 Reference Raw Card Used 62 Bit 4 Bit O Reference Raw Card RICE 0x24 Bit 6 Bit 5 Reference Raw Card Revision Rev 1 Bit 7 Reserved 0 Registered DIMM Module Attributes 63 Bit 1 Bit O of Registers used on RDIMM 1 Register 0x09 Bit 3 Bit 2 of Rows of DRAMs on RDIMM 2 Rows Bit 7 Bit 4 Reserved 0 RDIMM Thermal Heat Spreader Solution 64 Bit 6 Bit O Heat Spreader Thermal Characteristics 0 0x00 Bit 7 Heat Spreader Solution No HS 65 Register Manufacturer ID Code Least Significant Byte Optional 0x80 66 Register Manufacturer ID Code Most Significant Byte Optional OxB3 67 Register Revision Number Optional 0x61 Register Type 68 Bit 2 0 Support Device SSTE32882 0x00 Bit 7 3 Reserved 0 69 SSTE32882 RC1 MS Nibble RCO LS Nibble Reserved UNUSED 0x00 70 SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength 0x50 Command Address Document 06015 Revision A 10 Sep 10 Dataram Corporation 2010 Page 10 Ta DTM64316E EE SGB 240 Pin 2Rx4 Registered ECC DDR3 DIMM
8. CB6 194 Vop 224 DQ54 SCL SPD Clock Input 15 DQS1 45 CB2 75 Voo 105 Daso 135 DQS10 165 CB7 195 ODTO 225 DQ55 SDA SPD Data Input Output 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss EVENT Temperature Sensing 17 Vss 47 Vss 77 ODT1 107 Vss 137 DQ14 167 NC TEST 197 Vpp 227 DQ60 IRESET Reset for register and DRAMs 18 DQ10 48 Vrr 78 Voo 108 DQ56 138 DQ15 f168 RESET 198 S3 NC 228 DQ61 PAR_IN Parity bit for Addr Ctrl 19 DQ11 49 Vir 79 S2 NC 109 DQ57 139 Vss 169 CKE1 199 Vss 229 Vss ERR_OUT Error bit for Parity Error 20 Vss 50 CKEO 80 Vss 110 Vss 140 DQ20 170 Voo 200 Da36 230 DQS16 A12 BC Combination input Addr12 Burst Chop 21 DQ16 51 Voo 81 Da32 111 Das7 141 DQ21 171 A15 201 DQ37 231 DQS16 A10 AP Combination input Addr10 Auto precharge 22 DQ17 52 BA2 82 DQ33 112 DQs7 142 Vss 172 A14 202 Vss 232 Vss Vss Ground 23 Vss 53 Err_Our 83 Vss 113 Vss 143 DQS11 173 Voo 203 DQS13 233 DQ62 Voo Power 24 IDQS2 54 Vpp 84 DQs4 114 DQ58 144 DQS11 174 A12 BC 204 DQS13 234 DQ63 Vopsep SPD EEPROM Power 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 AQ 205 Vss 235 Vss VrerDa Reference Voltage for DQ s 26 Vss 56 A7 86 Vss 116 Vss 146 DQ22 176 Vpp 206 DQ38 236 Voospp Vnerca Reference Voltage for CA 27 DQ18 57 Voo 87 DQ34 117 SAO 147 DQ23 177 A8 207 DQ39 237 SA1 Vor Termination Voltage 28 DQ19 58 A5 88 DQ35 118 SCL 148 Vss 178 AG 208 Vss 238 SDA NC No Connection 29 Vss 59 A4 89 Vss 119 SA2 149 DQ28 179 Voo 2
9. Delay Time tRASmin Least Significant 36 0ns 0x20 23 Minimum Active to Active Refresh Delay Time tRCmin Least 49 125ns 0x89 Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least Significant 160 0ns 24 Byte 0x00 25 a Refresh Recovery Delay Time tRFCmin Most Significant 160 0ns 0x05 26 Minimum Internal Write to Read Command Delay Time tWTRmin 7 5ns 0x3C 27 Minimum Internal Read to Precharge Command Delay Time tRTPmin 7 5ns 0x3C Upper Nibble for tFAW 28 Bit 3 Bit 0 FAW Most Significant Nibble 0 0x00 Bit 7 Bit 4 Reserved 0 29 Minimum Four Activate Window Delay Time tFAWmin Least 30 0ns OXFO Significant Byte SDRAM Optional Features Bit 0 RZQ 6 X 30 Bit 1 RZQ 7 X 0x83 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support 31 SDRAM Drivers Supported 0x01 Document 06015 Revision A 10 Sep 10 Dataram Corporation 2010 Page 9 Ta DTM64316E EE SGB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Extended Temperature Range X Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Partial Array Self Refresh PASR Module Thermal Sensor 32 Bit 6 Bit 0 Thermal Sensor Accuracy 0 0x80 Bit 7 Thermal Sensor With TS SDRAM Device Type Bit 6 Bit 0 Non Standard Device Description 0 33 Bit 7 SDR
10. be signals SDRAM Addressing Row Col Bank 15 1 1 3 Fully ROHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 Vperpe 31 DQ25 61 A2 91 DQ41 121 Vss 151 Vss 181 A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32 Vss 62 Von 92 Vss 122 DQ4 152 DQS12 182 Voo 212 DQS14 DQ 63 0 Data Bits 3 DQO 33 Das3 63 ck1 93 DQS5 123 DQ5 153 DQS12 183 Voo 213 DQS14 DQS 17 0 DQS 17 0 Differential Data Strobes 4 DQ1 34 Das3 64 cki 94 DQs5 124 Vss 154 Vss 184 CKO 214 Vss CK 1 0 CK 1 0 Differential Clock Inputs 5 Vss 35 Vss 65 Voo 95 Vss 125 DQs9 155 DQ30 185 CKO 215 DQ46 CKE 1 0 Clock Enables 6 DQSO 36 DQ26 66 Von 96 Das2 i26 Dase 156 DQ31 186 Vop 216 DQ47 ICAS Column Address Strobe 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 EVENT 217 Vss IRAS Row Address Strobe 8 Vss 38 Vss 68 Parin 98 Vss 128 DQ6 158 CB4 188 A0 218 DQ52 S 3 0 Chip Selects 9 DQ2 39 CBO 69 VDD es Da4s 129 Da7 159 CBS 189 Vop 219 DQ53 MWE Write Enable 10 DQ3 40 CB1 70 A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss A 15 0 Address Inputs 11 Vss 41 Vss 71 BAO 101 Vss 131 DQ12 161 DQS17 191 Voo 221 DQS15 BA 2 0 Bank Addresses 12 DQ8 42 DQS8 72 Voo 102 DQS6 132 DQ13 f162 DQS17 192 RAS 222 DQS15 ODT 1 0 On Die Termination Inputs 13 DQ9 43 DQS8 73 WE 103 DQS6 f133 Vss 163 Vss 193 SO 223 Vss SA 2 0 SPD Address 14 Vos 44 Vss 74 ICAS 104 Vss 134 DQS10 164
11. been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06015 Revision A 10 Sep 10 Dataram Corporation 2010 Page 13
12. nput Logic High ViH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low ViL DIFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix Pat PDE iy Capacitance T 25 C f 100 MHz PARAMETER Pin Symb Minimu Maximum Unit ol m Input Capacitance Clock CKO CKO Cek 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 Ci 1 5 2 5 pF DQ 63 0 CB 7 0 DQS 17 0 Input Output Capacitance DQS 17 0 Cio 3 5 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 18 18 yA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current lot 10 10 pA 2 3 0V lt VOUT lt VDDQ Notes 1 All other pins not under test 0 2 Values are shown per pin V 3 DQ DQS DQS and ODT are disabled D See A gg Document 06015 Revision A 10 Sep 10 Dataram Corporation 2010 Page 5 DTM64316E 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V wae Max g PARAMETER Symbol Test Condition Value Unit Operating One Bank Active IppO Operating current One bank ACTIVATE to PRECHARGE 2420 mA Precharge Current Operating One 3 i Bank Active Read loo1 Ada One bank ACTIVATE to READ to 2600 mA Precharge C
13. ry DTM64316E Optimizing Value and Performance Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5V 0 075 I O Type SSTL_15 On board IC temperature sensor with integrated Serial Presence Detect SPD EEPROM Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 and 9 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Identification DTM64316E 1Gx72 8GB 2Rx4 PC3 10600R 9 E1 Performance range Clock Module Speed CL trco trp 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64316E is a registered 1Gx72 memory module which conforms to JEDEC s DDR3 PC3 10600 standard The assembly is Dual Rank Each Rank is comprised of eighteen 512Mx4 DDR3 1333 Samsung SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Bi directional Differential Data Stro
14. tck Data Input Hold Time after DQS Strobe tou 65 ps DQ Input Pulse Width toipw 400 ps DQS Output Access Time from Clock toasck 255 255 ps Write DQS High Level Width toos 0 45 0 55 tcktavo Write DQS Low Level Width toast 0 45 0 55 tck avo DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tek avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tue minimum of tcy or teL ns Address and Command Hold Time after Clock tin 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time tmRD 4 tck DQ to DQS Hold ton 0 38 tck avg Active to Precharge Time tras 36 9 trer1 ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trco 13 125 ns Average Periodic Refresh Interval 0 C lt Tease lt 85 C tREFI 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C tREFI 3 9 us Auto Refresh Row Cycle Time treo 160 ns Row Precharge Time tre 13 125 ns Read DQS Preamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay trtp Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twpRE 0 9 tck avg Write DQS Postamble Time twest 0 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Ma
15. timizing Value and Performance 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM IRS1 O RSO O DQSRO O l DQSR9 O DQSRO O DASRI O Vss O t DQS DAS CS DM DOS DOS DQS DAS CS DM DOS DOS DAR 3 0 O 1 0 3 0 1 0 3 0 DQR 7 4 O 1 0 3 0 1 0 3 0 DQSR1 O DQSR10 O DQS DAS CS DM DOS DOS DQR 11 8 O DQR 15 12 O 1 0 3 0 1 0 3 0 DQSR2 O DQSR11 O DQSR2 O DQSR11 O DQS DAS CS DM IDOS DOS DQS DAS CS DM DOS DOS DAR 19 16 O 1 0 3 0 1 0 3 0 DQR 23 20 O 1 0 3 0 1 0 3 0 DQSR3 O DQSR12 O mM DQSR3 O DQSR12 O A i IDOS DOS CS DOS DOS CS DQR 27 24 O 1 0 3 0 DQR 31 28 O 1 0 3 0 DQSR8 O DQSR17 O DQSRE O DQSR17 O DQS DAS CS DM DOS DOS CS DM q pes DOS CS CBR 3 0 O 1 0 3 0 1 0 3 0 CBR 7 4 O 1 0 3 0 DQSR4 O DQSR13 O DASR4 O Feo DQSR13 O aa T DQS DAS CS DM DOS DOS CS DM DQS DAS C DOS DOS CS DQR 35 32 O 1 0 3 0 1 0 3 0 DQR 39 36 O 1 0 3 0 1 0 3 0 DQSR5 DQSR 4 O DQSR5 DASR14 O DQS DAS CS DM IDOS DOS DQS DAS CS DM DOS DOS C DQR 43 40 1 0 3 0 1 0 3 0 DQR 47 44 O 1 0 3 0 1 0 3 0 E e dr e i DQSR6 DQSR15 O IDOS DOS CS DQS DAS CS DM DOS DOS CS DAQR 51 48 1 0 3 0 DQR 55 52 O 1 0 3 0 1 0 3 0 DQSR7 IDQSR16 O F DQSR7 DQSR16 O T IDOS DOS CS DQS DAS CS DM DOS DOS CS DQR 59 56 O 1 O 3 0 1 0 3 0 DQR 63 60 O 1 0 3 0 1 0 3 0 All 15 OHMS TO SDRAMS DECOUPLING
16. urrent Precharge Power oy Down Current Ipp2P Precharge power down current Slow exit 1042 mA Precharge Power e Down Current lop2P Precharge power down current Fast exit 1330 mA Precharge Standby a Current Ipp2N Precharge standby current 1940 mA Active Power Down ee p Current lbo3P Active power down current 1690 mA Active Standby a Current Ipp3N Active standby current 2650 mA Operating Burst e Write Current lbo4W Burst write operating current 3510 mA Operating Burst B Read Current Ipp4R Burst read operating current 3140 mA Burst Refresh pe Current lop5B Refresh current 4360 mA Self Refresh rr ano Current Ipp6 Self refresh temperature current MAX Tc 85 C 1032 mA Operating Bank Interleave Read loo7 All bank interleaved read current 4940 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation Document 06015 Revision A 10 Sep 10 Dataram Corporation O 2010 Page 6 DTM64316E IN2DATARAM Optimizing Value and Performance AC Operating Conditions 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay teco 4 tok Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width toL avg 0 47 0 53
17. x 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06015 Revision A 10 Sep 10 Dataram Corporation 2010 Page 7 D DATARAM Optimizing Value and Performance DTM64316E 8GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Serial Presence Detect Byte Function Value Hex Number of Bytes Used Number of Bytes in SPD Device CRC Coverage 0 Bit 3 Bit 0 SPD Bytes Used 176 0x92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 1 SPD Revision Rev 1 0 0x10 2 Key Byte DRAM Device Type DDR3 SDRAM 0x0B Key Byte Module Type 3 Bit 3 Bit 0 Module Type RDIMM 0x01 Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks 4 Bit 3 Bit 0 Total SDRAM capacity in megabits 2Gb 0x03 Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 SDRAM Addressing 5 Bit 2 Bit 0 Column Address Bits 11 Ox1A Bit 5 Bit 3 Row Address Bits 15 Bit 7 6 Reserved 0 6 Reserved 0x00 Module Organization 7 Bit 2 Bit 0 SDRAM Device Width 4 Bits 0x08 Bit 5 Bit 3 Number of Ranks 2 Rank Bit 7 6 Reserved 0 Module Memory Bus Width 8 Bit 2 Bit O Primary bus width in bits 64 Bits 0x0B Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Dividend
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