Dataram 4GB, 240-Pin
Contents
1. Bit 3 Bit 2 of Rows of DRAMs on RDIMM 2 Rows Bit 7 Bit 4 Reserved O R RDIMM Thermal Heat Spreader Solution Bit 6 Bit 0 Heat Spreader Thermal Characteristics Bit 7 Heat Spreader Solution Register Manufacturer ID Code Least Significant Byte Optional Register Manufacturer ID Code Most Significant Byte Optional 67 Register Revision Number Optional O al Register Type UNUSED UNUSED Bit 2 0 Support Device SSTE32882 Bit 7 3 Reserved SSTE32882 RC1 MS Nibble RCO LS Nibble SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength Command Address Y o 0 UNUSED Bit 1 Bit 0 RC2 DA3 4 Value RESERVED Bit 3 Bit 2 RC2 DBAO 1 Value RESERVED Bit 5 Bit 4 RC3 DA4 3 value Command Address A Outputs Moderate Bit 7 Bit 6 RC3 DBAO 1 value Command Address B Outputs SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Clock 7 Moderate Control and Bit 1 Bit 0 RC4 DA3 4 Control Signals A Outputs Moderate Bit 3 Bit 2 RC4 DBAO 1 Control Signals B Outputs Moderate Bit 5 Bit 4 RC5 DA4 3 value Y1 Y1 and Y3 Y3 Clock Outputs Moderate Bit 7 Bit 6 RC5 DBAO 1 value YO YO and Y2 Y2 Clock Outputs 72 SSTE32882 RC7 MS Nibble RC6 LS Nibble a 73 74 75 SSTE32882 RC9 MS Nibbl2. Down Current Ipp2P Precharge power down current Slow exit 970 mA Precharge Power e Down Current lop2P Precharge power down current Fast exit 1330 mA Precharge Standby a Current Ipp2N Precharge standby current 1580 mA Active Power Down ee p Current lbo3P Active power down current 1510 mA Active Standby a Current Ipp3N Active standby current 2470 mA Operating Burst e Write Current lbo4W Burst write operating current 2880 mA Operating Burst B Read Current Ipp4R Burst read operating current 2870 mA Burst Refresh pe Current lobn5B Refresh current 3190 mA Self Refresh rr ano Current Ipp6 Self refresh temperature current MAX Tc 85 C 960 mA Operating Bank Interleave Read Ipp7 All bank interleaved read current 4130 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation Document 06606 Revision A 08 Sep 10 Dataram Corporation 2010 Page 6 DTM64313H De Optimizing Value and Performance AC Operating Conditions 4GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay teco 4 tok Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width toL avg 0 47 0 53 tck Data Input Hold Time after DQS Strob
3. Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions Ta O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V 1 0 Reference Voltage VREFDQ 0 49 Vpp 0 50 Vpop 0 51 Voo V 1 1 O Reference Voltage VREFCA 0 49 Voo 0 50 Vpp 0 51 Voo V 1 Notes 1 The value of Vrer is expected to equal one half Voo and to track variations in the Voo DC level Peak to peak noise on Vrer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH DC Vrer 0 1 Vpop V Logical Low Logic 0 Vic Vss Vrer 0 1 V AC Input Logic Levels Single Ended T O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 175 V Logical Low Logic 0 ViL ac Vrer 0 175 V gt IEEE AE A AAA A Document 06606 Revision A 08 Sep 10 Dataram Corporation O 2010 Page 4 a 4GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High ViH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differenti
4. CL 5 Bit 2 CL 6 Bit 3 CL 7 Bit 4 CL 8 Bit 5 CL 9 Bit 6 CL 10 Bit 7 CL 11 Document 06606 Revision A 08 Sep 10 Dataram Corporation 2010 Page 8 paz D1M64313H Optimizing Value and Performance 4GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved al 16 17 18 19 0 2 N Upper Nibbles for tRAS and tRC Bit 3 Bit 0 tRAS Most Significant Nibble 1 Bit 7 Bit 4 tRC Most Significant Nibble 2 Minimum Active to Precharge Delay Time tRASmin Least Significant Byte Minimum Active to Active Refresh Delay Time tRCmin Least Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Most Significant Byte N w N N al 26 27 2 Upper Nibble for tFAW 1 tWTRmin tRTPmin Bit 3 Bit 0 tFAW Most Significant Nibble Bit 7 Bit 4 Reserved 9 Minimum Four Activate Window Delay Time tFAWmin Least Significant Byte SDRAM Optional Features N oO o Bit 0 RZQ 6 Bit 1 RZQ 7 Bit 6 Bit 2 Res
5. 0 3 0 1 0 3 0 All 15 OHMS TO SDRAMS DECOUPLING DQ 63 0 O VAW O DQR 63 0 Ki Voospo __ Serial PD CB 7 0 O WW O CBRI T 0 a 22 OHMS _ VDD All Devices ee VREF_DQ All SDRAMs DQS 17 0 O VWA O__DASRI17 0 181 AM IRS V All Devi BA 2 0 WM BA 2 0 R ss evices DQS 17 0 O VA O DQSR 17 0 A 15 0 Ww A I5 0 R VREF_CA All SDRAMs IRAS WA IRASR Vi alll SDRAMs GLOBAL SDRAM CONNECTS Mec en Te ee All 36 OHMS CKE 1 0 y n a 36 OHMS ena i CKERT1 0 LCLK 1 0 O VWW O LCLK 1 0 2 0 R A 15 0 R ODT 1 0 Vw 2 ODTR 1 0 RCLK 1 0 O VA O_ RCLK 1 0 RASR x PARIN AA 4 ERR_OUT CASR ki ERCH EVENT IWER VTT 150 i OHMS All 240 OHMS ICKO J ILR CLK 1 0 TEMPERATURE MONITOR ung al 2 SDA SA0 SA1 SA2 CKE 1 0 R ODT 1 0 R owd IRS 1 0 VIT ie Ol ec SDRAMS ZQ a Vss Document 06606 Revision A 08 Sep 10 Dataram Corporation 2010 Page 3 DTM64313H 4GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Dr Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TSTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tcase 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on
6. 10 Dataram Corporation O 2010 paz D1M64313H Optimizing Value and Performance 4GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM IRS1 O IRSO O DQSRO O l DQSR9 O DQSRO O DASRI O Vss O t DQS DAS CS DM DOS DOS DQS DAS CS DM DOS DOS DAR 3 0 O 1 0 3 0 1 0 3 0 DQR 7 4 O 1 0 3 0 1 0 3 0 DQSR1 O DQSR10 O DQS DAS CS DM DOS DOS DQR 11 8 O DQR 15 12 O 1 0 3 0 1 0 3 0 DQSR2 O DQSR11 O DQSR2 O DQSR11 O DQS DAS CS DM IDOS DOS DQS DAS CS DM DOS DOS DAR 19 16 O 1 0 3 0 1 0 3 0 DQR 23 20 O 1 0 3 0 1 0 3 0 DQSR3 O DQSR12 O mM DQSR3 O DQSR12 O A i IDOS DOS CS DOS DOS CS DQR 27 24 O 1 0 3 0 DQR 31 28 O 1 0 3 0 DQSR8 O DQSR17 O DQSRE O DQSR17 O DQS DAS CS DM DOS DOS CS DM q pes DOS CS CBR 3 0 O 1 0 3 0 1 0 3 0 CBR 7 4 O 1 0 3 0 DQSR4 O DQSR13 O DASR4 O Feo DQSR13 O aa T DQS DAS CS DM DOS DOS CS DM DQS DAS C DOS DOS CS DQR 35 32 O 1 0 3 0 1 0 3 0 DQR 39 36 O 1 0 3 0 1 0 3 0 DQSR5 DQSR 4 O DQSR5 DASR14 O DQS DAS CS DM IDOS DOS DQS DAS CS DM DOS DOS C DQR 43 40 1 0 3 0 1 0 3 0 DQR 47 44 O 1 0 3 0 1 0 3 0 E e dr e i DQSR6 DQSR15 O IDOS DOS CS DQS DAS CS DM DOS DOS CS DAQR 51 48 1 0 3 0 DQR 55 52 O 1 0 3 0 1 0 3 0 DQSR7 IDQSR16 O F DQSR7 DQSR16 O T IDOS DOS CS DQS DAS CS DM DOS DOS CS DQR 59 56 O 1 O 3 0 1 0 3 0 DQR 63 60 O 1
7. 9 DQ28 179 Voo 209 DQ44 239 Vss 30 DQ24 60 Voo 90 DQ40 120 Vm 150 Da29 180 A3 210 DQ45 240 Vir Not used Document 06606 Revision A 08 Sep 10 Dataram Corporation 2010 Page 1 a DTM64313H EEE AGB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Front view 133 35 5 250 9 50 0 374 30 00 1 181 A 17 30 0 681 0 197 i oe 5 175 lt 47 00 a 71 00 gt 0 204 1 850 2 795 Back view Side view 3 94 Max 0 155 Max 0 YN a T M 5 ll I ll I il a VANIDAD MALA 0 157 Min O NNNMNNN nnana L o O 1 27 10 ls 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches A A A Page 2 Document 06606 Revision A 08 Sep
8. AM Addressing Row Col Bank 14 11 3 Fully ROHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 Vrerpa 31 DQ25 61 A2 91 DQ41 121 Vss 151 Vss 181 A1 211 Vos CB 7 0 Data Check Bits 2 Vss 32 Vss 62 Vo 92 Vss 122 Da4 152 DQS12 182 Voo 212 DQS14 DAa 63 0 Data Bits 3 DQO 33 DQS3 63 ck1 93 DQS5 123 pas 153 DQs12 183 Voo 213 DQS14 DQS 17 0 DQS 17 0 Differential Data Strobes 4 DQ1 34 Das3 64 cK1 94 DQS5 124 Vss 154 Vss 184 CKO 214 Vss CK 1 0 CK 1 0 Differential Clock Inputs 5 Vss 35 Vss 65 Vo 95 Vss 125 DaS9 155 DQ30 185 ICKO 215 DQ46 CKE 1 0 Clock Enables 6 DQSO 36 DQ26 66 Vo 96 DQ42 i26 Dase 156 DQ31 186 Voo 216 DQ47 ICAS Column Address Strobe 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vos 157 Vss 187 EVENT 217 Vss IRAS Row Address Strobe 8 Vss 38 Vss 68 Party 98 Vss 128 DQ6 158 CB4 188 A0 218 DQ52 S 3 0 Chip Selects 9 DQ2 39 CBO 69 VDD 99 Da4s 129 Da7 159 CB5 189 Von 219 DQ53 MWE Write Enable 10 DQ3 40 CB1 70 A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss A 15 0 Address Inputs 11 Vss 41 Vss 71 BAO 101 Vss i31 DQ12 161 DQS17 191 Voo 221 DQS15 BA 2 0 Bank Addresses 12 DQ8 42 DQS8 72 Voy 102 DQS6 132 DQ13 162 DQS17_ 192 RAS 222 DQS15 ODT 1 0 On Die Termination Inputs 13 DQ9 43 Dass 73 WE 103 Dase 133 Vss 163 Vss 193 SO 223 Vss SA 2 0 SPD Address 14 Vos 44 Vss 74 CAS 104 Vss 134 Dasto 164 CB6 194 V
9. Syl DTM64313H Md Optimizing Value and Performance Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high 4GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Identification DTM64313H 512Mx72 4GB 2Rx4 PC3 10600R 9 10 E1 Performance range Clock Module Speed CL trco tre 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64313H is a registered 512Mx72 memory module Operating Voltage 1 5V 0 075 which conforms to JEDEC s DDR3 PC3 10600 standard VO Type SSTL_15 The assembly is Dual Rank Each rank is comprised of eighteen 256Mx4 DDR3 Samsung SDRAMs One 2K bit On board IC temperature sensor with integrated Serial Presence Detect SPD EEPROM EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 and 9 Bi directional Differential Data Strobe signals SDR
10. al Input Logic Low ViL DIFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage E relative to VDD 2 Vix SASN 0 190 id Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Min Max Unit Input Capacitance Clock CKO CKO Cck 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 15 2 5 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 Ci 15 25 pF Input Output Capacitance DQ 63 0 CB 7 0 DQS 17 0 DQS 17 0 Cio 3 5 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 18 18 pA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current loL 10 10 yA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled gt A a a E p E EEE Document 06606 Revision A 08 Sep 10 Dataram Corporation 2010 Page 5 PO 4GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V as Max F PARAMETER Symbol Test Condition Value Unit Operating One Bank Active Ipp0 Operating current One bank ACTIVATE to PRECHARGE 2060 mA Precharge Current Operating One 3 i Bank Active Read loo1 Ada One bank ACTIVATE to READ to 2240 mA Precharge Current Precharge Power oy
11. e RC8 LS Nibble SSTE32882 RC11 MS Nibble RC10 LS Nibble SSTE32882 RC13 MS Nibble RC12 LS Nibble a O oO oO oo Moderate 0x00 0x00 Ox0F 0x11 0x24 0x09 0x00 0x00 0x00 o o Xx T T 0x00 0x00 0x50 0x55 x00 x00 x00 x00 oO Document 06606 Revision A 08 Sep 10 Dataram Corporation O 2010 U 2 Q o o iy Le D1M64313H EEE AGB 240 Pin 2Rx4 Registered ECC DDR3 DIMM SSTE32882 RC15 MS Nibble RC14 LS Nibble UNUSED 117 Module Manufacturer ID Code Least SignificantByte ow 118 Module Manufacturer ID Code Most Significant Byte 0x1 UNUSED i 0 CRC 1 0 RC CRC A T A A v 142 Module Par Number A 126 147 Module Revision Cogs Fr UNUSED UNUSED Manufacturer s Specific Data UNUSED UNUSED Document 06606 Revision A 08 Sep 10 Dataram Corporation 2010 Page 11 Syl DTM64313H MA BH Optimizing Value and Performance 4GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM V2 DATARAM Md BH Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document d
12. e tou 65 ps DQ Input Pulse Width toipw 400 ps DQS Output Access Time from Clock toasck 255 255 ps Write DQS High Level Width toos 0 45 0 55 tcktavo Write DQS Low Level Width toast 0 45 0 55 tck avo DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tek avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tue minimum of tcy or teL ns Address and Command Hold Time after Clock tin 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time tmRD 4 tck DQ to DQS Hold ton 0 38 tck avg Active to Precharge Time tras 36 9 trer1 ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trco 13 125 ns Average Periodic Refresh Interval 0 C lt Tease lt 85 C tREFI 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C tREFI 3 9 us Auto Refresh Row Cycle Time treo 110 ns Row Precharge Time tre 13 125 ns Read DQS Preamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay trtp Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twpRE 0 9 tck avg Write DQS Postamble Time twest 0 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The max
13. erved Bit 7 DLL Off Mode Support ow SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout 0x00 o x69 x78 x69 x30 x69 j 0x20 0x89 0x70 0x03 0x3C 0x3C 0x00 OxFO 0x83 0x01 N 00 O o pojo x Reserved Reserved Reserved Partial Array Self Refresh PASR 32 Module Thermal Sensor 0x80 Document 06606 Revision A 08 Sep 10 Dataram Corporation 2010 Page 9 paz D1M64313H Optimizing Value and Performance 4GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Bit 6 Bit O Thermal Sensor Accuracy 0 Bit 7 Thermal Sensor SDRAM Device Type With TS Bit 6 Bit 0 Non Standard Device Description 0 Bit 7 SDRAM Device Type Module Nominal Height Std Mono UNUSED Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 Bit 7 Bit5 Reserved Module Maximum Thickness 0 Bit 3 Bit 0 Front in mm baseline thickness 1 mm Bit 7 Bit 4 Back in mm baseline thickness 1 mm Reference Raw Card Used O N Bit 4 Bit 0 Reference Raw Card Bit 6 Bit 5 Reference Raw Card Revision Bit 7 Reserved 63 Registered DIMM Module Attributes Bit 1 Bit 0 of Registers used on RDIMM 1 Register
14. imum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06606 Revision A 08 Sep 10 Dataram Corporation 2010 Page 7 paz D1M64313H A 41GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 Key Byte DRAM Device Type DDR3 SDRAM 3 Key Byte Module Type 0x01 Bit 3 Bit 0 Module Type Bit 7 Bit 4 Reserved SDRAM Density and Banks 0x02 Bit 3 Bit O Total SDRAM capacity in megabits 1Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 0x12 Bit 2 Bit 0 Column Address Bits Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved UNUSED Module Organization 0x08 Bit 2 Bit 0 SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved Module Memory Bus Width 0x0B Bit 2 Bit 0 Primary bus width in bits Bit 4 Bit 3 Bus width extension in bits Bit 7 Bit 5 Reserved Fine Timebase FTB Dividend Divisor 0x52 Bit 3 Bit O Fine Timebase FTB Divisor Bit 7 Bit 4 Fine Timebase FTB Dividend Medium Timebase MTB Dividend 0 125ns Medium Timebase MTB Divisor 0 125ns SDRAM Minimum Cycle Time tCKmin Ox0C UNUSED 000 CAS Latencies Supported Least Significant Byte 0x3C Bit O CL 4 Bit 1
15. oes not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06606 Revision A 08 Sep 10 Dataram Corporation 2010 Page 12
16. oo 224 DQ54 SCL SPD Clock Input 15 DQS1 45 CB2 75 Vo 105 DQ50 135 DQS10 165 CB7 195 ODTO 225 DQ55 SDA SPD Data Input Output 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss EVENT Temperature Sensing 17 Vss 47 Vss 77 ODT1 107 Vss 137 DQ14 167 NC TEST 197 Voo 227 DQ60 IRESET Reset for register and DRAMs 18 DQ10 48 Vr 78 Vpp 108 DQ56 138 DQ15 168 RESET 198 S3 NC 228 DQ61 PAR_IN Parity bit for Addr Ctrl 19 DQ11 49 Vrr 79 S2 NC 109 DQ57 139 Vss 169 CKE1 199 Vss 229 Vss ERR_OUT Error bit for Parity Error 20 Vss 50 CKEO 80 Vss 110 Vss h40 DQ20 170 Voo 200 DQ36 230 DQS16 A12 BC Combination input Addr12 Burst Chop 21 DQ16 51 Voo 81 DQ32 111 DQs7 141 Da21 171 A15 201 DQ37 231 DQS16 A10 AP Combination input Addr10 Auto precharge 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172 A14 202 Vss 232 Vss Vss Ground 23 Vss 53 JERR Our 83 Vss 113 Vss h43 DQS11 173 Voo 203 DQS13 233 DQ62 Voo Power 24 IDQS2 54 Voo 84 DQS4 114 Da58 144 DQs11 174 A12 BC 204 DQS13 234 DQ63 Vopsep SPD EEPROM Power 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 A9 205 Vss 235 Vss VREFDa Reference Voltage for DQ s 26 Vss 56 A7 86 Vss 116 Vss h46 DQ22 176 Vop 206 DQ38 236 Vppspp VREFCA Reference Voltage for CA 27 DQ18 57 Voo 87 DQ34 117 sao i47 DQ23 177 A8 207 DQ39 237 SA1 Vir Termination Voltage 28 DQ19 58 A5 88 DQ35 118 SCL 148 Vss 178 AG 208 Vss 238 SDA NC No Connection 29 Vss 59 A4 89 Vss 119 SA2 14
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