Dataram DTM63389C memory module
Contents
1. Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches D a A AA A 22 st Document 06611 Revision A 28 Oct 2010 Dataram Corporation O 2010 Page 2 DTM63389C IAS 512MB 240 Pin Unbuffered ECC DDR2 DIMM TNIDATARAM ISO O DQSRO o DQSR4 O DQSRO 0 DQSRA 0 DQSRY o DQSR5 O DOSRA o DQSR5 o E 13 pF DMRO o _ DMR4 O j DMRI 0 DMR5 Oy SSN HH HN S 5 000 000 Oo oO 33885888 38858888 2 gt 52338 DQR 15 8 o UNO 15 8 DQR 47 40 o UNO 15 8 DQR 7 0 o LIO 7 0 DAR 39 32 o LIO 7 0 IDQSR2 O DQSRE O DASR o DASR Oo DQSRI 07 3 1DQSR7 O p 1 5 pF DASR O _ pasr7 Oo DMR2 O _ DMR6 O _ DMR3 Oy DMR7 o 33838838 3808888 8 0 6 3 a D 4 oo gt Dp J 2 324 2 DQR 31 24 Oo UIO 15 8 DQR 63 56 O UI O 15 8 DQR 23 16 O UO 7 0 DQR 55 48 o LIO 7 0 DQSRE O DECOUPLING DASR o VbDpsPD 4 Serial PD Vop All Devices VREF T All SDRAMs V All Devices DMR8 0 SS S3000000 fe 6 8283 E a 88 22 2 22 22 UNO 15 8 SY Ohms SOhms SOhm2. DTM63389C IAS 512MB 240 Pin Unbuffered ECC DDR2 DIMM MRI DATARAM Identification DTM63389C 64Mx72 512MB 1Rx16 DDR2 667E 555 Performance range Clock Module Speed CL trco trp 333MHz DDR2 667 5 5 5 267MHz DDR2 533 4 4 4 200MHz DDR2 400 3 3 3 Features Description 240 pin DIMM 133 35 mm wide by 30 mm high DTM63389C is an Unbuffered ECC 64Mx72 Sa a cau CSM Mds si N s memory module The DIMM has one Rank Operating Voltage 1 8 V 40 1 comprised of five 64Mx16 DDR2 Samsung 1 0 Type SSTL_18 SDRAMs One 2K bit EEPROM is used for Serial Data Transfer Rate 5 3 Gigabytes sec Presence Detect Both output driver strength and input termination Data Bursts 4 or 8 bits Sequential or Interleaved ordering impedance are programmable to maintain signal Programmable I O driver strength OCD integrity on the I O signals Programmable On Die Termination ODT The assembly is a Dual In line Memory Module intended for mounting into 240 pin edge connector Programmable CAS Latency 3 4 or 5 sockets Differential Redundant Data Strobe signals SDRAM Addressing Row Col Bank 13 10 3 Fully ROHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDD 211 DM5 CB 7 0 Data Check Bits 2 VSS 32 VSS 62 VDD 92 DQS5 122 DQ4 152 DQ28 182 A3 212 NC DQ 63 0 Data Bits 3 DQO 33 DQ24 63 A2 93 DQS5 123 DQ
3. ns 46 PLL Relock Time us UNUSED 47 DRAM maximun Case Temperature Delta Degree C 0x03 DT4R4W Delta Bits 0 3 Tcasemax delta Bits 7 4 Thermal Resistance of DRAM Package from Top Case to a Ambient Psi T A DRAM C Watt 49 DRAM Case Temperature Rise from Ambient due to Activate Lo Mode Bits DTO Mode Bits Degree C Bit 0 If 0 DRAM does not support high temperature self refresh entry Bit 1 If 0 Do not need double refresh rate for the proper operation DTO Bits 2 7 MS Case Temperature Rise from Ambient due to Precharge Quiet Standby DT2N DT2Q Degree C DRAM Case Temperature Rise from Ambient due to MA ai Precharge Power Down DT2P Degree C 52 DRAM Case Temperature Rise from Ambient due to Active Standby DT3N Degree C 53 DRAM Case temperature Rise from Ambient due to Active SS Power Down with Fast PDN Exit DT3Pfast Degree C DRAM Case temperature Rise from Ambient due to Active 0x56 Power Down with Slow PDN Exit DT3Pslow Degree C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree C Bit 0 0 if DT4W is greater than DT4R DTAR Bits 1 7 56 DRAM Case Temperature Rise from Ambient due to Burst 24 5 0x31 Refresh DT5B Degree C Document 06611 Revision A 28 Oct 2010 Dataram Corporation 2010 Page 10 TT PTM63389C A 512MB 240 Pin Unbuffere
4. 170 VDD 200 DQ37 230 DQ61 VREF Reference Voltage 21 DQ10 51 VDD 81 DQ33 111 DQ57 141 DQ15 171 NC 201 VSS 231 VSS NC No Connection 22 DQ11 52 CKEO 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4 232 DM7 23 VSS 53 VDD 83 DQS4 113 DQS7 143 DQ20 173 A15 203 NC 233 NC 24 DQ16 54 BA2 84 DQS4 114 DQS7 144 DQ21 174 A14 204 VSS 234 VSS 25 DQ17 55 NC 85 VSS 115 VSS 145 VSS 175 VDD 205 DQ38 235 DQ62 26 VSS 56 VDD 86 DQ34 116 DQ58 146 DM2 176 A12 206 DQ39 236 DQ63 27 DQS2 57 A11 87 DQ35 117 DQ59 147 NC 177 A9 207 VSS 237 VSS 28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD 29 VSS 59 VDD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SAO 30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1 Connected but not used Document 06611 Revision A 28 Oct 2010 Dataram Corporation 2010 Page 1 DTM63389C A 512MB 240 Pin Unbuffered ECC DDR2 DIMM INIDATARAM Front view 133 35 5 250 gt 10 00 4 00 0 394 0 00 10 157 SA E 1 181 G i 17 80 4 T 0 700 O NNNNA N coc S a zain 5 18 63 00 55 00 i dl 10 204 AA 2 480 2 165 123 00 4 843 Back view Side view EN 2 72Max 0 105 Max C C 4 00 Min 0 157 Min O 127510 m 0 0500 0 0040
5. Load Mode Command Cycle Time turD 2 tck DQ to DQS Hold to thp tons Data Hold Skew Factor tans 340 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 60 ns RAS to CAS Delay trep 15 ns Average Periodic Refresh Interval tREFI 7 8 us Auto Refresh Row Cycle Time tree 127 5 ns Row Precharge Time trp 15 ns Read DQS Preamble Time RPRE 0 9 1 1 tex Read DQS Postamble Time trest 0 4 0 6 tex Row Active to Row Active Delay trrD 7 5 ns Internal Read to Precharge Command Delay tRTP 7 5 ns Write DQS Preamble Time twPRE 0 35 ps Write DQS Postamble Time twpPsT 0 4 0 6 tex Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr terc min 10 ns Exit Self Refresh to Read Command txsrpD 200 tck Document 06611 Revision A 28 Oct 2010 Dataram Corporation 2010 Page 7 TT PTM63389C OS 512MB 240 Pin Unbuffered ECC DDR2 DIMM SERIAL PRESENCE DETECT MATRIX T z 0 Module Attributes Number of Ranks Package and Height 0x60 of Ranks 1 Card on Card No DRAM Package Planar gt U 5 Module Height 30mm Module Data Width 0x48 7 UNUSED Voltage Interface Level of this assembly SSTL 1 8V 0x05 SDRAM Cycle time Max Supported CAS Latency CL X MN 0x30 tCK ns 3 SDRAM Access from Clock Highest CAS latency tAC ns 0x45 DIMM configuration type Non par
6. 5 153 DQ29 183 A1 213 VSS DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VDD 214 DQ46 DM 8 0 Data Mask 5 VSS 35 VSS 65 VSS 95 DQ42 125 DMO 155 DM3 185 CKO 215 DQ47 CK 2 0 CK 2 0 Differential Clock Inputs 6 DQSO 36 DQS3 66 VSS 96 DQ43 126 NC 156 NC 186 CKO 216 VSS CKEO Clock Enables 7 DQSO 37 DQS3 67 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52 ICAS Column Address Strobe 8 VSS 38 VSS 68 NC 98 DQ48 128 DQ6 158 DQ30 188 A0 218 DQ53 IRAS Row Address Strobe 9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 VSS SO Chip Selects 10 DQ3 40 DQ27 70 A10 100 VSS 130 VSS 160 VSS 190 BA1 220 CK2 WE Write Enable 11 VSS 41 VSS 71 BAO 101 SA2 131 DQ12 161 CB4 191 VDD 221 CK2 A 15 0 Address Inputs 12 DQ8 42 CBO 72 VDD 102 NC 132 DQ13 162 CB5 192 RAS 222 VSS BA 2 0 Bank Addresses 13 DQ9 43 CB1 73 WE 103 VSS 133 VSS 163 VSS 193 SO 223 DM6 ODTO On Die Termination Inputs 14 VSS 44 VSS 74 CAS 104 DQS6 134 DM1 164 DM8 194 VDD 224 NC SA 2 0 SPD Address 15 DQS1 45 DQS8 75 VDD 105 DQS6 135 NC 165 NC 195 ODTO 225 VSS SCL SPD Clock Input 16 DQS1 46 DQS8 76 NC 106 VSS 136 VSS 166 VSS 196 A13 226 DQ54 SDA SPD Data Input Output 17 VSS 47 VSS 77 NC 107 DQ50 137 CK1 167 CB6 197 VDD 227 DQ55 VSS Ground 18 NC 48 CB2 78 VDD 108 DQ51 138 CK1 168 CB7 198 VSS 228 VSS VDD Power 19 NC 49 CB3 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ36 229 DQ60 VDDSPD SPD EEPROM Power 20 VSS 50 VSS 80 DQ32 110 DQ56 140 DQ14
7. ach input of a differential pair 2 Vic specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Vipiac Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 Voo and is expected to track variations in Vpp Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CK 2 0 CK 2 0 CIN1 6 2 8 2 pF Input Capacitance Address and Control BA 2 0 A 13 0 RAS CAS WE CIN2 5 0 10 0 pF Input Capacitance Control CKEO ODTO SO CIN3 31 5 36 5 pF Input Output Capacitance or CB 7 0 DQS 8 0 DQSI8 0 CIO 2 5 3 5 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address lu 10 10 yA 1 Input Leakage Current CKO CKO lu 2 2 pA 1 Input Leakage Current CK 1 0 CK 1 0 lu 4 4 yA 1 Input Leakage Current DM lu 2 2 pA 1 Output Leakage Current DQS DQ loz 2 2 pA 2 Output Minimum Source DC Current loH 13 4 mA 3 Output Minimum Sink DC Current lot 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 DQxand ODT are disabled and 0 V lt Vout lt Vop 3 Voo 1 7 V Vout 1420 mV Vour Voo lon must be less than 21 Ohms for valu
8. d ECC DDR2 DIMM Interleave Reads with Auto Precharge DT7 Degree C 58 Thermal Resistance of PLL Package from Top to Ambient UNUSED 0x00 Psi T A PLL C Watt Thermal Resistance of Register Package from Top to Ambient UNUSED DRAM Case Temperature Rise from Ambient due to Bank 33 5 0x43 59 iad Psi T A Register C Watt PLL Case Temperature Rise from Ambient due to PLL Active UNUSED 0x00 DT PLL Active Degree C 61 Register Case Temperature Rise from Ambient due to Register Active Mode Bit 0x00 DT Register Active Mode Bit Bit 0 If O Unit for Bits 2 7 is 0 75C 0 75 Bit 1 RFU Default O 0 Register Active Bits 2 7 0 SPD Revision 0x12 63 Checksum for Bytes 0 62 2 0 73 90 Module Part Number O foa 1 92 0x0 Fel bea Specific Data UNUSED 0x00 127 Document 06611 Revision A 28 Oct 2010 Dataram Corporation 2010 Page 11 DTM63389C MA BH Optimizing Value and Performance 512MB 240 Pin Unbuffered ECC DDR2 DIMM MR DATARAM TNIDATARAM MA A A Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any licens
9. e under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06611 Revision A 28 Oct 2010 Dataram Corporation 2010 Page 12
10. ed CAS Latency CL X 1 ns Fa ca Data Access Time tAC from Clock at CL X 1 a EX Clock Minimum Clock Cycle Time atCL X 2 ns Time at CL X 2 ns 26 oe Data Access Time i a from Clock at CL X 2 7 minima Minimum Row Precharge Time tRP ns a O Peas THRAF RE as 28 Minimum Row Active to Row Active Delay tRRD 7 5 0x1E 29 Minimum RAS to CAS Delay RCD n z 15 0x3C 30 ici Active o Precharge Te RASI 020 32 ries an Command Setup Tne Baie CES 02 foe 33 Address and Command Hold Time ma En qu 734 ala input Setup Time Before Strobe DS ns 01 oxao 35 Data Input Hold Time After Strobe OH E o 36 Write Recovery Time tWR ns 45 oC Document 06611 Revision A 28 Oct 2010 Dataram Corporation O 2010 Page 9 DRPATARAM DTM63389C ios 512MB 240 Pin Unbuffered ECC DDR2 DIMM En nternal write to read command delay tWTR 75 Ox Internal read to precharge command delay TRIP 75 Ox EE Analysis Probe Characteristics UNUSED oa Extension of Byte 41 tRC and Byte 42 tRFC ns Add this value to byte 41 Add this value to byte 42 SDRAM Device Minimum Active to Active Auto Refresh Time Po ed tRC ns 42 SDRAM Device Minimum Auto Refresh to Active Auto Na 5 Es Refresh Command Period tRFC ns SDRAM Device Maximum Cycle Time tCK max 8 0x80 ie Dev DQS DQ Skew for DOS amp DQ ws 20050 A ee ns e SDRAM Device Read Data Hold Skew Factor tQHS 0 34 0x22
11. es of Vout between Von and Vopn 280 mV 4 Vpp 1 7 V Vout 280 mV Vour lo must be less than 21 Ohms for values of Vout between 0 V and 280 mV A A gt XS Document 06611 Revision A 28 Oct 2010 Dataram Corporation O 2010 Page 5 DTM63389C Serres 512MB 240 Pin Unbuffered ECC DDR2 DIMM INIDATARAM loo Specifications and Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition VA Unit Operating One Bank i Active Precharge lo00 CKE is HIGH ICS is HIGH between valid commands Address bus 450 mA inputs are switching Data bus inputs are switching Current Operating One Bank _ BE o Active Read loo lout 0 mA BL 4 CL 5 ns AL 0 CKE is HIGH CS is HIGH 575 mA between valid commands Address bus inputs are switching All banks idle CKE is LOW Other control and address bus inputs Precharge Current Precharge Power Down Current loo2P are stable Data bus inputs are floating 50 ma Precharge Quiet lor2Q All banks idle CKE is HIGH CS is HIGH Other control and 150 mA Standby Current ae address bus inputs are stable Data bus inputs are floating Precharge Standby lop2N All banks idle CKE is HIGH CS is HIGH Other control and 200 mA Current i address bus inputs are switching Data bus inputs are switching All banks open CKE is LOW Other control and address bus inputs lop3P are stable Data bus inputs are floating Fast Power down
12. exit 125 mA Mode Register bit 12 0 All banks open CKE is LOW Other control and address bus inputs lop3P are stable Data bus inputs are floating Slow Power down exit 60 mA Active Power Down Current Active Power Down Current Mode Register bit 12 1 All banks open tras 70 ms CKE is HIGH CS is HIGH between re loo3N valid commands Other control and address bus inputs are 250 mA switching Data bus inputs are switching Operating Burst All banks open Continuous burst writes BL 4 CL 5 tcx AL 0 i lon4W tras 70 ms CKE is HIGH CS is HIGH between valid commands 975 mA Write Current F eet i ae Address bus inputs are switching Data bus inputs are switching All banks open Continuous burst reads lout 0 mA BL 4 Operating Burst Iop4R CL 5 tck AL 0 tras 70 ms CKE is HIGH CS is HIGH 975 mA Read Current pp between valid commands Address bus inputs are switching Data bus inputs are switching Burst Refresh Refresh command at every 75 ns CKE is HIGH CS is HIGH loo5 between valid commands Other control and address bus inputs are 875 mA Current E abn switching Data bus inputs are switching Self Refresh lon6 CK and CK at 0 V CKE lt 0 2 V Other control and address bus 50 mA Current is inputs are floating Data bus inputs are floating All bank interleaving reads lout 0 mA BL 4 CL 5 tex AL tRCD IDD 1 x tCK IDD trro 7 5 ns CKE is HIGH CS is HIGH be
13. ical Maximum Unit Note Power Supply Voltage Vo 1 7 1 8 1 9 V 1 O Reference Voltage VREF 0 49 Vop 0 50 Vop 0 51 Vop V 1 Bus Termination Voltage Vit Vrer 0 04 VREF Vrer 0 04 V Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Veer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Logical High Logic 1 Veer 0 125 Voo 0 300 Logical Low Logic 0 Veer 0 125 AC Input Logic Levels Single Ended T O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 250 V Logical Low Logic 0 ViL ac Vrer 0 250 V A a gt ns Document 06611 Revision A 28 Oct 2010 Dataram Corporation 2010 Page 4 DTM63389C Serres 512MB 240 Pin Unbuffered ECC DDR2 DIMM INIDATARAM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note DC Input Signal Voltage Vin Dc 0 300 Voo 0 300 V 1 DC Differential Input Voltage Vip oc 0 250 Vpop 0 600 V 2 AC Differential Input Voltage Vip ac 0 500 Voo 0 600 V 3 AC Differential Cross Point Voltage Vixac 0 50 Vpb 0 175 0 50 VDD 0 175 V 4 Notes 1 Vnpo specifies the allowable DC excursion of e
14. ity Parity or ECC 0x02 Data Parity Data ECC Address Command Parity o TBD TBD TBD TBD TBD 2 Refresh Rate Type us Primary SDRAM Width 0x10 Error Checking SDRAM Width 8 0x08 Reserved 0x00 SDRAM Device Attributes Burst Lengths Supported TBD TBD Burst Length 4 Burst Length 8 TBD TBD TBD TBD 17 SDRAM Device Attributes CAS Latency TBD TBD Latency 2 U a ala lt Document 06611 Revision A 28 Oct 2010 Dataram Corporation 2010 Page 8 DI DATARAM DTM63389C OS 512MB 240 Pin Unbuffered ECC DDR2 DIMM Latency 3 Latency 4 Latency 5 Latency 6 TBD XXX DIMM type information Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm ve Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UDIMM 82 0mm SDRAM Module Attributes Refer to Byte20 for DIMM type information Number of active registers on the DIMM N A for UDIMM Number of PLL on the DIMM N A for UDIMM FET Switch External Enable TBD Analysis probe installed TBD 22 SDRAM Device Attributes General Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Self Refresh TBD TBD TBD TBD TB eel Clock Cycle Time at Reduc
15. s 3 x 200 OHMS CBRI7 0 O LIO 7 0 L L L NW no SDRAM X 1 22 Ohms ICKO O 4 gt 1x1pF 22 Ohms 2x 2 2 pF CBI7 0 9 WW O CBR 7 0 scL SERIAL PD SDA 3 x 200 OHMS DQ 63 0 O VVy O O DQR 63 0 AWN DQS 8 0 O VW O DOSR 8 0 SAO SA1 SA2 i gt SDRAM X 2 DQS 8 0 O VWA O DQSR 8 0 Hm DM 8 0 O WW O DMR 8 0 en pF IT 2 2 pF GLOBAL SDRAM CONNECTS 3 x 200 OHMS ANN 10 Ohms CKEO a Wiese CKEO ie BA 2 0 O WA O BA 2 0 R 22 3x 1 5 pF Icke SDRAM X 2 A 12 0 OWN O AL12 0 R FE I OMM 0 RAS aoe ODTO ODTO 2x1pF ICAS O WM O CASR 5 m WE O W O MWER T A 5 At 2 2 pF D a n Document 06611 Revision A 28 Oct 2010 Dataram Corporation 2010 Page 3 DTM63389C 512MB 240 Pin Unbuffered ECC DDR2 DIMM INIDATARAM Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tcase 0 95 C Voltage on Vpp relative to Vss Vop 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Notes Temperature above 85C requires doubling the refresh rate i e 3 9us instead of 7 8us Recommended DC Operating Conditions Ta O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typ
16. tween valid commands Address bus inputs are stable during deselects Data bus inputs are switching Operating Bank Interleave Read Ipp7 Current 1325 mA Notes For all IppX measurements tex 3 ns trc 60 ns treo 15 ns tras 45 ns and trp 15 ns unless otherwise specified All currents are based on absolute maximum values Document 06611 Revision A 28 Oct 2010 Dataram Corporation 2010 Page 6 DTM63389C ioe 512MB 240 Pin Unbuffered ECC DDR2 DIMM INIDATARAM AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 450 450 ps CAS to CAS Command Delay teco 2 tck Clock High Level Width tou 0 48 0 52 tex Clock Cycle Time tex 3000 8000 ps Clock Low Level Width teL 0 48 0 52 tck Data Input Hold Time after DQS Strobe tou 175 ps DQ Input Pulse Width toipw 0 35 tex DQS Output Access Time from Clock toasck 400 400 ps Write DQS High Level Width toasH 0 35 tex Write DQS Low Level Width toast 0 35 tck DQS Out Edge to Data Out Edge Skew toasa 240 ps Data Input Setup Time Before DQS Strobe tos 100 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tex DQS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tur minimum of tc or teL ns Address and Command Hold Time after Clock tin 275 ps Address and Command Setup Time before Clock tis 200 ps
Download Pdf Manuals
Related Search