Integral INAFM8G44VMXB flash memory
Contents
1. 20 Set Multiple Mode C6h Y Y 21 Sleep E6h Y aa 22 Standby E2h Y 23 Standby Immediate E0h z Y M EX 24 Write Buffer E8h Y z ER 25 Write DMA CAh Y 26 Write Multiple C5h Y 27 Write Sectot s 30h Y Note FR Feature Register HD Head No of Drive Head Register SC Sector Count Register LBA LBA mode supported SN Sector Number Register Y Set up CY Cylinder Low High Register Not set up DR Drive bit of Drive Head register 4 3 Identify Drive Information The Identity Drive Command enables Host to receive parameter information from the device The parameter words in the buffer have the arrangement and meanings defined in below table All reserve bits or words are zeto Word Address Default Value Total Bytes Data Field Type Information 0 044Ah 2 General configuration bit significant for 22 Non removable device 1 xxxxh 2 Default number of cylinders 2 0000h 2 Reserved 3 xxxxh 2 Default number of heads 4 7E00h 2 Retired 5 0200h 2 Retired 6 xxxxh 2 Default number of sectors per track 7 8 xxxxh 4 Number of sectors per device 9 0000h 2 Retired 10 19 xxxxh 20 Serial Number in ASCII 20 0002h 2 Retired 21 0002h 2 Retired Number of ECC Bytes passed on Read Write Long 22 0004h 2 Commands 23 26 Aaaah 8 Firmware revis2. DA2 CS0 CS1 A OA NOTES 1 See 9 14 4 1 Host terminating an Ultra OMA data out burst 2 The definitions for Ihe STOP DOMARDY and HSTROBE signal lines are no longer in effect after DMARO and DMACK are negated Host terminating an Ultra DMA data out burst DMARO device DMACK host P STOP host DDMARDY device HSTROBE host a gt tom DD 15 0 host CRG ODS LI LI DAO DA1 DA y CS0 CS1 OK NOTES 1 See 9 14 4 2 Device pausing an Ultra DMA data out burst 2 The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and OMACK are negated Device terminating an Ultra DMA data out burst 20 3 4 Power Management System Power Consumption Ta 0 to 70 C Symbol Parameter Conditions MIN TYP MAX Unit Iccr Read current 5V 100 mA Iccw Write current 5V 105 mA Ipd Power down current 5V 0 2 0 4 mA Iccr Read current 3 3V 150 mA Iccw Write current 3 3V 160 mA Ipd Power down current 3 3V 0 3 mA 4 0 Software Interface 4 1 ATA Task File Registers The I O decoding of each register is as follows CS1 CS0 A2 Al AO DIOR 0 DIOW 1 DIOW 0 DIOR 1 1 0 0 0 0 Data Read Data Write 1 0 0 0 1 Error Feature 1 0 0 1 0 Sector Count Sector Count 1 0 0 1 1 Sector Number LBA7 0 Sector Number
3. LBA7 0 1 0 1 0 0 Cylinder Low LBA 15 8 Cylinder Low LBA 15 8 1 0 1 0 1 Cylinder High LBA 23 16 Cylinder High LBA 23 16 1 0 1 1 0 Drive Head LBA 27 24 Drive Head LBA 27 24 1 0 1 1 1 Status Command 0 1 1 1 0 Alternate Status Device Control 0 1 1 1 1 Drive Address Reserved 4 2 Command Sets Below table summarizes the AFM PATA DOM command set with the paragraphs that follow describing the individual commands and task file for each command No Command Set Code FR SC SN CY DR HD LBA 1 CFA Erase Sector s C0h Y Y Y Y 2 CFA Request Extended Error Code 03h 3 CFA Translate Sector 87h Y Y Y Y 21 4 CFA Write Multiple w o Erase CDh Y 5 CFA Write Sector w o Erase 38h Y 6 Check Power Mode E5h Y d x 7 Execute Device Diagnostic 90h as Y de EX 8 Identify Device ECh a Y d 9 Idle E3h Y Y En 10 Idle Immediate Eth Y 11 Initialize Device Parameters 91h Y Y Y 12 NOP 00h Y Er 13 Read Buffer E4h Y MN sz 14 Read DMA C8h Y Y Y Y Y Y 15 Read Multiple C4h Y Y Y Y Y Y 16 Read Sector s 20h Y Y Y Y Y Y 17 Read Verify Sector s 40h Y Y Y Y Y Y 18 Seek 70 Y Y Y Y Y 19 Set Features EFh Y I Y M
4. bit DMA channel and this signal will not be asserted 35 33 36 DA0 DA2 Device Address I This is 3 bit binary coded Address Bus 34 PDIAG Passed diagnostics I O This signal will be asserted by Device 1 to indicate to Device 0 that Device 1 has completed diagnostics CBLID Cable assembly type identify 37 38 CS0 CS1 Chip select I These signals are used to select the Command Block and Control Block registers When DMACK is asserted Cs0 and Cs1 shall be negated and transfers shall be 16 bit wide 39 DASP Device active Device I O During the reset protocol DASP shall be 1 present asserted by Device 1 to indicate that the device is present 41 42 VCC P Power supply 02 19 22 24 26 30 GND Ground 40 43 Note SI An input from the host system to the device o An output from the device to the host system I O An input output bi direction common ep Power supply Pin41 44 Only for 44pin AFM 2 3 Jumper Setting Follow diagram define AFM Master Slave Jumper J2 settings 2 3 144pin H V Jumper Settings c I Os O Os Co 2 O co 7 ml Master Slave 44pin Horizontal 44pin Vertical 2 3 240pin V Jumper Settings Master Slave Cable Select BEEBBEEBEEBEREBERBEI 40pin Vertical 2 3 340pin H Jumper Settings Cable Select Master 40pin Horizontal 3 0 Elect
5. the device is used to extend the register transfer cycle The determination of whether the cycle is to be extended is made by the host after ta from the assertion of DIOR or DIOW The assertion and negation of IORDY are described in the following three cases 3 1 Device never negates IORDY devices keeps IORDY released no wait is generated 3 2 Device negates IORDY before ta but causes IORDY to be asserted before ta IORDY is released prior to negation and may be asserted for no more than 5 ns before release no wait generated 3 3 Device negates IORDY before ts IORDY is released prior to negation and may be asserted for no more than 5 ns before release wait generated The cycle completes after IORDY is reasserted For cycles where a wait is generated and DIOR is asserted the device shall place read data on DD 7 0 for tap before asserting IORDY 4 DMACK shall remain negated during a register transfer 10 PIO timing parameters Mode 0 Model Mode2 Mode3 Mode 4 Note ns ns ns ns ns to Cycle time min 600 383 240 180 120 1 4 t Address valid to 70 50 30 30 25 DIOR DIOW setup min t2 DIOR DIOW min 165 125 100 80 70 1 toi DIOR DIOW recovery time 70 25 1 min t3 DIOW data setup min 60 45 30 30 20 t DIOW data hold min 30 20 15 10 10 t5 DIOR data setup min 50 35 20 20 20 te DIOR data hold min 5 5 5 5 5 tez DI
6. the sender connector 3 The parameter teyc shall be measured at the recipient s connector farthest from the sender 4 The parameter tu shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively Both the incoming signal and the outgoing response shall be measured at the same connector 5 The parameter taz shall be measured at the connector of the sender or recipient that is driving the bus but must release the bus the allow for a bus turnaround 15 Ultra DMA data burst timing descriptions Itzcverye Typical sustained average two cycle time LYP NG Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE Two cycle time allowing for clock variations from rising edge to next rising edge or from falling edge to next falling edge of STROBE Data setup time at recipient from data valid until STROBE edge See note 2 5 Data hold time at recipient from STROBE edge until data may become invalid See note 2 5 Data valid setup time at sender from data valid until STROBE edge See note 3 Data valid hold time at sender from STROBE edge until data may become invalid See note 3 z CRC word valid hold time at sender from DMACK negation until CRC may become invalid See note 3 Unlimited interlock time See note 1 Envelope time from DMACK to STOP and HDMARDY during data in burst initiation and from DMACK
7. to STOP during data out burst initiation Ready to final STROBE time no STROBE edges shall be sent this long after negation of ltos ovs ics ltcy tovs zs ltozes es lu tz tza tzan z pause time that recipient shall wait to pause after negating v2 A Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst E Pd NOTES 1 The parameters ty tj in Figure 74 and Figure 75 and t indicate sender to recipient or recipient to sender interlocks i e one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding ty is an unlimited interlock that has no maximum time value tyu is a limited time out that has a defined minimum t is a limited time out that has a defined maximum 2 80 conductor cabling See 7 3 shall be required in order to meet setup tos tes and hold toy tci times in modes greater than 2 3 Timing for tous town tevs and tevy shall be met for lumped capacitive loads of 15 and 40 pf at the connector where the Data and STROBE signals have the same capacitive load value Due to reflections on the cable these timing measurements are not valid in a normally functioning system 4 For all modes the parameter tziorpy may be greater than teny due to the fact that the host has a pull up on IORDY giving it a known state when released 5 The parameters tos and to for mode 5 are defined for a recipie
8. OER DIAGRAM eor 4 SPECIFICA UL NAAA MY 4 2 1 PIN ASSIGNMENTS dede 4 2 2 PIN DESGRIPTION 442 20 2 BADING GAAN NG NG edere iua c eeu re eoo MAG AG NONA eoe e ice 5 2 5 JUMPER SETTING 5e hei ia etti AN cs leia 7 2 3 1 44pin H V Jumper Settings emen 7 2 3 2 40pin V Jumper Settings aa 7 2 3 3 40pin H Jumper Settings eee essen 8 ELECIRICAL CHARACTERIST ICS 5 es oe eo eh roto esae oerte ae ea Oeo e erano do dea Senes cione KARERA 9 3 1 ABSOLUTE MAXIMUM RATING ccccccccessseececcceceecesescecccecesueseccececscusuenescesesscuauesesceseesauens 9 3 2 DC CHARACTERISTICS OF 5 0V I O CELLS HOST INTERFACE eee 9 3 3 AC CHARACTERISTICS u G TAB NN a e eo gage tances vore PR Fea RERO 10 3 3 1 PIO Data Transfert io oai n t deret e NANANG ee RE RA 10 3 3 2 Multiword DMA Data Transfer eese ehem eene aa esee ee nene 12 3 3 3 Ultra DMA Data Transfer oocccccncncnnnoccccnononnnnniroconononnnnnnonccncnnnnaninoronncnonnanininccn s 15 3 4 POWER MANAGEMENT cccscsssesseccccceccesescecesecuscenesscccsscusceseecececscuecscecesecuecesesseceseenees 21 SOFTWARE INTERFACE Jj nananana ap ndi AA AA NAA 21 4 1 ATA TASK FILE REGISTERS 0ccccccceeseseseseveseseveseveceveversvesevevesesesevesesevesesecesesesereseeeeenens 21 4 2 COMMAND SES ia 21 4 3 IDENTIFY DRIVE INFORMATION ccccccceseececcceceecesscecececeaueueececeseceaueeeseeceseseaunes
9. OR data tristate max 30 30 30 30 30 2 to DIOR DIOW to address 20 15 10 10 10 10 valid hold min trp Read Data Valid to IORDY 0 0 0 0 0 active if IORDY initially low after ta min ta IORDY Setup time 35 35 35 35 35 3 tp IORDY Pulse Width max 1250 1250 1250 1250 1250 tc IORDY assertion to release 5 5 5 5 5 max Notes 1 tois minimum total cycle t is minimum DIOR DIOW assertion time and tj is the minimum DIOR DIOW negation time A host implementation shall lengthen tz to ensure that to is equal to or greater than the value reported in the devices IDENTIFY DEVICE data A device implementation shall support any length host implementation 2 This parameter specifies the time from the negation edge of DIOR to the time that the data is released by the device 3 The delay from the activation of FIOR or DIOW until the state of IORDY is first sampled If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle is complete If the device is not driving IORDY negated at the ta after the activation of DIOR or DIOW that ts shall be met and tgp is not applicable If the device is driving IORDY 11 negated at the time ta after the activation of DIOR or DIOW then tRD shall be met and ts is not applicable 4 Mode may be selected at the highest mode for the device if CS 1 0 and DA 2 0 do not change between read or write cycle or select
10. data in burst 2 The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Device terminating an Ultra DMA data in burst DMACK host STOP host HDMARDY host DSTROBE device DAO DAT DA2 CS0 CS1 NOTES 1 See 9 13 4 2 Host pausing an Ultra DMA data in burst 2 The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Host terminating an Ultra DMA data in burst 18 DMARQ device tui DMACK host lack STOP DDMARDY device HSTROBE host D DD 15 0 AR res SCR PAWAYANAW ANA tack DAO DA1 DA2 CS0 CS1 NOTES 1 See 8 14 1 Initiating an Ultra DMA data out burst 2 The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Initialing an Ultra DMA data out data burst HSTROBE at host DD 18 0 at host HSTROBE at device DD 15 0 at device ZOO TEE EEE ION NOTES 1 See 9 14 2 The data out transfer 2 DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Sustained Ultra DMA data out butst 19 DAO DA1
11. eeeeeeauaas 22 PHYSICAL DIMENSION sec ssscsicvstecadesssosssabccescassavevshecscdessesasecseecsesedses aveuss odcesssebaneceseetesescesatass 25 5 1 44 PIN HORIZONTAL 42 53 ee o 25 5 2 44PIN VERTICAL c ccssescececccnccessecscccececcevescecesecusceseececeesceeceesecssccuceeseesecesecuecereesseeseeeees 26 5 3 AOPIN VERTICAL 3p Ana AO BIRD aE REET 27 5 4 40PIN HORIZONTAL CONNECTOR AT TOP u s nananana asana saaan 28 5 5 40PIN HORIZONTAL CONNECTOR AT BOTTOM iseeeeee eee eee ee enne 29 1 0 Block Diagram Controller 2 0 Specification 2 1 Pin Assignments a ee 01 RESET 02 GND 03 DD7 04 DD8 05 DD6 06 DD9 07 DD5 08 DD10 09 DD4 10 DD11 11 DD3 12 DD12 13 DD2 14 DD13 15 DD1 16 DD14 17 DDO 18 DD15 19 GND 20 KEY_PIN OPEN 21 DMARQ 22 GND 23 DIOW STOP 24 GND 25 DIOR HDMARDY HSTOBE 26 GND 27 IORDY DDMARDY DSTROBE 28 CSEL 29 DMACK 30 GND 31 INTRQ 32 IOIS16 33 DA1 34 PDIAG CBLID 35 DAO 36 DA2 37 CS0 38 CS1 39 DASP 40 GND 41 VCC 42 VCC 43x GND 44 NC Note Pin 41 44 only for 44pin AFM 2 2 Pin Description Pin No Signal I O Description 01 RESET I Hardware reset signal from the host 17 15 13 11 09 07 DD0 DD15 Device Data I O 16 bit bi direction Data Bus DD 7 0 are 05 03 04 06 08 10 used for 8 bit regi
12. integral STORAGE TECHNICAL DATASHEET ATA Flash Module AFM PATA DOM Specification Version 2 3 Features O Standard ATA IDE Bus Interface 512 Bytes Sector ATA command set compatible Selectable Master Slave Setting Capacities 8GB up to 64GB SLC or MLC Data Transfer mode Support Data Transfer up to PIO mode 6 Support Data Transfer up to Multiword DMA mode 2 Support Data Transfer up to Ultra DMA mode 5 Performance Integral Z Series MLC Sustain Read Speed up to 43MB s Sustain Write Speed up to 36MB s Integral E Series SLC Pls call for availability Sustain Read Speed up to 45MB s Sustain Write Speed up to 44MB s Temperature Ranges gt Commercial grade e 0 C to 70 C for operating environment e 25 C to 85 C for storage environment gt Industrial grade Pls call for availability e 40 C to 85 C for operating environment e 40 C to 85 C for storage environment Operating Voltage 33V 5 0V O Standard Female IDE Connector 44 pin Vertical Horizontal 40 pin Vertical Horizontal with Power adapter 4 pin LP4 power connector Intelligent ATA IDE Module Built in Embedded Flash File System Implements dynamic wear leveling algorithms and static wear leveling algorithms to increase endurance of flash media Built in ECC corrects up to 12 random bits error per 512 bytes RoHS Compliance 1 0 2 0 3 0 4 0 5 0 TABLE OF CONTENTS BE
13. ion in ASCII 27 46 xxxxh 40 Model number in ASCII Maximum number of sector that shall be 47 8001h 2 transferred on Read Write Multiple commands 48 0000h 2 Reserved 49 2B00h 2 Capabilities LBA DMA Supported 50 4000h 2 Reserved 51 0200h 2 PIO data transfer cycle timing mode 2 52 0000h 2 Retired 53 0007h 2 Word 54 58 64 70 and 88 are valid 54 xxxxh 2 Current numbers of cylinders 55 xxxxh 2 Current numbers of heads 56 xxxxh 2 Current sectors per track Word Address Default Value Total Bytes Data Field Type Information Current capacity in sectors LBAs Word 57 LSW 57 58 xxxxh 4 Word 58 MSW 59 0101h 2 Multiple sector setting is valid 60 61 xxxxh 4 Total number of sectors addressable in LBA Mode 62 0000h 2 Retired 63 0007h 2 Multiword DMA mode 2 and below are supported 64 0003h 2 Advance PIO transfer modes supported 65 0078h 2 Minimum Multiword DMA transfer cycle time 23 120nsec Manufacturer s recommended Multiword DMA 66 0078h 2 transfer cycle time 120nsec Minimum PIO transfer cycle time without flow 67 0078h 2 control 120nsec Minimum PIO transfer cycle time with IORDY flow 68 0078h 2 control 120nsec 69 79 0000h 26 Reserved 80 0030h Major version number 81 0000h Reserved 82 7009h 2 Supports Security Mode feature set 83 5004h 2 Reserved 84 4000h 85 7009h Feature Setting 86 1004h Feature Setting 87 4000h Feature Setting Ultra DMA mode 5 and below are
14. nt at the end of the cable only in a configuration with a single device located at the end of the cable This could result in the minimum values for tys and to for mode 5 at the middle connector being 3 0 and 3 9 ns respectively 16 DMARQ device DMACK host tack a tew STOP me 670707013 tenw lack HDMARDY M N wap taoroy tng tzrs DSTROBE device town taz DD 15 0 KKK KKK tacx DAO DAT DA2 eee CS0 CS1 XXXXA NOTES 1 See 9 13 1 Initiating an Ultra DMA data in burst 2 The definitions for the DIOW STOP DIOR HDMARDY HSTROBE and IORDY DDMARDY DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Initialing an Ultra DMA data in burst OSTROBE at device DD 15 0 at device OSTROBE at host 4 trac tonic bac pn 24916479479 489 479747079 9 PEI II NOTES 1 See 9 13 2 The data in transfer 2 DD 15 0 and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Sustained Ultra DMA data in burst 17 DMARQ device DMACK host STOP host Mm tu HDMARDY ZARZ host Na tss DSTROBE device DD 15 0 DAO DA1 DA2 CS0 CS1 NOTES 1 See 9 13 4 1 Device terminating an Ultra DMA
15. rical Characteristics 3 1 Absolute Maximum Rating Item Symbol Parameter MIN MAX Unit 1 Vpp Vss DC Power Supply 0 3 5 5 V 2 VIN Input Voltage Vss 0 3 Vpp 0 3 V 3 Ta Operating Temperature 0 70 9C 4 Tst Storage Temperature 25 85 C Parameter Symbol MIN TYP MAX Unit Vpp Voltage Vpp 3 0 3 3 3 6 V 4 5 5 0 5 5 V 3 2 DC Characteristics of 5 0V I O Cells Host Interface Symbol Parameter Conditions MIN TYP MAX Unit Vil Input Low Voltage TTL 5V 0 85 V Vih Input High Voltage 1 25 V Vil Input Low Voltage TTL 3 3V 105 V Vih Input High Voltage 1 75 V Vol Output Low Voltage Iol 4 32 mA 0 4 V Voh Output High Voltage Ioh 4 32 mA 2 4 V lin Input Leakage Current No pull up or pull 10 1 10 pA down loz Tri state Output Leakage 10 1 10 pA Current 3 3 AC Characteristics 3 3 1PIO Data Transfer ADDR valid v YTY See note 1 KAKA NA t ty ag ta DIOR DIOW WRITE DOTS s NZ O DDi7 0 See note 2 ts t READ DD Oe I a oS See note 2 ts te B to IORDY See note 3 3 1 er JORDY AXAXXA MARA XA AX XL See note 3 3 2 IORDY NAA XA AAA See note 3 3 3 ab to NOTES 1 Device address consists of signals CS0 CS1 and DA 2 0 2 Data consists of DD 7 0 3 The negation of IORDY by
16. s at the highest mode supported by the slowest device if CS 1 0 and DA 2 0 do change between read or write cycles 3 3 2Multiword DMA Data Transfer CS0 CS1 See note 1 See note 4 DMACK DIOR DIOW DD 15 0 Write DD 15 0 NOTE The host shall not assert DMACK or negate both CSO and CS1 until the assertion of DMARQ is detected The maximum time from the assertion of DMARQ to the assertion of DMACK or the negation of both CSO and CS1 is not defined Initialing a Multiword DMA data burst 12 CS0 CS1 DMARQ DMACK DIOR DIOW Read DD 15 0 Write DD 15 0 Sustaining a Multiword DMA data burst CS0 CS1 ty DMARQ See note DMACK DIOR DIOW Read DD 15 0 Write DO 1 0 XXX XXX XXX KKK XX NOTE To terminate the data burst the Device shall negate DMARO within t of the assertion of the current DIOR or DIOW pulse The last data word for the burst shall then be transferred by the negation of the current DIOR or DIOW pulse If all data for the command has not been transferred the device shall reassert DMARQ again at any later time to resume the OMA operation as shown in figure 66 Device terminating a Multiword DMA data burst 13 CS0 CS1 ty DMARQ YYY See note 2 DMACK See note 1 DIOR DIOW Read DD 15 0 Write DD 15 0 NOTE 1 To terminate the transmission of a data burst the ho
17. st shall negate DMACK within t after a DIOR or DIOW pulse No further DIOR or DIOW pulses shall be asserted for this burst 2 If the device is able to continue the transfer of data the device may leave DMARQ asserted and wait for the host to reassert DMACK or may negate DMARO at any time after detecting that DMACK has been negated Host terminating a Multiword DMA data burst Multiword DMA timing parameters Mode 0 Model Mode2 Note ns ns ns to Cycle time min 480 150 120 See note tp DIOR DIOW asserted pulse width min 215 80 70 See note tg DIOR data access max 150 60 50 tp DIOR data hold min 5 5 5 tG DIOR DIOW data setup min 100 30 20 tH DIOW data hold min 20 15 10 tr DMACK to DIOR DIOW setup min 0 0 0 ty DIOR DIOW to DMACK hold min 20 5 5 tkR DIOR negated pulse width min 50 50 25 See note tkw DIOW negated pulse width min 215 50 25 See note tg DIOR to DMACK delay max 120 40 35 ttw DIOW to DMACK delay max 40 40 35 tm CS 1 0 valid to DIOR DIOW min 50 30 25 tn CS 1 0 hold min 15 10 10 tz DMACK to read data released max 20 25 25 Notes ty is the minimum total cycle tp is the minimum DIOR DIOW assertion time and tk tkR or tkw 14 as appropriate is the minimum DIOR DIOW negation time A host shall lengthen tp and or tx to ensure that to is equal to the val
18. ster transfers 12 14 16 18 21 DMARQ DMA Request O For DMA data transfers Device will assert DMARQ when the device is ready to transfer data to or from the host 23 DIOW 1 O Write I This is the strobe signal used by the host to write to the device register or Data port STOP Stop UDMA Burst The host assert this signal during an UDMA burst to stop the DMA burst 25 IORDY I O channel ready O This signal is used to temporarily stop the host register access read or write when the device is not ready to respond to a data transfer request DDMARDY UDMA ready The device will assert this signal to indicate that the device is ready to receive UDMA data out burst DSTROBE UDMA data When UDMA mode DMA Read is active strobe this signal is the data in strobe generated by the device 28 CSEL Cable select I This pin is used to configure this device as Device 0 or Device 1 29 DMACK DMA I This signal is used by the host in respond acknowledge to DMARQ to initiate DMA transfer 31 INTRQ Interrupt O When this device is selected this signal is the active high Interrupt Request to the host Pin No Signal I O Description 32 IOIS16 O During PIO transfer mode0 1or 2 this pin indicates to the host the 16 bit data port has been addressed and the device is prepared to send or receive a 16 bit data word When transferring in DMA mode the host must use a 16
19. supported 88 203Fh 2 UDMA modes select 89 92 0000h 8 Reserved 93 xxxxh 94 128 0000h 2 Enhanced security erase supported 129 159 0000h 62 Reserved vendor unique bytes 160 255 0000h 192 Reserved Note 1 a Vender Specific Configuration 2 n Host Selectable Configuration 24 5 0 Physical Dimension 5 1 44pin Horizontal Note 1 Unit mm 2 General Tolerance 0 1 25 5 2 44pin Vertical Note 1 Unit mm 2 General Tolerance 0 1 26 5 3 40pin Vertical e Note 1 Unit mm 01 2 General Tolerance 27 5 4 40pin Horizontal Connector at Top 23 00 hole 2 2 R Q 8 N 5 o 30 00 30 00 28 20 TOP SIDE 417 HS 5 9666 0 olo oo 0 oo oo ojej 0 00 LESS HESS EB EEE EHE HE HT 0 00 6 00 8 3 28 R 83 8 ei 8 w o 26 00 30 00 30 00 BOTTOM SIDE 417 0 00 0 00 55 00 27 50 4 64 0 00 28 5 5 40pin Horizontal Connector at bottom 3 00 hole 2 8 3 N 8 o 30 00 30 00 28 20 TOP SIDE PEPEE PSA A 4 17 0 00 epi tee e ele E A 0 00 9500 m 3 3 88 e N 88 8 8 B o 66 00 30 00 30 00 BOTTOM SIDE AEREO PEREA 4 17 gt 0 00 UIUHHUHEHHHHEHEHHEHHBHHHHHHNHI 0 00 7 40 00 55 00 27 50 4 64 0 00 Note 1 Unit mm 2 General Tolerance 0 1 29
20. ue reported in the devices IDENTIFY DEVICE data 3 3 3Ultra DMA Data Transfer Ultra DMA data burst timing requirements m KAKIK em in ns in ns in ns x LADA in ns location Min Max Min Max Min Max Min Max Min Max Min Max 30 Sender Note 3 Sender Recipient Recipient Sender Sender Device Device Host Host Device Sender Device Note 4 Host Host Note 5 Host Device Host Sender Recipient Device Device Host Sender E 3 d ro o el les Fr o lt lo 3 v Bj x1 pur Sl h alala alis nil lols BEEEE o dee w o M 5 5 o o o N nl a TT lst lala Ja als RE tw os o 3 2 See 8 s a hee 9 4 ro o o af 0 0 cn cn a afen 74 N 4 O 7M r 2 6 md f mg ah S Ma S E o o eV En o W e Cn e en e e e a tn ho lo to aja ue oo a olo S N e ro N r NI td o o M 23 o lo P S 211 R o on ero tow tes ten tes tem zs Hozes ites ty oo tu he itz ET no tew as ra ltospyz_ ltzospy tack itss OTES N 1 All timing measurement switching points low to high and high to low shall be taken at 1 5 V 2 All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column For example in the case of ters both STROBE and DMARDY transitions are measured at
Download Pdf Manuals
Related Search