Integral INMPCIE64G50MXB solid state drive
Contents
1. 1 05 V Vih Input High Voltage 1 75 V Vol Output Low Voltage IIoll 4 32 mA 0 4 V Voh Output High Voltage IIohlz 4 32 mA 2 4 V lin Input Leakage Current No pull up or pull 10 1 10 pA down Ioz Tri state Output Leakage 10 1 10 pA Current 3 3 AC Characteristics 3 3 1 PIO Data Transfer ADDR valid 7 VAVAYAT See note 1 XXXX NX X X K n ty ta DIOR DIOW WRITE DOCS Oy a DD 7 0 See note 2 READ DD T 0 See note 2 ts ts la e ta IORDY See note 3 3 1 cai IORDY XX XX XAIX XX X XX See note 3 3 2 IORDY XAXXXXXXXXXXN See note 3 3 3 t NOTES 1 Device address consists of signals CSO CS1 and DA 2 0 2 Data consists of DD 7 0 3 The negation of IORDY by the device is used to extend the register transfer cycle The determination of whether the cycle is to be extended is made by the host after ta from the assertion of DIOR or DIOW The assertion and negation of IORDY are described in the following three cases 3 1 Device never negates IORDY devices keeps IORDY released no wait is generated 3 2 Device negates IORDY before ta but causes IORDY to be asserted before ta IORDY is released prior to negation and may be asserted for no more than 5 ns before release no wait generated 3 3 Device negates IORDY before ta IORDY is released prior to negation and may be asserted for no more than 5 ns before release wait genera2. Note 4 Host Host Note 5 Host Device Host Sender Recipient Device Device Host Sender D D Em M fele al L ho to EE un nii n ho s amp o d o o N tovc trs tous tes us tozes tes ty CT DEN az tza tzan as se tac ss OTES N 1 All timing measurement switching points low to high and high to low shall be taken at 1 5 V 2 All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column For example in the case of ters both STROBE and DMARDY transitions are measured at the sender connector 3 The parameter tc shall be measured at the recipient s connector farthest from the sender 4 The parameter tu shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively Both the incoming signal and the outgoing response shall be measured at the same connector 5 The parameter taz shall be measured at the connector of the sender or recipient that is driving the bus but must release the bus the allow for a bus turnaround 15 Ultra DMA data burst timing descriptions Typical sustained average two cycle time rye teve Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE edge 2 Two cycle time allowing for clock variations from rising edge to next rising edge or from falling edge to
3. This parameter specifies the time from the negation edge of DIOR to the time that the data is released by the device 3 The delay from the activation of FIOR or DIOW until the state of IORDY is first sampled If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle is complete If the device is not driving IORDY negated at the t4 after the activation of DIOR or DIOW that t shall be met and tgp is not applicable If the device is driving IORDY 10 negated at the time t after the activation of DIOR or DIOW then tRD shall be met and t is not applicable Mode may be selected at the highest mode for the device if CS 1 0 and DA 2 0 do not change between read or write cycle or selects at the highest mode supported by the slowest device if CS 1 0 and DA 2 0 do change between read or write cycles 11 3 3 2 Multiword DMA Data Transfer See note 4 DMACK DIOR DIOW Read XX KX XXX DD 15 0 Write DD 15 0 NOTE The host shall not assert DMACK or negate both CSO and CS1 until the assertion of DMARQ is detected The maximum time from the assertion of DMARQ to the assertion of DMACK or the negation of both CSO and CS1 is not defined Initialing a Multiword DMA data burst CS0 CS1 DMARQ DMACK DIOR DIOW Read DD 15 0 Write DD 15 0 Sustaining a Multiwo
4. Y 8 Identify Device ECh Y 9 Idle E3h Y Y 10 Idle Immediate Elh Y 2x 11 Initialize Device Parameters 91h Y Y Y 12 NOP 00h Y E 13 Read Buffer E4h i z Y as sa 14 Read DMA C8h Y Y Y Y Y Y 15 Read Multiple C4h Y Y Y Y Y Y 16 Read Sector s 20h Y Y Y Y Y Y 17 Read Verify Sector s 40h Y Y Y Y Y Y 18 Seek 70 Y Y Y Y Y 19 Set Features EFh Y Y 20 Set Multiple Mode C6h Y Y PS E 21 Sleep E6h Y E 22 Standby E2h Y da 23 Standby Immediate E0h La si Y i 24 Write Buffer E8h Y E i2 25 Write DMA CAh Y 26 Write Multiple C5h Y 27 Write Sector s 30h Y Note FR Feature Register HD Head No of Drive Head Register SC Sector Count Register LBA LBA mode supported SN Sector Number Register Y Set up CY Cylinder Low High Register Not set up DR Drive bit of Drive Head register 22 4 3 Identify Drive Information The Identity Drive Command enables Host to receive parameter information from the device The parameter words in the buffer have the arrangement and meanings defined in below table All reserve bits or words are Zero Word Address Default Value Total Bytes Data Field Type Information General configuration bit significant for 0 040Ah 2 Non removable device 1 Aaaah 2 Defaul
5. for lumped capacitive loads of 15 and 40 pf at the connector where the Data and STROBE signals have the same capacitive load value Due to reflections on the cable these timing measurements are not valid in a normally functioning system 4 For all modes the parameter tziorpy may be greater than teny due to the fact that the host has a pull up on IORDY giving it a known state when released 5 The parameters tos and ton for mode 5 are defined for a recipient at the end of the cable only in a configuration with a single device located at the end of the cable This could result in the minimum values for tos and to for mode 5 at the middle connector being 3 0 and 3 9 ns respectively 16 DMARQ device DMACK host tack je few STOP me RXXX tu tack HDMARDY M SSA wap taoroy lese ters DSTROBE device town taz DD 150 PODI tacx DAO DAT DA2 vert CS0 CS1 PDA NOTES 1 See 9 13 1 Initiating an Ultra DMA data in burst 2 The definitions for the DIOW STOP DIOR HDMARDY HSTROBE and IORDY DDMARDY DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Initialing an Ultra DMA data in burst OSTROBE at device DD 15 0 at device OSTROBE at host 4 trac tonic tosc pn 24916479479 499 4797470799 7D 7474747070707 NOTES 1 See 9 13 2 The dala in transfer 2 DD 15 0 and DSTROBE signals are shown at both the host and the device to emphasize
6. next falling edge of STROBE Data setup time at recipient from data valid until STROBE edge See note 2 5 Data hold time at recipient from STROBE edge until data may become invalid See note 2 5 Data valid setup time at sender from data valid until STROBE edge See note 3 Data valid hold time at sender from STROBE edge until data may become invalid See note 3 CRC word valid hold time at sender from DMACK negation until CRC may become invalid See note 3 Unlimited interlock time See note 1 Envelope time from DMACK to STOP and HDMARDY during data in burst initiation and from DMACK to STOP during data out burst initiation tzcvc tos ovs tes ca toys tyes tozrs uo taz za Ito 2 A Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst find id NOTES 1 The parameters ty tj in Figure 74 and Figure 75 and t indicate sender to recipient or recipient to sender interlocks i e one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding ty is an unlimited interlock that has no maximum time value tyu is a limited time out that has a defined minimum t is a limited time out that has a defined maximum 2 80 conductor cabling See 7 3 shall be required in order to meet setup tos tes and hold tpi tci times in modes greater than 2 3 Timing for tous town tevs and tevy shall be met
7. cas s Sea Sscessesiassceassstsedecsstasuassessevaseasacbssssessscsssocsascecsstacen 25 WEIGHT E R 25 1 0 Block Diagram PATA Link Controller 1 4 Capacity Specification 16GB 16 441 270 272 16383 16 63 32GB 32 279 224 320 16383 16 63 64GB pls call 16383 16 63 2 0 Specification 2 1 Pin Assignments M CTU UCU TNT Pin Number Signal Pin Number Signal 1 HDO 2 HD15 3 HD1 4 GND 5 HD2 6 HD14 7 HD3 8 HD13 9 GND 10 HD12 11 HD4 12 HD11 13 HD5 14 HD10 15 GND 16 HD9 17 HD6 18 GND 19 HD7 20 HD8 21 GND 22 nHRESET 23 NC 24 nHIOW 25 NC 26 CSEL 27 GND 28 nHIOR 29 GND 30 nDMACK 31 NC 32 DMARQ 33 NC 34 GND 35 GND 36 NC 37 HAO 38 NC 39 HAI 40 GND 41 HA2 42 IORDY 43 nIOIS16 44 INTRQ 45 nPDIAG 46 nHCSO 47 3V3 48 nHCS1 49 3V3 50 GND 51 3V3 52 nDASP 2 2 Pin Description Pin No Signal I O Description 22 RESET I Hardware reset signal from the host 1 3 5 7 11 13 17 HD0 HD15 Device Data VO 16 bit bi direction Data Bus DD 7 0 are 19 20 16 14 12 used for 8 bit register transfers 10 8 6 2 32 DMARQ DMA Request o For DMA data transfers Device will assert DMARQ when the device is ready to transfer data to or from the host 24 DIOW LO Write I This is the s
8. cer Read current 3 3V 55 mA Iccw Write current 3 3V 55 mA Ipd Power down current 3 3V 0 3 mA 4 0 Software Interface 4 1 ATA Task File Registers The I O decoding of each register is as follows CS1 CS0 A2 AI AO DIOR 0 DIOW 1 DIOW 0 DIOR 1 1 0 0 0 0 Data Read Data Write 1 0 0 0 1 Error Feature 1 0 0 1 0 Sector Count Sector Count 1 0 0 1 1 Sector Number LBA7 0 Sector Number LBA7 0 1 0 1 0 0 Cylinder Low LBA 15 8 Cylinder Low LBA 15 8 1 0 1 0 1 Cylinder High LBA 23 16 Cylinder High LBA 23 16 1 0 1 1 0 Drive Head LBA 27 24 Drive Head LBA 27 24 1 0 1 1 1 Status Command 0 1 1 1 0 Alternate Status Device Control 0 1 1 1 1 Drive Address Reserved 21 4 2 Command Sets Below table summarizes the PATA MINI PCIE command set with the paragraphs that follow describing the individual commands and task file for each command No Command Set Code FR SC SN CY DR HD LBA 1 CFA Erase Sector s COh Y Y Y Y Y Y 2 CFA Request Extended Error Code 03h Y 3 CFA Translate Sector 87h Y 4 CFA Write Multiple w o Erase CDh Y 5 CFA Write Sector w o Erase 38h Y 6 Check Power Mode E5h s5 Y E pe 7 Execute Device Diagnostic 90h
9. e asserted by Device 1 to indicate to Device 0 that Device 1 has completed diagnostics CBLID Cable assembly type identify 46 48 CS0 CS1 Chip select I These signals are used to select the Command Block and Control Block registers When DMACK is asserted Cs0 and Cs1 shall be negated and transfers shall be 16 bit wide 52 DASP Device active Device I O During the reset protocol DASP shall be 1 present asserted by Device 1 to indicate that the device is present 47 49 51 VCC P Power supply 9 15 21 27 29 35 GND Ground Note p An input from the host system to the device O po p An output from the device to the host system An input output bi direction common Power supply 3 0 Electrical Characteristics 3 1 Absolute Maximum Rating Item Symbol Parameter MIN MAX Unit 1 Vpp Vss DC Power Supply 0 3 5 5 V 2 VIN Input Voltage Vss 0 3 Vpp 0 3 V 3 Ta Operating Temperature 0 70 C 4 Tst Storage Temperature 25 85 C Parameter Symbol MIN TYP MAX Unit Vpp Voltage Vpp 3 0 3 3 3 6 V 4 5 5 0 5 5 V 3 2 DC Characteristics of 5 0V I O Cells Host Interface Symbol Parameter Conditions MIN TYP MAX Unit Vil Input Low Voltage TTL SV 0 85 V Vih Input High Voltage 1 25 V Vil Input Low Voltage TTL 3 3V
10. eode epa ose een c es a pa ici cedebsaadssisssbeasedsssanesees 6 ELECTRICAL CHARACTERISTICS sisesccsisstssssssesscessssscssecseseseassateasevsseasessssasadecseassassctssbeseesss 8 3 1 ABSOLUTE MAXIMUM RATING csssccsssscsssccescccescccecccssccccececescceescccssccesssecsscccsssecssccessceessse 8 3 2 DC CHARACTERISTICS OF 5 0V I O CELLS HOST INTERFACE e eee ee ee eene een neo 8 3 33 AC CHARACTERISTICS wecosiiscssscesssesstiascessssedsccssssnisdesssccacsshossusteaedsecesseateossedececssisvieeavesdeescuases 9 3 3 1 PIO Data Transfer oir deccccssssesseveseecccsasosveseedseesuccuseesuvassscceseceseesesduesdecsectesvvessecs 9 3 3 2 Multiword DMA Data Transfer eee esee eee eee en enne ette tna sese eee tette asse seen 12 3 3 3 Ultra DMA Data Transtfer e eeee cree eee ee eee eee tna n esee ettet sa sese see teen asses eee 15 3 4 POWER MANAGEMENT sissisvisicrissicisiconicionisciossciaziciesionisioseericienionivioniscivivibntiscosisnicionivziatetio 21 SOFTWARE INTERFACE eoe tiara eher Un a eaae eo seta da e trossos sviesos o Una Roca leva sieste eoa ia nado 21 4 1 ATA TASK FILE REGISTERS e oese eo ener kao etn aa tUa boo eta Pao bo pe len oae toa aae i pa Fo e dvo Te Pa aseo Ed 21 42 COMMAND SETS lan and nntennn Sab duane duc ti 22 4 3 IDENTIFY DRIVE INFORMATION sccccssssscssssccsessscccesssccccssssccccnscaccscsacccessssccccsssescesacecessnees 23 PHYSICAE DIMENSION ees es es
11. integral STORAGE TECHNICAL DATASHEET Integral Mini PCle 50mm Specification Version 1 0 Features e Standard ATA IDE Bus Interface 512 Bytes Sector ATA command set compatible Selectable Master Slave Setting Capacities Integral Z Series MLC 16GB 32GB 64GB Integral E Series SLC 16GB Data Transfer mode Support Data Transfer up to PIO mode 6 Support Data Transfer up to Multiword DMA mode 2 Support Data Transfer up to Ultra DMA mode 5 Performance Integral Z Series MLC Flash Sustain Read Speed up to 35MB s Sustain Write Speed up to 15MB s Integral E Series SLC Flash Sustain Read Speed up to 45MB s Sustain Write Speed up to 35MB s Temperature Ranges 0 C to 70 C for operating 25 C to 85 C for storage Operating Voltage 33V Intelligent ATA IDE Module Built in Embedded Flash File System Implements dynamic wear leveling algorithms and static wear leveling algorithms to increase endurance of flash media Built in ECC corrects up to 12 random bits error per 512 bytes RoHS Compliance 1 0 2 0 3 0 4 0 5 0 6 0 TABLE OF CONTENTS BLOCK DIAGRAM 2 illa 4 KE CAPACITY SPECICATION isdn tee Uva rode ed Cue ep vean sbesssessubeededescesavchesdecveesesess 4 SPECIFICATION nate seeicoseeseeebeddeecceoa e altipiani siete terrei Tua addu 5 2 1 PINASSIGNMENTS anyets nn Ant nan nn Ans 5 2 2 PIN DESCRIPTIONS suisse di desde sssses elo eda aep sa erp ci
12. n 5 5 5 tg DIOR DIOW data setup min 100 30 20 ty DIOW data hold min 20 15 10 ti DMACK to DIOR DIOW setup min 0 0 0 ty DIOR DIOW to DMACK hold min 20 5 5 tkr DIOR negated pulse width min 50 50 25 See note txw DIOW negated pulse width min 215 50 25 See note tir DIOR to DMACK delay max 120 40 35 tiw DIOW to DMACK delay max 40 40 35 tm CS 1 0 valid to DIOR DIOW min 50 30 25 ty CS 1 0 hold min 15 10 10 tz DMACK to read data released max 20 25 25 Notes t is the minimum total cycle tp is the minimum DIOR DIOW assertion time and tx txr or tkw as appropriate is the minimum DIOR DIOW negation time A host shall lengthen tp and or tg to ensure that t is equal to the value reported in the devices IDENTIFY DEVICE data 14 3 3 3 Ultra DMA Data Transfer Ultra DMA data burst timing requirements s in ns in ns in ns in ns in ns in ns location Min Max 30 53 5 Min Max Min Max Min Max Min Max ST 4 Sender 54 ot 5l Note 3 115 SN EE Sender 3 Recipient 50 Recipient Sender 62 Sender Device 50 Device Host 62 Host LU i Device Sender Device o EP to cer tet feel EI LL ER LLL LL LE N o e ed no oO 5 o o a e o e aldio o e E E E Ni ho LLL El EL L da o B a N o ci ho o on e e e
13. rd DMA data burst CS0 CS1 ty DMARQ See note DMACK DIOR DIOW Read DD 15 0 DD 15 0 GX KX KKXKX XXX KX NOTE To terminate the data burst the Device shall negate DMARQ within t of the assertion of the current DIOR or DIOW pulse The last data word for the burst shall then be transferred by the negation of the current DIOR or DIOW pulse If all data for the command has not been transferred the device shall reassert DMARQ again at any later time to resume the OMA operation as shown in figure 66 Device terminating a Multiword DMA data burst CS0 CS1 ty DMARQ XXXX See note 2 DMACK See note 1 DIOR DIOW Read DD 15 0 Write DD 15 0 NOTE 1 To terminate the transmission of a data burst the host shall negate DMACK within t after a DIOR or DIOW pulse No further DIOR or DIOW pulses shall be asserted for this burst 2 If the device is able to continue the transfer of data the device may leave DMARQ asserted and wait for the host to reassert DMACK or may negate DMARO at any time after detecting that DMACK has been negated Host terminating a Multiword DMA data burst 13 Multiword DMA timing parameters Mode 0 Mode 1 Mode2 Note ns ns ns to Cycle time min 480 150 120 See note tp DIOR DIOW asserted pulse width min 215 80 70 See note te DIOR data access max 150 60 50 tr DIOR data hold mi
14. t number of cylinders 2 0000h 2 Reserved 3 Aaaah 2 Default number of heads 4 0000h 2 Retired 5 0200h 2 Retired 6 Aaaah 2 Default number of sectors per track 7 8 Aaaah 4 Number of sectors per device 9 0000h 2 Retired 10 19 Aaaah 20 Serial Number in ASCII 20 Aaaah 2 Retired 21 0002h 2 Retired Number of ECC Bytes passed on Read Write Long 22 0004h 2 Commands 23 26 Aaaah 8 Firmware revision in ASCII 27 46 Aaaah 40 Model number in ASCII Maximum number of sector that shall be 47 0001h 2 transferred on Read Write Multiple commands 48 0000h 2 Reserved 49 0300h 2 Capabilities LBA DMA Supported 50 0000h 2 Reserved 51 0200h 2 PIO data transfer cycle timing mode 2 52 0000h 2 Retired 53 0007h 2 Word 54 58 64 70 and 88 are valid 54 Nnnnh 2 Current numbers of cylinders 55 Nnnnh 2 Current numbers of heads 56 Nnnnh 2 Current sectors per track 23 Word Address Default Value Total Bytes Data Field Type Information Current capacity in sectors LBAs Word 57 LSW 57 58 Nnnnh 4 Word 58 MSW 59 0101h 2 Multiple sector setting is valid 60 61 Aaaah 4 Total number of sectors addressable in LBA Mode 62 0000h 2 Retired 63 0n07h 2 Multiword DMA mode 2 and below are supported 64 0003h 2 Advance PIO transfer modes supported Minimum Multiword DMA transfer cycle time 65 0078h 2 120nsec Manufacturer s recommended Multiword DMA 66 0078h 2 transfer cycle time 120nsec Minim
15. ted The cycle completes after IORDY is reasserted For cycles where a wait is generated and DIOR is asserted the device shall place read data on DD 7 0 for tap before asserting IORDY 4 DMACK shall remain negated during a register transfer PIO timing parameters Mode 0 Model Mode2 Mode3 Mode4 Note ns ns ns ns ns to Cycle time min 600 383 240 180 120 1 4 ti Address valid to 70 50 30 30 25 DIOR DIOW setup min b DIOR DIOW min 165 125 100 80 70 1 ti DIOR DIOW recovery time 70 25 1 min t DIOW data setup min 60 45 30 30 20 ty DIOW data hold min 30 20 15 10 10 ts DIOR data setup min 50 35 20 20 20 ts DIOR data hold min 5 5 5 5 5 ts DIOR datatristate max 30 30 30 30 30 2 ty DIOR DIOW to address 20 15 10 10 10 10 valid hold min trp Read Data Valid to IORDY 0 0 0 0 0 active if IORDY initially low after t4 min ta IORDY Setup time 35 35 35 35 35 3 tg IORDY Pulse Width max 1250 1250 1250 1250 1250 tc IORDY assertion to release 5 5 5 5 5 max Notes 1 tg is minimum total cycle t is minimum DIOR DIOW assertion time and tz is the minimum DIOR DIOW negation time A host implementation shall lengthen tz to ensure that t is equal to or greater than the value reported in the devices IDENTIFY DEVICE data A device implementation shall support any length host implementation 2
16. that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Sustained Ultra DMA data in burst 17 DMARQ device DMACK host STOP host fe ty HDMARDY N FS host te tss DSTROBE device DD 15 0 DAO DA1 DA CSQ0 CS1 NOTES 1 See 9 13 4 1 Device terminating an Ultra DMA data in burst 2 The definitions for the STOP HOMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Device terminating an Ultra DMA data in burst OM 5 5 al E tu Art lui H RE o host Wan STOP host HOMARDY DSTROBE device tovs DD 15 0 XXX ED EL xu X DAO DA1 DA CS0 CS1 NOTES 1 See 9 13 4 2 Host pausing an Ultra DMA data in burst 2 The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Host terminating an Ultra DMA data in burst 18 DMARQ device tu DMACK host lack STOP p DDMARDY device HSTROBE host host 26262526 lack DAD DA1 DA2 CS0 CS1 NOTES 1 See 8 14 1 Initiating an Ultra DMA data out burst 2 The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Initialing an Ultra DMA data out data b
17. trobe signal used by the host to write to the device register or Data port STOP Stop UDMA Burst The host assert this signal during an UDMA burst to stop the DMA burst 42 IORDY I O channel ready o This signal is used to temporarily stop the host register access read or write when the device is not ready to respond to a data transfer request DDMARDY UDMA ready The device will assert this signal to indicate that the device is ready to receive UDMA data out burst DSTROBE UDMA data When UDMA mode DMA Read is active 4 18 26 34 40 50 strobe this signal is the data in strobe generated by the device 26 CSEL Cable select I This pin is used to configure this device as Device 0 or Device 1 30 DMACK DMA I This signal is used by the host in respond acknowledge to DMARQ to initiate DMA transfer 44 INTRQ Interrupt O When this device is selected this signal is the active high Interrupt Request to the host 43 IOIS16 o During PIO transfer mode0 lor 2 this pin indicates to the host the 16 bit data port has been addressed and the device is prepared to send or receive a 16 bit data word When transferring in DMA mode the host must use a 16 bit DMA channel and this signal will not be asserted 37 39 41 HA0 HA2 Device Address I This is 3 bit binary coded Address Bus 45 PDIAG Passed diagnostics I O This signal will b
18. um PIO transfer cycle time without flow 67 0078h 2 control 120nsec Minimum PIO transfer cycle time with IORDY flow 68 0078h 2 control 120nsec 69 81 0000h 26 Reserved 82 0002h 2 Supports Security Mode feature set 83 87 0000h 10 Reserved 88 On7Fh 2 Ultra DMA mode 6 and below are supported 89 127 0000h 78 Reserved 128 0021h 2 Enhanced security erase supported 129 159 0000h 62 Reserved vendor unique bytes 160 255 0000h 192 Reserved Note 1 a Vender Specific Configuration 2 n Host Selectable Configuration 24 5 0 Physical Dimension Top View 2 90 Q a 50 95 48 06 e g o g Side amp Bottom View 370 2 BOTTOM SIDE 1 1020 10 Note 1 Unit mm General Tolerance 0 1 6 0 Weight 1 4 TSOP Flash 6 8g 2 2 TSOP Flash 5 7g 3 1 TSOP Flash 4 1g 11 90 27 10 30 00 30 00 2 02 89 HOLES 50 95 48 06 21 50 50 95 25
19. urst HSTROBE at host DD 18 0 at host HSTROBE at device DD 15 0 KXXXXXX III XKXXXXXX at device NOTES 1 See 9 14 2 The data out transfer 2 DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Sustained Ultra DMA data out burst 19 DAO DA1 DA CS0 CS1 A F4 6e NOTES 1 See 9 14 4 1 Host terminating an Ultra DMA data out burst 2 The definitions for lhe STOP DOMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Host terminating an Ultra DMA data out burst DMARO device DMACK host oe STOP host ODMARDY device HSTROBE host v di te DD 15 0 host CRE ODS n LI DADO DA1 DA2 CS0 CS1 OK NOTES 1 See 9 14 4 2 Device pausing an Ultra DMA data out burst 2 The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and OMACK are negated Device terminating an Ultra DMA data out burst 20 3 4 Power Management System Power Consumption Ta 0 to 70 C Symbol Parameter Conditions MIN TYP MAX Unit Icer Read current 5V 75 mA Iccw Write current SV 75 mA Ipd Power down current SV 0 4 mA I
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