Home

Samsung M378B5673EH1-CF8 memory module

1. 5 50 0990 DQS4 DQSO 0954 DMO DM4 W I DM CS DM CS DM CS DM CS 595 DQO w 1 00 1 0 0 DQ32 w 1 00 1 0 0 DQ1 I 01 00 1 08 0033 I O 1 04 1 012 002 w 02 2 0034 102 2 w 4 1 03 0035 1 03 1 0 3 DQ4 w 4 I 04 4 0036 w 1 0 4 4 095 w 5 5 0037 w4 05 5 w 1 06 1 0 6 DQ38 1 06 1 0 6 DQ7 w 1 07 ZQ VO7 20 0039 07 20 VO 7 70 mas 5 E E DQS1 W DQS5 WS DQS1 DQS5 9 DM1 M DM5 DM CS DM CS Das DM CS DM CS w 1 00 1 0 0 DQ40 wv 1 00 1 0 0 DQ9 w 1 01 1 DQ41 w I O 1 1 010 02 D1 2 ps DQ42 1 0 2 D 1 0 2 D13 0011 w 1 03 043 4 1 03 1 0 3 012 I 04 4 DQ44 w 1 0 4 4 0013 05 VO5 DQ45 wr 1 05 5 0014 A 06 1 0 6 DQ46 A 1 0 6 1 0 6 DQ15 A I 07 VO7 20 0047 A 1 0 7 zar VO7 20 4 3 DQS2 DQS6 0052 DQS6 DM2 T DM6 DM CS DM CS DM CS DM CS DQ16 w 1
2. Part Number Density Organization Component Composition E of Height M378B2873EH1 CF8 H9 KO 1GB 128Mx64 128Mx8 K4B1G0846E HC 8 1 30mm M391B2873EH1 CF8 H9 KO 1GB 128Mx72 128Mx8 K4B1G0846E HC 9 1 30mm M378B5673EH1 CF8 H9 KO 2GB 256Mx64 128Mx8 K4B1G0846E HC 16 2 30mm M391B5673EH1 CF8 H9 KO 2GB 256Mx72 128Mx8 K4B1G0846E HC 18 2 30mm Note HP F8 H9 KO F8 1066Mbps 7 7 7 amp H9 1333Mbps 9 9 9 amp KO 1600Mbps 11 11 11 2 0 Key Features Speed DDR3 1066 DDR3 1333 DDR3 1600 7 7 7 9 9 9 11 11 11 1 875 1 5 1 25 ns CAS Latency 7 9 11 tCK tRCD min 13 125 13 5 13 75 ns tRP min 13 125 13 5 13 75 ns tRAS min 37 5 36 35 ns tRC min 50 625 49 5 48 75 ns JEDEC standard 1 5V 0 075V Power Supply Vppgo 1 5V 0 075V 533MHz for 1066Mb sec pin 667MHz fo for 1333Mb sec pin 8independent internal bank Programmable CAS Latency 6 7 8 9 10 Programmable Additive Latency Posted CAS 0 CL 2 or CL 1 clock Programmable CAS Write Latency CWL 6 DDR3 1066 and 7 DDR3 1333 8 bit pre fetch Burst Length 8 Interleave without any limit sequential with starting address 000 only 4 with tCCD 4 which does not allow seamless read or write either On the fly using A12 or MRS Bi directional Differential Data Strobe nternal self calibration Internal self calibration through ZQ RZQ 240 ohm 1
3. EUM tDVAC ps 350mV tDVAC ps 300mV min max min max 4 0 75 175 s 4 0 57 170 3 0 50 167 s 2 0 38 163 1 8 34 162 1 6 29 161 14 22 159 12 13 155 s 1 0 0 150 lt 1 0 0 150 18 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 12 3 3 Single ended Requirements for Differential Signals Each individual component of a differential signal 00 DQSL DQSU CK 005 DQSL or DQSU has also to comply with certain requirements for single ended signals CK and CK have to approximately reach Vsg max approximately equal to the ac levels Vj AC for ADD CMD signals in every half cycle DQS DQSL DQSU 29 DQSL have to reach Veg max approximately the ac levels Vi AC Vj AC for DQ signals in every half cycle proceeding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if Vj150 AC Vjj 150 AC is used for ADD CMD sig nals then these ac levels apply also for the single ended signals CK and CK Vpp VsEH min VsEH Vpp 2 or Vppo 2 CK or DOS VSEL Ves or V SS 550 stime Figure 4 Single ended requirement for differential signals Note that while ADD CMD DQ signal req
4. 5 4 0 x64 DIMM Pin Configurations Front side Back Side 6 5 0 x72 DIMM Pin Configurations Front side Back side 7 6 0 Pin DESCMDMNOM eR 8 7 0 SPD and Thermal Sensor for ECC UDIMMS 8 8 0 Input Output Functional Description 9 8 1 Address Mirroring Feature METER 10 8 1 1 DRAM Pi Wiring a a 10 9 0 Function Block Diagram sssssssssssnunnnnnnnnennnnnnnnnnnnnnnnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn 11 9 1 512MB 64Mx64 Module Populated 1 rank of x16 DDR3 SDRAMs 11 9 2 1GB 128Mx64 Module Populated as 1 rank of x8 DDR3 SDRAMS 12 9 3 1GB 128Mx72 ECC Module Populated as 1 rank of x8 DDR3 SDRAMS 13 9 4 2GB 256Mx64 Module Populated as 2 ranks of x8 DDR3 SDRAMS 14 9 5 2GB 256Mx72 ECC Module Populated as 2 ranks of x8 DDR3 SDRAMS 15 10 0 Absolute Maximum
5. Vpp and Vppg pins are tied common to a single power plane on these designs 7 0 SPD and Thermal Sensor for ECC UDIMMs On DIMM thermal sensor will provide DRAM temperature readout through a integrated thermal sensor SCL p SDA EVENT m WP EVENT R1 5 0 SA1 SA2 09 540 SA1 SA2 V Note 1 Raw Cards D 1Rx8 ECC and E 2Rx8 ECC support a thermal sensor 2 When the SPD and the thermal sensor are placed on the module R1 is placed but R2 is not When only the SPD is placed on the module R2 is placed but R1 is not Temperature Sensor Characteristics Temperature Sensor Accuracy Grade Range Units Notes Min Typ Max 75 lt lt 95 0 5 1 0 40 lt lt 125 1 0 2 0 20 lt lt 125 2 0 3 0 Resolution 0 25 LSB 8 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 8 0 Input Output Functional Description Symbol Type Function 1 and are differential clock inputs All the DDR3 SDRAM addr cntl inputs are sampled on the crossing of positive CK0 CK4 SSTL edge of CK and negative edge of CK Output read data is reference to the crossing of CK and CK Both directions of crossing Activates the SDRAM CK signal when high and deactivates the CK sign
6. ELECTRONICS 33 of 39 Rev 1 03 July 2009 Unbuffered DIMM DDR3 SDRAM Speed DDR3 1066 DDR3 1333 DDR3 1600 Units Note Parameter Symbol MIN MAX MIN MAX MIN MAX Power Down Timing Exit Power Down with DLL on to any valid com max max mand Exit Percharge Power Down with DLL 3nCK frozen to commands not requiring a locked DLL 7 5ns 3nCK 6ns 3nCK 6ns max max max 2 2770 10nCK 10nCK 10nCK 2 quiring 24ns 24ns 24ns max max max CKE minimum pulse width tCKE 3nCK 3nCK 5 625ns 5 625ns 3nCK 5ns Command pass disable delay tCPDED 1 1 1 nCK Power Down Entry to Exit Timing tPD tCKE min 9 tREFI CKE min 9 tREFI tCKE min 9 tREFI tCK 15 Timing of ACT command to Power Down entry tACTPDEN 1 1 1 nCK 20 Timing of PRE command to Power Down entry tPRPDEN 1 1 1 nCK 20 Timing of RD RDA command to Power Down entry tRDPDEN 4 1 4 1 4 1 Timing of WR command to Power Down entry tWRPDEN WL 4 tWR WL 4 tWR WL 4 tWR nCK 9 BL8OTF BL8MRS BL4OTF tCK avg CK avg tCK avg Timing of WRA command to Power Down entry _ _ _ BL8OTF BL8MRS BLAOTF tWRAPDEN WL 4 WR 1 WL 4 WR 1 WL 4 WR 1 nCK 10 Timing of WR command to Power Down entry WL 2 tWR WL 2 tWR WL 2 tWR BL
7. DM CS w 00 1 0 0 DQ32 w 1 00 1 0 0 Ba wW 1 00 1 09 te 1 D4 1 013 wr 02 02 wr 02 VO 2 w 1 03 02035 w 1 03 004 wy I 04 4 0036 w 1 0 4 4 DQ5 w 0 5 VO5 0037 w 1 05 VO5 DQ6 w I O 6 DQ38 1 06 1 0 6 DQ7 w I 07 VO 7 DQ39 wr 1 0 7 VO7 ZQ E 20 20 3 20 E DQS1 NN DQS5 DQS1 DQS5 DM1 VW DM5 NAE na DM CS DM CS DM CS Das DM CS w 00 1 0 0 040 1 00 1 0 0 pato w og P1 ioe 90 2 2 95 jo 014 0011 w 1 03 1 0 3 DQ43 wr 1 03 1 0 3 DQ12 04 4 DQ44 wr 1 0 4 4 DQ13 w 1 05 5 0045 1 05 5 0014 1 06 46 1 06 1 0 6 DQ15 I 07 za lO 7 zo DQ47 l O 7 za VOT 20 DQS2 1 0956 1 DQS2 DQS6 VW DM2 DM6 NAE Dai w CS DM CS DQS CS Das DM CS Das w 00 00 00 00 DQ17 w 1 01 D2 1 011 DQ49 w 1 D6 VO 1 D15 DQ18 w 1 02 2 0950 1 0 2 2 019 1 03 1 0 3 0951 w4 1 03 1 0 3 DQ20 wr 1 0 4 I O 4 52 1 0 4 4 DQ21 w 1 05 5 0053 1 0 5 5 DQ22 w 1 06 1 0 6 DQ54 8 6 6 0023 w 1 07 20 VO7 za 0955 M za VO7 22 053 DQS7 053 DQS7 DM3 DM7 CS DQS D
8. Die Termination using ODT Average Refresh Period 7 8us at lower then 85 C 3 9us at 85 lt Tease lt 95 Asynchronous Reset 3 0 Address Configuration Organization Row Address Column Address Bank Address Auto Precharge 128x8 1Gb based Module A0 A13 0 9 BAO BA2 A10 AP ROOM Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 4 0 x64 DIMM Pin Configurations Front side Back Side Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREFDQ 121 Vss 42 NC 162 NC 82 DQ33 202 Vss 2 Vss 122 DQ4 43 NC 163 Vss 83 Vss 203 DM4 3 123 DQ5 44 Vss 164 NC 84 DQS4 204 NC 4 001 124 Vss 45 NC 165 NC 85 DQS4 205 Vas 5 Vss 125 DMO 46 NC 166 Vss 86 Vss 206 DQ38 6 5950 126 NC 47 Vss 167 NC TEST 87 DQ34 207 DQ39 7 DQSO 127 Vss 48 NC 168 Reset 88 DQ35 208 Vss 8 Vss 128 DQ6 KEY 89 Vss 209 DQ44 9 DQ2 129 DQ7 49 NC 169 CKE1 NC 90 0040 210 2045 10 130 Vss 50 CKEO 170 91 0041 211 Vas 11 Vss 131 DQ12 51 Vpp 171 NC 92 Vss 212 DM5 12 DQ8 132 DQ13 52 BA2 172 NC 93 DQS5 213 NC 13 Dag 133 Vss 53 NC 173 94 DQS5 214 Vas 14 Vss 134 DM1 54 Vpp 174 A12 BC 95 Vss 215 0046 15 0951 135 NC 55 A11 175 A9 96 DQ42 216 DQ47 16 DQS1 136 Vss 56 176 97 0043 217 Vss 17 Vss 137 DQ14 57 177 A8 98 Vss 218 DQ52 18 DQ10 138 DQ1
9. Unit Notes IDDO 540 585 TBD 1551 675 720 TBD mA IDD2PO slow exit 90 90 TBD mA IDD2P 1 fast exit 225 225 TBD mA IDD2N 270 315 TBD mA IDD2Q 270 315 TBD mA IDD3P fast exit 225 225 TBD mA IDD3N 405 450 TBD mA 15548 945 1125 TBD mA IDDAW 1035 1215 TBD mA IDD5B 1350 1440 TBD mA 1006 90 90 TBD mA IDD7 1575 2070 TBD mA M391B5673EH1 2GB 256Mx72 Module F H K Symbol Unit Notes IDDO 810 900 TBD mA IDD1 945 1035 TBD mA IDD2PO slow exit 180 180 TBD mA IDD2P 1 fast exit 450 450 TBD mA IDD2N 540 630 TBD mA IDD2Q 540 630 TBD mA IDD3P fast exit 450 450 TBD mA IDD3N 675 765 TBD mA IDD4R 1215 1440 TBD mA IDDAW 1305 1530 TBD mA IDD5B 1620 1755 TBD mA 1006 180 180 TBD mA 1557 1845 2385 TBD mA 26 of 39 ELECTRONICS Rev 1 03 July 2009 Unbuffered DIMM 15 0 Input Output Capacitance 15 1 Non ECC UDIMM DDR3 SDRAM M378B2873EH1 MET 0053 1066 0063 1333 0053 1600 ere TOME Min Max Min Max Min Max Input output capacitance 0 TDQS TDQS cig a pF Input capacitance CK and CK CCK TBD TBD TBD pF Input capacitance All other input only pins CI TBD TBD TBD pF Input output capacitance of ZQ pin CZQ TBD TBD TBD pF M378B5673EH1 Parameter Symbol ESO Units Notes Min Max Min Max Input output
10. 7 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM 6 0 Pin Description DDR3 SDRAM Pin Name Description Pin Name Description 0 13 SDRAM address bus SCL 2 serial bus clock for EEPROM BAO BA2 SDRAM bank select SDA 2 serial bus data line for EEPROM RAS SDRAM row address strobe SA0 SA2 IC serial address select for EEPROM CAS SDRAM column address strobe Vpp SDRAM core power supply WE SDRAM write enable SDRAM Driver power supply S0 S1 DIMM Rank Select Lines VREFDQ SDRAM I O reference supply CKEO CKE1 SDRAM clock enable lines VREFCA SDRAM command address reference supply ODT1 termination control lines Vss Power supply return ground DQO DQ63 DIMM memory data bus VppsPD Serial EEPROM positive power supply CB7 DIMM ECC check bits NC Spare Pins no connect SDRAM data strobes Used by memory bus analysis tools 0050 DQS8 TEST E positive line of differential pair unused on memory DIMMs DaSo Dasg gt differential data strobes RESET Set DRAMs Known State negative line of differential pair SDRAM dat ks high data strob DM0 DM8 Reserved for optional temperature sensing hardware SDRAM clocks CK1 V SDRAM I O terminati positive line of differential pair CK1 SDRAM clocks VE RFU Reserved for future use negative line of differential pair
11. gt 0 2 SDRAMs 00 D7 gt A0 A13 SDRAMs 00 D7 RAS SDRAMs 00 D7 gt CAS SDRAMs 00 D7 CKE SDRAMs 00 D7 SDRAMs 00 D7 SDRAMs 00 D7 SDRAMs 00 D7 DQS4 DQS4 DM DQS5 DQS5 DMS WwW DQS6 DQS6 DM DQS7 DQS7 DM7 DQ32 WH 0033 Ww 0935 Ww DQ36 Ww Ww DQ38 0939 LA DM 00 1 2 4 5 1 0 6 VO7 CS D4 A DQ40 w DQ41 DQ42 v DQ43 w DQ44 0045 A DQ46 DQ47 wr DM CS 59 1 0 0 lO 1 2 1 03 4 1 05 1 0 6 1 07 05 0048 A 0049 A 00950 w4 0951 0052 WW 0053 00954 00955 DM CS 09 100 1 I O 2 1 0 4 1 05 1 0 6 1 07 D6 Serial PD SCL WP i gt SDA A2 SAO SA1 SA2 SPD DO D7 VREFDQ 20 07 Vss 4 VREFCA x DO D7 DM CS DQ56 1 0 0 DQ57w 1 0 1 D7 0958 wr 1 0 2 DQ59 wr 1 0 3 1 0 4 00961 0 5 DQ62 1 0 6 20 0963 07 E Note 1 DQ to I O wiring is shown as recommen
12. lated as 0 5 T 20 33 128ms 1 5 x 1 0 15 x 15 24 from 13 cycles to 50 cycles This row defines 38 parameters 25 tCH abs is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge 26 tCL abs is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge 27 The tlS base AC150 specifications are adjusted from the tlS base specification by adding an additional 100 ps of derating to accommodate for the lower alter nate threshold of 150 mV and another 25 ps to account for the earlier reference point 175 mv 150 mV 1 V ns 28 Pulse width of a input signal is defined as the width between the first crossing of and the consecutive crossing of Vgge DC 29 tDQSL describes the instantaneous differential input low pulse width on DQS DQS as measured from one falling edge to the next consecutive rising edge 30 describes the instantaneous differential input high pulse width on DQS DQS as measured from one rising edge to the next consecutive falling edge 31 tDQSH act tDQSL act 1 tCK act with tXYZ act being the actual measured value of the respective timing parameter in the application 32 tDSH act tDSS act 1 tCK act with tXYZ act being the actual measured value of the respective timing parameter in the application 36 of 39 Rev 1 03 July 2009 ELECTRONICS
13. 16 3 Speed Bins and CL tRCD tRC and tRAS for corresponding Bin 30 16 3 1 Speed Bin Table Mates 31 17 0 Timing Parameters by Speed Grade 32 17 1 Jitter Notos E Um 35 17 2 Timing Parameter Notes 36 17 3 Address Command Setup Hold Derating 37 17 4 Data Setup Hold and Slew Rate Derating 140 43 18 0 Physical Dimensions Aet ansann aaaea 48 18 1 64Mbx16 based 64Mx64 Module 1 Rank 4 0 48 18 2 128Mbx8 based 128Mx64 x72 Module 1 Rank 49 18 3 128Mbx8 based 256Mx64 x72 Module 2 Ranks 50 nore Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM Revision History Revision Month Year History 1 0 December 2008 First release 1 01 January 2009 Corrected Module Physical Dimensions 1 02 February 2009 Added Tolerances to Physical Dimensions 1 03 July 2009 Corrected Typo ELECTRONICS 4 of 39 Rev 1 03 July 2009 Unbuffered DIMM DDR3 SDRAM 1 0 DDR3 Registered DIMM Ordering Information
14. AN N i 3 80 0 2 0 15 1 50 0 10 B 1 00 lt g gt lt 2 50 Detail Detail B The used device is 128M x8 DDR3 SDRAM FBGA DDR3 SDRAM Part KAB1G0846E HC Note Tolerances on all dimensions 0 15 unless otherwise specified 390139 Rev 1 03 July 2009 ELECTRONICS
15. Average high pulse width tCH avg 0 47 0 53 0 47 0 53 0 47 0 53 tCK avg Average low pulse width tCL avg 0 47 0 53 0 47 0 53 0 47 0 53 tCK avg Clock Period Jitter tJIT per 90 90 80 80 70 70 ps Clock Period Jitter during DLL locking period tJIT per Ick 80 80 70 70 60 60 ps Cycle to Cycle Period Jitter 180 160 140 ps Cycle to Cycle Period Jitter during DLL locking period tJIT cc Ick 160 140 120 ps Cumulative error across 2 cycles tERR 2per 132 132 118 118 103 103 ps Cumulative error across 3 cycles tERR 3per 157 157 140 140 122 122 ps Cumulative error across 4 cycles tERR 4per 175 175 155 155 136 136 ps Cumulative error across 5 cycles tERR 5per 188 188 168 168 147 147 ps Cumulative error across 6 cycles tERR 6per 200 200 177 177 155 155 ps Cumulative error across 7 cycles tERR 7per 209 209 186 186 163 163 ps Cumulative error across 8 cycles tERR 8per 217 217 193 193 169 169 ps Cumulative error across 9 cycles tERR 9per 224 224 200 200 175 175 ps Cumulative error across 10 cycles tERR 10per 231 231 205 205 180 180 ps Cumulative error across 11 cycles tERR 11per 237 237 210 210 184 184 ps Cumulative error across 12 cycles tERR 12per 242 242 215 215 188 188 ps Cumulative error across n 7 13 14 49 50 cycles tERR nper M ps 24 Absolute clock HIGH pulse width tCH abs 0 43 0 43 0 43 tCK avg 25 Absolute clock Low pulse width tCL abs 0 43
16. 16 10 1 Absolute Maximum RatingS 16 10 2 DRAM Component Operating Temperature Range 16 11 0 amp DC Operating Conditions EK RA SATA Mun an 16 11 1 Recommended DC Operating Conditions SSTL 15 0 0 16 12 0 AC amp DC Input Measurement Levels 17 12 1 AC amp DC Logic Input Levels for Single ended Signals 17 grau ap ccn Me 18 12 3 AC amp DC Logic Input Levels for Differential Signals nnn nnn 19 12 3 1 Differential Signals Definition E exu n UP as A NM RR CENE S MM 19 12 3 2 Differential Swing Requirement for Clock CK CK and Strobe DQS DQS 19 12 3 3 Single ended Requirements for Differential Signals 20 12 3 4 Differential Input Cross Point Voltage 21 12 4 Slew Rate Definition for Single ended Input Signals 21 12 5 Slew Rate Definition for Differential Input Signals 21 13 0 amp
17. FBGA DDR3 SDRAM Part 4 1 0846 Note Tolerances on all dimensions 0 15 unless otherwise specified 380133 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 18 3 128Mbx8 based 256Mx64 x72 Module 2 Ranks Units Millimeters 133 35 0 15 gt 5 S 128 95 gt 5 x 5 v N A 64 SPD m pr EE ME r o o for x72 e B 2 9 2 50 N 54 675 47 00 71 00 4 0 gt O O J pus ES C 1 270 0 10 gt lt S e gt
18. Intermal read command to first data tAA 13 125 59 20 ns 13 75 ACT to internal read or write delay time tRCD 13 125 59 ns PRE command period tRP dia apne ns 48 75 to or REF command period tRC 48 125 59 ns ACT to PRE command period tRAS 35 9 tREFI ns 5 tCK AVG 2 5 3 3 ns 1 2 3 8 CL 6 CWL 6 tCK AVG Reserved ns 1 2 3 4 8 7 8 tCK AVG Reserved ns 4 CWL 5 tCK AVG Reserved ns 4 1 875 lt 2 5 CWL 6 tCK AVG ns 1 2 3 4 8 CL 7 Optional Note 5 9 7 tCK AVG Reserved ns 1 2 3 4 8 8 tCK AVG Reserved ns 4 5 tCK AVG Reserved ns 4 T CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 8 7 tCK AVG Reserved ns 1 2 3 4 8 8 tCK AVG Reserved ns 1 2 3 4 CWL 5 6 tCK AVG Reserved ns 4 1 5 1 875 CL 9 7 tCK AVG ns 1 2 3 4 8 Optional Note 9 10 8 tCK AVG TBD ns 1 2 3 4 CWL 5 6 tCK AVG Reserved ns 4 1 5 1 875 CL 10 CWL 7 tCK AVG ns 1 2 3 8 Optional Note 9 10 8 tCK AVG Reserved ns 1 2 3 4 pesa CWL 5 6 7 tCK AVG Reserved ns 4 CWL 8 tCK AVG 1 25 1 5 ns 1 2 3 5 Supported CL Settings 6 7 8 9 10 11 nCK Supported CWL Settings 5 6 7 8 nCK 30 of 39 Rev 1 03 July 2009 Unbuffered DIMM DDR3 SDRAM 16 3 1 Speed Bin Table Notes Absolute Specification Toper Vpp 1 5V 0 075 Note 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When making a selection of tCK AVG
19. It shows a valid reference voltage Vrer t as a function of time V amp ge stands for and Vggepg likewise Vrer DC is the linear average of Vgep t over a very long period of time e g 1 sec This average has to meet the min max requirements Fur thermore Vgge t may temporarily deviate from Vage DC by no more than 1 Vpp voltage VRef DC max VDD 2 VRet DC ymin Figure 2 Illustration of tolerance and ac noise limits The voltage levels for setup and hold time measurements Vi DC Vi AC and DC are dependent on Vrer shall be understood as Vper DC as defined in Figure 2 This clarifies that dc variations of affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for Vgge DC deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with ac noise Timing and voltage effects due to ac noise Vggr up to the specified limit 1 of Vpp are included in DRAM timings and their associated deratings 17 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 12 3 AC amp DC Logic Input Levels for Diff
20. both need to be ful filled Requirements from CL setting as well as requirements from CWL setting 2 tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchronized by the DLL all possible intermediate frequen cies may not be guaranteed An application should use the next smaller JEDEC standard tCK AVG value 2 5 1 875 1 5 or 1 25 ns when calculat ing CL ns tCK AVG ns rounding up to the next SupportedCL 3 tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED 4 Reserved settings are not allowed User must program a different value 5 Optional settings allow certain devices in the industry to support this setting however it is not a mandatory feature Refer to supplier s data sheet and or the DIMM SPD information if and how this setting is supported 6 Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 7 Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 8 Any DDR3 1600 speed bin also supports functional operation at lower freq
21. where 2 lt lt 12 Specific Note When the device is operated with input clock jitter this parameter needs to be derated by the actual tJIT per act of the input clock out put deratings are relative to the SDRAM input clock For example if the measured jitter into a DDR3 800 SDRAM has tCK avg act 2500 ps tJIT per act min 72 ps and tJIT per act max 93 ps then tRPRE min derated tRPRE min tJIT per act min 0 9 x tCK avg act tUlT per act min 0 9 x 2500 ps 72 ps 2178 ps Similarly tQH min derated tQH min tJIT per act min 0 38 x tCK avg act tUlT per act min 0 38 x 2500 ps 72 ps 878 ps Caution the min max usage 35 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 17 2 Timing Parameter Notes 1 Actual value dependant upon measurement level definitions which are TBD 2 Commands requiring a locked DLL are READ and RAP and synchronous ODT commands 3 The max values are system dependent 4 WR as programmed in mode register 5 Value must be rounded up to next higher integer value 6 There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI T For definition of RTT turn on time tAON see Device Operation 8 For definition of RTT turn off time tAOF see Device Operation 9 tWR is defined in ns for calculation of tWRPDEN it is necessary to round up tWR to the next integer 10 WR in clock cycles as
22. DC output high measurement level for IV curve linearity 0 8 x VDDQ Vom DC DC output mid measurement level for IV curve linearity 0 5 x VDDQ DC DC output low measurement level for IV curve linearity 0 2 x VDDQ V AC output high measurement level for output SR 0 1 x Vppo V 1 output low measurement level for output SR 0 1 x Vppa V 1 Note 1 The swing of 0 1 is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 400 and an effective test load of 250 to 2 13 2 Differential AC amp DC Output Levels Differential AC and DC output levels Symbol Parameter DDR3 1066 1333 Units Notes AC differential output high measurement level for output SR 0 2 X V 1 Voi gig DC AC differential output low measurement level for output SR 0 2 x VDDQ V 1 Note 1 The swing of 0 2xVppq is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 400 and an effective test load of 250 to 2 at each of the differential outputs 13 3 Single ended Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo AC and for single ended signals as shown in below Single Ended Output slew ra
23. Symbol Parameter Units Notes Min Typ Max Vpp Supply Voltage 1 425 1 5 1 575 V 1 2 Supply Voltage for Output 1 425 1 5 1 575 V 1 2 Note 1 Under all conditions must be less than or equal to 2 tracks with Vpp AC parameters are measured with Vpp and tied together 15 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 12 0 AC amp DC Input Measurement Levels 12 1 AC amp DC Logic Input Levels for Single ended Signals Single Ended AC and DC input levels for Command and Address DDR3 1066 DDR3 1333 Symbol Parameter Unit Notes Min Max Min Max Vin ca DC input logic high Vrer 100 Vpp Vngr 100 Vpp mV 1 Vit ca DC input logic low Vss 100 Vss Vngr 100 mV 1 input logic high Vnegr 175 Vngr 175 mV 1 2 Vit cA AC AC input logic low Vngr 175 Vngr 175 mV 1 2 150 input logic high Vngr 150 mV 1 2 Vit ca AC150 input logic low 150 12 Reference Voltage for ADD V DC i 0 49 V 0 51 V 0 49 V 0 51 V V 3 4 CMD inputs DD DD DD DD i Note 1 For input only pins except RESET Vrerca DC 2 See Overshoot and Undershoot specifications section 3 The AC peak noise on Veer may not allow to d
24. 0 15 unless otherwise specified 3 0133 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 18 2 128Mbx8 based 128Mx64 x72 Module 1 Rank Units Millimeters 133 35 0 15 gt 5 S 128 95 gt 5 x 5 v N A 64 SPD m pr EE ME r o o for x72 hy 8 2 9 2 50 N 54 675 47 00 E 71 00 Max 4 0 S mca 1 270 0 10 _ S 5 00 0 80 0 05 2x 2 10 0 15 2 gt AN N i 3 80 0 2 0 15 1 50 0 10 B 1 00 lt g gt lt 2 50 Detail Detail B The used device is 128M x8 DDR3 SDRAM
25. 0 43 0 43 tCK avg 26 Data Timing DQS DQS to DQ skew per group per access tDQSQ 150 125 100 ps 13 DQ output hold time from DQS DQS tQH 0 38 0 38 0 38 tCK avg 13 4 DQ low impedance time from CK tLZ DQ 600 300 500 250 450 225 ps 13 14 f DQ high impedance time from CK CK tHZ DQ 300 250 225 ps 13 14 f 11 tDS base 25 30 10 ps 4 17 Das to tDH base 100 65 45 ps 417 DQ and DM Input pulse width for each input tDIPW 490 400 360 ps 28 Data Strobe Timing DQS DQS READ Preamble tRPRE 0 9 Note 19 0 9 Note 19 0 9 Note 19 tCK 13 19 g DQS DQS differential READ Postamble tRPST 0 3 Note 11 0 3 Note 11 0 3 Note 11 tCK 11 13 b DQs DAS output high time tQSH 0 38 0 4 0 4 tCK avg 13 4 Das 605 output low time tQSL 0 38 0 4 0 4 tCK avg 13 4 DQS DQS WRITE Preamble tWPRE 0 9 0 9 0 9 tCK DQS DQS WRITE Postamble tWPST 0 3 0 3 0 3 tCK oo rising edge output access time from rising tDOSCK 300 300 255 255 225 225 ps 134 29 DQS low impedance time Referenced from RL 1 tLZ DQS 600 300 500 250 450 225 ps 13 144 n high impedance time Referenced from 1HZ DQS _ 300 250 225 12 13 14 DQS DQS differential input low pulse width tDQSL 0 45 0 55 0 45 0 55 0 45 0 55 tCK 29 31 DQS DQS differential input high pulse width tDQSH 0 45 0 55 0 45 0 55 0 45 0 55 tCK 30 31 DQS DQS rising edge to CK CK rising edge tDQSS 0 25 0 25 0 25 0 25 0 27 0 2
26. 00 1 0 0 048 1 0 0 1 0 0 DQ17 v 01 D2 VO 1 D10 DQ49 w 1 D6 VO 1 D14 DQ18 1 0 2 1 0 2 050 1 02 2 0019 1 03 DQ51 w 1 03 1 0 3 020 1 0 4 4 0052 wr 1 0 4 4 0021 10 5 5 DQ53 A 1 05 5 0022 w 4 1 0 6 1 0 6 DQ54 1 0 6 1 0 6 DQ23 w I 07 20 VO7 20 0055 1 0 7 20 VO7 20 3 3 3 DQS3 0957 DQs3 DQS7 DM3 DM7 DM CS CS DM CS DM CS DQS DQ24 1 00 1 0 0 DQ56 w 1 0 0 1 0 0 DQ25 1 0 1 D3 1 D11 057 1 0 1 D7 1 D15 0026 w 1 02 2 058 1 0 2 1 0 2 027 DQ59 wr4 1 03 1 0 3 DQ28 A I O 4 4 DQ60 A 1 0 4 4 0029 05 5 0061 A 1 05 5 0030 wr 1 06 1 0 6 DQ62 1 0 6 1 0 6 DQ31 r 7 20 VO7 20 0063 1 07 20 VO7 ZQ 3 E BAO 2 BAO BA2 SDRAMs 00 015 Serial PD Note A0 A15 gt A0 A15 SDRAMs 00 015 SCL CKE1 CKE SDRAMs D8 D15 WP lt gt SDA 1 2 wiring is shown as recommended but be SDRAMs DO D7 2 DQ DQS DQS ODT DM CKE 5 relationships must be A DN maintained as shown RAS RAS SDRAMs 00 D15 SA0 SA1 SA2 3 DQ DM DQS DQS resistors Refer to associated CAS gt CAS SDRAMs DO D15 topology diagram as
27. 1 DM6 21 DQ16 141 DQ21 61 A2 181 Al 102 0056 222 22 0017 142 Vss 62 Vpp 182 Vpp 103 DQS6 223 Vss 23 Vss 143 DM2 63 CK1 NC2 183 Vpp 104 Vss 224 DQ54 24 DQS2 144 NC 64 CK1 NC 184 105 0050 225 00955 25 DQS2 145 Vss 65 Vpp 185 106 0051 226 Vss 26 Vss 146 DQ22 66 Vpp 186 Vpp 107 Vss 227 27 0018 147 0023 67 187 108 00956 228 0061 28 0019 148 Vss 68 NC 188 AO 109 DQ57 229 Vss 29 Vss 149 DQ28 69 Vpp 189 Vpp 110 Vss 230 DM7 30 DQ24 150 DQ29 70 A10 AP 190 BA1 111 DQs7 231 NC 31 DQ25 151 Vss 71 BAO 191 Vpp 112 DQS7 232 Vss 32 Vss 152 DM3 72 Vpp 192 RAS 113 Vss 233 0062 33 5053 153 NC 73 WE 193 50 114 234 0963 34 DQS3 154 Vss 74 CAS 194 Vpp 115 DQ59 235 Vss 35 Vss 155 DQ30 75 195 116 Vss 236 VppsPD 36 DQ26 156 DQ31 76 S1 NC 196 A13 117 SAO 237 SA1 37 DQ27 157 Vss 77 ODT1 NC 197 Vpp 118 SCL 238 SDA 38 Vss 158 4 78 Vpp 198 NC 119 SA2 239 Vss 39 CBO 159 CB5 79 NC 199 Vss 120 Vr 240 40 CB1 160 Vss 80 Vss 200 DQ36 41 Vss 161 DM8 81 DQ32 201 DQ37 NC No Connect NF No Function NU Not Usable RFU Reserved Future Use 1 1 ODT1 1 Used for dual rank UDIMMs NC on single rank UDIMMs 2 CK1 NC CK1 NC Used for dual rank UDIMMs not used single rank UDIMMs but terminated 3 TEST pin 167 used by memory bus analysis tools unused on memory DIMMs SAMSUNG ELECTRONICS Ltd reserves the right to change products and specifications without notice
28. 167 used by memory bus analysis tools unused on memory DIMMs SAMSUNG ELECTRONICS Ltd reserves the right to change products and specifications without notice 6 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 5 0 x72 DIMM Pin Configurations Front side Back side Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREFDO 121 Vss 42 NC 162 NC 82 DQ33 202 Vss 2 Vss 122 DQ4 43 NC 163 Vss 83 Vss 203 DM4 3 000 123 005 44 Vss 164 CB6 84 50954 204 4 091 124 Vss 45 CB2 165 CB7 85 205 Vss 5 Vss 125 DMO 46 CB3 166 Vss 86 Vss 206 DQ38 6 5950 126 47 Vss 167 NC TEST 87 DQ34 207 DQ39 7 DQSO 127 Vss 48 NC 168 Reset 88 DQ35 208 Vss 8 Vss 128 DQ6 KEY 89 Vss 209 DQ44 9 DQ2 129 007 49 169 1 90 0040 210 0045 10 130 Vss 50 CKEO 170 VDD 91 DQ41 211 Vss 11 Vss 131 DQ12 51 171 NC 92 Vss 212 DM5 12 DQ8 132 DQ13 52 BA2 172 NC 93 DQS5 213 NC 13 DQ9 133 Vas 53 NC 173 94 DQS5 214 Vss 14 Vss 134 DM1 54 Vpp 174 A12 BC 95 Vss 215 DQ46 15 DQS1 135 NC 55 A11 175 A9 96 DQ42 216 DQ47 16 DQS1 136 Vss 56 AT 176 Vpp 97 DQ43 217 Vss 17 Vss 137 DQ14 57 Vpp 177 A8 98 Vss 218 DQ52 18 DQ10 138 DQ15 58 5 178 6 99 0048 219 0053 19 0011 139 Vss 59 A4 179 Vpp 100 DQ49 220 Vss 20 Vss 140 DQ20 60 Vpp 180 A3 101 Vss 22
29. 4MRS WREDEN tCK avg CK avg tCK avg 9 eae command to Power Down entry tWRAPDEN WL 2 WR 1 WL 2 WR 1 WL 2 WR 1 nCK 10 Timing of REF command to Power Down entry tREFPDEN 1 1 1 20 21 Timing of MRS command to Power Down entry tMRSPDEN tMOD min tMOD min tMOD min ODT Timing ODT high time without write command or with wirte ODTH4 4 4 E 4 _ 4 ODT high time with Write command 8 ODTH8 6 6 6 nCK Asynchronous RTT tum on delay Power Down with tAONPD 2 85 2 85 2 85 ns DLL frozen Asynchronous RTT tum off delay Power Down with tAOFPD 2 85 2 85 2 85 fis DLL frozen ODT turn on tAON 300 300 250 250 225 225 ps 7 RTT NOM and RTT WR turn off time from ODTLoff tAOF 0 3 0 7 0 3 0 7 0 3 0 7 tCK avg 8f reference RTT dynamic change skew tADC 0 3 0 7 0 3 0 7 0 3 0 7 tCK avg f Write Leveling Timing First Das pulse rising edge after tDQSS margining tWLMRD 40 40 40 _ 3 mode is programmed DQS DQS delay after tDQS margining mode is pro tWLDQSEN 25 25 25 3 grammed Setup time for tDQSS latch tWLS 245 195 165 ps Write leveling hold time from rising 00 DQS cross tWLH 245 195 165 ing to rising CK CK crossing Write leveling output delay tWLO 0 9 0 9 0 7 5 ns Write leveling output error tWLOE 0 2 0 2 0 2 ns 34 of 39 ELECTRONICS Rev 1 03 July 2009 Unbuffered DIMM DDR3 SDRAM 17 1 Jitter Notes Specific Note a Uni
30. 5 58 5 178 99 0048 219 0053 19 0011 139 Vss 59 A4 179 100 0049 220 Vss 20 Vss 140 DQ20 60 Vpp 180 A3 101 Vss 221 DM6 21 DQ16 141 0021 61 2 181 A1 102 DQS6 222 NC 22 DQ17 142 Vss 62 Vpp 182 103 223 Vss 23 Vss 143 DM2 63 CK1 NC 183 104 Vss 224 DQ54 24 DQS2 144 NC 64 CK1 NC2 184 CKO 105 DQ50 225 DQ55 25 DQS2 145 Vss 65 Vpp 185 106 0051 226 Vss 26 Vss 146 DQ22 66 186 Vpp 107 Vss 227 27 0018 147 00923 67 VggeCA 187 NC 108 DQ56 228 0961 28 0019 148 Vss 68 NC 188 A0 109 DQ57 229 Vss 29 Vss 149 DQ28 69 Vpp 189 Vpp 110 Vss 230 DM7 30 DQ24 150 DQ29 70 A10 AP 190 BA1 111 DQS7 231 NC 31 DQ25 151 Vss 71 BAO 191 112 0087 232 Vss 32 Vss 152 DM3 72 192 113 Vss 233 DQ62 33 DQS3 153 NC 73 193 50 114 234 2063 34 DQS3 154 Vss 74 CAS 194 Vpp 115 DQ59 235 Vss 35 Vss 155 DQ30 75 Vpp 195 ODTO 116 Vss 236 VppsPp 36 DQ26 156 DQ31 76 51 196 A13 117 SAO 237 SA1 37 DQ27 157 Vss 77 ODT1 NC 197 Vpp 118 SCL 238 SDA 38 Vss 158 NC 78 198 119 SA2 239 Vss 39 NC 159 NC 79 NC 199 Vss 120 Vir 240 Vir 40 NC 160 Vss 80 Vss 200 DQ36 41 Vss 161 NC 81 DQ32 201 DQ37 No Connect NF No Function NU Not Usable RFU Reserved Future Use 1 1 ODT1 1 Used for dual rank UDIMMs NC on single rank UDIMMs 2 CK1 NC and CK1 NC Used for dual rank UDIMMs not used on single rank UDIMMs but terminated 3 TEST pin
31. 6 0027 Ww 0028 0029 Ww 0030 0031 wr DM 1 00 1 1 02 4 5 1 0 6 1 07 20 DQS 2 wr CB5 CB6 DM 1 00 1 1 02 1 0 4 5 1 0 6 1 07 es D8 Das DQS 0954 4 DQS5 DQS5 DMS DQS6 DQS6 DM DQS7 DQS7 DM wN DM CS 1 00 33 01 0034 1 02 DQ35 w 1 03 DQ36 1 0 4 DQ37 1 05 DQ38 1 06 za 0039 1 1 07 CS 00 DQS 040 1 00 DQ41 w 1 0 1 D5 DQ42 wr 1 0 2 DQ43 A 1 03 DQ44 w 4 DQ45 w 1 0 5 0046 1 06 20 DQ47 1 07 E MW DM CS DQS 048 1 0 0 049 1 0 1 D6 DQ50 w 1 0 2 DQ51 1 03 0952 Ww I O 4 0953 w 1 05 20 54 1 0 6 55 1 07 E DM CS DQS DQ56 w 00 DQ57 1 01 D7 DQ58 wy 1 02 DQ59 1 03 0060 w 1 04 DQ61 1 05 62 106 20 0963 07 Serial PD SCL EVENT EVENT lt gt SDA AO A1 A2 SA0 5 1
32. 7 tCK avg DQS DQS faling edge setup time to CK CK rising edge tDSS 0 2 0 2 0 18 tCK avg 32 DQS DQS faling edge hold time to CK CK rising edge tDSH 0 2 0 2 0 18 tCK avg 32 32 of 39 Rev 1 03 July 2009 Unbuffered DIMM DDR3 SDRAM Speed DDR3 1066 DDR3 1333 DDR3 1600 Units Note Parameter Symbol MIN MAX MIN MAX MIN MAX Command and Address Timing DLL locking time tDLLK 512 512 512 internal READ Command to PRECHARGE Command tRTP max max delay 4nCK 7 5ns 4nCK 7 5ns 4nCK 7 5ns Delay from start of internal write transaction to internal WTR max _ e 18 read command 4 7 5 4nCK 7 5ns 4nCK 7 5ns WRITE recovery time tWR 15 15 15 ns e Mode Register Set command cycle time tMRD 4 4 4 nCK Mode Register Set command update delay MOD 12nCK 1 Bns 1 5ns 12nCK 1 5 CAS to CAS command delay CCD 4 4 4 Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK AVG Multi Purpose Register Recovery Time tMPRR 1 1 1 nCK 22 ACTIVE to PRECHARGE command period RAS See 13 3 Speed Bins and CL tRCD tRP tRC and tRAS for corresponding Bin on page 37 ns e ACTIVE to ACTIVE command period for 1KB pagesize tRRD AnCK 7 5ns 4nCK 6ns 4nCK z e ACTIVE to ACTIVE c
33. C see Table 30 BL 82 AL 0 CS High between REF Command Address Bank Address Inputs partially toggling according to Table 38 Data IO MID LEVEL DM stable at 0 Bank Activity REF command every nRFC see Table 38 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 38 Self Refresh Current Normal Temperature Range IDD6 0 85 Auto Self Refresh Disabled Self Refresh Temperature Range SRT Normal Low External clock Off CK and CK LOW CL see Table 30 BL 8 AL 0 5 Command Address Bank Address Data IO MID LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL 23 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM Symbol Description Self Refresh Current Extended Temperature Range optional IDDGET 0 95 Auto Self Refresh Disabled Self Refresh Temperature Range SRT Low External clock Off CK and LOW CL see Table 30 BL 89 AL 0 CS Command Address Bank Address Data IO MID LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Auto Self Refresh Current optional f IDDGTC TCASE 0 95 Auto Self Refresh Enable
34. DC Output Measurement Levels 2 44 0 nnns 22 13 1 Single ended AC amp DC Output Levels eene nennen nnn nnns nnn 22 13 2 Differential AC amp DC Output Levels MEE MEE MEM EE 22 13 3 Single ended Output Slew Rate nennen enn n nnn enhn nnn 22 13 4 Differential Output Slew Rate 23 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 14 0 IDD Specification Definition lt gt 2 lt lt lt 24 14 1 IDD SPEC 2 26 15 0 Input Output Capacitance 4 4 29 151 Non ECG UDIMM 29 uU rAzsuuil 29 16 0 Electrical Characteristics and AC timing 30 16 1 Refresh Parameters by Device Density 1 1 1 1 4 nnn nnn 30 16 2 Speed Bins and CL tRCD tRP tRC and tRAS for Corresponding Bin 30
35. Differential output slew rate for rising edge Delta TRdiff Differential output slew rate for falling edge Vouais AC Delta TFdiff Note Output slew rate is verified by design and characterization and may not be subject to production test Differential Output slew rate DDR3 1066 DDR3 1333 DDR3 1600 Parameter Symbol Units Min Max Min Max Min Max Differential output slew rate SRQse 5 10 5 10 TBD 10 Vins Description SR Slew Rate Query Output like in DQ which stands for Data in Query Output diff Singe ended Signals delta TFdiff delta TRdiff Figure 8 Differential Output Slew Rate definition 220139 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 14 0 IDD Specification Definition Symbol Description Operating One Bank Active Precharge Current IDDO CKE High External clock On tCK nRC nRAS CL see Table 30 BL 89 AL 0 CS High between ACT and PRE Command Address Bank Address Inputs partially toggling according to Table 32 Data IO MID LEVEL DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table32 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 32 Operating One Bank Active Read Prech
36. M CS boss DM CS Das DM CS Das w 1 0 0 00 w 00 00 DQ25 wr 1 0 1 1 012 0057 w I O 1 07 1 016 DQ26 w I 02 2 0958 w 1 0 2 VO2 0027 w 1 0 3 0059 w 1 03 1 0 3 0928 A 1 0 4 4 DQ60 w I 04 4 0029 wr 1 05 5 0061 05 5 0030 A 1 06 1 0 6 DQ62 w 1 0 6 1 0 6 0031 w 1 07 za VOT 20 02063 w 1 0 7 za VO7 20 2 3 3 3 DQS8 DM8 VW i ahs L Serial PD DM CS CS 005 100 00 SCL 1 01 O1 017 EVENT EVENT lt gt SDA CB2 w 1 0 2 2 Ww 1 03 3 A0 A1 A w l O4 1 0 4 CB5 w 1 05 5 SA1 5 2 CB6 w l O6 1 0 6 I 07 VOT ZQ E 20 E BAO BA2 BAO0 BA2 SDRAMs 00 017 Note 0 15 A0 A15 SDRAMs 00 D17 1 DQ to I O wiring is shown as recommended but may be changed _ GRE GRE Vppspp gt SPD 2 DQ DQS DQS ODT DM CKE S relationships must be CKE SDRAMs 00 D8 maintained as shown Vpp Vppa DO 017 3 CB DQS 00 resistors Refer to associated RAS RAS SDRAMs 00 017 topology diagram CAS CAS SDRAMs DO 017 VREFDQ DO DT 4 Refer to section 7 1 of this document for details on E Vss 1 1 00 017 address mirroring WE WE SDRAMs 00 017 L 5 For each DRAM a uniq
37. M supplier data sheet and or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material 16 2 Speed Bins and CL tRCD tRP tRC and tRAS for Corresponding Bin Speed DDR3 1066 DDR3 1333 DDR3 1600 Bin CL tRCD tRP 7 7 7 9 9 9 11 11 11 Units Note Parameter min min min CL 7 9 11 tCK tRCD 13 13 13 5 13 75 ns tRP 13 13 13 5 13 75 ns tRAS 37 5 36 35 ns tRC 50 63 49 5 48 75 ns tRRD 7 5 6 0 6 0 ns tFAW 37 5 30 30 ns 16 3 Speed Bins and CL tRCD tRP tRC and tRAS for corresponding Bin DDR3 SDRAM Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin DDR3 1066 Speed Bins Speed DDR3 1066 CL nRCD nRP 7 7 7 Units Note Parameter Symbol min max Internal read command to first data tAA 13 125 20 ns ACT to internal read or write delay time tRCD 13 125 ns PRE command period tRP 13 125 ns ACT to ACT or REF command period tRC 50 625 ns ACT to PRE command period tRAS 37 5 9 tREFI ns 8 _ 5 tCK AVG 2 5 3 3 ns 1 2 3 6 CWL 6 tCK AVG Reserved ns 1 2 3 4 ares CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 4 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 Supported CL Settings 6 7 8 nCK Supported CWL Settings 5 6 nCK 28 of 39 ELECTRONICS Rev 1 03 July 2009 Unbuf
38. RAM device supports tnPARAM nCK RU tPARAM ns tCK avg ns which is in clock cycles assuming all input clock jitter specifications are satisfied For example the device will support tnRP RU tRP tCK avg which is in clock cycles if all input clock jitter specifications are met This means For DDR3 800 6 6 6 of which tRP 15ns the device will support tnRP RU tRP tCK avg 6 as long as the input clock jitter specifications are met i e Precharge command at Tm and Active command at Tm 6 is valid even if Tm 6 Tm is less than 15ns due to input clock jitter Specific Note f When the device is operated with input clock jitter this parameter needs to be derated by the actual tERR mper act of the input clock where 2 lt m lt 12 output deratings are relative to the SDRAM input clock For example if the measured jitter into DDR3 800 SDRAM has tERR mper act min 172 ps and tERR mper act max 193 ps then tDQSCK min derated tDQSCK min tERR mper act max 400 ps 193 ps 593 ps and tDQSCK max derated tDQSCK max tERR mper act min 400 ps 172 ps 572 ps Similarly tLZ DQ for DDR3 800 derates to tLZ DQ min derated 800 ps 193 ps 993 ps and tLZ DQ max derated 400 ps 172 ps 572 ps Caution on the min max usage Note that tERR mper act min is the minimum measured value of tERR nper where 2 lt n lt 12 and tERR mper act max is the maximum measured value of tERR nper
39. S stable at 1 Command Address Bank Address Inputs stable at 0 Data lO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pecharge Power Down Mode Slow Exi Precharge Power Down Current Fast Exit IDD2P4 CKE Low External clock On tCK CL see Table 30 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pecharge Power Down Mode Fast Exit Precharge Quiet Standby Current IDD2Q CKE High External clock On tCK CL see Table 30 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data lO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Active Standby Current IDD3N CKE High External clock On tCK CL see Table 30 BL 82 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 34 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode ODT Sig nal stable at 0 Pattern Details see Table 34 Active Power Down Current IDD3P CKE Low External clock On tCK CL see Table 30 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inp
40. SA2 BAO BA2 SDRAMs 00 08 SPD Note A0 A15 A0 A15 SDRAMs 00 08 Vpp Vppa 1 DQ to I O wiring is shown as recommended but may be changed _ RAS RAS SDRAMs 00 08 3 00 08 2 pg pas DQS ODT DM CKE S relationships must be CAS CAS SDRAMs DO D8 Vss JT 00 08 maintained as shown a 3 DQ CB DM DQS DQS resistors Refer to associated CKE SDRAMs 00 D8 VREEGA 4 20 08 topology diagram WE TT 4 Refer to the appropriate clock wiring topology under the WE WESSDRAMSDO D6 DIMM wiring details section of this document ODTO ODT SDRAMs 00 D8 5 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 240 Ohm 1 SDRAMs 00 D8 6 Refer to SPD and Thermal sensor for ECC UDIMMs for SPD detail 120f 39 ELECTRONICS Rev 1 03 July 2009 Unbuffered DIMM DDR3 SDRAM 9 3 2GB 256Mx64 Module Populated as 2 ranks of x8 DDR3 SDRAMs
41. Unbuffered DIMM DDR3 SDRAM 18 0 Physical Dimensions 18 1 64Mbx16 based 64Mx64 Module 1 Rank Units Millimeters 133 35 0 15 gt 5 S 128 95 gt 5 x 5 1 v Y H SPD 5 LJ 8 2 Eo e f 2 a 2 50 N 54 675 B 47 00 E 71 00 Max 4 0 S 1 270 0 10 le 5 00 0 80 0 05 2 2 10 0 15 e gt AN N i 3 80 0 2 0 15 1 50 0 10 B 1 00 lt g gt lt 2 50 Detail A Detail B The used device is 64M x16 DDR3 SDRAM FBGA DDR3 SDRAM Part NO 4 161646 Note Tolerances on all dimensions
42. Unbuffered DIMM DDR3 SDRAM DDR3 SDRAM Specification 240pin Unbuffered DIMM based on 1Gb E die 64 72 bit Non ECC ECC 78FBGA with Lead Free amp Halogen Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS AND IS SUBJECT TO CHANGE WITHOUT NOTICE NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHER WISE TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL OGY ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS AS IS BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND 1 For updates or additional information about Samsung products contact your nearest Samsung office 2 Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where Product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply Samsung Electronics reserves the right to change products or specification without notice 1 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM Table Contents 1 0 DDR3 Registered DIMM Ordering Information 5 20 Key Feature 5 3 0 Address Configuration
43. Vppspp SPD 4 Refer to section 7 1 of this document for details on WE SDRAMs 00 015 address mirroring ODTO ODT SDRAMs DO D7 00 015 5 For each DRAM a unique ZQ resistor is connected to v Dis ground The ZQ resistor is 240 Ohm 1 ODT1 gt ODT SDRAMs 08 015 REFDQ 7 6 One SPD exists module CK SDRAMs D0 D7 eg gt SDRAMs 08 015 VREFCA Doe Bits 13 of 39 ELECTRONICS Rev 1 03 July 2009 Unbuffered DIMM DDR3 SDRAM 9 4 2GB 256Mx72 ECC Module Populated as 2 ranks of 8 DDR3 SDRAMs 51 50 DQSO 0954 WwW DQSO 0954 DMO T DM4 M DM CS DM CS DM CS
44. al when low By deactivating the clocks CKE low CKEO CKE1 SSTL initiates the Power Down mode or the Self Refresh mode Enables the associated SDRAM command decoder when low disables the command decoder when high When the S0 S1 SSTL decoder is disabled new command are ignored but previous operations continue This signal provides for external rank selection on systems with multiple ranks RAS CAS WE SSTL CAS and WE ALONG WITH S define the command being entered When high termination resistance is enabled for all DQ DQS DQS and DM pins assuming the function is enabled in SIE the Extended Mode Register Set EMRS VREFDQ Supply Reference voltage for SSTL 15 I O inputs VREFCA Supply Reference voltage for SSTL 15 command address inputs V Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity For all current DDR3 unbuffered UPP Y DIMM designs shares the same power plane as Vpp pins BAO BA2 SSTL Selects which SDRAM bank of eight is activated During a Bank Activate command cycle Address input defines the row address RAO RA13 During a Read or Write command cycle Address input defines the column address In addition to the column address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is high autoprecharge is 0 13 SSTL selected and BAO 1 BA2 defines the bank to be precharged If AP
45. arge Current IDD4 CKE High External clock On tCK nRC nRAS nRCD CL see Table 30 BL 82 AL 0 CS High between ACT RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 33 DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table33 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 33 Precharge Standby Current IDD2N CKE High External clock On tCK CL see Table 30 BL 82 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 34 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 34 Precharge Standby ODT Current DD2NT CKE High External clock On tCK CL see Table 30 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 35 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling according to Table 35 Pattern Details see Table 35 DDQ2NT Precharge Standby ODT IDDQ Current optional Same definition like for IDD2NT however measuring IDDQ current instead of IDD current Precharge Power Down Current Slow Exit IDD2PO CKE Low External clock On tCK CL see Table 30 BL 82 AL 0 C
46. capacitance bu Dos poe TDQS TDQS TBD i TBD pF Input capacitance CK and CK CCK TBD TBD pF Input capacitance All other input only pins CI TBD TBD pF Input output capacitance of ZQ CZQ TBD TBD pF 15 2 ECC UDIMM M391B2873EH1 Parameter Symbol cabins Units Notes Min Max Min Max Input output capacitance pU bee os TDQS TDS Sm TBD TBR pF Input capacitance CK and CK CCK TBD TBD pF Input capacitance All other input only pins CI TBD TBD pF Input output capacitance of ZQ pin CZQ TBD TBD pF M391B5673EH1 Parameter Symbol Units Notes Min Max Min Max Input output capacitance D sities TDOS TDQS TM TBD i TBB pF Input capacitance CK and CK CCK TBD TBD pF Input capacitance All other input only pins CI TBD TBD pF Input output capacitance of ZQ pin CZQ TBD TBD pF 27 of 39 ELECTRONICS Rev 1 03 July 2009 Unbuffered DIMM 16 0 Electrical Characteristics and AC timing 0 lt 95 1 5V 0 075V Vpp 1 5V 0 075V 16 1 Refresh Parameters by Device Density DDR3 SDRAM Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units Note All Bank Refresh to active refresh cmd time tRFC 110 160 300 350 ns 09 lt TcASE lt 85 7 8 7 8 7 8 7 8 us Average periodic refresh interval tREFI 85 lt TcASE lt 95 3 9 3 9 3 9 3 9 us 1 Note 1 Users should refer to the DRA
47. ctivation precharge autoprecharge or refresh are in progress but power down IDD spec will not be applied until finishing those operations 21 Altough is allowed to be registered LOW after a REFRESH command once tREFPDEN min is satisfied there are cases where additional time such as tXPDLL min is also required See Device Operation 22 Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function 23 One ZQCS command can effectively correct a minimum of 0 5 96 ZQCorrection of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the Output Driver Voltage and Temperature Sensitivity and ODT Voltage and Temperature Sensitivity tables The appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters One method for calculating the interval between ZQCS commands given the temperature Tdriftrate and voltage Vdriftrate drift rates that the SDRAM is sub ject to in the application is illustrated The interval could be defined by the following formula ZQCorrection TSens x Tdriftrate VSens x Vdriftrate where TSens max dRTTdT dRONdTM and VSens max dRTTdV dRONdVM define the SDRAM temperature and voltage sensitivities For example if TSens 1 5 C VSens 0 1596 mV Tdriftrate 1 sec and Vdriftrate 15 mV sec then the interval between ZQCS commands is calcu
48. d Self Refresh Temperature Range SRT Normal Low External clock Off CK and LOW CL see Table 30 BL 82 AL 0 CS Command Address Bank Address Data IO MID LEVEL DM stable at 0 Bank Activity Auto Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Operating Bank Interleave Read Current CKE High External clock tCK nRC nRAS nRCD nRRD nFAW CL see Table 30 BL 88 9 AL CL 1 CS High between ACT and RDA Command IDD7 Address Bank Address Inputs partially toggling according to Table 39 Data IO read data bursts with different data between one burst and the next one according to Table 39 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different addressing see Table 39 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 39 a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT_Nom enable set MR1 A 9 6 2 011B RTT_Wr enable set MR2 A 10 9 10B c Pecharge Power Down Mode set MRO 12 for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 to disable or 1B to enable feature Self Refresh Temperature Range SRT set MR2 A7 0B for normal or 1B for extended temperature range f Refer to DRAM supplier data sheet and or DIMM SPD to det
49. ded but may be changed 2 DQ DQS DQS ODT DM CKE S relationships must be maintained as shown 3 DQ DM DQS DQS resistors Refer to associated topology diagram 4 Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document 5 Refer to section 7 1 of this document for details on address mirroring 6 For each DRAM a unique ZQ resistor is connected to 7 ground The ZQ resistor is 240 Ohm 1 One SPD exists per module ELECTRONICS 11 of 39 Rev 1 03 July 2009 Unbuffered DIMM DDR3 SDRAM 9 2 1GB 128Mx72 Module Populated as 1 rank of x8 DDR3 SDRAMs 50 DQSO DQSO DQS1 DQS1 DM1 DQS2 DQS2 w j w paz DQ4 w DQ5 DM 1 00 1 1 02 04 VO5 1 0 6 VO7 cs 00 Das DOS E pas 009 DQ10 wr wr DQ12 wr DQ13 wr 0014 wr 0015 Ww DM 1 00 VO 1 y o 2 1 03 1 0 4 1 05 1 0 6 1 07 CS 01 DM DQs3 DQs3 DQS8 DQS8 DM8 DQ16 DQ17 Ww DQ18 wr DQ19 Ww DQ20 ww DQ21 DQ22 DQ23 DM 1 00 VO 1 y o 2 1 03 1 0 4 5 1 0 6 VO7 65 02 00 DOS BN 0924 0025 ww 002
50. e address pins A3 A4 A5 7 8 and bank address pins BAO and Refer to Table Rank 0 DRAM pins are wired straight with no mismatch between the connector assignment and the DRAM pin assignment Some of the Rank 1 DRAM pins are cross wired as defined in the table Pins not listed in the table are wired straight 8 1 1 DRAM Pin Wiring Mirroring Connector Pin DRAM Pin Rake Rank 1 i es 4 4 4 5 x 6 A AT A7 8 A8 x BAO BAO BAT BA1 BA1 BAO Figure 1 illustrates the wiring in both the mirrored and non mirrored case The lengths of the traces to the DRAM pins is obviously shorter The via grid is smaller as well 222 A7 DRAM top side N 4 A7 signal A8 DRAM v NS Green darker is top side Figure 1 Wiring Differences for Mirrored and Non Mirrored Addresses Since the cross wired pins have no secondary functions there is no problem in normal operation Any data written is read the same way There are limi tations however When writing to the internal registers with a mode operation the specific address is required This requires the controller to know if the rank is mirrored or not This requires a few rules Mirroring is done on 2 rank modules and can only be done on the second rank There is not a requirement that the second rank be mirrored There is a b
51. e less than 500mV Vref may be equal to or less than 300mV 10 2 DRAM Component Operating Temperature Range Symbol Parameter rating Unit Notes TOPER Operating Temperature Range 0 to 95 C 1 2 3 Note 1 Operating Temperature Toper is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the JEDEC document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case tem perature must be maintained between 0 859 under all operating conditions 3 Some applications require operation of the Extended Temperature Range between 85 and 95 case temperature Full specifications are guaran teed in this range but the following additional conditions apply Refresh commands must be doubled in frequency therefore reducing the refresh interval tREFI to 3 9us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 Ob and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 05 11 0 AC amp DC Operating Conditions 11 1 Recommended DC Operating Conditions SSTL 15 Rating
52. e system board SCL This signal is used to clock data into and out of the SPD EEPROM An external resistor may be connected from the SCL bus time to Vppspp to act as a pull up on the system board Power supply for SPD EEPROM This supply is separate from the Vpp Vppo power plane EEPROM supply is operable VppsPD Supply from 3 0V to 3 6V RESET The RESET pin is connected to the RESET on each DRAM When low all DRAMs are set to a know state EVENT Output This signal indicates that a thermal event has been detected in the thermal sensing device The system should guaran tee the electrical level requirement is met for the EVENT pin on TS SPD part 9 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 8 1 Address Mirroring Feature There is a via grid located under the DRAMs for wiring the CA signals address bank address command and control lines to the DRAM pins The length of the traces from the vias to the DRAMs places limitations on the bandwidth of the module The shorter these traces the higher the bandwidth To extend the bandwidth of the CA bus for DDR3 modules a scheme was defined to reduce the length of these traces The pins on the DRAM are defined in a manner that allows for these short trace lengths The CA bus pins in Columns 2 and 8 ignoring the mechanical support pins do not have any special functions secondary functions This allows the most flexibility with these pins These ar
53. erential Signals 12 3 1 Differential Signals Definition tDVAC Vi DIFF AC MIN Differential Input Voltage DQS DQS CK CK 0 0 half cycle Vi DIFF MAX Vi DIFF AC MAX time gt Figure 3 Definition of differential ac swing and time above ac level tDVAC 12 3 2 Differential Swing Requirement for Clock CK CK and Strobe DQS DQS DDR3 1066 1333 Symbol Parameter unit Note min max differential input high 0 2 note 3 V 1 Vit differential input low note 3 0 2 V 1 differential input high ac 2 x Vi AC Vner note 3 V 2 ViLai AC differential input low ac note 3 2 ViL AC V 2 Notes 1 Used to define a differential signal slew rate 2 for CK CK use VjJ Vj AC of ADD CMD and Vperca for DOS DOS DQSL DQSL DQSU DQSU use AC of DQs and if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however they single ended signals CK CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits Vj DC max DC min for single ended signals as well as the limitations for overshoot and undershoot Refer to overshoot and Undersheet Specification on page20 Allowed time before ringback tDVAC for CLK CLK and DQS DQS
54. ermine if optional features or requirements are supported by DDR3 SDRAM device 9 IDD current measure method and detail patterns are described on DDR3 component datasheet 24 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 14 1 IDD SPEC Table M378B2873EH1 1GB 128Mx64 Module F H K Symbol TRI UNA E DDR3 1 SEC Unit Notes IDDO 480 520 TBD mA IDD1 600 640 TBD mA IDD2PO slow exit 80 80 TBD mA IDD2P 1 fast exit 200 200 TBD mA IDD2N 240 280 TBD mA IDD2Q 240 280 TBD mA IDD3P fast exit 200 200 TBD mA IDD3N 360 400 TBD mA IDD4R 840 1000 TBD mA IDDAW 920 1080 TBD mA IDD5B 1200 1280 TBD mA 1006 80 80 TBD mA 1007 1400 1840 TBD mA M378B5673EH1 2GB 256Mx64 Module F H K pube OP enn pni Notes IDDO 720 800 TBD mA IDD1 840 920 TBD mA IDD2PO slow exit 160 160 TBD mA IDD2P 1 fast exit 400 400 TBD mA IDD2N 480 560 TBD mA IDD2Q 480 560 TBD mA IDD3P fast exit 400 400 TBD mA IDD3N 600 680 TBD mA IDD4R 1080 1280 TBD mA IDDAW 1160 1360 TBD mA IDD5B 1440 1560 TBD mA 1006 160 160 TBD mA 1557 1640 2120 TBD mA 25 of 39 ELECTRONICS Rev 1 03 July 2009 Unbuffered DIMM DDR3 SDRAM M391B2873EH1 1GB 128Mx72 Module F H K gymbel secre
55. eviate from Vgge DC by more than 1 for reference approx 15mV 4 For reference approx Vpp 2 x 15mV Single Ended AC and DC input levels for DQ and DM DDR3 1066 DDR3 1333 1600 Symbol Parameter Unit Notes Min Max Min Max Vig po DC100 DC input logic high Vrer 100 Vrer 100 1 0 100 input logic low Vss Vrer 100 Vss Vrer 100 1 175 AC input logic high 175 150 mV 1 2 5 Vi 175 AC input logic low Vngr 175 Vrer 150 mV 1 2 5 150 input logic high 150 2 mV 1 2 5 Vit 150 input logic low Note 2 Vrer 150 E z mV 1 2 5 Reference Voltage DQ 0 49 Vpp 0 51 0 49 Vpp 0 51 Vpp V 344 Note 1 For input only pins except RESET Vggr Vrerpa DC 2 See 9 6 Overshoot and Undershoot specifications section 3 The AC peak noise on Vggr may not allow Vggr to deviate from Vgge DC by more than 1 for reference approx 15mV 4 For reference approx Vpp 2 15mV 5 Single ended swing requirement for DQS DQS is 350mV peak to peak Differential swing for DQS DQS is 700mV peak to peak ELECTRONICS 16 of 39 Rev 1 03 July 2009 Unbuffered DIMM DDR3 SDRAM 12 2 Vref Tolerances The dc tolerance limits and ac noise limits for the reference voltages and are illustrate in Figure 2
56. fered DIMM DDR3 SDRAM DDR3 1333 Speed Bins Speed DDR3 1333 CL nRCD nRP 9 9 9 Units Note Parameter Symbol min max Internal read command to first data tAA 13 5 13 125 59 20 ns ACT to internal read or write delay time tRCD 13 5 13 125 59 ns PRE command period tRP 13 5 13 125 59 ns ACT to ACT or REF command period 49 5 49 125 gt 9 ns ACT to PRE command period tRAS 36 9 tREFI ns 8 5 tCK AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 tCK AVG Reserved ns 1 2 3 4 7 7 tCK AVG Reserved ns 4 5 tCK AVG Reserved ns 4 1 875 2 5 7 CWL 6 tCK AVG ns 1 2 3 4 7 Optional Note 5 9 7 tCK AVG Reserved ns 1 2 3 4 5 tCK AVG Reserved ns 4 CL 8 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 tCK AVG Reserved ns 1 2 3 4 TN CWL 5 6 tCK AVG Reserved ns 4 7 tCK AVG 1 5 1 875 ns 1 2 3 4 CWL 5 6 tCK AVG Reserved ns 4 CL 10 1 5 1 875 ns 1 2 3 CWL 7 tCK AVG Optional ns 5 Supported CL Settings 6 7 8 9 nCK Supported CWL Settings 5 6 7 nCK 290139 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 1600 Speed Bins DDR3 SDRAM ELECTRONICS Speed DDR3 1600 CL nRCD nRP 11 11 11 Units Note Parameter Symbol min max 13 75
57. is low autoprecharge is disabled During a pre charge command cycle AP is used in conjunction with BAO BA1 BA2 to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BA1 or BA2 If AP is low BAO BA1 and BA2 are used to define which bank to precharge A12 BC is sampled during READ and WRITE commands to determine if burst chop on the fly will be performed HIGH no burst chop Low burst chopped 000 0063 CBO CB7 SSTL Data and Check Bit Input Output pins DM is an input mask signal for write data Input data is masked when DM is sampled High coincident with that input data DMO DM8 SSTL during a write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loading Power and ground for DDR3 SDRAM input buffers and core logic Vpp and pins are tied to Vpp Vppo planes on Vpp Vss Supply these modules DQS0 DQS8 SSTL Data strobe for input and output data For raw cards using x16 organized DRAMs Pins DQO 7 are associated with the DQS0 DQS8 LDQS and LDQS pins and Pins DQ8 15 are associated with UDQS and UDQS pins SA0 SA2 These signals and tied at the system planar to either Vss or Vppspp to configure the serial SPD EERPOM address range SDA This bidirectional pin is used to transfer data into or out of the SPD EEPROM An external resistor may be connected 7 from the SDA bus line to to act as a pull up on th
58. it assignment in the SPD that indicates whether the module has been designed with the mir rored feature or not See the DDR3 UDIMM SPD specification for these details The controller must read the SPD and have the capability of de mirroring the address when accessing the second rank 10 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 9 0 Function Block Diagram 9 1 1GB 128Mx64 Module Populated as 1 rank of x8 DDR3 SDRAMs 50 DQSO DQSO DQS1 DQO DQ1 DQ2 003 004 005 006 007 DM 1 0 0 VO 1 2 3 4 5 1 0 6 7 20 CS Das DQS1 DM1 DQS2 A 098 pag 0910 0012 wr 0013 0014 0015 DM VO 0 1 yo 2 yo 1 0 4 05 1 0 6 1 07 D1 ZQ CS Das DQS2 DM2 DQs3 W DQ16 0017 Ww DQ18 Ww DQ19 Ww 0020 w 0021 Ww 0022 0023 DM 1 00 1 1 02 yo 1 0 4 yo 5 1 0 6 1 07 D2 ZQ CS Das 00 3 W w A13 RAS CAS CKEO WE ODTO DM NU CS 59 024 100 025 1 DQ26 w 1 0 2 DQ27 Ww 1 0 3 028 104 29 05 30 1 06 20 DQ31 wr 07
59. lew rate definitions for address and command signals See Data Setup Hold and Slew Rate Derating for single ended slew rate definitions for data signals tDH nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vi DC min and the first crossing of Vper 12 5 Slew Rate Definition for Differential Input Signals Input slew rate for differential signals CK CK and 00 005 are defined and measured as shown in below Differential input slew rate definition Measured Description Defined b P From To m gt ViLdiffmax Differential input slew rate for rising edge CK CK and DQS DQS ViLdiffmax Delta TRdif elta P 7 ViLdiffmax Differential input slew rate for falling edge DQS DQS Vit diffmax Delta TEdiff elta Note The differential signal CK CK 005 DQS must be linear between these thresholds delta TFdiff delta TRdiff Figure 6 Differential Input Slew Rate definition for DQS DQS and CK CK 20 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 13 0 AC amp DC Output Measurement Levels 13 1 Single ended AC amp DC Output Levels Single Ended AC and DC output levels Symbol Parameter DDR3 1066 1333 Units Notes
60. o Overshoot and Undershoot Specification 19 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 12 3 4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK and DQS DQS must meet the requirements in below table The differential input cross point voltage Vix is measured from the actual cross point of true and complement signal to the mid level between of Vpp and Vss Vpp DQS CK DQS Vss Figure 5 Vix Definition Cross point voltage for differential input signals CK DQS DDR3 1066 1333 Symbol Parameter Unit Notes Y Min Max Vix Differential Input Cross Point Voltage relative to 2 for CK CK 80 150 175 175 1 Vix Differential Input Cross Point Voltage relative to Vpp 2 for DQS DQS 150 150 mV Note 1 Extended range for Vix is only allowed for clock and if single ended clock input signals CK and CK are monotonic have a single ended swing of at least Vpp 2 250 mV and the differential slew rate of CK CK is larger than V ns Refer to table 11 on page 17 for and standard values 12 4 Slew Rate Definition for Single ended Input Signals See Address Command Setup Hold and Derating for single ended s
61. ommand period for 2KB pagesize tRRD 4nCK_10ns AnCK T Te Sns Four activate window for 1 page size FAW 37 5 30 30 ns e Four activate window for 2KB page size FAW 50 45 40 ns e pata 125 65 5 TBD ps 646 ame o 200 140 TBD ps b16 EE estas 180125 ps Control amp Address Input pulse width for each input tIPW 780 620 560 ps 28 Calibration Timing Power up and RESET calibration time tZQinitl 512 512 512 Normal operation Full calibration time tZQoper 256 256 256 nCK Normal operation short calibration time tZQCS 64 64 64 23 Reset Timing Exit Reset from CKE HIGH to a valid command tXPR hcic de 2 dde Self Refresh Timing Exit Self Refresh to commands not requiring a locked max 5nCK tRFC max 5nCK tRFC max 5nCK tRFC DLL XS 10ns 40ns 5 101 Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK min tDLLK min tDLLK min low width for Self refresh entry to exit ftCKE min ICKE min tCKE min Valid Clock Requirement after Self Refresh Entry tCKSRE 5 E max 5nCK 1 5 _ SRE or Power Down Entry PDE 10ns 10ns 10ns Valid Clock Requirement before Self Refresh Exit tCKSRX 5 max 5nCK max 5nCK _ SRX or Power Down Exit or Reset Exit 10ns 10ns 10ns
62. programmed in MRO 11 The maximum read postamble is bound by tDQSCK min plus tQSH min on the left side and tHZ DQS max on the right side See Device Operation Datasheet 12 Output timing deratings are relative to the SDRAM input clock When the device is operated with input clock jitter this parameter needs to be derated by TBD 13 Value is valid for RON34 14 Single ended signal parameter 15 tREFI depends on 16 tIS base and tIH base values are for 1V ns CMD ADD single ended slew rate and 2V ns CK CK differential slew rate Note for DQ and DM signals VggeDQ DC FOr input only pins except RESET Vgge DC VggeCA DC See Address Command Setup Hold and Derating 17 tDS base and tDH base values are for 1V ns DQ single ended slew rate and 2V ns DQS DQS differential slew rate Note for DQ and DM signals Vrer DC VgggDQ DC For input only pins except RESET Vggg DC VggeCA DC See Data Setup Hold and Slew Rate Derating 18 Start of internal write transaction is definited as follows For BL8 fixed by MRS and on the fly Rising clock edge 4 clock cycles after WL For 4 on the fly Rising clock edge 4 clock cycles after WL For BC4 fixed by MRS Rising clock edge 2 clock cycles after WL 19 The maximum read preamble is bound by tLZDQS min on the left side and tDQSCK max on the right side See Device Operation 20 CKE is allowed to be registered low while operations such as row a
63. t tCK avg represents the actual tCK avg of the input clock under operation Unit nCK represents one clock cycle of the input clock counting the actual clock edges ex tMRD 4 nCK means if one Mode Register Set command is registered at Tm another Mode Register Set command be registered at Tm 4 even if 4 is 4 x tCK avg tERR Aper Specific Note b These parameters are measured from a command address signal CS RAS CAS WE ODT A1 etc transition edge to its respective clock signal CK CK crossing The spec values are not affected by the amount of clock jitter applied i e tJIT per tJIT cc etc as the setup and hold are relative to the clock signal crossing that latches the command address That is these param eters should be met whether clock jitter is present or not Specific Note c These parameters are measured from a data strobe signal DQS L U DQS L U crossing to its respective clock signal CK CK cross ing The spec values are not affected by the amount of clock jitter applied i e tJIT per tJIT cc etc as these are relative to the clock signal crossing That is these parameters should be met whether clock jitter is present or not Specific Note d These parameters are measured from a data signal DM L U DQ L U 0 DQ L U 1 etc transition edge to its respective data strobe signal DQS L U DQS L U crossing Specific Note e For these parameters the DDR3 SD
64. te definition Measured Description Defined by From To Single ended output slew rate for rising edge Voi AC 99 PE SS Delta TRse Single ended output slew rate for falling edge Voi AC _ Delta TFse Note Output slew rate is verified by design and characterization and may not be subject to production test Single Ended Output slew rate DDR3 1066 DDR3 1333 DDR3 1600 2 Parameter Symbol Units Min Max Min Max Min Max Single ended output slew rate SRQse 2 5 5 2 5 5 TBD 5 Vins Description SR Slew Rate Query Output like DQ which stands for Data in Query Output se Singe ended Signals For Ron RZQ 7 setting VoH AC VoL AC delta TFse delta TRse Figure 7 Single Ended Output Slew Rate definition pen Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 13 4 Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between and Vonairt AC for differential signals as shown in below Differential Output slew rate definition Measured Description Defined by From To
65. ue ZQ resistor is connected to ODT SDRAMs 00 D8 VREFCA 017 ground 20 resistor is 240 Ohm 1 6 Refer to SPD and Thermal sensor for ECC UDIMMs ODT1 ODT SDRAMs 09 017 for SPD detail SDRAMs DO D8 SDRAMs D9 017 14 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 10 0 Absolute Maximum Ratings 10 1 Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes Vpp Voltage on Vpp pin relative to Vss 0 4 V 1 975 V V 1 3 Vppo Voltage on Vppg pin relative to Vss 0 4 V 1 975 V V 1 3 Vin Vout Voltage on any pin relative to Vss 0 4 V 1 975 V V 1 Storage Temperature 55 to 100 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 Vpp and must be within 300mV of each other at all times and Vgge must be not greater than 0 6 x When Vpp and ar
66. uencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 9 For devices supporting optional downshift to CL 7 and CL 9 tAA tRCD tRP min must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333 CL9 devices supporting downshift to DDR3 1066 CL7 should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600 CL 11 devices supporting downshift to DDR3 1333 CL9 or DDR3 1066 CL7 should pro gram 13 125 ns SPD bytes for tAAmin Byte16 tRCDmin Byte 18 and tRPmin Byte 20 Once Byte 20 is programmed to 13 125ns tRC min Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36ns 13 125ns for DDR3 1333 CL9 and 48 125ns tRASmin tRPmin 35ns 13 125ns for DDR3 1600 CL 11 31 of 39 Rev 1 03 July 2009 ELECTRONICS Unbuffered DIMM DDR3 SDRAM 17 0 Timing Parameters by Speed Grade ELECTRONICS Speed DDR3 1066 DDR3 1333 DDR3 1600 Units Note Parameter Symbol MIN MAX MIN MAX MIN MAX Clock Timing Minimum Clock Cycle Time DLL off mode A 8 8 8 ns 6 Average Clock Period tCK avg See Speed Bins Table ps Clock Period
67. uirements are with respect to the single ended components of differential signals have a requirement with respect to 2 this is nominally the same The transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach Vsg max has no bearing on timing but adds a restriction on the common mode characteristics of these signals Single ended levels for CK 00 DQSL DQSU CK DQS DQSL or DQSU Symbol Parameter Min Unit Notes Single ended high level for Vpp 2 0 175 Note3 V 4 Single ended high level for CK CK Vpp 2 0 175 Note3 V 1 Veet Single ended low level for stones Note3 Vpp 2 0 175 V 1 Single ended low level for CK CK Note3 Vpp 2 0 175 V 1 Notes 1 For CK use AC of ADD CMD for strobes 005 DQS DASL DSL DQSU DQSU use AC of DQs 2 AC for DQs is based on Vggepo AC for ADD CMD is based on if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values not defined however they single ended signals CK 00 005 DQSL DQSL DQSU DQSU need to be within the respective limits Vj DC max Vj DC min for single ended signals as well as the limitations for overshoot and undershoot Refer t
68. uts stable at 0 Data lO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Operating Burst Read Current CKE High External clock On tCK CL see Table 30 BL 82 AL 0 CS High between RD Command Address Bank Address Inputs partially toggling IDD4R according to Table 36 Data seamless read data burst with different data between one burst and the next one according to Table 36 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 on page 10 Output Buffer and RTT Enabled in Mode Regis ters ODT Signal stable at 0 Pattern Details see Table 36 IDDQ4R Operating Burst Read IDDQ Current optional Same definition like for IDD4R however measuring IDDQ current instead of IDD current Operating Burst Write Current CKE High External clock On tCK CL see Table 30 BL 82 0 CS High between WR Command Address Bank Address Inputs partially tog IDDAW gling according to Table 37 Data IO seamless write data burst with different data between one burst and the next one according to Table 37 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 37 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at HIGH Pattern Details see Table 37 Burst Refresh Current IDD5B CKE High External clock On tCK CL nRF

Samsung M378B5673EH1-CF8 memory module

Contents

Download Pdf Manuals

Related Search

Related Contents