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Infineon HYB39S256400CT-7.5 memory module

1. 1 1 Auto Refresh Auto Refresh Activate Read Command Command Command Command Command All Banks Bank A Bank A SPTO3920 2 INFINEON Technologies 38 n Infineon HYB39S256400 800 160CT L 256 MBit Synchronous DRAM 15 Random Column Read Page within same Bank 15 1 CAS Latency 2 Burst Length 4 CAS Latency 2 TO T1 T2 T3 T4 T5 T6 7 T8 T9 T10 T1 T12 T13 T14 115 116 T17 T18 T19 T20 121 722 y cs NI V V ____ Addr D D DQM Hi Z TE r t Ge GH A A Activate Read Read Read Precharge Activate Read Command Command Command Command Command Command Command Bank A Bank A Bank A Bank A Bank A Bank A Bank A SPT03921 INFINEON Technologies 39 Infineon HYB39S256400 800 160CT L 256 MBit Synchronous DRAM 15 2 CAS Latency 3 CLK CKE RAS BS AP Addr D _ EE Wy ANA DON Burst Length 4 CAS Latency 3 T5 T6 T7 T8 T9 110
2. INFINEON Technologies 8 8 00 HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM Operation Definition All of SDRAM operations are defined by states of control signals CS RAS CAS WE and DQM at the positive edge of the clock The following list shows the truth table for the operation commands Operation Device CKE CS RAS CAS WE State 1 1 10 Bank Active Idle H X X V V V L L H H Bank Precharge Any H X X V L X L L H L Precharge All Any H X X X H X L L H L Write Active H X X V L V L H L L Write with Autoprecharge Active H X X V H V L H L L Read Active H X D V L V L H L H Read with Autoprecharge Active H X X V H V L H L H Mode Register Set Idle H L L L L No Operation Any H X L H H H Burst Stop Active H X X X X X L H H L Device Deselect Any H X X X X X H X X X Auto Refresh Idle H H X X X X L L L H Self Refresh Entry Idle H L L L L H Self Refresh Idle H X X X Ge L H L H H X Clock Suspend Entry Active H L X X X X X X X X Power Down Entry Idle H active Active H L X X X X E B B x standby Clock Suspend Exit Active L H X X X X X X X X Power Down Exit Any H X X X L H L H H L Data Write Output Enable Active H X
3. Infineon 256MBit Synchronous DRAM 9 AP 12 Column Address Column Address Row Address Refresh Counter Counter Buffer Buffer 5 216 Se 5 elo O18 Column Decoder Sense amplifier 4 Bus Column Decoder Column Decoder Sense amplifier 4 Bus Input Buffer Output Buffer Control Logic amp DQO 007 Block Diagram for 32M x 8 SDRAM 13 10 2 addressing INFINEON Technologies 5 8 00 HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM AP 12 Column Address Column Address Row Address Refresh Counter Counter Buffer Buffer Memory Array Memory Memory Array Array Memory Array Bank 1 Bank 2 Bank 3 5 216 Se 5 elo O18 c Column Decoder Sense amplifier 4 Bus Column Decoder Column Decoder Sense amplifier 4 Bus 8192 x 512 8192 x 512 x 16 Bit x 16 Bit 8192 x 512 x 16 Bit Input Buffer Output Buffer 000 DQ15 Block Diagram for 16M x16 SDRAM 13 9 2 addressing INFINEON Technologies 6 8 00 Infineon Signal Pin Description HYB39S256400 800 160CT L 256MBit Synchronous DRAM Pin Type Signal Polarity Function CLK Input Pulse Positive
4. Aio Precharge Bank A RAS 21 CAS gt Activate Activate Activate Write Precharge Activate Activate Command Command Command Command Command Command Command Bank A Bank B Bank Bank A Bank A Bank A Bank B Write with Write with Auto Precharge Auto Precharge Command Command Bank A Bank B SPT03910_2 INFINEON Technologies 28 Infineon 8 2 AC Parameters for a Read Timing HYB39S256400 800 160CT L 256 MBit Synchronous DRAM TO T1 T2 Burst Length 2 CAS Latency 2 T5 T6 7 Tio TH TI2 A A A A A Activate Read Activate Read with Precharge Activate Command Command Command Auto Precharge Command Command Bank A Bank A Bank B Command Bank A Bank A Bank B SPT03911_2 INFINEON Technologies 29 HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 9 Mode Register Set CAS Latency 2 T1 T2 T3 T4 T5 16 T7 9 10 T11 12 13 714 715 116 17 718 19 20 T21 cl KE Address Addr Command All Banks Mode Register Set Command SPT03912 2
5. INFINEON Technologies 30 Ce HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 10 Power on Sequence and Auto Refresh CBR CLK CKE High Level is required TO RAS _ m CAS 7 NN SSR a BS AP Address Key Addr m 25 20522 ddl uu E E A A A A A Precharge 8th Auto Refresh lode Register Any Command Command Set Command Command All Banks Inputs musi be tst Auto Refresh stable for 200 us Command SPT03913 INFINEON Technologies 31 HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 11 Clock Suspension Using CKE 11 1 Clock Suspension During Burst Read CAS Latency 2 CLK CAS BS AP DQM DQ Addr Burst Length 4 CAS Latency 2 TO T1 T2 T3 T4 T5 T6 T7 T8 T9 T12 T13 114 T15 T16 T17 118 T19 T20 121 722 SUUUUUUUUUUUUUUUUUUUUU UL luz Hi Z ag Activate Read Clock Clock Clock Command Command Suspend Suspend Suspend Bank A Bank A 1 Cycle 2 Cycles 3 Cycles SPT03914
6. Von 64 4 DD N C DQO Vsso N C N C Dat Vsso CAS RAS CS BAO BA1 A10 AP AO Al A2 Pinout for x4 x8 amp x16 organised 256M DRAMs INFINEON Technologies ss N C Vsso N C DQ3 DOM CLK CKE 12 11 54 400 875 0 8 pitch 55 007 005 CLK CKE 12 11 55 0015 Vssa 0014 0013 0012 0011 0010 Dag 008 UDOM CLK CKE 12 11 9 7 5 4 Vss SPP04126 8 00 HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM A9 A11 AP 12 Column Address Column Address Row Address Row Row Row Row Decoder Decoder Decoder Decoder Memory Array Memory Array Memory Array Memory Array 5 ale SIS 5 elo O18 c Column Decoder Sense amplifier amp Bus Column Decoder Sense amplifier amp Bus Column Decoder Sense amplifier amp Bus Input Buffer Output Buffer Control Logic amp pU Timing Generator DQO 003 Block Diagram for 64M x 4 SDRAM 13 11 2 addressing INFINEON Technologies 4 8 00 HYB39S256400 800 160CT L
7. Burst Read Operation Burst Length 4 CAS latency 2 3 TO Ti T2 T3 T4 T5 T6 T7 T8 Command CAS latency 2 DOUT A1 A DOUT A2 A DOUT toko DQ s CAS latency 3 DOUT A1 X DOUT A2 toka 005 SPTOSTI2 INFINEON Technologies 22 HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 3 Read Interrupted by a Read Burst Length 4 CAS latency 2 3 TO Ti T2 T3 T4 T5 T6 T7 T8 Command CAS latency 2 DOUT B1 ADOUT DQ s CAS latency 3 DOUT A0 XDOUT B0 DOUT B1 ADOUT B2 ADOUT toka DQ s 5 03713 4 Read to Write Interval 4 1 Read to Write Interval Burst Length 4 CAS latency 3 TO Ti T2 T3 T4 T5 T6 17 T8 Minimum delay between the Read and Write Commands 4 1 5 cycles Write latency of DOMx DQMx me il Lag NOP H H NOP Must be Hi Z before the Write Command Or AE SPT03787 INFINEON Technologies 23 v Infineon HYB39S256400 800 160CT L 256 MBit Synchronous DRAM 4 2 Minimum Read to Write Interval Burst Length 4 CAS latency 2 TO Ti T2 T3 T4 T5 T6 T7 T8 DOM 2 4 lpgz Clk Interval lt Command NOP H NOP H BA H H NOP Must be Hi Z before CAS the Write Co
8. Edge The system clock input All of the SDRAM inputs are sampled on the rising edge of the clock CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low thereby initiates either the Power Down mode Suspend mode or the Self Refresh mode Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue RAS CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock CAS RAS and WE define the command to be executed by the SDRAM A12 Input Level During a Bank Activate command cycle A0 A12 define the row address RAO RA12 when sampled at the rising clock edge During a Read or Write command cycle AO An define the column address when sampled at the rising clock edge CAn depends from the SDRAM organization 64M x4 SDRAM 9 CA11 Page Length 2048 bits 32M x8 SDRAM CAn CA9 Page Length 1024 bits 16M x16 SDRAM CAn CA8 Page Length 512 bits In addition to the column address 10 AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If A10 is high autoprecharge is selected and BA1 defines the bank to be precharged If A10 is low autoprecharge is disabled During a Prech
9. INFINEON Technologies 32 Infineon technologies HYB39S256400 800 160CT L 256 MBit Synchronous DRAM 11 2 Clock Suspension During Burst Read CAS Latency 3 Burst Length 4 CAS Latency 3 TO T2 T3 T4 T5 T6 T7 T8 T9 TIO 11 12 T13 114 115 T16 T17 T18 T19 T20 T21 722 cs NI NI Ey s PE ANE Saas Addr D D tos DON log lt lt log lt d Hi Z pa Activate Read Clock Clock Clock Command Command Suspend Suspend Suspend Bank Bank A 1 2 Cycles 3 Cycles SPT03915 INFINEON Technologies 33 HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 11 3 Clock Suspension During Burst Write CAS Latency 2 Burst Length 4 CAS Latency 2 TO T2 T3 T4 T5 T6 T7 T8 T9 12 T13 T14 T15 T16 T17 T18 T19 T20 T21 722 e fi ZR PT Addr d pom A Hi Z Gg op epos A Activate Clock Clock Clock Command Suspend Suspend Suspend Bank A 1 Cycle 2 Cycles 3 Cycles Write Command SPT0391
10. T19 T20 121 722 cs RAS CAS WE BS AP Addr Activate Write Write Write Precharge Activate Write Command Command Command Command Command Command Command Bank B Bank B Bank B Bank B Bank B Bank B Bank BSPT03924 INFINEON Technologies 42 t HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 17 Random Row Read Interleaving Banks with Precharge 17 1 CAS Latency 2 Burst Length 8 CAS Latency 2 1 T2 T3 T5 6 T7 T8 T9 T10 T11 T12 T13 T14 T15 16 T17 18 19 T20 T21 High CAS BS AP Addr DOM Fair 2 GI x EE BEX Bx E AZA Ax AXE Bo BY 1 Activate Read Activate Precharge Activate Read Command Command Command Command Command Command Bank B Bank B Bank A Bank D Bank Bank B Read Command Bank A 925 2 INFINEON Technologies 43 Infineon 17 2 CAS Latency HYB39S256400 800 160CT L 256 MBit Synchronous DRAM TO T1 T2 T3 CLK CKE RAS CAS BS AP Addr 5 EN DQM Activate Read Command Command Bank B Bank B 17 T8 Activate Command Bank A Burst Length 8 CAS Latency 14 115 T16 T
11. before any activate command after the initial power up Any content of the mode register can be altered by re executing the mode set command All banks must be in precharged state and CKE must be high at least one clock before the mode set operation After the mode register is set a Standby or NOP command is required Low signals of RAS CAS and WE at the positive edge of the clock activate the mode set operation Address input data at this timing defines parameters to be set as shown in the previous table Read and Write Operation When RAS is low and both CAS and WE are high at the positive edge of the clock a RAS cycle starts According to address data a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay tcp from the RAS timing WE is used to define either a read WE or a write WE L at this stage SDRAM provides a wide variety of fast access modes In a single CAS cycle serial data read or write operations are allowed at up to a 133 MHz data rate The numbers of serial data bits are the burst length programmed at the mode set operation i e one of 1 2 4 8 and full page where full page is an optional feature on this device Column addresses are segmented by the burst length and serial data accesses are done within this boundary The first column address to be accessed is supp
12. to Active nsc 2 2 2 delay Power Down Mode Entry Time top 0 7 5 0 8 0 8 5 Common Parameters Row to Column Delay Time trop 20 20 20 ns 5 Row Precharge Time trp 20 20 20 ns 5 Row Active Time tras 45 100k 48 100k 48 100k 5 Row Cycle Time 67 70 70 INFINEON Technologies 17 8 00 HYB39S256400 800 160CT L 256MBit Synchronous DRAM Infineon Parameter Symbol Limit Values Unit 7 5 8 i PC133 PC100 PC100 333 222 322 min max min min max m Activate a to Activate b 15 16 16 ns 5 Command period CAS a to CAS b Command d 1 1 CLK period Refresh Cycle Refresh Period 8192 cycles 64 64 64 ms Self Refresh Exit Time 1 1 1 6 Data Hold Time 3 3 3 5 Data Out Low Time tiz ns Data Out to High Impedance Time ns DOM Data Out Disable Latency toaz CLK Write Cycle Data Input to Precharge twr 2 2 2 8 write recovery DQM Write Mask Latency 0 0 0 INFINEON Technologies 18 8 00 e HYB39S256400 800 160CT L Infineon 256MBit Synchro
13. 1 T2 T3 T4 T5 T6 T7 18 T9 10 T11 112 714 115 T16 17 118 119 20 T21 122 CLK CKE cs RAS CAS WE BS AP Addr 7 8 D wend deeg Ge twr sa lais Ga uni si DQM Hi Z ota 9 DA OAG 0 E ER KD amp xo EH EH OM OH NDN2 Di Activate Write Activate Write Precharge Activate Write Precharge Command Command Command Command Command Command Command Command Bank A Bank A Bank B Bank Bank A Bank A Bank A Bank SPT03928 INFINEON Technologies 46 HYB39S256400 800 160CT L e Infineon 256 MBit Synchronous DRAM 19 Precharge termination of a Burst 19 1 CAS Latency 2 Burst Length 8 or Full Page CAS Latency 2 TO 12 I8 T4 T5 T6 T7 T8 T9 12 T13 14 115 116 T17 T18 T19 T20 121 High cs CAS WE BS Xe D D adar AEX pp pp Rp 9 DOM 2 JC EN A A A Activate Write Precharge Read Precharge Read Precharge Command Command Command Command Command Command Command Bank A Bank A Bank A Bank A Bank A Bank A Bank A Precharge Termination Activate Activate of a Wr
14. 11 712 T13 T14 115 T16 117 118 T19 T20 T21 722 Hi Z po yy ee Activate Read Read Read Precharge Activate Read Command Command Command Command Command Command Command Bank A Bank A Bank A Bank A Bank A Bank A Bank SPT03922 INFINEON Technologies 40 HYB39S256400 800 160CT L oo Infineon 256 MBit Synchronous DRAM 16 Random Column write Page within same Bank 16 1 CAS Latency 2 Burst Length 4 CAS Latency 2 TO T1 T2 T3 T5 T7 T8 T9 10 T11 12 13 T14 715 116 17 18 19 20 T21 CLK CKE RAS CAS BS AP Addr DQM Activate Write Write Write Precharge Activate Read Command Command Command Command Command Command Command Bank B Bank B Bank B Bank B Bank B Bank B Bank B SPT03923_2 INFINEON Technologies 41 Infineon 16 2 CAS Latency HYB39S256400 800 160CT L 256 MBit Synchronous DRAM Burst Length 4 CAS Latency 3 TO T1 T2 T3 T5 T6 T7 T8 T9 110 11 12 113 Tl4 115 16 T17 T18
15. 160CT L Infineon 256MBit Synchronous DRAM refreshes in a burst refresh mode The same rule applies to any access command after the automatic refresh operation The chip has an on chip timer and the Self Refresh mode is available The mode restores the word lines after RAS CAS low and WE is high ata clock timing All of external control signals including the clock are disabled Returning CKE to high enables the clock and initiates the refresh exit operation After the exit command at least one tRC delay is required prior to any access command DQM Function DQM has two functions for data I O read and write operations During reads when it turns to high at a clock timing data outputs are disabled and become high impedance after two clock delay DOM Data Disable Latency tpoz It also provides a data mask function for writes When DQM is activated the write operation at the next clock is prohibited DQM Write Mask Latency tpow zero clocks Suspend Mode During normal access mode CKE is held high enabling the clock When CKE is low it freezes the internal clock and extends data read and write operations One clock delay is required for mode entry and exit Clock Suspend Latency tesu Power Down In order to reduce standby power consumption a power down mode is available All banks must be precharged and the necessary Precharge delay trp must occur before the SDRAM can enter the Power Down m
16. 17 T18 T19 T20 T21 T22 Command Command A A A Activate Read Precharge Command Command Command Bank B Bank B Bank A SPT03926 INFINEON Technologies HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 18 Random Row Write Interleaving Banks with Precharge 18 1 CAS Latency 2 CLK CKE RAS CAS BS AP DOM DO Addr Burst Length 8 CAS Latency 2 1 2 T3 T5 T6 17 T9 10 T11 T12 T13 14 15 16 17 18 T19 20 T21 __ __ SSS NIA eS KEE See EE CX LXX 1 1 1119 No usu Hi Z Da DA A Activate Write Activate Write Activate Precharge Command Command Command Command Command Command Bank A Bank A Bank B Bank B Bank A Bank B Precharge Write Command Command Bank A Bank A SPT03927_2 INFINEON Technologies 45 HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 18 2 CAS Latency Burst Length 8 CAS Latency 3 TO T
17. 5 to 150 Input output voltage 0 3 to Vdd 0 3 V Power supply voltage Vn ut niti 0 310 4 6 V Power DISSIDaltiOn e 1W Data out current short CIrCUll ioi e 50 mA Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device Exposure to absolute maximum rating conditions for extended periods may affect device reliability Recommended Operation and Characteristics 0 to 70 Vas 0 V Von 3 3 0 3 Symbol Limit Values Unit Notes min Input high voltage 2 0 Vdd 0 3 V 1 2 Input low voltage Mu 0 3 0 8 V 11 2 Output high voltage 4 0 mA Vou 2 4 Output low voltage 4 0 mA VoL 0 4 3 Input leakage current any input 5 5 uA 0 V lt Vn lt all other inputs 0 Output leakage current Tow 5 5 uA DQ is disabled 0 V lt Voy lt Notes 1 All voltages are referenced to VSS 2 Vih may overshoot to Vdd 2 0 V for pulse width of lt 4ns with 3 3V Vil may undershoot to 2 0 V for pulse width lt 4 0 ns with 3 3V Pulse width measured at 50 points with amplitude measured peak to DC reference Capacitance 0 to 70 C 3 3 V 0 3 f 1 MHz Parameter Symbol Values Unit min max Inpu
18. 6 Bank A INFINEON Technologies 34 HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 11 4 Clock Suspension During Burst Write CAS Latency Burst Length 4 CAS Latency TO T1 T2 T3 14 T5 T6 T7 T8 19 110 111 12 T13 T14 T15 116 T17 118 T19 T20 T21 22 CKE y df e DQMx B 4 Activate Clock Clock Clock Command Suspend Suspend Suspend Bank 1 Cycle 2 Cycles 3 Cycles Write Command SPT03917 Bank A INFINEON Technologies 35 e Infineon 12 Power Down Mode and Clock Suspend HYB39S256400 800 160CT L 256 MBit Synchronous DRAM CLK CKE RAS CAS BS AP Addr DQM DQ T5 T6 T7 T8 T9 T10 11 T12 113 114 115 116 Burst Length 4 CAS Latency 2 117 T18 119 120 21 T22 Hi Z Power Down Precharge Any Standby Command Power Down t eater Activate Active Read Clock Mask Clock Mask Precharge Command Standby Command Start End Command Bank Bank Bank Clock Suspend Clock Suspend Mode Entry Mode Exit M
19. 8 Input data must be removed from the DQ s at least one clock cycle before the Read data appears on the outputs to avoid data contention 3719 INFINEON Technologies 26 HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 7 Burst Write and Read with Auto Precharge 7 1 Burst Write with Auto Precharge Burst Length 2 CAS latency 2 3 CAS Latency 2 DQ s CAS Latency 3 Bank A Write A Command active Auto Precharag DQ s og get i Begin Auto Precharge Bank can be reactivated after trp 7 2 Burst Read with Auto Precharge Burst Length 4 CAS latency 2 3 CLK Command CAS latency 2 m i tR CAS 3 SPT03721_2 Bank can be reactivated after trp INFINEON Technologies 27 HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 8 AC Parameters 8 1 AC Parameters for a Write Timing Burst Length 4 CAS Latency 2 T4 T5 Te T7 T12 T13 T14 T15 16 T17 18 T19 20 T22 CLK CKE Begin Autp
20. 9S256800CT 8 100 222 620 P TSOP 54 2 400mil 125MHz 4B x 8M x 8 SDRAM HYB 39S256800CT 8A 100 322 620 125 2 4 8 8 SDRAM 395256160 7 5 133 333 520 P TSOP 54 2 400mil 133MHz 4B x 4M x 16 SDRAM 395256160 8 100 222 620 P TSOP 54 2 400mil 125MHz 4B x 4M x 16 SDRAM 398256160CT 8A PC100 322 620 P TSOP 54 2 400mil 125MHz 4B x 4M x 16 SDRAM HYB39S256xx0CTL PC100 xxx 620 P TSOP 54 2 400mil P TSOP 54 2 400mil Low Power Versions on request Pin Description and Pinouts CLK Clock Input DQ Data Input Output CKE Clock Enable DQM LDQM UDQM Data Mask cs Chip Select Vdd Power 3 3V RAS Row Address Strobe Vss Ground CAS Column Address Strobe Vddq Power for DQ s 3 3V WE Write Enable Vssq Ground for DQ s 0 12 Address Inputs NC not connected Bank Select INFINEON Technologies 8 00 Infineon HYB39S256400 800 160CT L 256MBit Synchronous DRAM 16 16 DQO pai 002 004 005 006 LDQM WE CAS RAS CS BAO BA1 A10 AP AO A1 A2 A3 32 8 Von DQO Vopa N C 001 Vsso N C 002 003 Vsso Von CAS RAS Cs BAO A10 AP 2
21. HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM 256 MBit Synchronous DRAM High Performance Multiple Burst Read with Single Write pm Operation 75 9 is Automatic and Controlled Precharge CK E EZ Eea MH Command Data Mask for Read Wri x4 x8 75 8 8 Data Mask for Rea rite control x4 x8 54 e Data Mask for byte control x16 225 Auto Refresh CBR and Self Refresh tCK2 10 10 12 n EGENEAXEJN Power Down and Clock Suspend Mode ejeje ns tAG2 8192 refresh cycles 64 ms 7 8 us Random Column Address every CLK 1 N Rule e Single 3 3V 0 3V Power Supply e Fully Synchronous to Positive Clock Edge Oto 70 operating temperature Four Banks controlled by BAO amp BA1 De ineat E Programmable CAS Latency 2 amp e Plastic Packages e Programmable Wrap Sequence Sequential P TSOPII 54 400mil width x4 x8 x16 Interl 7 5 parts for PC133 3 3 3 operation Programmable Burst Length 8 parts for PC100 2 2 2 operation 1 2 4 8 8A parts for 100 3 2 2 operation Full page burst length optional for sequential wrap around The HYB39S256400 800 160CT L are four bank Synchronous DRAM s organized as 4 banks 16MBit x4 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architec
22. L X X X X X X X Data Write Output Disable Active H X H X X X X X X X Notes 1 V Valid x Don t Care L Low Level High Level 2 CKEn signal is input level when commands are provided CKEn 1 signal is input level one clock before the commands are provided 3 This is the state of the banks designated by signals 4 Power Down Mode can t be entered in a burst cycle When this command assert in the burst mode cycle device is clock suspend mode INFINEON Technologies 9 8 00 HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM Selen Tar AY Y Y Y v EY vy Operation Mode CAS CAS Latency Burst Burst Length Mode Register Mx Operation Mode Mode Burst Type Type burst burst write burst read single write 0 Sequential Burst Length Length 2 1 GE CAS Latency Reserved Reserved Reserved Reserved Reserved optional feature on this device INFINEON Technologies 10 8 00 HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM Power and Initialization The default power on state of the mode register is supplier specific and may be undefined The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs Like a conventional DRAM the Synchronous DRAM must
23. a out to apply the precharge command INFINEON Technologies 13 8 00 HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM Bank Selection by Address Bits all Banks Burst Termination Once a burst read or write operation has been initiated there are several methods in which to terminate the burst operation prematurely These methods include using another Read or Write Command to interrupt an existing burst operation use a Precharge Command to interrupt a burst cycle and close the active bank or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention The Burst Stop Command however has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed If a Burst Stop command is issued during a burst write operation then any residual data from the burst write cycle will be ignored Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory INFINEON Technologies 14 8 00 HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM Absolute Maximum Ratings Operating temperature range 0 to 70 Storage temperature ANGE 5
24. arge command cycle A10 2 AP is used in conjunction with BAO and to control which bank s to precharge If A10 is high all four banks will be precharged regardless of the state of and If A10 is low then are used to define which bank to precharge BA1 Input Level Bank Select Inputs Bank address inputs selects which of the four banks a command applies to DQx Input Output Level Data Input Output pins operate in the same manner as on conventional DRAMs INFINEON Technologies 7 8 00 Infineon HYB39S256400 800 160CT L 256MBit Synchronous DRAM Pin Type Signal Polarity Function DQM Input Pulse Active The Data Input Output mask places the DQ buffers in a LDQM High high impedance state when sampled high In Read mode UDQM DQM has a latency of two clock cycles and controls the output buffers like an output enable In Write mode DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high One DQM input it present in x4 and x8 SDRAMs LDQM and UDQM controls the lower and upper bytes in x16 SDRAMs Power ground for the input buffers core logic Vss Isolated power supply and ground for the output buffers to provide improved noise immunity
25. be powered up and initialized in a predefined manner During power on all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the state The power on voltage must not exceed VDD 0 3V on any of the input pins VDD supplies The CLK signal must be started at the same time After power on an initial pause of 200 us is required followed by a precharge of all banks using the precharge command To prevent data contention on the DQ bus during power on it is required that the DQM and CKE pins be held high during the initial pause period Once all banks have been precharged the Mode Register Set Command must be issued to initialize the Mode Register A minimum of eight Auto Refresh cycles CBR are also required These may be done before or after programming the Mode Register Failure to follow these steps may lead to unpredictable start up modes Programming the Mode Register The Mode register designates the operation mode at the read or write cycle This register is divided into 4 fields A Burst Length Field to set the length of the burst an Addressing Selection bit to program the column access sequence in a burst cycle interleaved or sequential a CAS Latency Field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation Burst read and burst Write and a special Burst Read and Single Write mode The mode set operation must be done
26. ion and 0 pF load 8 The write recovery time twr 2 CLK cycles is a digital interlock on this device Special devices with twr 1 CLK for operations at less or equal 83 MHz will be available INFINEON Technologies 19 8 00 HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM Package Outlines Plastic Package P TSOPII 54 400 mil 0 8 mm lead pitch Thin Small Outline Package SMD 10 16 0 13 015 54x 11 76 0 2 54x 54 28 d 1 2 5 27 1 22 22 0 13 GPX09039 Index Marking 1 Does not include plastic or metal protrusion of 0 15 max per side 2 Does not include plastic protrusion of 0 25 max per side 3 Does not include dambar protrusion of 0 13 max per side INFINEON Technologies 20 8 00 Infineon 1 5 Bank Activate Command Cycle Burst Read Operation Read Interrupted by a Read Read to Write Interval 4 1 Read to Write Interval 4 2 Minimum Read to Write Interval 4 3 Non Minimum Read to Write Interval 5 Burst Write Operation 6 Write and Read Interrupt 9 10 11 12 13 14 15 16 17 18 19 6 1 Write Interrupted Write 6 2 Write Interrupted Read Burst Write amp Read with Auto Precharge 7 1 Burst Write with Auto Precharge 7 2 Burst Read w
27. ite Burst Command Command Precharge Termination Write Data is masked Bank A Bank A of a Read Burst SPT03933 INFINEON Technologies 47 HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM INFINEON Technologies 48 HYB39S256400 800 160CT L 256MBit Synchronous DRAM Infineon Change List Clock Suspend Mode not supported anymore Dr Savignac Changes on pages 1 8 amp 15 Waveforms chapters 11 amp 12 deleted and renumbered 3 12 99 some PC133 parameters changed according to INTELs PC133 specification 27 1 2000 Some ICC currents changed after measurement of first lots UU Datasheet changed from Target to Preliminary 11 4 2000 confusion note 4 on page 8 removed burst stop is supported for BL 22 4 amp 8 Full page burst is functional beginning with designstep DD3A 14 4 2000 Implemented into the datasheet as optional untested feature Mail from Ralf Schneider April 12 00 Power Down Exit with one clock beginning with DD3D designstep Clock suspend mode functional with DD3D designstep Clock suspend mode is added in the datasheet and the waveform drawings again 25 4 2000 Tras interlock changed to 4 clocks twr 2 Clock on this design version Note for availability of components with twr 1 clock interlock Preliminary datasheet changed to final Change request from Mr L ken Text change on page 16 for clarification page 17 mode register set up time renamed to Mode Register set to Ac
28. ith Auto Precharge AC Parameters 8 1 AC Parameters for a Write Timing 8 2 AC Parameters for a Read Timing Mode Register Set Power on Seguence and Auto Refresh CBR Clock Suspension using CKE HYB39S256400 800 160CT L 256 MBit Synchronous DRAM 11 1 Clock Suspension During Burst Read CAS Latency 2 11 2 Clock Suspension During Burst Read CAS Latency 3 11 3 Clock Suspension During Burst Write CAS Latency 2 11 4 Clock Suspension During Burst Write CAS Latency 3 Power Down Mode and Clock Suspend Self Refresh Entry and Exit Auto Refresh CBR Random Column Read Page within same Bank 15 1 CAS Latency 2 15 2 CAS Latency 3 Random Column Write Page within same Bank 16 1 CAS Latency 2 16 2 CAS Latency 3 Random Row Read Interleaving Banks with Precharge 17 1 CAS Latency 2 17 2 CAS Latency 3 Random Row Write Interleaving Banks with Precharge 18 1 CAS Latency 2 18 2 CAS Latency 3 Precharge Termination of a Burst INFINEON Technologies 21 v Infineon 1 Bank Activate Command Cycle HYB39S256400 800 160CT L 256 MBit Synchronous DRAM CAS latency 3 T0 T Row Addr Address B Col Addr I lgcp T a Command 4 pane pom mm mm mm T T Bank A Row Addr n ME Joen Bank A tro H H or T Bank Row Addr Bank Activate SPT03784 2
29. lied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence For example in a burst length of 8 with interleave sequence if the first address is 2 then the rest of the burst sequence is 3 0 1 6 7 4 and 5 Full page burst operation is only possible using sequential burst type and page length is a function of the I O organisation and column addressing Full page burst operation do nor self terminate once the burst length has been reached In other words unlike burst length of 2 4 or 8 full page burst INFINEON Technologies 11 8 00 HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM continues until it is terminated using other commands Full page operation is an optional feature on this device which is built in by design but not tested on every component Similar to the page mode of conventional DRAM s burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers The maximum tras or the refresh interval time limits the number of random column accesses new burst access can be done even before the previous burst ends The interrupt operation at every clock cycle is supported When the previous burst is interrupted the remaining addresses are overridden by the new address with the full burst length An interrupt which accompanies an operation change from a read to a write is possible by exploiti
30. lues are measured 133 operation freguency for 7 5 devices at 100 MHz for 8 8A devices Input signals are changed once during tck 4 These parameters are measured with continuous data stream during read access and all DQ toggling CL 3 and BL 4 is assumed and the VDDQ current is excluded INFINEON Technologies 16 8 00 HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM AC Characteristics 1 2 010 70 Vas 0 Vdd 3 3 V 0 3 1 1 ns Parameter Symbol Limit Values Unit 7 5 8 8A PC133 PC100 PC100 333 222 322 min Clock Clock Enable Clock Cycle Time CAS 3 ty 7 5 8 8 ns CAS Latency 2 10 10 12 Clock Frequency CAS Latency 3 133 125 125 2 CAS Latency 2 100 100 83 MHz Access Time from Clock CAS Latency 3 tac 54 6 6 ns 2 CAS Latency 2 6 6 6 ns Clock High Pulse Width 2 5 3 3 Ins Clock Low Pulse Width toL 2 5 3 3 Ins Transition time ty 0 3 1 2 0 5 10 0 5 10 ns Setup and Hold Times Input Setup Time tis 1 5 2 2 ns 4 Input Hold Time 0 8 1 1 4 Time toks 1 5 2 2 ins 4 Hold Time 0 8 1 1 ns 4 Mode Register
31. mmand latency 2 DIN AO DIN A1 H DIN A2 H DIN toxe DOS Or SPT03939 4 3 Non Minimum Read to Write Interval Burst Length 4 CAS latency 2 3 CLK DQM Command CAS latency 2 DQ s CAS latency lei DQ s TO Ti T2 T3 T4 T5 T6 T7 T8 seh DOW Ly _ oe Must be Hi Z before the Write Command Gara or N B1 DIN B2 SPT03940 INFINEON Technologies Jm HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 5 Burst Write Operation Burst Length 4 CAS latency 2 3 TO Ti T2 13 T5 T6 T7 T8 DQ s The first data element and the Write Extra data is ignored after are registered on the same clock edge termination of a Burst SPT03790 INFINEON Technologies 25 v Infineon 6 Write and Read Interrupt 6 1 Write Interrupted by a Write HYB39S256400 800 160CT L 256 MBit Synchronous DRAM Burst Length 4 CAS latency 2 3 1 2 T3 CLK 1 Clk Interval a DQ s T4 T5 T6 T7 T8 SPT03791 6 2 Write Interrupted by a Read Burst Length 4 CAS latency 2 3 TO 1 2 T3 CLK Command CAS latency 2 DIN 0 DOS CAS toxg DOS Input data for the Write is ignored T4 T5 T6 T7 T
32. ng DQM to avoid bus contention When two or more banks are activated sequentially interleaved bank read or write operations are possible With the programmed burst length alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages Once two or more banks are activated column to column interleave operation can be performed between different pages Burst Length and Sequence Burst Starting Address Sequential Burst Addressing Interleave Burst Addressing Length A2 A1 decimal decimal 2 xx0 0 1 xx1 1 0 4 00 0 1 2 3 01 1 0 3 2 10 2 3 0 1 x11 3 2 1 0 8 012 3 4 5 6 7 10325476 23016745 321076654 45670123 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 Full not supported optional Refresh Mode SDRAM has two refresh modes Auto Refresh and Self Refresh Auto Refresh is similar to the CAS before RAS refresh of conventional DRAMs All banks must be precharged before applying any refresh mode An on chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes The chip enters the Auto Refresh mode when RAS and CAS are held low and CKE and WE are held high at a clock timing The mode restores word line after the refresh and no external precharge command is necessary A minimum tRC time is required between two automatic INFINEON Technologies 12 8 00 HYB39S256400 800
33. nous DRAM Notes for AC Parameters 1 For proper power up see the operation section of this data sheet 2 AC timing tests have 0 4 and 2 4 V with the timing referenced to the 1 4 V crossover point The transition time is meas ured between and All AC measurements assume 1 with the AC output load circuit shown in fig 1 Specified tac and toh parameters are measured with a 50 pF only without any resistive termination and with a input signal of 1V ns edge rate between 0 8V and 2 0 V 50 pF 5 505140 50 Measurement conditions for tac and toh OUTPUT SPT03404 fig 1 If clock rising time is longer than 1 ns a time 572 0 5 ns has to be added to this parameter If tT is longer than 1 ns a time tz 1 ns has to be added to this parameter These parameter account for the number of clock cycle and depend on the operating frequency of the clock as follows the number of clock cycle specified value of timing period counted in fractions as a whole number 6 Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered 7 Access time from clock tac is 4 6 ns for PC133 components with no termination and 0 pF load Data out hold time toh is 1 8 ns for PC133 components with no terminat
34. ode Once the Power Down mode is initiated by holding CKE low all of the receiver circuits except CLK and CKE are gated off The Power Down mode does not perform any refresh operations therefore the device can t remain in Power Down mode longer than the Refresh period tref of the device Exit from this mode is performed by taking CKE One clock delay is required for power down mode entry and and exit Auto Precharge Two methods are available to precharge SDRAMs In an automatic precharge mode the CAS timing accepts one extra address CA10 to determine whether the chip restores or not after the operation If CA10 is high when a Read Command is issued the Read with Auto Precharge function is initiated If CA10 is high when a Write Command is issued the Write with Auto Precharge function is initiated The SDRAM automatically enters the precharge operation a time delay equal to twr write recovery time after the last data in Precharge Command There is also a separate precharge command available When RAS and WE are low and CAS is high at a clock timing it triggers the precharge operation Three address bits BAO BA1 and A10 are used to define banks as shown in the following list The precharge command can be imposed one clock before the last data out for CAS latency 2 and two clocks before the last data out for CAS latency Writes require a time delay twr write recovery time of 2 clocks minimum from the last dat
35. ode Entry Mode Exit SPT03918 INFINEON Technologies 36 HYB39S256400 800 160CT L 256 MBit Synchronous DRAM 13 Self Refresh Entry and Exit TO T1 T2 T3 T4 5 6 T7 18 9 T10 11 12 13 14 15 16 17 118 119 T20 T21 122 CLK CKE y f tas tos gt a cs ri 1 os vc 0 RES ete 4 0 t La tac DOM 4 Hi Z DQ hae 20 060 Sg A A A A A All Banks Self Refresh Begin Self Refresh Any must be idle Entry Exit Command Command Self Refresh Exit Self Refresh Command issued Exit 4 minimum RAS cycle time depends on CAS 5 103919 2 Latency and INFINEON Technologies 37 HYB39S256400 800 160CT L Infineon 256 MBit Synchronous DRAM 14 Auto Refresh CBR Burst Length 4 CAS Latency 2 71 2 74 5 T7 T8 T9 10 T11 12 113 14 15 16 17 18 19 20 21 T22 CLK CKE ig Minimum Interval DQM Hi Z
36. t capacitance 2 5 3 5 Input 2 5 3 8 A0 A12 BAO BA1 RAS CAS WE CS DQM Input Output capacitance DQ Cio 4 0 6 0 pF INFINEON Technologies 15 8 00 HYB39S256400 800 160CT L Infineon 256MBit Synchronous DRAM Operating Currents 0 to 70 C Vdd 3 3V 0 3V Recommended Operating Conditions unless otherwise noted Parameter amp Test Condition Symb 7 5 8 8A Note max max OPERATING CURRENT ICC 230 170 tck tckmin All banks operated in random access 3 4 all banks operated in ping pong manner PRECHARGE STANDBY CURRENT in tck min 2 2 2 3 Power Down Mode CS lt PRECHARGE STANDBY CURRENT tck min ICC2N 40 30 mA 3 Non Power Down Mode CS min CKE gt Vih min NO OPERATING CURRENT CKE VIH min ICC3N 50 45 3 tck min CS VIH min active state 4 banks CKE lt VIL max ICC3P 10 10 BURST OPERATING CURRENT 4 150 100 tck min 3 4 Read command cycling AUTO REFRESH CURRENT 5 240 220 3 tck min tre tremin Auto Refresh command cycling SELF REFRESH CURRENT standard version ICC6 3 3 mA Self Refresh Mode CKE 0 2V tck infinity L version 1 7 1 7 Notes 3 These parameters depend the cycle rate All va
37. tive 28 6 2000 delay Waveform Drawing changed from SPT03910 to 03910 2 Waveform Drawing changed from SPT03923 to 5 923 2 Waveform Drawing changed from SPT03925 to 5 925 2 Waveform Drawing changed from SPT03927 to 03927 2 Last minute changes requested by Mr L ken 20 7 2000 page 16 note 4 for ICC1 a Waveform Drawing changed from SPT03911 to SPTO3911 2 Waveform Drawing SPT03925 2 trp arrow corrected 8 8 2000 ICC6 for Low Power Versions changed from 1 5 to 1 7 mA ni Discussion with Hahn and L ken INFINEON Technologies 21 8 00
38. ture that prefetches multiple bits and then synchronizes the output data to a system clock The chip is fabricated with INFINEON s advanced 0 17 um 256MBit DRAM process technology The device is designed to comply with all industry standards set for synchronous DRAM products both electrically and mechanically All of the control address data input and output circuits are synchronized with the positive edge of an externally supplied clock Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs A sequential and gapless data rate is possible depending on burst length CAS latency and speed grade of the device Auto Refresh CBR and Self Refresh operation are supported These devices operates with a single 3 3V 0 3 power supply and are available in packages INFINEON Technologies 1 8 00 Infineon HYB39S256400 800 160CT L 256MBit Synchronous DRAM Ordering Information Type Speed Grade Package Description 39S256400CT 7 5 133 333 520 P TSOP 54 2 400mil 133MHz 4B x 16M x 4 SDRAM 395256400 8 PC100 222 620 P TSOP 54 2 400mil 125MHz 4B x 16M x 4 SDRAM HYB 395256400 PC100 322 620 P TSOP 54 2 400mil 125MHz 4B x 16M x 4 SDRAM 395256800 7 5 133 333 520 P TSOP 54 2 400mil 133MHz 48 x 8M 8 SDRAM 3

Infineon HYB39S256400CT-7.5 memory module

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