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Elixir M2U25664DS88B3G-5T memory module

1. Byte Description DDR400 DDR333 DDR266 5T 6K 75B SPD Value hexadecimal SPD Value hexadecimal SPD Value hexadecimal 0 Number of Serial PD Bytes Written during Production 128 80 128 80 128 80 1 Total Number of Bytes in Serial PD device 256 08 256 08 256 08 2 Fundamental Memory Type DDR SDRAM 07 DDR SDRAM 07 DDR SDRAM 07 3 Number of Row Addresses on Assembly 13 0 13 0 13 0 4 Number of Column Addresses Assembly 10 0A 10 0A 10 0A 3 Number of DIMM Bank 1 01 1 01 1 01 6 Data Width of Assembly X64 40 X64 40 X64 40 7 Data Width of Assembly X64 00 X64 00 X64 00 8 Voltage Interface Level of this Assembly SSTL 2 5V 04 SSTL 2 5V 04 SSTL 2 5V 04 9 DDR SDRAM Device Cycle Time at CL 3 Sns 50 6ns 60 7 5ns 75 10 DDR SDRAM Device Access Time from Clock at CL 3 0 6ns 60 0 7ns 70 0 75ns 75 11 DIMM Configuration Type Non Parity 00 Non Parity 00 Non Parity 00 12 Refresh Rate Type SR 1x 7 8us 82 SR 1x 7 8us 82 SR 1x 7 8us 82 Self Refresh Flag Self Refresh Flag Self Refresh Flag 13 Primary DDR SDRAM Width X8 08 X8 08 X8 08 14 Error Checking DDR SDRAM Device Width N A 00 N A 00 N A 00 15 DDR SDRAM Device Attr Min CIk Delay Random Col 1 Clock 01 1 Clock 01 1 Clock 01 Access 16 DDR SDRAM Device Attributes Burst Length Supported 2 4 8 2 4 8 2 4 8 17 DDR SDRAM Device Attributes Number of Device Banks 4 04
2. Active Standby Current one bank active precharge CS gt Vin gt tac tras tex tck mny DQ DM and DQS inputs changing twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank Burst 2 reads continuous burst address and control inputs changing once per clock cycle DQ and DQS outputs changing twice per clock cycle CL 2 5 uw lour OMA Operating Current one bank Burst 7 2 writes continuous burst address and control inputs changing once per clock cycle DQ and DQS inputs changing twice per clock cycle CL 2 5 Auto Refresh Current tac terc uiv Self Refresh Current CKE lt 0 2V Operating Current four bank four bank interleaving with BL 4 address and control inputs randomly changing 50 of data changing at every transfer tac tre min lour OMA 1 IDD specifications are tested after the device is properly initialized 2 Input slew rate 1V ns 3 Current at 7 8 is time averaged value of IDD5 at and IDD2P over 7 8 us All IDD current values are calculated from device level REV 2 2 14 Aug 3 2004 Preliminary Celixir Notes 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 3 1 2 1 2 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2U51264DS8HB3G M2U25664DS88B
3. C 2 C 1 27 0 10 Detail A Detail B 0 050 0 004 k 8 1 00 Width ee gt 0 039 LU 000 qe ee 0 05 1 80 0 071 Note All dimensions are typical with tolerances of 0 15 0 006 unless otherwise stated Units Millimeters Inches REV 2 2 19 Aug 3 2004 NANYA the right t B NANYA TECHNOLOGY CORPORATION H reserves the change products and specifications without notice Preliminary nd M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB Cal zx PC3200 PC2700 and PC2100 el Unbuffered DDR DIMM Package Dimensions Non ECC 8 TSOP devices FRONT P 133 35 5 250 128 93 5 076 4 S X amp 5 8 C elg 25 cd 4 ele 0 RE R Pit e B 82 50 Pad z eo 0 098 Detail A Detail B Side BACK T cS DOLIO 1 27 0 10 Detail A Detail B 0 050 0 004 lt 38 8 E 1 00 Width soe 0 039 1000000 000 00000 635 0250 1 27 Pitch 0 05 1 80 0 071 Note All dimensions are typical with tolerances of 0 15 0 006 unless otherwise stated Units Millimeters Inches REV 2 2 20 ii 3 2004 NANYA the right t S TECHNOLOGY CORTO RATION 4 reserves the io change products and specifications without notice Preliminary 9 ge p M2U51
4. N 02 05 Clock Input ahs CKO CKO 4 SDRAMs gt 00 015 CK1 CK1 6 SDRAMs 00 015 CK2 CK2 6 SDRAMs Strap see Note 4 Serial PD lt gt SDA 1 50 DQSO DMO DQS9 M DM CS DQS DM CS DQS DQO 107 1 00 N 106 1 DQ2 101 1 0 6 N 00 08 DQ4 M 105 2 DQ5 N 104 yo N 103 1 0 4 DQ7 N O2 I 05 DQS1 DM1 DQS10 A DM CS DQS DM CS DQs DQ8 1 07 1 0 0 M 06 01 DQ10 AN 1 y o 6 DQ11 D1 09 DQ12 05 2 DQ13 M 4 3 DQ14 N 03 4 DQ15 02 5 0992 DM2 DQS11 M DM CS DQS DM CS 00 00916 N 107 1 0 0 DQ17 N 06 1 DQ18 01 1 0 6 DQ19 100 D2 010 DQ20 M 5 y o 2 0021 N 104 3 DQ22 M 4 DQ23 N 102 5 DQS3 DM3 DQS12 DM cS 00 DM CS DQS DQ24 N 1 07 DQ25 M 1 0 6 1 DQ26 N 4 VO 1 1 0 6 DQ27 N 0 53 0028 N 105 VO2 DQ29 104 DQ30 N 103 4 4 DQ31 N 02 1 05 BA0 BA1 N M BA0 BA1 SDRAMs D0 D15 Vopsep AO A13 gt A0 A13 SDRAMs 00 015 Voo Vppa V RAS M RAS SDRAMs 00 015 va SS CAS N CAS SDRAMs 00 015 Vibio CKEO CKE SDRAMs D0 D7 CKE1 SDRAMs 08 015 WE WE S
5. 11 DQ38 A 11 M 109 DQ39 M 109 TS cs DQS3 LDQS DQS7 LDQS DM3 DQS12 A LDM DM7 DQS16 LDM DQ24 M 1 0 6 DQ56 M 6 DQ25 104 00957 104 0926 JM 1 0 1 DQ58 M 1 DQ27 N 103 DQ59 N 103 DQ28 VO2 M VO2 009029 N 00 0061 N 00 0030 05 0062 05 0031 VO7 DQ63 M VO7 D1 D3 DQS2 UDQS DQS6 UDQS DM2 DQS11 UDM DM6 DQS15 UDM DQ16 JM 8 DQ48 M 1 0 8 DQ17 M 1010 DQ49 A 4 010 pais JA V0 15 DQ50 N 4 15 DQ19 JA 013 DQ51 M 013 DQ20 JA 10 12 DQ52 N 4 10 12 DQ21 14 DQ53 A 10 14 DQ22 M VO 11 DQ54 N 4 VO 11 DQ23 N 09 DQ55 N 09 BAO BA1 JAN J BAO BA1 SDRAMs 00 03 AO A13 A0 A13 SDRAMs DO D3 Clock Wind KMS BAS BAS CKO CKO NC RAS N RAS SDRAMs 00 03 CKIKI 2 SDRAMs CAS N CAS SDRAMs 00 03 CK2 CK2 2 SDRAMs CKEO NS CKE SDRAMs 00 03 Wire per Clock Loading Table Wiring Diagrams WE WE SDRAMs D0 D3 Vopsep gt SPD do Serial PD 20 03 gt 6 SDA REE lt 00 03 WP gt ao A1 A2 Vis D0 D3 7 sho sh sho Vooo Strap see Note 4 Notes 1 DQ to I O wiring is shown as recommended but may be changed 2 DQ DQS DM CKE S relationships must be maintai
6. 106 DQ41 N 106 DQ10 N VO 1 DQ42 N VO 1 DQ11 D1 DQ43 M D5 DQ12 05 DQ44 N 05 DQ13 1 0 4 DQ45 M 4 DQ14 AN 103 DQ46 N 4 DQ15 N 02 DQ47 N 02 2 pase DM2 DQS11 DM6 DQS15 DM cs 00 DM CS 09 DQ16 N 107 0048 N 107 0017 N 06 0049 N 6 0918 1 DQ50 1 0019 A 100 02 DQ51 00 06 0020 1 05 DQ52 5 0921 104 0053 N 04 0922 M 03 DQ54 DQ23 N 102 00955 N 2 DQS3 DQS7 M DM3 DQS12 N 4 DM7 DQS16 WwW DM CS 00 DM CS 005 DQ24 107 DQ56 N 107 DQ25 N 6 DQ57 N 6 DQ26 N 01 DQ58 1 01 DQ27 N 0 D3 DQ59 0 D7 DQ28 N 05 N 05 DQ29 N 04 DQ61 N 104 DQ30 03 DQ62 N 103 DQ31 N 02 DQ63 N 102 BAO BA1 A JM BAO BA1 SDRAMs 00 07 Clock Wi AO A13 gt A0 A13 SDRAMs 00 07 Clock put BAS BAS f 2 SDRAMs RAS N RAS SDRAMs D0 D7 3 SDRAMs CAS N CAS SDRAMs D0 D7 CK2 CK2 3 SDRAMs CKEO M CKE SDRAMs 00 07 Wire per Clock Loading Table Wiring Diagrams WE N WE SDRAMs D0 D7 V e gt SPD 2 DDSPD Serial PD 00 07 gt le gt spa Ver F e 00 07 A0 22 Vas D0 D7
7. 146 0036 85 Voo 177 DM7 DQS16 25 DQS2 117 0921 55 0033 147 0037 86 DQS7 178 DQ62 26 Vss 118 A11 56 DQS4 148 87 0058 179 0063 27 A9 119 DM2 DQS11 57 0034 149 DM4 DQS13 88 0059 180 28 0018 120 58 Vss 150 DQ38 89 Vss 181 SAO 29 A7 121 DQ22 59 BAO 151 0039 90 WP 182 SA1 30 122 A8 60 0935 152 Vss 91 SDA 183 SA2 31 0919 123 DQ23 61 0040 153 DQ44 92 SCL 184 Vppsep Note All f 8 REV 2 2 3 Aug 3 2004 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice Preliminary M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB PC3200 PC2700 and PC2100 Unbuffered DDR DIMM Celixir Input Output Functional Description Symbol CKO CK1 CK2 KO CK1 CK2 CKEO CKE1 1 A9 A10 AP A11 A12 DQO DQ63 DQSO DQS7 DQS9 00516 CBO CB7 DMO DM8 Vpp Vss SAO SA2 SDA SCL Vopspp REV 2 2 Aug 3 2004 Preliminary Type SSTL SSTL SSTL SSTL Supply Supply SSTL SSTL SSTL SSTL SSTL Input Supply Supply Polarity Cross point Active High Active Low Active Low Active High Active High Function The system clock inputs All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK A Delay Locked Loop DLL circuit is driven from the cloc
8. 4 04 4 04 18 DDR SDRAM Device Attributes CAS Latencies Supported 2 2 5 3 212 5 0 2 2 5 0 19 DDR SDRAM Device Attributes CS Latency 0 01 0 01 0 01 20 DDR SDRAM Device Attributes WE Latency 1 02 1 02 1 02 21 DDR SDRAM Device Attributes Differential Clock 20 Differential Clock 20 Differential Clock 20 22 DDR SDRAM Device Attributes General 0 2V Voltage 00 0 2V Voltage 00 0 2V Voltage 00 Tolerance Tolerance Tolerance 23 Minimum Clock Cycle at CL 2 5 6 0ns 60 7 5ns 75 10ns AO 24 Maximum Data Access Time tac from Clock at CL 2 5 0 7ns 70 0 70ns 70 0 75ns 75 25 Minimum Clock Cycle Time at CL 2 7 5ns 75 N A 00 N A 00 26 Maximum Data Access Time tac from Clock at CL 2 7 5ns 75 N A 00 N A 00 27 Minimum Row Precharge Time tgp 15ns 3C 18ns 48 20ns 50 28 Minimum Row Active to Row Active delay tarp 10ns 28 12ns 30 15ns 3C 29 Minimum RAS to CAS delay tgcp 15ns 3C 18ns 48 20ns 50 30 Minimum RAS Pulse Width tras 40ns 28 42ns 2A 45ns 2D 3 Module Bank Density 256MB 40 256MB 40 256MB 40 32 Address and Command Setup Time Before Clock 0 6ns 60 0 75ns 75 0 9ns 90 33 Address and Command Hold Time After Clock 0 6ns 60 0 75ns 75 0 915 90 34 Data Input Setup Time Before Clock 0 4ns 40 0 45ns 45 0 5ns 50 35 Data Input Hold Time After Clock 0 4ns 40 0 45ns 45 0 5ns 50 36 40 Reserved Undefined 00 Undefined 00 Undefined 00 4 Minimum Active Auto Refresh Time tRC 55ns 37 60ns 3C 65ns 41 42 SDRAM Device Minimum Auto Refresh to Active Auto 70ns 4
9. and DM input hold time tos DQ and DM input setup time toipw DQ and DM input pulse width each input tuz Data out high impedance time from CK CK tiz Data out low impedance time from CK CK DQS DQ skew DQS amp associated signals t Minimum half clk period for any given cycle Hd defined by clk high tc or clk low tc time tou Data output hold time from DOS tous Data hold Skew Factor toass Write command to ist DQS latching transition tros DQS input low high pulse width 1 write cycle DQS falling edge to CK setup time toss write cycle DQS falling edge hold time from CK tos write cycle Mode register set command cycle time tweres Write preamble setup time twest Write postamble twere Write preamble Address and control input hold time fast slew rate Address and control input setup time lis fast slew rate t Address and control input hold time n slow slew rate REV 2 2 Aug 3 2004 Preliminary 5T PC3200 Min Max 0 65 0 65 0 55 0 55 0 45 0 55 0 45 0 55 5 8 6 12 0 4 0 4 1 75 0 6 0 6 0 6 0 6 0 4 tcu or tet tup tous 0 5 0 75 1 25 0 35 0 2 0 2 2 0 0 40 0 60 0 25 0 6 0 6 0 7 16 6K PC2700 Min Max 0 7 0 7 0 7 0 7 0 45 0 55 0 45 0 55 6 12 7 5 12 0 45 0 45 1 75 0 7 0 7 0 7 0 7 0 45 tcu or tet lup tous 0 55 0 75 1 25 0 35 0 2 0 2 2 0 0 40 0 60 0 25 0 75 0 75 0 8 Celixir 75B PC2100 Min Max 0 75 0 75 0
10. equal to the actual system clock cycle time For example for PC2100 at 2 5 toa 15ns 7 5ns 20ns 7 0ns 2 3 5 14 An input setup and hold time derating table is used to increase tis and in the case where the input slew rate is below 0 5 V ns Input Slew Rate Delta tis Delta ti Unit Note 0 5 V ns 0 0 ps 1 2 0 4 V ns 50 0 ps 1 2 0 3 V ns 100 0 ps 1 2 1 Input slew rate is based on the lesser of the slew rates determined by either Vin ac to Vit acy Or po tO Vit oc similarly for rising transitions 2 These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device 15 An input setup and hold time derating table is used to increase tps and tpp in the case where the I O slew rate is below 0 5 V ns Input Slew Rate Delta tps Delta tox Unit Note 0 5 V ns 0 0 ps 1 2 0 4 V ns 75 75 ps 1 2 0 3 V ns 150 150 ps 1 2 1 slew rate is based on the lesser of the slew rates determined by either Viu ac to Vit acy OF Vin tO Vi Similarly for rising transitions 2 These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device 16 An I O Delta Rise Fall Derating table is used to increase tps and tpp in the case where DQ DM and DQS slew rates differ Delta Rise and Fall Rate Delta tps Delta tpi Unit Note 0 0 ns V 0 0 ps 1 4 0 25 ns V 50 50 ps 1
11. or indirectly arising from any claim of loss injury or death associated with unintended or unauthorized use even if such claims alleges Nanya was negligent regarding design or manufacture of the part Nanya and the Nanya logo are trademarks of the Nanya Technology Corporation Printed in Taiwan 2004 REV 2 2 22 Dg 3 2004 NANYA the right t S TECHNOLOGY CORTO RATION T A reserves the ri io change products and specifications without notice Preliminary 9 ge p
12. period Active to Read or Write delay 15 18 20 ns 1 4 trap Active to Read Command with Auto precharge 15 18 20 ns 1 4 trp Precharge command period 15 18 20 ns 1 4 1 Active bank A to Active bank B command 10 12 15 ns 1 4 twr Write recovery time 15 15 15 ns 1 4 twr twr twe tck toat Auto precharge write recovery precharge time tre tee tee tck 1 4 13 twtr Internal write to read command delay 1 1 1 1 4 tppex Power down exit time 5 6 7 5 ns 1 4 txsnr Exit self refresh to non read command 75 75 75 ns 1 4 txsrp Exit self refresh to read command 200 200 200 1 4 Average Periodic Refresh Interval 7 8 7 8 7 8 us 1 4 8 REV 2 2 17 Aug 3 2004 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice Preliminary M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB Cal PC3200 PC2700 and PC2100 elixir Unbuffered DDR DIMM AC Timing Specification Notes 1 Input slew rate 1V ns 2 The CK CK input reference level for timing reference to CK CK is the point at which CK and CK cross the input reference level for signals other than CK CK is Vner 3 Inputs are not recognized as valid until Vrer stabilizes 4 The Output timing reference level as measured at the timing reference point indicated in AC Characteristics Note 3 is Vr 5 taz and tz transitions occur in the same access ti
13. 0 PC2700 and PC2100 Unbuffered DDR DIMM SPD Values for M2U51264DS8HB3G Byte Description DDR400 DDR333 DDR266 5T 6K 75 SPD Value hexadecimal SPD Value hexadecimal SPD Value hexadecimal 0 Number of Serial PD Bytes Written during Production 128 80 128 80 128 80 1 Total Number of Bytes in Serial PD device 256 08 256 08 256 08 2 Fundamental Memory Type DDR SDRAM 07 DDR SDRAM 07 DDR SDRAM 07 3 Number of Row Addresses on Assembly 13 0 13 0 13 0 4 Number of Column Addresses on Assembly 10 0A 10 0A 10 0A 5 Number of DIMM Bank 2 02 2 02 2 02 6 Data Width of Assembly X64 40 X64 40 X64 40 7 Data Width of Assembly X64 00 X64 00 X64 00 8 Voltage Interface Level of this Assembly SSTL2 5V 04 SSTL 2 5V 04 SSTL 2 5V 04 9 DDR SDRAM Device Cycle Time at CL 3 Sns 50 6ns 60 7 5ns 75 10 DDR SDRAM Device Access Time from Clock at CL 3 0 6ns 60 0 7ns 70 0 75ns 75 11 DIMM Configuration Type Non Parity 00 Non Parity 00 Non Parity 00 12 Refresh Rate Type SR Ix 7 8us 82 SR Ix 7 8us 82 SR 1x 7 8us 82 Self Refresh Flag Self Refresh Flag Self Refresh Flag 13 Primary DDR SDRAM Width X8 08 X8 08 X8 08 14 Error Checking DDR SDRAM Device Width N A 00 N A 00 N A 00 15 DDR SDRAM Device Attr Min CIk Delay Random Col Clock 01 1 Clock 01 Clock 01 Access 16 DDR SDRAM Device Attributes Bu
14. 264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB Cal zx PC3200 PC2700 and PC2100 el Unbuffered DDR DIMM Package Dimensions Non ECC 4 TSOP devices FRONT P 133 35 5 250 128 93 5 076 4 S 5 Als 53 ME 4 ele 0 RE R PETA Psp e t 02 50 a P z eo 0 098 Detail A Detail B Side BACK T cS DOLIO 1 27 0 10 Detail A Detail B 0 050 0 004 lt 38 8 E 1 00 Width soe 0 039 1000000 000 00000 635 0250 1 27 Pitch 0 05 1 80 0 071 Note All dimensions are typical with tolerances of 0 15 0 006 unless otherwise stated Units Millimeters Inches REV 2 2 21 ii 3 2004 NANYA the right t S TECHNOLOGY CORTO RATION 4 reserves the io change products and specifications without notice Preliminary 9 ge p M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB EE PC3200 PC2700 and PC2100 el Unbuffered DDR DIMM Revision Log Rev Date Modification 0 1 12 2003 Updated format 1 0 Dec 19 2003 Release Correction to block diagram label 1 1 Feb 11 2004 Correction to SPD bank and checksum values Package dimension added for x8 wide devices Document reorganized by order of B die generation size and DIMM format 2 0 Mar 4 2004 DIMM unbuffered DIMM Speed grades 5T 6
15. 3G M2U12864DSH4B3G 512MB 256MB and 128MB Cal PC3200 2700 and PC2100 elixir Unbuffered DDR DIMM M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G Symbol PC3200 PC2700 PC2100 PC3200 PC2700 PC2100 PC3200 PC2700 PC2100 5T 6K 75B 5T 6K 75B 5T 6K 75B IDDO 1915 1755 1585 995 915 825 460 420 380 IDD1 1995 1995 1825 1035 1035 945 480 480 440 IDD2P 340 340 340 180 180 180 80 80 80 IDD2N 765 765 680 405 405 360 180 180 160 IDD3P 357 357 306 189 189 162 84 84 72 1275 1275 1105 675 675 585 300 300 260 10048 3275 3275 2705 1675 1675 1385 800 800 660 IDDAW 3195 3195 2625 1635 1635 1345 780 780 640 IDD5 3675 2875 2785 1875 1475 1425 900 700 680 1206 51 51 51 27 27 27 12 12 12 1007 5275 5275 4065 2675 2675 2065 1300 1300 1000 REV 2 2 15 Aug 3 2004 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice Preliminary M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB PC3200 PC2700 and PC2100 Unbuffered DDR DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module Ta 0 70 Vopa Vpp7 2 5V 0 2V PC2100 PC2700 Vppa7 Vpp7 2 6V 0 1V PC3200 Part 1 of 2 Symbol Parameter tac DQ output access time from CK CK toasck DQS output access time from CK CK CK high level width tot CK low level width Clock cycle time CL 3 tck Clock cycle time CL 2 5 tck Clock cycle time CL 2 ton DQ
16. 4 0 5 ns V 100 100 ps 1 4 1 Input slew rate is based on the lesser of the slew rates determined by either Vin ac to Vit acy Or tO Vit similarly for rising transitions 2 Input slew rate is based on the larger of AC to AC delta rise fall rate and DC to DC delta rise fall rate 3 delta rise fall rate is calculated as 1 slew rate 1 1 slew rate 2 For example slew rate 1 0 5 V ns slew rate 2 0 4 V ns Delta rise fall 1 0 5 1 0 4 ns V 0 5 ns V Using the table above this would result an increase in tps and tp of 100 ps 4 These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device REV 2 2 18 ii 3 2004 NANYA the right t S TECHNOLOGY CORTO RATION 4 reserves the ri change products and specifications without notice Preliminary 9 ge p M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB Cal zx PC3200 PC2700 and PC2100 el Unbuffered DDR DIMM Package Dimensions Non ECC 16 TSOP devices FRONT 133 35 5 250 4 128 93 hb 5 076 gt 2 28 D 4 n O hnonnnnnnnnnnnnfnnmnnnamnmnmmi i 0 098 Detail A Detail B NIS BACK Side 4 00 Ol TTT OO 0 157 MAX
17. 6 72ns 48 75ns 4B Refresh Command Period tRFC 43 SDRAM Device Maximum Cycle Time tCK max 8 20 12 30 12 30 44 SDRAM Device Maximum DQS DQ Skew Time tDQSQ 0 4 28 0 4 28 0 5 32 45 SDRAM Device Maximum Read Data Hold Skew Factor 0 5 50 0 55 55 0 75 75 tQHS 46 Superset Information may be used in future Undefined 00 Undefined 00 Undefined 00 47 SDRAM device Attributes DDR SDRAM DIMM Height 31 75mm 01 31 75mm 01 31 75mm 01 48 61 Superset Information may be used in future Undefined 00 Undefined 00 Undefined 00 62 SPD Revision 1 0 10 1 0 10 1 0 10 63 Checksum Data 9F 4C 33 64 71 Manufacturer s JEDED ID Code OB Hex bank 3 7 7 7 OB Hex bank 3 7F7F7FOBO00 OB Hex bank3 7F7F7FOBO00 00000 00000 00000 72 Module Manufacturing Location Notel Notel Notel 73 25 Reserved Undefined Note 2 Undefined Note 2 Undefined Note 2 gt 3 please refer to BNDCJ 0082 4 byte 73 255 please refer to NDCJ 0969 REV 2 2 10 Aug 3 2004 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice Preliminary M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB PC3200 PC2700 and PC2100 Unbuffered DDR DIMM SPD Values for M2U12864DSH4B3G elixir Byte Description DDR400 DDR333
18. 700 and PC2100 Unbuffered DDR DIMM Functional Block Diagram 2 Ranks 16 devices 32Mx8 DDR SDRAMs DQS4 DM4 DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 elixir M SPD e gt 00 015 ne Ww DM CS Das DM CS Das N 07 00 N 4 06 1 01 06 00 D4 O7 D12 M 05 O02 N 04 0 3 M 03 04 N 02 105 DM CS Das DM CS 005 07 00 M 06 1 01 06 WW 0 D5 VO7 D13 N 05 O02 WW 04 03 N 03 04 2 5 M W DM CS 00 DM CS Das N 07 00 M 106 1 01 1 06 00 pe O7 D14 W 105 IO 2 N 104 03 WW 03 04 N 4 102 05 Ww DM cs 09 DM CS pas N 07 M 06 1 01 1 0 6 00 VO7 D15 N 05 02 N 04 03 N 03 04
19. 75 0 75 0 45 0 55 0 45 0 55 7 5 12 10 12 0 5 0 5 1 75 0 75 0 75 0 75 0 75 0 5 tcu or tet lup tans 0 75 0 75 1 25 0 35 0 2 0 2 2 0 0 40 0 60 0 25 0 9 0 9 1 0 Unit ns ns ns ns ns ns ns ns ns ns Notes 1 4 1 4 1 4 1 4 1 4 1 4 15 16 1 4 15 16 1 4 1 4 5 1 4 5 1 4 1 4 1 4 1 4 1 4 1 4 1 4 7 1 4 6 2 4 9 11 12 2 4 9 11 12 2 4 10 11 12 14 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB PC3200 256MB and 128MB PC2700 and PC2100 Unbuffered DDR DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module Ta 0 70 Vopa Vpp7 2 5V 0 2V PC2100 PC2700 Vppa7 Vpp7 2 6V 0 1V PC3200 Part 2 of 2 Celixir 5T 6K 75B Unit Notes Symbol Parameter PC3200 PC2700 PC2100 Min Max Min Max Min Max Address and control input setup time 24 tis 0 7 0 8 1 0 ns 10 12 slow slew rate 14 tpw Input pulse width 2 2 2 2 2 2 ns 2 4 12 tre RE Read preamble 0 9 1 1 0 9 1 1 0 9 1 1 1 4 tap st Read postamble 0 40 0 60 0 40 0 60 0 40 0 60 1 4 tras Active to Precharge command 42ns 120us 42ns 120us 45ns 120us 1 4 trc Active to Active Auto refresh command period 55 60 65 ns 1 4 Auto refresh to Active Auto refresh command 70 72 75 ns 1 4
20. DDR266 5T 6K 75B SPD Value hexadecimal SPD Value hexadecimal SPD Value hexadecimal 0 Number of Serial PD Bytes Written during Production 128 80 128 80 128 80 1 Total Number of Bytes in Serial PD device 256 08 256 08 256 08 2 Fundamental Memory Type DDR SDRAM 07 DDR SDRAM 07 DDR SDRAM 07 3 Number of Row Addresses on Assembly 13 0 13 0 13 0 4 Number of Column Addresses Assembly 9 09 9 09 9 09 5 Number of DIMM Bank 1 01 1 01 1 01 6 Data Width of Assembly X64 40 X64 40 X64 40 7 Data Width of Assembly X64 00 X64 00 X64 00 8 Voltage Interface Level of this Assembly SSTL2 5V 04 SSTL 2 5V 04 SSTL 2 5V 04 9 DDR SDRAM Device Cycle Time at CL 3 Sns 50 6ns 60 75ns 75 10 DDR SDRAM Device Access Time from Clock at CL 3 0 6ns 60 0 7ns 70 0 75ns 75 DIMM Configuration Type Non Parity 00 Non Parity 00 Non Parity 00 12 Refresh Rate Type SR 1x 7 8us 82 SR 1x 7 8us 82 SR 1x 7 8us 82 Self Refresh Flag 13 Primary DDR SDRAM Width X16 10 X16 10 X16 10 14 Error Checking DDR SDRAM Device Width N A 00 N A 00 N A 00 15 DDR SDRAM Device Attr Min Clk Delay Random Col 1 Clock 01 1 Clock 01 1 Clock 01 Access 16 DDR SDRAM Device Attributes Burst Length Supported 2 4 8 2 4 8 2 4 8 17 DDR SDRAM Device Attributes Number of Device Banks 4 04 4 04 4 04 18 DDR SDRAM Device Attributes CAS Latencies Supported 2 2 5 3 2 2 5 0 2 2 5 0C 19 DDR SDRAM Device Attributes CS Latency 0 01 0 01 0 01 20 DDR SDRAM Device Attributes WE Lat
21. DRAMs 00 015 SCL gt WP gt Notes 1 DQ to I O wiring is shown as recommended but may be changed 2 DQ DQS DM CKE S relationships must be maintained as shown 3 DQ DQS DM DQS resistors 22 Ohms 4 Vppip Strap connections for memory device STRAP OUT OPEN V STRAP IN Vss V is not equal to Vong Aug 3 2004 Preliminary A0 A1 A2 sho sh2 Wire per Clock Loading Table Wiring Diagrams NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB PC3200 PC2700 and PC2100 Unbuffered DDR DIMM Functional Block Diagram 1 Rank 8 devices 32Mx8 DDR SDRAMs elixir 50 DQSO DQS4 DMO DQS9 N DM4 DQS13 A 4 DM CS DOS DM cs 00 DQ0 M DQ32 07 DQ1 M 06 DQ33 N 6 DQ2 N 4 01 DQ34 N 01 DQ3 N 00 DO DQ35 N 100 p4 DQ4 N 05 DQ36 N 05 DQ5 M 104 DQ37 N 4 104 N 03 DQ38 N 3 DQ7 N 102 DQ39 02 DQS1 M pass M DM1 DQS10 JA DM5 DQS14 A DM CS 005 DM CS 005 1 07 DQ40 VO7 DQ9 M
22. H4B3G 5T 16Mx64 M2U51264DS8HB3G 6K 64Mx64 PC2700 166MHz 6ns CL 2 5 M2U25664DS88B3G 6K 32Mx64 DDR333 Gold 2 5 3 3 133MHz 7 5ns CL 2 M2U12864DSH4B3G 6K 16Mx64 2 5V M2U51264DS8HB3G 75B 64Mx64 PC2100 133MHz 7 5ns CL 2 5 M2U25664DS88B3G 75B 32Mx64 DDR266B 2 5 3 3 100MHz 10ns CL 2 M2U12864DSH4B3G 75B 16Mx64 For the closest sales office or information please visit www elixir memory com Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd Kueishan Taoyuan 333 Taiwan R O C Tel 886 3 328 1688 REV 2 2 2 3 2004 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice Preliminary M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB E E PC3200 PC2700 and PC2100 elixir Unbuffered DDR DIMM Pin Description CKO CK1 CK2 IN Differential Clock Inputs 000 0063 Data input output CKO CK1 CK2 CKEO CKE1 Clock Enable DQS0 DQS7 Bidirectional data strobes RAS Row Address Strobe DM0 DM7 Input Data Mask CAS Column Address Strobe WE Write Enable Supply voltage for DQs S0 S1 Chip Selects Vss Ground 9 A11 A12 Address Inputs NC No Connect A10 AP Address Input Auto precharge SCL Serial Pre
23. K 75B 2 1 May 11 2004 Added M2U25664DS88B3G 6K speed grade to ordering information 2 2 Aug 3 2004 Corrected SPD contents Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd Kueishan Taoyuan 333 Taiwan R O C Tel 886 3 328 1688 Please visit our home page for more information www elixir memory com Nanya reserves the right to make changes or deletions without any notice to any of its products Nanya makes no guarantee warranty or representation regarding the suitability of its products for any particular purpose Nanya assumes no liability arising out of the application or use of its products All parameters can and do vary in its application and must be validated for each customer application by the customer s technician By purchasing Nanya products Nanya does not convey any license under its patent rights not the rights of others Nanya products are not designed or intended or authorized for use in systems intended for the military or surgical implants or any other applications where life is involved or where injury or death may occur or the loss corruption of data or the loss of system reliability or mission critical applications Should the buyer purchase or use Nanya products in such unintended or unauthorized application the Buyer and user shall indemnify and hold Nanya and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages all fees and expenses directly
24. M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB PC3200 PC2700 and PC2100 el Unbuffered DDR DIMM 184 pin Unbuffered DDR DIMM Based on DDR400 333 266 256M bit B Die device Features 184 Dual In Line Memory Module DIMM DRAM DLL aligns DQ and DQS transitions with clock transitions Unbuffered DDR DIMM based on 256M bit die B device Address and control signals are fully synchronous to positive organized as either 32Mbx8 or 16Mbx16 clock edge Performance Programmable Operation PC3200 PC2700 PC2100 DIMM CAS Latency 2 2 5 3 Speed Sort 5T 6K 75B Unit Burst Type Sequential or Interleave DIMM CAS Latency 3 2 5 2 5 Burst Length 2 4 8 fox Clock Frequency 200 166 133 MHz Operation Burst Read and Write ick Clock Cycle 5 6 75 ns Auto Refresh CBR and Self Refresh Modes DQ Burst Frequency 400 333 266 MHz Automatic and controlled precharge commands Intended for 133 166 and 200 MHz applications 7 8 us Max Average Periodic Refresh Interval Inputs and outputs are SSTL 2 compatible Serial Presence Detect EEPROM Vona 2 5V 0 2 2 6V 0 1V for PC3200 Gold contacts SDRAMs have 4 internal banks for concurrent operation SDRAMs are packaged in TSOP packages Differential clock inputs Data is read or written on both clock edges Description M2U51264DS8HB3G M2U25664DS88B3G and M2U12864DSH4B3G are unbuffered 184 Pin Double Data Rate DDR Synchronous DRAM D
25. Refresh Time tRC 55ns 37 60ns 3C 65ns 41 42 SDRAM Device Minimum Auto Refresh to Active Auto 70ns 46 72ns 48 75ns 4B Refresh Command Period tRFC 43 SDRAM Device Maximum Cycle Time tCK max 8 20 12 30 12 30 44 SDRAM Device Maximum DQS DQ Skew Time tDQSQ 04 28 04 28 0 5 32 45 SDRAM Device Maximum Read Data Hold Skew Factor 0 5 50 0 55 55 0 75 75 tQHS 46 Superset Information may be used in future Undefined 00 Undefined 00 Undefined 00 47 SDRAM device Attributes DDR SDRAM DIMM Height 31 75mm 01 31 75mm 01 31 75mm 01 48 61 Superset Information may be used in future Undefined 00 Undefined 00 Undefined 00 62 SPD Revision 1 0 10 1 0 10 1 0 10 63 Checksum Data 4D 34 64 71 Manufacturer s JEDED ID Code OB Hex bank 3 7 7 7 OB Hex bank 3 7F7F7FO0BO00 OB Hex bank 3 7F7F7FOBO000 00000 00000 00000 72 Module Manufacturing Location Notel Notel Notel 73 25 Reserved Undefined Note 2 Undefined Note 2 Undefined Note 2 5 please refer to BNDCJ 0082 a byte 73 255 please refer to NDCJ 0969 REV 2 2 9 ii 3 2004 NANYA the right t um TECHNOLOGY CORPO RATION T reserves the ri io change products and specifications without notice Preliminary 9 ge p M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB PC3200 PC2700 and PC2100 Unbuffered DDR DIMM SPD Values for M2U25664DS88B3G
26. al 23 Minimum Clock Cycle CL 2 5 24 Maximum Data Access Time from Clock at CL 2 25 Minimum Clock Cycle Time at CL 1 REV 2 2 Aug 3 2004 Preliminary Byte 26 27 28 29 30 31 32 33 34 35 36 40 41 42 43 44 45 46 61 62 63 64 71 72 73 90 91 92 93 94 95 98 99 127 Celixir Description Maximum Data Access Time from Clock at CL 1 Minimum Row Precharge Time trp Minimum Row Active to Row Active delay Minimum RAS to CAS delay taco Minimum RAS Pulse Width tras Module Bank Density Address and Command Setup Time Before Clock Address and Command Hold Time After Clock Data Input Setup Time Before Clock Data Input Hold Time After Clock Reserved Minimum Active Auto refresh Time tac Auto refresh to Active Auto refresh Command Period trec Max Cycle Time tck max Maximum DQS DQ Skew Time tpasa Maximum Read Data Hold Skew Factor tous Reserved SPD Revision Checksum Data Manufacturer s JEDEC ID Code Module Manufacturing Location Module Part number Module Revision Code Module Manufacturing Data Binary coded decimal year code 0 99 Decimal 00 63 Hex ww Binary coded decimal year code 01 52 Decimal 01 34 Hex Module Serial Number Reserved NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB cone PC320
27. ardless of the state of 1 If AP is low then BAO BA1 are used to define which bank to pre charge Data and Check Bit input output pins operate in the same manner as on conventional DRAMs Data strobes Output with read data input with write data Edge aligned with read data centered on write data Used to capture write data Data Check Bit Input Output pins Used on ECC modules and is not used on x64 modules The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect DM8 is associated with check bits CBO CB7 and is not used on x64 modules Power and ground for the DDR SDRAM input buffers and core logic Address inputs Connected to either Voo or Vss the system board to configure the Serial Presence Detect EEPROM address This bi directional pin is used to transfer data into or out of the SPD EEPROM A resistor must be connected from the SDA bus line to V DD to act as a pull up This signal is used to clock data into and out of the SPD EEPROM A resistor may be connected from the SCL bus time to V DD to act as a pull up Serial EEPROM positive power supply NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB PC3200 PC2
28. d Skew Factor 0 5 50 0 55 55 0 75 75 tQHS 46 Superset Information may be used in future Undefined 00 Undefined 00 Undefined 00 47 SDRAM device Attributes DDR SDRAM DIMM Height 31 75mm 01 31 75mm 01 31 75mm 01 48 61 Superset Information may be used in future Undefined 00 Undefined 00 Undefined 00 62 SPD Revision 1 0 10 1 0 10 1 0 10 63 Checksum Data 86 33 1 64 71 Manufacturer s JEDED ID Code OB Hex bank 3 7 7 7 OB Hex bank 3 7F7F7FOBO00 OB Hex bank3 7F7F7FOBO00 00000 00000 00000 72 Module Manufacturing Location Notel Notel Notel 73 25 Reserved Undefined Note 2 Undefined Note 2 Undefined Note 2 5 5 please refer to BNDCJ 0082 6 byte 73 255 please refer to NDCJ 0969 REV 2 2 11 Aug 3 2004 NANYA TECHNOLOGY CORPORATION Preliminary NANYA reserves the right to change products and specifications without notice M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB Cal c PC3200 PC2700 and PC2100 el Unbuffered DDR DIMM Absolute Maximum Ratings Symbol Parameter Rating Units Vin Vout Voltage on pins relative to Vss 0 5 to Vppa 0 5 V ViN Voltage on Input relative to Vss 0 5 to 3 6 V Voltage Vpp supply relative to Vss 0 5 to 3 6 V Voltage Vppo supply relative to Vss 0 5 to 3 6 V TA Operating Temperature Ambient 0 to 70 Tsrc Storage Temperature Plastic 55 to 150 C Pp Power Dissipation per device component 1 lour Short Circuit Outp
29. e between the input level on CK and the input level on CK 4 The value of Vix is expected to equal 0 5 Vppo of the transmitting device and must track variations in the DC level of the same REV 2 2 13 Dg 3 2004 NANYA the right t S TECHNOLOGY CORTO RATION 4 reserves the io change products and specifications without notice Preliminary 9 ge p M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB PC3200 PC2700 and PC2100 Unbuffered DDR DIMM Operating Standby and Refresh Currents Ta 0 C 70 C Vova Vpp7 2 5V 0 2V PC2100 PC2700 Vppa7 Vpp7 2 6V 0 1V PC3200 Symbol IDDO IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 Parameter Condition Operating Current one bank active precharge tnc tnc tcx mmn DQ DM and DQS inputs changing twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank active read precharge Burst 2 tc tac CL 2 5 tek mn lour OMA address and control inputs changing once per clock cycle Precharge Power Down Standby Current all banks idle power down mode lt Vi Idle Standby Current CS gt Vin all banks idle gt Vin tck uy address and control inputs changing once per clock cycle Active Power Down Standby Current one bank active power down mode lt Vi
30. ency 1 02 1 02 02 21 DDR SDRAM Device Attributes Differential Clock 20 Differential Clock 20 Differential Clock 20 22 DDR SDRAM Device Attributes General 0 2V Voltage 00 0 2V Voltage 00 0 2V Voltage 00 Tolerance 23 Minimum Clock Cycle at CL 2 5 6 0ns 60 7 5ns 75 10ns AO 24 Maximum Data Access Time tac from Clock at CL 2 5 0 7ns 70 0 70ns 70 0 75ns 75 25 Minimum Clock Cycle Time at CL 2 7 5ns 75 N A 00 N A 00 26 Maximum Data Access Time tac from Clock at CL 2 7 5ns 75 N A 00 N A 00 27 Minimum Row Precharge Time trp 15ns 3C 18ns 48 20ns 50 28 Minimum Row Active to Row Active delay tarp 10ns 28 12ns 30 15ns 3C 29 Minimum RAS to CAS delay tren 15ns 3C 18ns 48 20ns 50 30 Minimum RAS Pulse Width tras 40ns 28 42ns 2A 45ns 2D 3 Module Bank Density 128MB 20 128MB 20 128MB 20 32 j Address and Command Setup Time Before Clock 0 6ns 60 0 75ns 75 0 9ns 90 33 Address and Command Hold Time After Clock 0 6ns 60 0 75ns 75 0 9ns 90 34 Data Input Setup Time Before Clock 0 4ns 40 0 45ns 45 0 5ns 50 35 Data Input Hold Time After Clock 0 4ns 40 0 45ns 45 0 5ns 50 36 40 Reserved Undefined 00 Undefined 00 Undefined 00 4 Minimum Active Auto Refresh Time tRC 55ns 37 60ns 3C 65ns 41 42 SDRAM Device Minimum Auto Refresh to Active Auto 70ns 46 72ns 48 75ns 4B Refresh Command Period tRFC 43 SDRAM Device Maximum Cycle Time tCK max 8 20 12 30 12 30 44 SDRAM Device Maximum DQS DQ Skew Time tDQSQ 04 28 04 28 0 5 32 45 SDRAM Device Maximum Read Data Hol
31. k inputs and output timing for read operations is synchronized to the input clock Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated DDR SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue Physical Bank 0 is selected by S0 Bank 1 is selected by S1 When sampled at the positive rising edge of the clock RAS CAS WE define the operation to be executed by the SDRAM Reference voltage for SSTL 2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity Selects which SDRAM bank is to be active During a Bank Activate command cycle A0 A12 defines the row address RAO RA12 when sampled at the rising clock edge During a Read or Write command cycle AO A9 defines the column address 9 when sampled at the rising clock edge In addition to the column address AP is used to invoke auto precharge operation at the end of the Burst Read or Write cycle If AP is high auto precharge is selected and BAO BA1 defines the bank to be precharged If AP is low auto precharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BA1 to control which bank s to precharge If AP is high all 4 banks will be precharged reg
32. me windows as valid data transitions These parameters are not referred to a specific voltage level but specify when the device is no longer driving HZ or begins driving LZ 6 The maximum limit for this parameter is not a device limit The device operates with a greater value for this parameter but system performance bus turnaround degrades accordingly 7 The specific requirement is that DQS be valid high low or some point on a valid transition on or before this CK edge A valid transition is defined as monotonic and meeting the input slew rate specifications of the device When no writes were previously in progress on the bus DQS will be transitioning from Hi Z to logic LOW If a previous write was in progress DQS could be HIGH LOW or transitioning from high to low at this time depending on tpass 8 A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device 9 For command address input slew rate gt 1 0 V ns Slew rate is measured between Vou and 10 For command address input slew rate gt 0 5 V ns and lt 1 0 V ns Slew rate is measured between Vou and Voi 11 CK CK slew rates are gt 1 0 V ns 12 These parameters guarantee device timing but they are not necessarily tested on each device and they may be guaranteed by design or tester characterization 13 For each of the terms in parentheses if not already an integer round to the next highest integer tcx is
33. ned as shown 3 DQ DQS DM DQS resistors 22 Ohms 4 Vppip Strap connections for memory device Vp STRAP OUT OPEN Vp Vopq STRAP IN Vgg V5 is not equal to REV 2 2 y Aug 3 2004 NANYA TECHNOLOGY CORPORATION Preliminary NANYA reserves the right to change products and specifications without notice M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB PC3200 PC2700 and PC2100 Unbuffered DDR DIMM Serial Presence Detect SPD Description Byte Description 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of DIMM Rank 6 Data Width of Assembly 7 Data Width of Assembly cont 8 Voltage Interface Level of this Assembly 9 DDR SDRAM Device Cycle Time CL 2 5 10 DDR SDRAM Device Access Time from Clock CL 2 5 11 DIMM Configuration Type 12 Refresh Rate Type 13 Primary DDR SDRAM Width 14 Error Checking DDR SDRAM Device Width 45 DDR SDRAM Device Attr Min CLK Delay Random Col Access 16 DDR SDRAM Device Attributes Burst Length Supported 17 DDR SDRAM Device Attributes Number of Device Banks 18 DDR SDRAM Device Attributes CAS Latencies Supported 19 DDR SDRAM Device Attributes CS Latency 20 DDR SDRAM Device Attributes WE Latency 21 DDR SDRAM Device Attributes 22 DDR SDRAM Device Attributes Gener
34. rst Length Supported 2 4 8 0E 2 4 8 0E 2 4 8 0E 17 DDR SDRAM Device Attributes Number of Device Banks 4 04 4 04 4 04 18 DDR SDRAM Device Attributes CAS Latencies Supported 2 2 5 3 IC 2 2 5 0C 2 2 5 0C 19 DDR SDRAM Device Attributes CS Latency 0 01 0 01 0 01 20 DDR SDRAM Device Attributes WE Latency 1 02 1 02 1 02 21 DDR SDRAM Device Attributes Differential Clock 20 Differential Clock 20 Differential Clock 20 22 DDR SDRAM Device Attributes General 0 2V Voltage 00 0 2V Voltage 00 0 2V Voltage 00 Tolerance Tolerance Tolerance 23 Minimum Clock Cycle at CL 2 5 6 0ns 60 7 5ns 75 10ns AO 24 Maximum Data Access Time tac from Clock at CL 2 5 0 7ns 70 0 70ns 70 0 75ns 75 25 Minimum Clock Cycle Time at CL 2 7 5ns 75 N A 00 N A 00 26 Maximum Data Access Time tac from Clock at CL 2 7 5ns 75 N A 00 N A 00 27 Minimum Row Precharge Time tgp 15ns 3C 18ns 48 20ns 50 28 Minimum Row Active to Row Active delay tarp 10ns 28 12ns 30 15ns 3C 29 Minimum RAS to CAS delay tgcp 15ns 3C 18ns 48 20ns 50 30 Minimum RAS Pulse Width tras 40ns 28 42ns 2A 45ns 2D 3 Module Bank Density 256MB 40 256MB 40 256MB 40 32 Address and Command Setup Time Before Clock 0 6ns 60 0 75ns 75 0 9ns 90 33 Address and Command Hold Time After Clock 0 6ns 60 0 75ns 75 0 9ns 90 34 Data Input Setup Time Before Clock 0 4ns 40 0 45ns 45 0 5ns 50 35 Data Input Hold Time After Clock 0 4ns 40 0 45ns 45 0 5ns 50 36 40 Reserved Undefined 00 Undefined 00 Undefined 00 4 Minimum Active Auto
35. sence Detect Clock Input BAO BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input output VREF Ref Voltage for SSTL_2 inputs 0 2 Serial Presence Detect Address Inputs Voo Identification flag Vbpsep Serial EEPROM positive power supply Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 93 Vss 32 A5 124 Vas 62 154 2 DQO 94 DQ4 33 0924 125 A6 63 WE 155 0045 3 Vss 95 DQ5 34 126 0028 64 0041 156 4 96 Vona 35 0025 127 0929 65 CAS 157 50 5 0050 97 59 36 DQS3 128 66 Vss 158 51 6 002 98 DQ6 37 4 129 DM3 DQS12 67 0055 159 DM5 DQS14 7T 99 DQ7 38 130 68 DQ42 160 Vss 8 003 100 Vss 39 0026 131 0930 69 0043 161 0046 9 NC 101 NC 40 DQ27 132 Vss 70 Voo 162 DQ47 10 NC 102 NC 41 A2 133 DQ31 71 NC 163 NC 11 Vss 103 NC 42 Vss 134 NC 72 DQ48 164 Vona 12 008 104 43 1 135 73 0049 165 0052 13 009 105 0012 44 NC 136 74 Vss 166 0053 14 DQS1 106 0013 45 NC 137 CKO 75 2 167 15 107 DM1 DQS10 46 Voo 138 CKO 76 2 168 16 CK1 108 47 NC 139 Vss 77 169 DM6 DQS15 17 109 DQ14 48 AO 140 NC 78 DQS6 170 DQ54 18 5 110 DQ15 49 NC 141 A10 79 0050 171 0055 19 0010 111 CKE1 50 142 NC 80 0051 172 20 0011 112 51 NC 143 81 173 21 113 NC 52 1 144 NC 82 174 DQ60 22 114 0020 KEY KEY 83 0056 175 DQe61 23 DQ16 115 12 53 0032 145 Vss 84 DQ57 176 Vss 24 0017 116 Vss 54
36. sho sh sho Strap see Note 4 Notes 1 DQ to I O wiring is shown as recommended but may be changed 2 DQ DQS DM CKE S relationships must be maintained as shown 3 DQ DQS DM DGS resistors 22 Ohms 4 Strap connections for memory device Vp V5po STRAP OUT OPEN Vy STRAP IN Vss Vp is not equal to Vppa REV 2 2 6 Aug 3 2004 NANYA TECHNOLOGY CORPORATION Preliminary NANYA reserves the right to change products and specifications without notice M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB PC3200 PC2700 and PC2100 Unbuffered DDR DIMM Functional Block Diagram 1 Rank 4 devices 16Mx16 DDR SDRAMs elixir 50 DQS1 JA LDQS DQS5 M LDQS DM1 DQS10 A LDM DM5 DQS14 LDM DQ8 M 06 DQ40 1 06 Dag N 104 DQ41 N 1 04 DQ10 01 0042 N 101 0011 N 03 0043 N 1 03 0012 N 02 0044 N 02 0013 N 00 0045 M 00 0014 5 0046 5 DQ15 107 DQ47 N 1 07 DQSO J UDQS 2o DQS4 M UDQS D DMO DQS9 M UDM DM4 DQS13 UDM 90 M 108 DQ32 N 108 DQ1 AM 10 DQ33 M 1 0 10 DQ2 M VO 15 DQ34 M 15 M VO 13 DQ35 M 13 DQ4 M 12 DQ36 M 12 295 M VO 14 DQ37 N VO 14 A
37. t load Refer to the AC Output Load Circuit below 4 AC timing and IDD tests may use a to Viu swing of up to 1 5V in the test environment but input timing is still referenced to Vrer or to the crossing point for CK CK and parameter specifications are guaranteed for the specified AC input levels under normal use conditions The minimum slew rate for the input signals is 1V ns in the range between Vi and ac unless otherwise specified 5 The AC and DC input level specifications are as defined in the SSTL 2 Standard i e the receiver effectively switches as a result of the signal crossing the AC input level and remains in that state as long as the signal does not ring back above below the DC input LOW HIGH level AC Output Load Circuits VTT 50 ohms Output VOUT Timing Reference Point 30pF AC Operating Conditions Ta 0 70 Vppa7 Vpp7 2 5V 0 2V PC2100 PC2700 Vppa7 Vpp7 2 6V 0 1V PC3200 Symbol Parameter Condition Min Max Unit Notes AC Input High Logic 1 Voltage 0 31 V 1 2 ac Input Low Logic 0 Voltage Vre 0 31 V 1 2 Vip AC Input Differential Voltage CK and CK Inputs 0 62 Vona 0 6 V 1 2 3 Vix ac Input Differential Pair Cross Point Voltage CK and CK Inputs 0 5 0 2 0 5 0 2 V 1 2 4 1 Input slew rate 1V ns 2 Inputs are not recognized as valid until Vrer stabilizes 3 Vip is the magnitude of the differenc
38. ual In Line Memory Modules DIMM M2U51264DS8HB3G is 512MB modules organized as dual ranks using sixteen 32Mx8 TSOP devices M2U25664DS88B3G is 256MB modules organized as single rank using eight 32Mx8 TSOP devices M2U12864DSH4B3G is 128MB modules organized as single rank using four 16Mx16 TSOP devices Depending on the speed grade these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves high speed data transfer rates of up to 400 MHz Prior to any access operation the device CAS latency and burst type length operation type must be programmed into the DIMM by address inputs and inputs BAO and BA1 using the mode register set cycle The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence detect implementation SPD can be accessed The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC REV 2 2 1 AU 3 2004 NANYA the right t id TECHNOLOGY CORRO RATION A reserves the ri change products and specifications without notice Preliminary 9 M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB Cal PC3200 PC2700 and PC2100 el Unbuffered DDR DIMM Ordering Information Organization Part Number Speed Power Leads M2U51264DS8HB3G 5T 64Mx64 PC3200 200MHz bns CL 3 M2U25664DS88B3G 5T 32Mx64 DDR400 2 6V 3 3 3 166MHz 6ns CL 2 5 M2U12864DS
39. ut Current 50 mA Note Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability DC Electrical Characteristics and Operating Conditions 0 C 70 Vopa Vpp7 2 5V 0 2V PC2100 PC2700 Ta 0 C 70 Vona Vpp7 2 6V 0 1V PC3200 Symbol Parameter Min Max Units Notes Supply Voltage PC2100 PC2700 2 3 2 7 V 1 PC3200 2 5 Supply Voltage PC2100 PC2700 2 3 2 7 V 1 PC3200 2 5 Vss Vssa Supply Voltage I O Supply Voltage 0 0 V VREF I O Reference Voltage 0 49 x Vppa 0 51 x Vppa V 1 2 Vit Termination Voltage System Vrer 0 04 Vrer 0 04 V 1 3 Input High Logic1 Voltage VREF 0 15 0 3 V 1 Vit po Input Low LogicO Voltage 0 3 Vrer 0 15 V 1 Vin Input Voltage Level CK and CK Inputs 0 3 Vona 0 3 V 1 Vip pc Input Differential Voltage CK and CK Inputs 0 30 Vona 0 6 V 1 4 Input Leakage Current li Any input OV lt VIN lt Vpp 10 10 1 All other pins not under test OV Output Leakage Current loz 10 10 1 DGs are disabled OV lt Vout lt Vppa Output High Current lon 16 8 mA 1 Vout 0 373V VREF min Vrt O
40. utput Low Current lon 16 8 mA 1 Vout 0 373 max VREF max 1 Inputs are not recognized as valid until Veer stabilizes 2 Veer is expected to be equal to 0 5 Vppo of the transmitting device and to track variations in the DC level of the same Peak to peak noise on Vrer may not exceed 2 of the DC value 3 Vr is not applied directly to the DIMM V is a system supply for signal termination resistors is expected to be set equal to Veer and must track variations in the DC level of Veer 4 Vip is the magnitude of the difference between the input level on CK and the input level on CK REV 2 2 12 ii 3 2004 NANYA the right t S TECHNOLOGY CORTO RATION 4 reserves the change products and specifications without notice Preliminary 9 ge p M2U51264DS8HB3G M2U25664DS88B3G M2U12864DSH4B3G 512MB 256MB and 128MB Cal gens PC3200 PC2700 and PC2100 Unbuffered DDR DIMM AC Characteristics Notes 1 5 apply to the following Tables Electrical Characteristics and DC Operating Conditions AC Operating Conditions Operating Standby and Refresh Currents and Electrical Characteristics and AC Timing 1 All voltages referenced to Vss 2 Tests for AC timing IDD and electrical AC and DC characteristics may be conducted at nominal reference supply voltage levels but the related specifications and device operation are guaranteed for the full voltage range specified 3 Outputs measured with equivalen

Elixir M2U25664DS88B3G-5T memory module

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