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Hynix HMP125U6EFR8C-S6 memory module

1. EMR 1 Programming BA2BA BAo Ats Ar3 Aie Ato Ae As Ao Address Field ot o 1 Qof RDQS DAS OCD program Rtt Additive latency mt D C DLL Extended Mode Register 1 BAO MR mode 2 Rit Nomnat 0 0 MR 0 0 ODT Disabled Ao DLL Enable 0 1 EMR 1 1 750 0 Enable 1 0 EMR 2 1 0 1500 1 Disable 1 1 EMR 3 Reserved 1 1 50 2 2 Optional for DDR2 400 533 667 Y Mandatory for DDR2 800 Y A9 7 OCD Calibration Program As Additive Latency 0 0 0 Calibration mode exit maintain setting 0 0 0 1 1 0 1 0 Drive 0 0 1 0 2 1100 0 Adjust mode 1 3 1 1 1 OCD Calibration default 4 110 0 4 8 When Adjust mode is issued AL from previously set value must be applied 1 0 1 5 4 After setting to default OCD mode needs to be exited by setting A9 A7 to 000 Refer to the following 1 2 2 3 section for detailed information 1 1 0 Reserved 1 1 1 Reserved A12 Qoff Optional Y 0 Output buffer enabled 1 Output buffer disabled A1 in CAE Dou 5 Outputs disabled DQs DQSs DQSs RDQS RDQS This feature is used in conjunction with DIMM IDD meaurements 0 Full Strength 100 when IDDQ is not
2. T3 T4 T5 T6 T7 T8 T9 f I 1 1 1 1 1 X 1 AL Write to Read 1 gt 5 NOP W NOP jede NOP scii Pai i ry 005 DaS 1 3 ENS E cp d Ale CL 3 s gt RL 5 i gt tWTR i i 1 1 1 1 1 1 1 DQ a SENE i Dou The minimum number of clock from the burst write command to the burst read command is CL 1 BL 2 tWTR This tWTR is not a write recovery time WR but the time required to transfer the 4bit write data from the input buffer into sense amplifiers in the array tWTR is defined in AC spec table of this data sheet Figure 27 Burst write followed by burst read RL 5 AL 2 CL 3 WL 4 tWTR 2 BL 4 27 hyuix DDR2 Device Operations amp Timing Diagram TO T2 T3 T4 T6 T7 T8 O eS H NOP H me NOP H NOP H NOP H NOP H NOP H NOP DQS Y r Y h Das Tas X d WL RLr124 i DQ s DNA DNA DNA DNA DNB DNB ONB DNB Figure 28 Seamless Burst Write Operation RL 5 WL 4 BL 4 The seamless burst write operation is supported by enabling a write command every other cloc
3. xm IIIILlLLL AL 1 ducas i 5 gt i RL 4 i i DQ s i DOUTA DOUTA DOUT A DOUT hy DOUTA DOUT j i i i i A A i A gt first 4 bit prefetch second 4 bit prefetch Precharge begins here Figure 38 Example 1 Burst Read Operation with Auto Precharge RL 4 AL 1 CL 3 BL 8 lt 2 clocks TO T1 T2 T3 T4 T5 T6 T7 T8 Bank A neg NOP H NOP Ae NOP at NOP H NOP H ES NOP 1 s ALAARTE gt 1 i r y DQS DQS i 1 1 1 Nes yt E 1 CL 3 gt gt i RL 4 i amp DQ s DOUTA DOUTA DOUTA DOUTA H A 4 bit prefetch gt t t RIP Precharge begins here Dr Figure 39 Example 2 Burst Read Operation with Auto Precharge RL 4 AL 1 CL 3 BL 4 gt 2 clocks 37 hyuix DDR2 Device Operations amp Timing Diagram TO T1 T2 T3 T4 5 T6 T7 T8 x in an on a V 10 1 10 1 i 1 1 1 1 1 1 1 CAS i Bank A CMD Post 5 H NOP NOP H NOP gt tR S min
4. differential cross point voltage 0 5 VDDQ 0 125 0 5 VDDQ 0 125 V 1 Notes 1 The typical value of Vox Ao is expected to be about 0 5 V of the transmitting device and Vox AC is expected to track variations VDDQ Vox 4O indicates the voltage at whitch differential output signals must cross Table 16 Differential AC output parameters 55 hyuix DDR2 Device Operations amp Timing Diagram 4 2 6 Overshoot Undershoot Specification Specification Parameter DDR2 DDR2 DDR2 DDR2 400 533 667 800 Maximum peak amplitude allowed for overshoot area See Figure 1 0 5V 0 5V 0 5V 0 5V Maximum peak amplitude allowed for undershoot area See Figure 1 0 5V 0 5V 0 5V 0 5V Maximum overshoot area above VDD See Figure1 1 33 V ns 1 0 V ns 0 8V ns 0 66V ns Maximum undershoot area below VSS See Figure 1 1 33 V ns 1 0 V ns 0 8V ns 0 66V ns A0 A15 BAO BA2 CS RAS CAS WE ODT Maximum Amplitude Maximum Amplitude Table 17 AC Overshoot Undershoot Specification for Address and Control Pins Overshoot Area Undershoot Area Time ns Figure 59 AC overshoot and undershoot definition for address and control pins Specification Parameter DDR2 DDR2 DDR2 DDR2 400 533 667 800 Maximum peak amplitude allowed for overshoot area See Figure 2 0 5V 0 5V 0 5V 0 5V Maximum peak amplitude allowed for unders
5. 87 Begins zu i i my DQS DQS AL 2 m 2 ate i HL 5 Ls i DQ s DOUTA DOUTA DOUT A DOUT Ay CL 3 Figure 40 Example 3 Burst Read with Auto Precharge Followed by an activation to the Same Bank tRC Limit RL 5 AL 2 CL 3 internal tRCD 3 BL 4 lt 2 clocks TO T1 T2 T3 T4 T5 T6 T7 T8 CK CK y T f A 1 1 I 1 1 Post CAS i Bank CMD READ SH BOF H J H H NOP gt 1 Auto Precharge Begins 1 i 1 DQS DQS gt tap gt RL 5 E DQ s DOUT Ay DOUTA DOUTA DOUT A CLi 3 gt gt Figure 41 Example 4 Burst Read with Auto Precharge Followed by an Activation to the Same Bank tRP Limit RL 5 AL 2 CL 3 internal tRCD 3 BL 4 lt 2 clocks 38 hyuix DDR2 Device Operations amp Timing Diagram Burst Write with Auto Precharge If A10 is HIGH when a Write Command is issued the Write with Auto Precharge function is engaged The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time WR programmed in the mode register The bank undergoin
6. X B7 Note 1 2 NONA Read burst interrupt function is only allowed on burst of 8 Burst interrupt of 4 is prohibited Read burst of 8 can only be interrupted by another Read command Read burst interruption by Write command or Precharge command is prohibited Read burst interrupt must occur exactly two clocks after previous Read command Any other Read burst interrupt timings are prohibited Read burst interruption is allowed to any bank inside DRAM Read burst with Auto Precharge enabled is not allowed to interrupt Read burst interruption is allowed by another Read with Auto Precharge command All command timings are referenced to burst length set in the mode register They are not referenced to actual burst For example Minimum Read to Precharge timing is AL BL 2 where BL is the burst length set in the mode register and not the actual burst which is shorter because of interrupt Figure 23 Read burst interrupt timing example CL 3 AL 0 RL 3 BL 8 25 hyuix DDR2 Device Operations amp Timing Diagram 1 4 4 Burst Write Operation The Burst Write command is initiated by having CS CAS and WE LOW while holding RAS HIGH at the rising edge of the clock The address inputs determine the starting column address Write latency WL is defined by a read latency RL minus one and is equal to AL CL 1 A data strobe signal DQS should be driven LOW preamble one cloc
7. 1 8 Power Down Power down is synchronously entered when is registered LOW along with Nop or Deselect command CKE is not allowed to go LOW while mode register or extended mode register command time or read or write operation is in progress CKE is allowed to go LOW while any of other operations such as row activation pre charge or autoprecharge or auto refresh is in progress but power down IDD spec will not be applied until fin ishing those operations Timing diagrams are shown in the following pages with details for entry into power down The DLL should be in a locked state when power down is entered Otherwise DLL should be reset after exit ing power down mode for proper read operation DRAM design guarantees its DLL in a locked state with any CKE intensive operations as long as DRAM controller complies with DRAM specifications Figure X and figure Y show two examples of CKE intensive applications In both examples DRAM maintains DLL in a locked state throughout the period If power down occurs when all banks are idle this mode is referred to as precharge power down if power down occurs when there is a row active in any bank this mode is referred to as active power down Entering power down deactivates the input and output buffers excluding CK CK ODT and CKE Also the DLL is dis abled upon entering precharge power down or slow exit active power down but the DLL is kept enabled dur ing fast exit active power down In power
8. 1 11 Deselect Command The Deselect command performs the same function as a No Operation command Deselect command occurs when CS is brought HIGH at the rising edge of the clock the RAS CAS and WE signals become don t cares 49 hyuix DDR2 Device Operations amp Timing Diagram 2 Truth Tables 2 1 Command truth table CKE M NN __ __ Function Previous Current CS RAS CAS WE BA1 A15 A11 A10 A9 AO Notes BA2 Cycle Cycle Extended Mode Register H H L L L L BA OP Code 1 2 Refresh REF H H L L L H X X X X 1 Self Refresh Entry H L L L L H X X X X 1 H X X X Self Refresh Exit L H X X X X 1 7 L H H H Single Bank Precharge H H L L H L BA X L X 1 2 Precharge all Banks H H L L H L X X H X 1 Bank Activate H H L L H H BA Row Address 1 2 Write H H L H L L BA Column L Column 1 2 3 Write with Auto Precharge H H L H L L BA Column H Column 1 2 3 H H L H L H BA Column L Column 1 2 3 Read with Auto Precharge H H L H L H BA Column H Column 1 2 3 No Operation H X L H H H X X X X 1 Device Deselect H X H X X X X X X X 1 H X X X Power Down Entry H L X X X X 1 4 L H H H H X X X Power Down Exit L H X X X X 1 4 L H H H 1 All DDR2 SDRAM commands are defined by states of CS RAS CAS WE and CKE at the rising edge of the clock 2 Bank addesses BAO BA1 BA2 BA determine which bank is to be operated
9. P wes C twest tbe tps Figure 24 Data E TO T1 T2 T3 T4 T5 T6 T7 Tn 1 l l cmp Pd UR NOP H NOP NOP NOP H NOP H NOP Precharge t tpssit ME Completion of with tDQSS max e the Burst Write zy M da DQS DQS gt l WLLRL 1 4 WR i gt DQs E on DNA DNA CASE2 with tDQSS min o osse TNCS 1 1 j TU I 1 DQS DQS XN 1 1 WL RL 1 4 gt gt 00 l DNA DNA DNA DNA Figure 25 Burst write operation RL 5 AL 2 CL 3 WL 4 BL 4 26 hyuix DDR2 Device Operations amp Timing Diagram TO T1 T2 T3 T4 5 Tm Tm 1 Tn eX EX XXX 1 1 1 1 1 1 1 1 ATA NOP b NOP H NOP e H NOP Prectarge Bank A JN Activate letion of i lt Dass the ri DQS 1 Uus i DQS Ut d gt gt 1 00 i DNA DNA DNA Figure 26 Burst write operation RL 3 AL 0 CL 3 WL 2 BL 4
10. Burst Length and Sequence Burst Length Starting Address A2 A1 A0 Sequential Addressing decimal Interleave Addressing decimal 000 0 1 2 3 0 1 2 3 001 1 2 3 0 1 0 3 2 010 2 3 0 1 2 3 0 1 011 3 0 1 2 3 2 1 0 000 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 001 1 2 3 0 5 6 7 4 1 0 3 2 5 4 7 6 010 2 3 0 1 6 7 4 5 2 3 0 1 6 7 4 5 011 3 0 1 2 7 4 5 6 3 2 1 0 7 6 5 4 8 100 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 101 5 6 7 4 1 2 3 0 5 4 7 6 1 0 3 2 110 6 7 4 5 2 3 0 1 6 7 4 5 2 3 0 1 111 7 4 5 6 3 0 1 2 7 6 5 4 3 2 1 0 Note Page length is a function of I O organization and column addressing Table 3 Burst length and sequence 21 hyuix DDR2 Device Operations amp Timing Diagram 1 4 3 Burst Read Command The Burst Read command is initiated by having CS and CAS LOW while holding RAS and WE HIGH at the rising edge of the clock The address inputs determine the starting column address for the burst The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency RL The data strobe output DQS is driven LOW 1 clock cycle before valid data DQ is driven onto the data bus The first bit of the burst is synchronized with the rising edge of the data strobe DQS Each subsequent data out appears on the DQ pi
11. Figure 32 Example 2 Burst Read Operation Followed by Precharge RL 4 AL 1 CL 3 BL 8 lt 2 clocks 32 hyuix DDR2 Device Operations amp Timing Diagram TO T1 T2 T3 T4 T5 T6 T7 T8 T f e f FP LP NP NM AN AL AR A RE I Y f n X A Crs i Bank A CMD Posted CAS NOP H NOP 4 4 H NOP Pd AL BL 2 cli i gt i i I ij T pasibas i i A2 CL 3 E E i RL 5 i DQ s DOUTA DOUT A DOUTA DOUT A gt thas CL 3 gt 1 Figure 33 Example 3 Burst Read Operation Followed by Precharge RL 5 AL 2 CL 3 BL 4 lt 2 clocks TO T1 T2 T3 4 5 6 7 T8 Y T N f 1 ec f FP LPN EN AN ALAR A RE A pF 4 CAS i i i i Bank A CMD 4 Past H NOP H NOP HPrecharoe NOP H NOP H H NOP AL 2 Clks gt DOS i Ae a AE ug i i L 2 CL 4 DQ s m DOUTA DOUTA gt thas PME pL 4 P RTP Figure 34 Example 4 Burst Re
12. 1 2 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the denter top side of the DRAM For the measurement conditions Please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300mV of each other at all times and VREF must be not greater than 0 6xVDDQ When VDD VDDQ and VDDL are less than 500mV Vref may be equal to or less than 300mV Table 9 Absolute maximum DC ratings 3 2 Operating Temperature Condition Symbol Parameter Rating Units Notes Operating Temperature 0 to 85 C 1 2 1 Operating Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 2 The operatin temperature range are the temperature where all DRAM specification will be supported Outside of this temperature rang even it is still within the limit of stress condition some deviation on portion of operation specification may be required During operation the DRAM case temperature must be maintained between 0 85 C under
13. AC Logic Level 4 2 5 Differential AC output parameters 4 2 6 Overshoot Undershoot Specification 4 3 Output Buffer Levels 4 3 1 Output AC Test Conditions 4 3 2 Output DC Current Drive 4 3 3 OCD default chracteristics 4 4 Default Output V I Characteristics 4 4 1 Full Strength Default Pulldown Driver Characteristics hyuix DDR2 Device Operations amp Timing Diagram 1 Functional Description 1 1 Simplified State Diagram Initialization Sequence OCD calibration Refreshing Refreshing Automatic Sequence Note Use caution with this diagram It is intended to provide a floorplan of the possible state transitions and the commands to control them not all details In particular situations involving more than one bank enabling disabling on die termination Power Down entry exit timing restrictions during state transitions among other things are not captured in full detail Active Power Down gt Command Sequence Active Read Read Reading Writing with Autoprecharge Reading with Autoprecharge CKEL LOW enter Power Down HIGH exit Power Down exit Self Refresh ACT Activate WR A Write with Autoprecharge RD A Read with Autoprecharge PR A Precharge All Extended Mode Register SRF Enter Self Refresh REF Refresh Figure 1 DDR2 SDRAM simplifie
14. Refer to Overshoot undershoot specifications for Vpeak value maximum peak amplitude allowed for overshoot adn undershoot Table 14 Input AC logic level 4 2 3 AC Input Test Conditions Symbol Condition Value Units Notes VREF Input reference voltage 0 5 VDDQ V 1 VSWING MAX Input signal maximum peak to peak swing 1 0 V 1 SLEW Input signal minimum slew rate 1 0 V ns 2 3 Notes 1 Input waveform timing is referenced to the input signal crossing through the level applied to the device under test 2 The input signal minimum slew rate is to be maintained over the range from Vggr max to ViH ac min for rising edges and the range from min to max for falling edges as shown in the below figure 3 AC timings are referenced with input waveforms switching from VIL ac to VIH ac on the positive transitions and VIH ac to VIL ac on the negative transitions Table 15 AC input test conditions Start of Falling Edge Input Timing Start of Rising Edge Input Timing V DDQ min min VSWING MAX Vaer max max V ATF ATR SS V V max V min V Falling Slew CER Rising Slew REF Figure 57 AC input test signal waveform 54 hyuix DDR2 Device Operations amp Timing Diagram 4 2 4 Differential Input AC logic Level Symbol Parameter Min Max Units Notes ac d
15. Reserved 5 speed bin 1 0 EMR 2 Reserved 1 1 1 Reserved 1 determined 1 1 EMR 3 Reserved 1 0 6 speed bin determined 1 1 1 Reserved 1 and A13 A15 are reserved for future use and must be programmed to 0 when setting the mode register 2 For DDR2 400 533 WR write recovery for autoprecharge min is determined by max and WR max is determined by min WR in clock cycles is calculated by dividing WR in ns by in ns and rounding up to the next integer WR cycles WR ns tCK ns For DDR2 667 800 WR min is determined by tCK avg max and WR max is determined by tCK avg min WR cycles WR ns tCK avg ns The mode register must be programmed to this value This is also used with tRP to determine tDAL 8 Speed bin determined Not required on all speed bins Figure 3 DDR2 SDRAM mode register set MRS hyuix DDR2 Device Operations amp Timing Diagram 1 2 2 2 DDR2 SDRAM Extended Mode Register EMR 1 The extended mode register 1 stores the data for enabling or disabling the DLL output driver strength additive latency ODT DQS disable OCD program RDQS enable The default value of the extended mode register 1 is not defined therefore the extended mode register 1 must be programmed during initialization for proper operation The extended mode register 1 is written by asserting LOW on CS RAS CAS WE HIGH on BAO and LOW while controlling the states of addres
16. all other specification parameters However in some applications it is desirable to operate the DRAM up to 95 C case temperature Therefore 2 spec options may exist 1 Supporting 0 85 C with full JEDEC AC amp DC specifications This is the minimum requirements for all oprating temperature options 2 Supporting 0 85 C and being able to extend to 95 C with doubling auto refresh commands in frequency to a 32 ms period tRFl 3 9us Note Currently the periodic Self Refresh interval is hard coded within the DRAM to a specificic value There is a migration plan to support higher temperature Self Refresh entry via the control of EMR 2 bit A7 However since Self Refresh control function is a migrated process For our DDR2 module user it is imperative to check SPD Byte 49 Bit 0 to ensure the DRAM parts support higer than 85 C case temperature Self Refresh entry 1 if SPD Byte 49 Bit 0 is a O means DRAM does not support Self Refresh at higher than 85 C then system have to ensure the DRAM is at or below 85 C case temperature before initiating Self Refresh operation 2 if SPD Byte 49 Bit 0 is a 1 means DRAM supports Self Refresh at higher than 85 C case temperature then system can use register bit A7 at EMR 2 control DRAM to operate at proper Self Refresh rate for higher temperature Please also refer to EMR 2 register definition section and DDR2 DIMM SPD definition for details Table 10 Operating temperature cond
17. completed or driver strength is set to default subsequent EMR commands not intended to adjust OCD characteristics must specify A9 A7 as 000 in order to maintain the default or calibrated value A9 A8 A7 Operation OCD calibration mode exit Drive 1 DQ DQS RDQS HIGH and DQS LOW Drive 0 DQ DQS RDQS LOW and DQS HIGH Adjust mode OCD calibration default ojo Table 1 drive mode program OCD impedance adjust To adjust output driver impedance controllers must issue the ADJUST EMR command along with 4bit burst code to DDR2 SDRAM as in table X For this operation Burst Length has to be set to BL 4 via MR com mand before activating OCD and controllers must drive this burst code to all DQs at the same time DTO in table X means bits at bit time 0 DT1 at bit time 1 and so forth The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting The maximum step count for adjustment is 16 and when the limit is reached further increment or decrement code has no effect The default setting may be any step within the 16 step range When Adjust mode command is issued AL from previously set value must be applied 4bit burst code inputs to all DQs Operation DTO DT1 DT2 DT3 Pull up driver strength Pull down d
18. down mode CKE LOW and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM and ODT should be in a valid state but all other input signals are Don t Care CKE LOW must be maintained until tCKE has been satisfied Maximum Power down dura tion is limited by the refresh rquirements of the device which allows a maximum of 9 tREFI if maximum post ing of REF is utilized immediately before entering power down The power down state is synchronously exited when is registered HIGH along with a Nop or Deselect command CKE HIGH must be maintained until tCKE has been satisfied A valid executable command can be applied with power down exit latency tXP tXARD or tXARDS after CKE goes HIGH Power down exit latency is defined in the AC spec table of this data sheet Basic Power Down Entry and Exit timing diagram 7 gt CN IS i ts y Command VALID NOP QC VALID 4 tcKE min txaRDS tcKE min Enter Power Down mode Exit Power Down mode Don t Care Figure 46 Basic power down entry and exit timing diagram 43 lau DDR2 Device Operations amp Timing Diagram E __ T0 Ti T2 Tx 1 2 Tx3 4 5 Tx47 Tx 8 Tx 9 CMD RD Readoperation starts with a read comm
19. exited and DLL must be RESET via EMR after precharge power down exit Depending on new clock frequency an additional MR command may need to be issued to appropriately set the WR CL etc During DLL re lock period ODT must remain off After the DLL lock time the DRAM is ready to operate with new clock frequency Tx 1 1 2 Ty 3 4 2 i S SS Ser Cue YR Oen Frequency Change Octurs here 200 Clocks Mus AE aC ODT mu id cu Vj i a i gt M T UP HH tAOFD 6 5 ODTis off during E J DLLRESET Stable new clock Minmum 2 alaks required before changing before power down exit Figure 56 Clock Frequency Change in Precharge Power Down Mode 48 hyuix DDR2 Device Operations amp Timing Diagram 1 10 No Operation Command The No Operation command should be used in cases when the DDR2 SDRAM is an idle or a wait state The purpose of the No Operation command NOP is to prevent the DDR2 SDRAM from registering any unwanted commands between operations A No Operation command is registered when CS is LOW with RAS CAS and WE held HIGH at the rising edge of the clock A No Operation command will not terminate a previous operation that is still executing such as a burst read or write cycle
20. prior to the tWR delay TO T1 T2 T3 T4 T5 T6 T7 T8 CMD Posted TAS NOP H NOP H NOP Hi NOP H NOP H Za NOP 4Precnarge n WRITEA Completion of the Burst Write K gt gt 20 595 4 i WL 3 i i gt 005 DINA DNA DIVA Figure 36 Example 1 Burst Write followed by Precharge WL RL 1 3 TO T1 T2 T3 T4 T5 T6 T7 T9 Posted NOP NOP NOP NOP NOP NOP Precharge CMD WRITE V H H A Completion of the Burst Write i i xK gt F E um m gt DQS DQS lt i zl WL 4 gt 005 DNA DNA DNA Figure 37 Example 2 Burst Write followed by Precharge WL RL 1 4 35 hyuix DDR2 Device Operations amp Timing Diagram 1 6 Auto Precharge Operation Before a new row in an active bank can be opened the active bank must be precharged using either the Pre charge command or the auto precharge function When a Read or a Write command is given to the DDR2 SDRAM the CAS timing accepts one extra address column address A10 to allow the active bank to auto matically begin precharge at the earliest possible moment during the burst read or write cycle If A10 is LOW when the READ or WRITE command is is
21. that can be achieved with a maximum 1 5 step size with no calibration error at the exact nominal conditions only i e perfect calibration procedure 1 5 O maximum step size guar anteed by specification Real system calibration error needs to be added to these values It must be under stood that these V I curves as represented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error Since this is a system specific phenomena it cannot be quantified here The values in the calibrated tables represent just the DRAM portion of uncertainty while look ing at one DQ only If the calibration procedure is used it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figures In such a situation the timing parameters in the specification cannot be guaranteed It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times If this can t be guaranteed by the system calibration procedure re calibration policy and uncertainty with DQ to DQ variation then it is recom mended that only the default values be used The nominal maximum and minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions If calibrated at an extreme condition the amount of va
22. value EMR 2 bit A7 is a migration plan to support higher Self Refresh entry However since this Self Refresh control function is an option and to be phased in by manufacturer individually checking on the DRAM parts for function availablity is necessary For more details please refer to Operating Temperature Condition section at Chapter 5 AC amp DC operation conditions 3 Optional in DDR2 SDRAM If PASR Partial Array Self Refresh is enabled data located in areas of the array beyond the specified address range will be lost if self refresh is entered Data integrity will be maintained if tREF conditions are met and no Self Refresh com mand is issued If the PASR feature is not supported EMR 2 A0 A2 must be set to 000 when programming EMR 2 4 Optional in DDR2 SDRAM JEDEC standard DDR2 SDRAM may or may not have DCC Duty Cycle Corrector implemented and in some of the DRAMs implementing DCC user may be given the controllability of DCC thru EMR 2 A3 bit JEDEC standard DDR2 SDRAM users can look at manufacturer s data sheet to check if the DRAM part supports DCC controllability If Optional DCC Controlla bility is supported user may enable or disable the DCC by programming EMR 2 A3 accordingly If the controllability feature is not sup ported EMR 2 A3 must be set to 0 when programming EMR 2 Figure 5 EMR 2 programming hyuix DDR2 Device Operations amp Timing Diagram EMR 3 No function is defined in extended mode re
23. with the rising clock after the un interrupted burst end and not from the end of actual burst end Oyo Figure 29 Write Burst Interrupt Timing Example CL 3 AL 0 RL 3 WL 2 BL 8 29 hyuix DDR2 Device Operations amp Timing Diagram 1 4 5 Write data mask One write data mask DM pin for each 8 data bits DQ will be supported on DDR2 SDRAMs Consistent with the implementation on DDR SDRAMs It has identical timings on write operations as the data bits and though used in a uni directional manner is internally loaded identically to data bits to insure matched system timing DM of x4 and x16 bit organization is not used during read cycles However DM of x8 bit organization can be used as RDQS during read cycles by EMR 1 settng Data Mask Timing DQS p DQS xX X DQ DM tDS tDH Data Mask Function WL 3 AL 0 BL 4 shown Case 1 tpass CK copeconepooepononeo COMMAND X Wite WL twr KOO a Boa am DQS DGS a i KH 00 TOO ou Figure 30 Write data mask lau DDR2 Device Operations amp Timing Diagram 1 5 Precharge Operation The Precharge Command is used to precharge or close a bank that has been activated The Precharge Com mand is triggered when CS RAS and WE are LOW and CAS is HIGH at the rising edge of the clock The Pre charge Command can be used t
24. 61 DDR2 default pulldown characteristics for full strength driver 60 lau DDR2 Device Operations amp Timing Diagram 4 4 2 Full Strengt Pullup Current mA h Minimum Nominal Default Nominal Default Maximum EE 23 4 Ohms Low 18 ohms High 18 ohms 12 6 Ohms ullup Arver Charac teristic 22 24 77 48 amp 3 o9 1 sa 45 684 753 805 12 846 1 3 87 7 14 90 8 15 92 9 16 94 9 17 97 0 1 9 994 Table 24 Default pullup characteristics for full strength output driver 20 P Minimum E 40 Default 5 60 3 Nominal 80 Default High 100 Maximum 120 0 2 0 4 0 6 0 8 1 0 1 2 1 4 1 6 1 8 0 3 0 5 0 7 0 9 1 1 1 3 1 5 1 7 1 9 VDDO to VOUT V Figure 62 DDR2 default pullup characteristics for full strength driver 61 lau DDR2 Device Operations amp Timing Diagram 4 4 3 Calibrated Output Driver V I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure in OCD impedance adjustment The below Tables show the data in tabular format suitable for input into simulation tools The nominal points represent a device at exactly 18 O The nominal low and nom inal high values represent the range
25. Bank Activate command must be applied before any Read or Write operation can be executed Immediately after the bank active command the DDR2 SDRAM can accept a read or write command on the following clock cycle If a R W command is issued to a bank that has not satisfied the tRCDmin specification then additive latency must be programmed into the device to delay when the R W command is internally issued to the device The additive latency value must be chosen to assure tRCDmin is satisfied Additive latencies of 0 1 2 3 and 4 are sup ported Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank The bank active and precharge times are defined as tRAS and tRP respec tively The minimum time interval between successive Bank Activate commands to the same bank is deter mined by the RAS cycle time of the device tac The minimum time interval between Bank Activate commands is tarp In order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices certain restrictions on operation of the 8 bank devices must be observed There are two rules One for restricting the number of sequential ACT commands that can be issued and another for allowing more time for RAS precharge for a Precharge All command The rules are as follows 8 bank device Sequential Bank Activation Restriction No more than 4 banks may be activated in a rolling tFAW wi
26. DR2 Device Operations amp Timing Diagram 1 4 Read and Write Access Modes After a bank has been activated a read or write cycle can be executed This is accomplished by setting RAS HIGH CS and CAS LOW at the clock s rising edge WE must also be defined at this time to determine whether the access cycle is a read operation WE HIGH or a write operation WE LOW The DDR2 SDRAM provides a fast column access operation A single Read or Write Command will initiate a serial read or write operation on successive clock cycles The boundary of the burst cycle is strictly restricted to specific segments of the page length For example the 32Mbit x 4 I O x 4 Bank chip has a page length of 2048 bits defined by 9 CA11 The page length of 2048 is divided into 512 or 256 uniquely addres sable boundary segments depending on burst length 512 for 4 bit burst 256 for 8 bit burst respectively A 4 bit or 8 bit burst operation will occur entirely within one of the 512 or 256 groups beginning with the column address supplied to the device during the Read or Write Command 0 11 The second third and fourth access will also occur within this group segment however the burst order is a function of the starting address and the burst sequence A new burst access must not interrupt the previous 4 bit burst operation in case of BL 4 setting However in case of BL 8 setting two cases of interrupt by a new burst access are allo
27. ad Operation Followed by Precharge RL 6 AL 2 CL 4 BL 4 lt 2 clocks 33 hyuix DDR2 Device Operations amp Timing Diagram TO T1 T2 T3 T4 T5 T6 T7 T8 C CK T T wef he RP RP MEN f Y f f n X 1 CAS eg er Hee Dm vor MORI AL 2 Clks nlaxtRTP 2 tCK 4 pasibas 1 1 1 1 1 0 CL 4 gt gt RL 4 DQ s i DOUT A me DOUT A DOUTA DOUT A DOUTA DOUT A J gt thas Se RN gt tarp gt first 4 bit prefetch second 4 bit prefetch rounded to next interger Figure 35 Example 5 Burst Read Operation Followed by Precharge RL 4 AL 0 CL 4 BL 8 gt 2 clocks 34 hyuix DDR2 Device Operations amp Timing Diagram Burst Write followed by Precharge Minimum Write to Precharge Command spacing to the same bank WL BL 2 clks tWR For write cycles a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command can be issued This delay is known as a write recovery time tWR referenced from the completion of the burst write to the precharge command No Precharge command should be issued
28. ad followed by a write to the same bank AL 2 and CL 3 RL AL CL 5 WL RL 1 4 BL 4 CU E Wet mE ow UE uc C UENIRE 3 Figure 17 Example 2 Read followed by a write to the same bank AL 0 and CL 3 RL AL CL 3 WL RL 1 2 BL 4 20 hyuix DDR2 Device Operations amp Timing Diagram 1 4 2 Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations write cycle or from memory locations read cycle The parameters that define how the burst mode will operate are burst sequence and burst length DDR2 SDRAM supports 4 bit burst and 8 bit burst modes only For 8 bit burst mode full interleave address ordering is supported however sequential address ordering is nibble based for ease of implementation The burst type either sequential or interleaved is programmable and defined by the address bit 3 of the MR which is similar to the DDR SDRAM operation Seamless burst read or write operations are supported Unlike DDR devices interruption of a burst read or write cycle during BL 4 mode operation is prohibited However in case of BL 8 mode interruption of a burst read or write operation is lim ited to two cases reads interrupted by a read or writes interrupted by a write Therefore the Burst Stop com mand is not supported on DDR2 SDRAM devices
29. and and CKE should be kept HIGH until the end of burst operation ook pa goose TO T1 T2 Tx 1 Tx 2 Tx3 4 Tx 45 Tx 6 TX 7 8 Tx 9 CKE should be kept HIGH until the end of burst operation CKE 7 Nic WE DQ E DOS ar DQS dct E E Figure 47 Read to power down entry TO T1 T2 Tx 1 2 3 4 Tx 5 Tx 6 7 Tx 8 Tx 9 CMD PRE Te Dr BL 2 T with tRTP 7 5ns CKE should be kepi HIGH CKE H anas min satisfied _ until the end of burst Ba ekeeke DQS DQS B TO T1 T2 Tx Tx 1 2 Tx 3 4 5 7 Tx 8 Tx 9 i Start internal precharge CMD RDA ES A mas E should be kept HIGH Dx amp tRAS min satisfied until the end of burst operation CKE 1 1 1 MT ooon MAS AS ARAS ARAS AS DOS ponad Das A Figure 48 Read with autoprecharge to power 44 DDR2 Device Operations amp Timing Diagram TO T1 Tm Tmi 2 Tm 3 Tx 1 Tx42 Ty 1 2 Ty 3 CMD CKE DQ DQS Tm Tm 1 ime Ns Edi Tm 5 1 Tx42 Tx43 ec ci im d Tx 4 CMD CKE essence DQS Figure 49 Write to power down
30. bration EMR OCD calibration mode exit EMR OCD calibration mode exit Enter Adjust Mode Enter Adjust Mode BL 4 code input to all DQs BL 4 code input to all DQs Inc Dec or NOP Inc Dec or NOP EMR OCD calibration mode exit EMR OCD calibration mode exit EMR OCD calibration mode exit End Figure 7 OCD Impedence adjustment hyuix DDR2 Device Operations amp Timing Diagram Extended Mode Register for OCD impedance adjustment OCD impedance adjustment can be done using the following EMR mode In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is depedent on EMR bit enabling RDQS operation In Drive 1 mode all DQ DQS and RDQS signals are driven HIGH and all DQS signals are driven LOW In drive 0 mode all DQ DQS and RDQS signals are driven LOW and all DQS signals are driven HIGH In adjust mode BL 4 of operation code data must be used In case of OCD calibration default output driver charac teristics have a nominal impedance value of 18 during nominal temperature and voltage conditions Output driver characteristics for OCD calibration default are specified in Table x OCD applies only to normal full strength output drive setting defined by EMR 1 and if half strength is set OCD default output driver characteristics are not applicable When OCD calibration adjust mode is used OCD default output driver characteristics are not applicable After OCD calibration is
31. calibration i Pull up and pull down mis 0 4 Q 1 2 3 match Output slew rate Sout 1 5 5 V ns 1 4 5 6 7 8 1 Absolute Specifications 0 C lt lt tbd C VDD 1 8 0 1 VDDQ 1 8V 0 1V 2 Impedance measurement condition for output source dc current VDDQ 1 7V VOUT 1420mV VOUT VDDQ loh must be less than 23 4 O for values of VOUT between VDDQ and VDDQ 280mV Impedance measurement condition for output sink dc current VDDQ 1 7V VOUT 280mV VOUT Iol must be less than 23 4 Q for values of VOUT between OV and 280mV 3 Mismatch is absolute value between pull up and pull down both are measured at same temperature and voltage 4 Slew rate measured from vil ac to vih ac 5 The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC This is guaranteed by design and characterization 6 This represents the step size when the OCD is near 18 O at nominal conditions across all process corners variations and represents only the DRAM uncertainty A 0 value no calibration can only be achieved if the OCD impedance is 18 Q 0 75 under nominal conditions 7 DRAM output slew rate specification applies to 400MT s amp 533MT s speed bins 8 Timing skew due to DRAM output slew rate mis match between DQS DQS and associated DQs is included tDQSQ and tQHS specification 9 DDR2 SDRAM output slew rate test load is defined in Gene
32. changed using the same command and clock cycle require ments during normal operation as long as all banks are in the precharge state EMR 2 Programming Address Field 2 BAo 15 A13 A12 Extended Mode Register 2 A7 High Temp Self refresh Rate Enable 0 Disable 1 Enable Optional BA1 MR mode 0 0 MR DCC Enable Optional 4 0 1 EMR 1 0 Disable 1 0 EMR 2 1 Enable 1 1 EMR 3 Reserved _ 2 1 Partial Array Self Refresh for 8 banks Partial Array Self Refresh for 4 banks 0 0 0 Full Array Full Array 0 0 1 Half Array BA 2 0 000 001 010 amp 011 Half Array BA 1 0 00 amp 01 0 1 0 Quarter Array BA 2 0 000 amp 001 Quarter Array 1 0 00 0 1 1 1 8th Array BA 2 0 000 Not Defined 1 0 0 3 4 Array 2 0 010 011 100 101 110 amp 111 3 4 Array 1 0 01 108 11 1 0 1 Half Array BA 2 0 2100 101 1108 111 Half Array 0 10 amp 11 1 1 0 Quarter Array BA 2 0 2110 amp 111 Quarter Array 0 11 1 1 1 1 8th Array BA 2 0 111 Not Defined 1 The rest bits in EMR 2 are reserved for future use and all bits except A7 BAO and BA1 must be programmed to 0 when setting the mode register during initialization 2 Currently the periodic Self Refresh interval is hard coded whithin the DRAM to a specific
33. d state diagram hyuix DDR2 Device Operations amp Timing Diagram 1 2 Basic Function amp Operation of DDR2 SDRAM Read and write accesses to the DDR2 SDRAM are burst oriented accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence Accesses begin with the registration of an Active command which is then followed by a Read or Write command The address bits registered coinci dent with the active command are used to select the bank and row to be accessed BAO BA2 select the bank AO A15 select the row The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued Prior to normal operation the DDR2 SDRAM must be initialized The following sections provide detailed infor mation covering device initialization register definition command descriptions and device operation 1 2 1 Power up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner Operational procedures other than those specified may result in undefined operation Power up and Initialization Sequence The following sequence is required for POWER UP and Initialization 1 Apply power and attempt to maintain below 0 2 VDDQ and ODT at a LOW state all other inputs may be undefined VDD VDDL and VDDQ are driven from a single power converte
34. desired to be included 1 Reduced Strength 60 L A10 005 0 Enable 1 Disable 6 RDQS Enable 11 10 Strobe Function Matrix 0 Disable RDQS Enable 005 Disable RDQS DM RDQS Das 005 1 Enable 0 Disable 0 Enable DM Hi z DQS DQS 6 If RDQS is enabled the DM 0 Disable 1 Disable DM Hi z DQS Hi z function is disabled RDQS is active ERG for reads and don t care for writes 1 Eriaple RDOS RDQS DoS 288 1 Enable 1 Disable RDQS Hi z Das Hi z 1 and A13 A15 are reserved for future use and must be set to 0 when programming the EMR 1 Figure 4 EMR 1 programming hyuix DDR2 Device Operations amp Timing Diagram EMR 2 The extended mode register 2 controls refresh related features The default value of the extended mode reg ister 2 is not defined therefore the extended mode register 2 must be programmed during initialization for proper operation The extended mode register 2 is written by asserting LOW CS RAS CAS WE HIGH BA1 and LOW while controling the states of address pins AO A15 The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register 2 The mode register set command cycle time tMRD must be satisfied to complete the write operation to the extended mode register 2 Mode register contents can be
35. e 7 Notes 1 is the logic state of CKE at clock edge N N 1 was the state of CKE at the previous clock edge 2 Current state is the state of the DDR SDRAM immediately prior to clock edge N 3 COMMAND N is the command registered at clock edge N and ACTION N is a result of COMMAND N 4 All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document 5 On Self Refresh Exit DESELECT NOP commands must be issued on every clock edge occurring during the tysyr period Read commands may be issued only after txsrp 200 clocks is satisfied 6 Self Refresh mode can only be entered from the Banks Idle state 7 Must be a legal command as defined in the Command Truth Table 8 Valid commands for Power Down Entry and Exit are NOP and DESELECT only 9 Valid commands for Self Refresh Exit are NOP and DESELECT only 10 Power Down and Self Refresh can not be entered while Read or Write operations Extended Mode Register operations or Precharge operations are in progress See section 1 8 Power Down and 1 7 2 Self Refresh Command for a detailed list of restrictions 11 tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration Thus after any CKE transition CKE may not transition from its valid level during the time period of tIS 2
36. echarge Clarification From Com Minimum Delay between From To oomimsnd Command to To Command Notas Read Precharge to same Bank as Read AL max RTP 2 clks 1 2 Precharge All AL BL 2 max RTP 2 2 clks 1 2 Precharge to same Bank as Read w AP AL BL 2 max RTP 2 2 clks 1 2 Read w AP Precharge All AL BL 2 max RTP 2 2 clks 1 2 Writ Precharge to same Bank as Read WL BL 2 WR clks 2 rite Precharge All WL WR clks 2 Precharge to same Bank as Read WL BL 2 WR clks 2 Write w AP Precharge All WL WR clks 2 Precharge to same Bank as Read 1 clks 2 Precharge Precharge All 1 clks 2 Precharge 1 clks 2 Precharge All Precharge All 1 clks 2 Note 1 RTP cycles RU tRTP ns tCK ns where RU stands for round up tCK avg should be used in place of tCK for DDR2 667 800 Note 2 For a given bank the precharge period should be counted from the latest precharge command either one bank precharge or precharge all issued to that bank The precharge period is satisfied after tRP or tRPall tRP for 4 bank device tRP 1 tCK for 8 bank device depending on the latest precharge command issued to that bank Table 5 Precharge amp auto precharge clarification 1 7 Refresh Commands DDR2 SDRAMs require a refresh of all rows in any rolling 64 ms interval Each refresh is generated in one of two ways by an explicit Auto Refresh command or by an internally t
37. ent can be missed when CKE is raised for exit from Self Refresh mode Upon exit from Self Refresh the DDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh mode 41 hyuix DDR2 Device Operations amp Timing Diagram T1 T2 T3 T4 T5 T6 Tm Tn s dq 4 4 4 T t dog ow pO jd LED ME ME ICH tCL E d lu CK EH P p ra x gt CK AN m I m I m A li a B SEN gt a 3 gt gt gt T 5 tls EE PE TH tis EET MENSES vines ic CMD ae NOP NOP Valid rop oe ee a ocxcepoxes T po ee hk vu s i DL o ox T x Device must be in the All banks idle state prior to entering Self Refresh mode ODT must be turned off tAOFD before entering Self Refresh mode and can be turned on again when tXSRD timing is satisfied IXSRD is applied for a Read or a Read with autoprecharge command tXSNR is applied for any command except a Read or a Read with autoprecharge command Figure 45 Self refresh operation 42 hyuix DDR2 Device Operations amp Timing Diagram
38. entry TO T1 Tm Tm 1 Tm 2 Tm 3 Tx 1 2 3 Tx 4 5 Tx 6 CK TT BAS A AGN X TA m die g E PAT CK i e PRISES S d d CMD pag 7 ox 222 27 gt u DQS i Das i i i i TO T1 Tm 1 Tme2 ames Time TIPPS Tx 1 Tx 2 3 4 CK Start Internal Precharge CMD R rius E Ens i 1 DQS ped 4 WR is programmed through MR Figure 50 Write with Autoprecharge to power down entry 45 lau DDR2 Device Operations amp Timing Diagram TO T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CMD go to LOW one clock after an Auto refresh command CKE Figure 51 Refr sh command to power down entry CMD ACT can go to LOW one clock after an Active command CKE lis Figure 52 Active command to power down entry PR OKE go to LOW one clock after a or Precha ge all command CKE i i i i i i i i Figure 53 Precharge Precharge all command to power down entry CMD MR or tis r tMRD SF Figure 54 MR EMR command to power down entry 46 hyuix DDR2 Device Operations amp Timing Diagram 1 9 Asynchronous CKE LOW Event DRAM requires to be maintained HIGH for all valid o
39. f Refresh mode The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon exist ing Self Refresh When the DDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE are don t care The DRAM initiates a minimum of one Auto Refresh command internally within tCKE period once it enters Self Refresh mode The clock is internally disabled during Self Refresh Operation to save power The minimum time that the DDR2 SDRAM must remain in Self Refresh mode is tCKE The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered however the clock must be restarted and stable before the device can exit Self Refresh operation The procedure for existing Self Refresh requires a sequence of commands First the clock must be stable prior to CKE going back HIGH Once Self Refresh Exit command is registered a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device CKE must remain HIGH for the entire Self Refresh exit period tXSRD for proper operation Upon exit from Self Refresh the DDR2 SDRAM can be put back into Self Refresh mode after tXSRD expires NOP or deselect commands must be registered on each positive clock edge during the Self Refresh exit interval ODT should also be turned off during tXSRD The Use of Self Refresh mode introduce the possibility that an internally timed refresh ev
40. g auto precharge from the com pletion of the write burst may be reactivated if the following two conditions are satisfied 1 The data in to bank activate delay time WR tRP has been satisfied 2 The RAS cycle time tRC from the previous bank activation has been satisfied TO T1 T2 T3 T4 5 T6 T7 CK CK b f Stages essere se 19 1 i CME Post CAS NOP H NOP H NOP H NOP H NOP NO H NOP i Completion ofthe Burst Write Auto s ee 1 i Y if i WL RL 1 2 gt i tae DQs DNA DNA DNA DNA gt the i gt Figure 42 Burst Write with Auto Precharge tRC Limit WL 2 WR 22 BL 4 tRP 3 T4 T5 T6 T7 T8 T9 T12 CK CK T I i i Bank A ees H nor H nor H noe H nor 5 Completion of the Burst Write Auto i r 172 i e d e d i WL RU 1 4 i i gt WR gt 2 DQs DNA DNA DNA DNA gt tro Figure 43 Burst Write with Auto Precharge WR tRP WL 4 WR 2 BL 4 tRP 3 lau DDR2 Device Operations amp Timing Diagram E Precharge amp Auto Pr
41. gister 3 The default value of the extended mode register 3 is not defined therefore the extended mode register 3 must be programmed during initialization for proper opera tion EMR 3 Programming 2 15 Az An Ato Ae As Ao Address Field Extended Mode x1 oy 1 1 or Register 2 71 All bits in EMR 3 except BAO BA1 are reserved for future use and must be programmed to 0 when setting the mode register during initialization Figure 6 EMR 3 programming lau DDR2 Device Operations amp Timing Diagram 1 2 2 3 Off Chip Driver OCD Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence Every calibration mode command should be followed by OCD calibration mode exit before any other command being issued All MR should be programmed before entering OCD impedance adjustment and ODT On Die Termiantion should be carefully controlled depending on system environment All MR shoud be programmed before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment EMR OCD calibration mode exit EMR Drive 1 EMR Drive 0 DQ amp DQS HIGH DAS LOW DQ amp 00 LOW DOS HIGH Calibration Need Cali
42. hoot area See Figure 2 0 5V 0 5V 0 5V 0 5V Maximum overshoot area above VDDQ See Figure 2 0 38 V ns 0 28 V ns 0 23 V ns 0 23 V ns Maximum undershoot area below VSSQ See Figure 2 0 38 V ns 0 28 V ns 0 23 V ns 0 23 V ns DQ U L R DQS U L R DQS DM CK CK Maximum Amplitude Maximum Amplitude Overshoot Area Undershoot Area Table 18 AC Overshoot Undershoot Specification for Clock Data Strobe and Mask Pins Time ns Figure 60 AC overshoot and undershoot definition for clock data strobe and mask pinsns 56 lau DDR2 Device Operations amp Timing Diagram Power and ground clamps are required on the following input only pins 1 BAO BA2 2 A0 A15 3 RAS 4 CAS 5 WE 6 CS 7 ODT 8 CKE Voltage across Minimum Power Minimum Ground clamp V Clamp Current mA Clamp Current mA 0 0 0 0 0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0 6 0 0 0 7 0 0 0 8 0 1 0 1 0 9 1 0 1 0 1 0 2 5 2 5 1 1 4 7 4 7 1 2 6 8 6 8 1 3 9 1 9 1 1 4 11 0 11 0 1 5 13 5 13 5 1 6 16 0 16 0 1 7 18 2 18 2 1 8 21 0 21 0 Table 19 V I Characteristics table for input only pins with clamps 57 hyuix DDR2 Device Operations amp Timing Diagram _ 4 3 Output Buffer Characteristics 4 3 1 Output AC Test Conditions Symbol Parameter SSTL_18 Class II Unit
43. ifferential input voltage 0 5 VDDQ V 1 3 differential cross point voltage 0 5 VDDQ 0 175 0 5 VDDQ 0 175 V 2 1 ViN DC specifies the allowable DC execution of each input of differential pair such CK CK DQS DQS LDQS LDQS UDQS and UDQS 2 specifies the input differential voltage VTR VcP required for switching where VTR is the true input such as CK 005 LDQS or UDQS level and Vcr is the complementary input such as CK DQS LDQS or UDQS level The minimum value is equal to ViH DC V IL DC 3 Refer to Overshoot undershoot specifications for Vpeak value maximum peak amplitude allowed for overshoot adn undershoot Table 15 AC input test conditions VDDQ Crossing point Vix or Vox Vssa Notes 1 Vib AC specifies the input differential voltage VTR VcP required for switching where is the true input signal such as CK DQS LDQS or UDQS and Vcr is the complementary input signal such as CK DQS LDQS UDQS The minimum value is equal to V iH AC VIL AC 2 The typical value of is expected to be about 0 5 VDDQ of the transmitting device and Vix Ac is expected to track variations in VDDQ Vix AC indicates the voltage at which differential input signals must cross Figure 58 Differential signal levels 4 2 5 Differential AC output parameters Symbol Parameter Min Max Units Notes
44. ime is called tRTP Read to Precharge For BL 4 this is the time from the actual read AL after the Read command to Precharge com mand For BL 8 this is the time from AL 2 clocks after the Read to the Precharge command 31 hyuix DDR2 Device Operations amp Timing Diagram TO T1 T2 T3 T4 T5 T6 T7 T8 M M M M wp LA LA A AR AAA AA 1 f p X p C NOP W NOP Preetaroe H NOP H NOP H NOP H potio H NOP AL 2 ciks gt 1 1 1 1 1 1 i EN ipe i i DQS DQS 1 1 1 1 h 1 1 1 1 1 1 1 1 gt tgp 1 AL 1 inb i i i gt RL 4 4 i DQ s DOUTA DOUTA DOUTA DOUTA i i sue DE i i i sk i 3 gt RTP gt Figure 31 Example 1 Burst Read Operation Followed by Precharge RL 4 AL 1 CL 3 BL 4 lt 2 clocks mPXTXIXIErrrixixiri om EY NOP W NOP RETE i 1 08 598 I EN 1 1 1 1 Y J I i 1 1 ALL 1 CL 3 gt i i i i RL 4 gt i i DQ s DOUTA 2074 DOUT A DOUTA DOUTA _ A gt RTP yl first 4 bit prefetch second 4 bit prefetch
45. imed event in SELF REFRESH mode Dividing the number of device rows into the rolling 64ms interval tREFI which is a guideline to controllers for distributed refresh timing For example a 512Mb DDR2 SDRAM has 8192 rows resulting in tREFI of 7 8 To avoid excessive interruptions to the memory controller higher density DDR2 SDRAMS maintain 7 80 average refresh time and perform multiple internal refresh bursts In these cases the refresh recovery times tRFC an tXSNR are extended to accomodate these internal operations 1 7 1 Auto Refresh Command AUTO REFRESH is used during normal operation of the DDR2 SDRAM This command is nonpersistent so it must be issued each time a refresh is required The refresh addressing is generated by the internal refresh controller This makes the address bits Don t Care during an AUTO REFRESH command When CS RAS and CAS are held LOW and WE HIGH at the rising edge of the clock the chip enters the Refresh mode REF All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the Pre charge time tRP before the Refresh command REF can be applied An address counter internal to the device supplies the bank address during the refresh cycle No control of the external address bus is required once this cycle has started When the refresh cycle has completed all banks of the DDR2 SDRAM will be in the precharged idle state A delay between the Refresh command REF and the next Activate comma
46. ion included on all DQs DM DQS DQS RDQS and RDQS pins Figure 10 Functional representation of ODT lau DDR2 Device Operations amp Timing Diagram ODT timing for active standby mode TO T1 T2 T3 T4 T5 T6 CKE i IS s ODT VIH ac ViL ac tAOFD tAOND lt Internal Term Res tAON min tAON max lt tAOF max Figure 11 ODT timing for active standby mode ODT timing for powerdown mode TO T2 T3 T4 T5 T6 CR pas CK oU ey y TY tIS tIS lt ODT ViH ac ViH ac gt tAOFPD min gt Internal R Term Res d tAONPD ming gt AONPD max a gt Figure 12 ODT timing for powerdown mode lau DDR2 Device Operations amp Timing Diagram ODT timing mode switch at entering power down mode ntering Slow Exit Active Power Down Mode or Precharge Power Down Mode ODT ViL ac Active amp Standby mode timings to Internal be applied Term Res ODT V Power Down mode timings to Internal be applied Term Res 15 4 ODT Active amp Standby Internal mode timings to Term Res RTT be applied ODT Po
47. ition 52 hyuix DDR2 Device Operations amp Timing Diagram 4 AC amp DC Operating Conditons 4 1 DC Operation Conditions 4 1 1 Recommended DC Operating Conditions SSTL 1 8 Rating Symbol Parameter Units Notes Min Typ Max VDD Supply Voltage 1 7 1 8 1 9 V 1 VDDL Supply Voltage for DLL 1 7 1 8 1 9 V 5 VDDQ Supply Voltage for Output 1 7 1 8 1 9 V 1 5 VREF Input Reference Voltage 0 49 VDDQ 0 50 VDDQ 0 51 VDDQ mV 2 3 VTT Termination Voltage VREF 0 04 VREF VREF 0 04 V 4 1 There is no specific device VDD supply voltage requirement SSTL 1 8 compliance However under all conditions VDDQ must be less than or equal to VDD 2 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 3 Peak to peak ac noise on VREF may not exceed 2 VREF dc 4 VTT of transmitting device must track VREF of receiving device 5 VDDQ tracks with VDD VDDL tracks with VDD AC parameters are measured with VDD VDDQ and VDDDL tied together 4 1 2 ODT DC electrical characteristics Table 11 REcommended DC operating conditions SSTL 1 8 PARAMETER CONDITION SYMBOL MIN NOM MAX UNITS NOTES Rit effective impedance value for EMRS A6 A2 0 1 75 Rtt1 eff 60 75 90 Q 1 Rtt effective i
48. k for BL 4 operation every four clocks for BL 8 operation This operation is allowed regardless of same or different banks as long as the banks are activated 28 hyuix DDR2 Device Operations amp Timing Diagram Writes interrupted by a write Burst write can only be interrupted by another write with 4 bit burst boundary Any other case of write interrupt is not allowed CKICR XX gt X Xx XX XX XX XX CMD NOP Write A NOP Write B NOP NOP NOP NOP NOP NOP CX X OX XX X OX XX XX XO Das lt AX 1 2 BOX 1 B3 X X BS X B6 X B7 Notes 1 Write burst interrupt function is only allowed on burst of 8 Burst interrupt of 4 is prohibited 2 Write burst of 8 can only be interrupted by another Write command Write burst interruption by Read command or Precharge command is prohibited 3 Write burst interrupt must occur exactly two clocks after previous Write command Any other Write burst interrupt timings are prohibited Write burst interruption is allowed to any bank inside DRAM Write burst with Auto Precharge enabled is not allowed to interrupt Write burst interruption is allowed by another Write with Auto Precharge command All command timings are referenced to burst length set in the mode register They are not referenced to actual burst For example minimum Write to Precharge timing is WL BL 2 WR where WR starts
49. k prior to the WL first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble The tDQSS specification must be satisfied for write cycles The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed which is 4 or 8 bit burst When the burst has finished any additional data supplied to the DQ pins will be ignored The DQ Signal is ignored after the burst write operation is complete The time from the completion of the burst write to bank precharge is the write recovery time WR DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMR Enable DQS mode bit timing advantages of differential mode are realized in system design The method by which the DDR2 SDRAM pin timings are measured is mode dependent In single ended mode timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF In differential mode these timing relationships are measured relative to the crosspoint of DQS and its com plement DQS This distinction in timing methods is guaranteed by design and characterization Note that when differential data strobe mode is disabled via the EMR the complementary pin DQS must be tied exter nally to VSS through a 20 O to 10 KO resistor to insure proper operation toast DQS BS x pos ud x
50. lau DDR2 Device Operations amp Timing Diagram DDR2 SDRAM Device Operation amp Timing Diagram hyuix DDR2 Device Operations amp Timing Diagram Contents 1 Functional Description 1 1 Simplified State Diagram 1 2 Basic Function amp Operation of DDR2 SDRAM 1 2 1 Power up and Initialization 1 2 2 Programming the Mode and Extended Mode Registers 1 2 2 1 DDR2 SDRAM Mode Register MR 1 2 2 2 DDR2 SDRAM Extended Mode Register 1 2 2 3 Off Chip Driver OCD Impedance Adjustment 1 2 2 4 ODT On Die Termination 1 3 Bank Activate Command 1 4 Read and Write Command 1 4 1 Posted CAS 1 4 2 Burst Mode Operation 1 4 3 Burst Read Command 1 4 4 Burst Write Operation 1 4 5 Write Data Mask 1 5 Precharge Operation 1 6 Auto Precharge Operation 1 7 Refresh Commands 1 7 1 Auto Refresh Command 1 7 2 Self Refresh Command 1 8 Power Down 1 9 Asynchronous CKE LOW Event 1 10 No Operation Command 1 11 Deselect Command 2 Truth Tables 2 1 Command Truth Table 2 2 Clock Enable CKE Truth Table for Synchronous Transistors 2 3 Data Mask Truth Table 3 Maximum DC Ratings 3 1 Absolute Maximum DC Ratings 3 2 Operating Temperature Condition 4 AC amp DC Operating Conditions 4 1 DC Operation Conditions 4 1 1 Recommended DC Operating Conditions SSTL 1 8 4 1 2 ODT DC Electrical Characteristics 4 2 DC amp AC Logic Input Levels 4 2 1 Input DC Logic Level 4 2 2 Input AC Logic Level 4 2 3 AC Input Test Conditions 4 2 4 Differential Input
51. ly a subset of the MR or EMR variables all variables within the addressed register must be redefined when the MRS or EMRS commands are issued MR EMR and Reset DLL do not affect array contents which means reinitialization including those can be executed any time after power up without affecting array contents lau DDR2 Device Operations amp Timing Diagram 1 2 2 1 DDR2 SDRAM Mode Register MR The mode register stores the data for controlling the various operating modes of DDR2 SDRAM It controls CAS latency burst length burst sequence test mode DLL reset WR and various vendor specific options to make DDR2 SDRAM useful for various applications The default value of the mode register is not defined therefore the mode register must be programmed during initialization for proper operation The mode register is written by asserting LOW on CS RAS CAS WE BAO BA1 while controlling the state of address pins A15 The DDR2 SDRAM should be in all bank precharge with already HIGH prior to writing into the mode register The mode register set command cycle time is required to complete the write operation to the mode register The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state The mode register is divided into various fields depending on functionality Burst length is defined by AO A2 with opti
52. m the burst read command to the burst write command is defined by a read to write turn around time which is 4 clocks in case of BL 4 operation 6 clocks in case of BL 8 operation 23 hyuix DDR2 Device Operations amp Timing Diagram TO T1 T2 T4 5 T6 T7 T3 T8 Y Y Ee 1 1 1 1 i meme H nor H wor H noe H Hm 7 095 595 poc gt i 5 gt m DQs DOUT Ay DOUTA AL 2 DOUT A DOUTA DOUTB DOUT Bj Figure 22 Seamless burst read operation RL 5 AL 2 and CL 3 BL 4 The seamless burst read operation is supported by enabling a read command at every other clock for BL 4 operation and every 4 clock for BL 8 operation This operation is allowed regardless of same or different banks as long as the banks are activated 24 hyuix DDR2 Device Operations amp Timing Diagram Reads interrupted by a read Burst read can only be interrupted by another read with 4 bit burst boundary Any other case of read interrupt is not allowed XK XX XX XXXXXXXXXXxXxx2 008 595 EN CMD lt Road S NOP n 8 X NOP c gt XX XK KK KKK XK A0 A2 X X Bo X B1 B2X B3 B4 X B5
53. mpedance value for EMRS A6 A2 1 0 150 Rtt2 eff 120 150 180 1 Rtt effective impedance value for EMRS A6 A2 1 1 50 Q Rtt2 eff 40 50 60 1 2 Deviation of VM with respect to VDDQ 2 AVM 6 46 96 1 Note 1 Test condition for Rtt measurements 2 Optional for DDR2 400 533 667 mandatory for DDR2 800 Measurement Definition for Rtt eff Apply ac and ac to test pin separately then measure current ac and I ac respectively ac ac and VDDQ values defined in SSTL_18 ac Rtt eff Measurement Definition for VM Measurement Voltage at test pin mid point with no load 2xVm VDDQ AVM 1 x100 Table 12 PDDT DC electrical characteristics 53 lau DDR2 Device Operations amp Timing Diagram 4 2 DC amp AC Logic I nput Levels 4 2 1 Input DC Logic Level Symbol Parameter Min Max Units Notes Viu dc dc input logic HIGH VREF 0 125 VDDQ 0 3 V dc dc input logic LOW 0 3 VREF 0 125 V Table 13 Input DC logic level 4 2 2 Input AC Logic Level DDR2 400 DDR2 533 DDR2 667 DDR2 800 Symbol Parameter Units Notes Min Max Min Max Vin ac ac input logic HIGH VREF 0 250 VDDQ Vpeak VREF 0 200 VDDQ Vpeak V 1 ac ac input logic LOW VSSQ Vpeak VREF 0 250 VSSQ Vpeak VREF 0 200 V 1 Notes 1
54. n in phase with the DQS signal in a source synchro nous manner The RL is equal to an additive latency AL plus CAS latency CL The CL is defined by the Mode Register MR similar to the existing SDR and DDR SDRAMs The AL is defined by the Extended Mode Register 1 EMR 1 DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMR 1 Enable DQS mode bit timing advantages of differential mode are realized in sys tem design The method by which the DDR2 SDRAM pin timings are measured is mode dependent In single ended mode timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF In differential mode these timing relationships are measured relative to the crosspoint of DQS and its com plement DQS This distinction in timing methods is guaranteed by design and characterization Note that when differential data strobe mode is disabled via the EMR the complementary pin DQS must be tied exter nally to VSS through a 20 O to 10 KO resistor to insure proper operation teL AED X X X DQS DQS DA s ipasamax Figure 18 Data output read timing ipasamax TO T2 T3 T4 T5 T6 T7 T8 T1 CK CK 1 7 f f f Po e a a A A a P d TAS l CMD po DA NOP H NOP H NOP H NOP H NOP H NOP H NOP H NOP V Y WE i
55. nd or subsequent Refresh com mand must be greater than or equal to the Refresh cycle time tRFC 40 hyuix DDR2 Device Operations amp Timing Diagram To allow for improved efficiency in scheduling and switching between tasks some flexibility in the absolute refresh interval is provided A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 9 tREFI Ti T2 T3 Tm Tn Tn 1 o Y 5 I 1 1 1 B 1 1 por cuo eda ur EN me um dec E Ro detis x ode 3 CKE eet gt N gt targ 2 CM Precharge H NOP H a E H H Figure 44 Refresh command 1 7 2 Self Refresh Operation The Self Refresh command can be used to retain data in the DDR2 SDRAM even if the rest of the system is powered down When in the Self Refresh mode the DDR2 SDRAM retains data without external clocking The DDR2 SDRAM device has a built in timer to accommodate Self Refresh operation The Self Refresh Command is defined by having CS RAS CAS and CKE held LOW with WE HIGH at the rising edge of the clock ODT must be turned off before issuing Self Refresh command by either driving ODT pin LOW or using EMR command Once the Command is registered CKE must be held LOW to keep the device in Sel
56. ndow Converting to clocks is done by dividing tFAW ns by tCK ns or tCK avg ns depending on the speed bin and rounding up to next integer value As an example of the rolling window if tFAW tCK or tFAW tCK avg rounds up to 10 clocks and an activate command is issued in clock N no more than three further activate commands may be issued at or betwen clock N 1 through N 9 8 bank device Precharge All Allowance tRP for a Precharge All command for an 8 Bank device will equal to tRP 1 tCK or tnRP 1 nCK depending on the speed bin where tnRP tRP tCK avg rounded up to the next interger where tRP is the value for a single bank pre charge Tn 1 Tn 2 Tn 3 ve Internal RAS CAS delay gt gt Bank Bank Bank BankB Bank A mm B BankA ADDRESS E Adar H Col Addr H Row H Col Addr 7 Addr Addr Row Addr CAS CAS delay time Coco t additive latency y delay a gt Read Begins gt RAS RAS delay time gt theo Bank A Bancs Bank B _ COMMAND Activate E dc oe Activate PostCas Precharge Precharge Activate H or L Bank Active gt tras Bank Precharge time gt tap RAS Cycle time gt tac Figure 15 Bank active command cycle tRCD 3 AL 2 tRP 3 tRRD 2 tcCD 2 hyuix D
57. ns amp Timing Diagram If OCD calibration is not used EMR OCD Default command A9 A8 A7 1 followed by EMR OCD Calibra tion Mode Exit command A9 A8 A7 0 must be issued with other operating parameters of EMR 13 The DDR2 SDRAM is now ready for normal operation 1 To guarantee ODT off VREF must be valid and a LOW level must be applied to the ODT pin 2 Sequence 5 and 6 may be performed between 8 and 9 Initialization Sequence after Power Up E u OOOO Follow Flowchart ODT i L L L L L command EEEIEE DEX St ee p tRFC t tMRD 1 RESET Default CAL MODE Figure 2 Initialization sequence after power up 1 2 2 Programming the Mode and Extended Mode Registers For application flexibility burst length burst type CAS latency DLL reset function write recovery time WR are user defined variables and must be programmed with a Mode Register Set MRS command Additionally DLL disable function driver impedance additive CAS latency ODT On Die Termination single ended strobe and OCD off chip driver impedance adjustment are also user defined variables and must be pro grammed with an Extended Mode Register Set EMRS command Contents of the Mode Register MR or Extended Mode Registers EMR can be altered by re executing the MRS and EMRS Commands Even if the user chooses to modify on
58. o precharge each bank independently or all banks simultaneously Three address bits A10 BAO and BA1 for 512Mb and four address bits A10 BAO BA2 for 1Gb and higher densities are used to define which bank to precharge when the command is issued For 8 bank devices refer to Bank Active section of this data sheet A10 BA2 BA1 BAO Precharged Bank s Remarks LOW LOW LOW LOW Bank 0 only LOW LOW LOW HIGH Bank 1 only LOW LOW HIGH LOW Bank 2 only LOW LOW HIGH HIGH Bank 3 only LOW HIGH LOW LOW Bank 4 only 1Gb and higher LOW HIGH LOW HIGH Bank 5 only 1Gb and higher LOW HIGH HIGH LOW Bank 6 only 1Gb and higher LOW HIGH HIGH HIGH Bank 7only 1Gb and higher HIGH DON T CARE DON T CARE DON T CARE All Banks Table 4 Bank selection for precharge by address bits Burst Read Operation Followed by Precharge Minimum Read to precharge command spacing to the same bank AL BL 2 max RTP 2 2 clocks For the earliest possible precharge the precharge command may be issued on the rising edge which is Additive latency AL BL 2 max RTP 2 2clocks after a Read command A new bank active command may be issued to the same bank after the RAS precharge time tap precharge command cannot be issued until tras is satisfied The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock egde that initiates the last 4 bit prefetch of a Read to Precharge command This t
59. ons of 4 and 8 bit burst lengths The burst length decodes are compatible with DDR SDRAM Burst address sequence type is defined by CAS latency is defined by A4 The DDR2 doesn t support half clock latency mode A7 is used for test mode A8 is used for DLL reset A7 must be set to LOW for normal MR operation Write recov time WR is defined by A9 A11 Refer to the table for specific codes BA2 BA BAo A15 12 A11 A7 As M 2 At Ao Address Field 11111001111 olo PD WR DLL CAS Latency BurstLength Mode Register m 8 DLL Reset A7 mode Burst rype Burst Length 0 No 0 Normal 0 Sequential A2 Ai BL 1 Yes 1 Test 1 Interleave 0 1 0 4 0 1 1 8 Y Y E RENO Rael Write recovery for autoprecharge CAS Latency down exit time 11 10 9 WR cycles 5 4 Latency 0 Fast exit use tXARD 0 0 0 Reserved 0 0 0 Reserved 1 Slow exit use tXARDS 0 0 1 2 9 ilo 0 0 1 Reserved 0 1 3 N 2 9 2 optional 1 BAO MR AJA 5 Alola 1 Sispesd bin mode 1 5 determined 0 0 MR 1 1 6 1 o 4 0 1 EMR 1 1 1 0
60. owing timing diagram Enter Drive mode OCD calibration mode exit evn 5 nor 5 nor 5 nor CK X f f iE CK O A 7 XN KK Xe PN HN PN Hi Z Hi Z pas Kos HIGH amp DOS LOW for Drive 1 20 LOW amp DQS HIGH for DQs HIGH for Drive 1 DQ DQs LOW for Drive 0 gt c M lt tOIT tOIT Figure 9 OCD drive mode hyuix DDR2 Device Operations amp Timing Diagram 1 2 2 4 ODT On Die Termination On Die Termination ODT is a feature that allows a DRAM to turn on off termination resistance for each DQ DQS DQS RDQS RDQS and DM signal for x4x8 configurations via the ODT control pin For x16 configura tion ODT is applied to each DQ UDQS UDQS LDQS LDQS UDM and LDM signal via the ODT control pin The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM con troller to independently turn on off termination resistance for any or all DRAM devices The ODT function is supported for ACTIVE and STANDBY modes ODT is turned off and not supported in SELF REFRESH mode FUNCTIONAL REPRESENTATION OF ODT VDDQ VDDQ VDDQ sw1 ewe Ned Rval1 Rval2 Rval va 2 2 val3 DRAM Input Prod Buffer sw1 sw2 VssQ VssQ VssQ Switch sw1 sw2 sw3 is enabled by ODT pin Selection among sw1 sw2 and sw3 is determined by Rtt nominal in EMR Terminat
61. perations as defined in this data sheet If asynchronously drops LOW during any valid operation DRAM is not guaranteed to preserve the contents of array If this event occurs memory controller must satisfy DRAM timing specification tDelay before turning off the clocks Stable clocks must exist at the input of DRAM before is raised HIGH again DRAM must be fully re initialized steps 4 thru 13 as described in initializaliation sequence DRAM is ready for normal opera tion after the initialization sequence See AC timing parametric table for tDelay specification Stable clocks asynchronously drops LOW Clocks can be turned off after this point Figure 55 Asynchronous CKE LOW event 47 hyuix DDR2 Device Operations amp Timing Diagram Input Clock Frequency Change during Precharge Power Down DDR2 SDRAM input clock frequency can be changed under following condition DDR2 SDRAM is in precharged power down mode ODT must be turned off and CKE must be at logic LOW level A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change SDRAM input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade During input clock frequency change ODT and CKE must be held at stable LOW levels Once input clock frequency is changed stable new clocks must be provided to DRAM before precharge power down may be
62. posck DQS DGS i X RL 5 gt DQs une DOUT A Figure 19 Burst read operation RL 5 AL 2 CLz3 BL 4 IES 22 hyuix DDR2 Device Operations amp Timing Diagram TD A i T READ H NOP H NOP H NOP H NOP H NOP H NOP H NOP H NOP A Wr a m dc DQS DQS 7 i i i 1 cil 1 1 CL 3 DOUTA RL 3 Figure 20 Burst read operation RL 23 AL 0 CL 3 BL 8 gt i DQs ZA ror ror TO T1 Tn 1 Tn 1 Tn 2 Tn 3 Tn 4 Tn 5 7 m fe x 58884 ic NOP yap NOP NOP ip NOP NOP 5 tatw Read tq Write turn time zn i i i MO MO essay j X X gu Ad Ll 5 C i lt DQ s mrs 2 4 DINA DNA Sw ERE Ss _ Figure 21 Burst read followed by burst write RL 5 WL RL 1 4 BL 4 The minimum time fro
63. r output AND VTT is limited to 0 95 V max AND Vref tracks VDDQ 2 or Apply VDD before or at the same time as VDDL Apply VDDL before or at the same time as VDDQ Apply VDDQ before or at the same time as VTT amp Vref at least one of these two sets of conditions must be met Start clock and maintain stable condition a 3 For the minimum of 200 us after stable power and clock CK CK then apply NOP or deselect amp take CKE HIGH 4 Wait minimum of 400ns then issue precharge all command NOP or deselect applied during 400ns period 5 Issue EMRS command to EMR 2 To issue EMRS command to EMR 2 provide LOW to BAO and 2 HIGH to BA1 6 Issue EMRS command to EMR 3 To issueEMRS command to EMR 3 provide LOW to BA2 HIGH to BAO and BA1 2 7 Issue EMR to enable DLL To issue DLL Enable command provide LOW to HIGH to BAO and LOW to BA1 2 and A13 A15 And A9 A8 A7 LOW must be sued when issuing this command 8 Issue a Mode Register set command for DLL reset To issue DLL reset command provide HIGH to A8 and LOW to BAO 2 and A13 15 9 Issue precharge all command 10 Issue 2 or more auto refresh commands 11 Issue a mode register command with LOW to A8 to initialize device operation i e to program operating parameters without resetting the DLL 12 At least 200 clocks after step 8 execute OCD Calibration Off Chip Driver impedance adjustment hyuix DDR2 Device Operatio
64. ral Note 3 of the AC Timing specification Table in Hynix DDR2 SDRAM component datasheet Table 22 Output DC current drive 4 4 Default Output characteristics DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the bits A7 A9 111 The above Figures show the driver characteristics graphically and tables show the same data in tabular format suitable for input into simulation tools Default Output Driver Charcateristic Curves Notes 1 The full variation in driver current from minimum to maximum process temperature and voltage will lie within the outer bounding lines of the V I curve of the following related Figures 2 Itis recommended that the typical IBIS V I curve lie within the inner bounding lines of the V I curves of the following related Figures 59 lau DDR2 Device Operations amp Timing Diagram 4 4 1 Full Strength Default Pulldown Driver Characteristics Pulldown Current mA Minimum Nominal Default Nominal Default Maximum 23 4 Ohms Low 18 ohms High 18 ohms 12 6 Ohms Table 23 Full strength default pulldown driver characteristics 120 T 100 Maximum 80 Nominal Default 60 High E Nominal 2 TU Default Low 20 gt Minimum O 2 0 4 O 6 O 8 1 0 1 2 1 4 1 6 1 8 3 0 5 0 7 0 9 1 1 1 3 1 5 1 7 1 9 VOUT to VSSQ Figure
65. riation could be as much as from the nominal minimum to the nominal maximum or vice versa The driver characteristics evaluation conditions are Nominal 25 T case VDDQ 1 8 V typical process b Nominal Low and Nominal High 25 T case VDDQ 1 8 V any process c Nominal Minimum TBD T case VDDQ 1 7 V any process d Nominal Maximum 0 T case VDDQ 1 9 V any process Calibrated Pulldown Current mA Nominal Nominal Nominal Nominal Minimum Low Nominal High Maximum 21 ohms 18 75 ohms 18 ohms 17 25 ohms 15 ohms Calibrated Pullup Current mA Nominal Nominal Nominal Nominal Minimum Low Nominal High Maximum 18 75 ohms LLL 17 25 ohms 15 ohms Table 26 Full strength calibrated pullup driver characteristics 62
66. river strength 0 0 0 0 NOP No operation NOP No operation 0 0 0 1 Increase by 1 step NOP 0 0 1 0 Decrease by 1 step NOP 0 1 0 0 NOP Increase by 1 step 1 0 0 0 NOP Decrease by 1 step 0 1 0 1 Increase by 1 step Increase by 1 step 0 1 1 0 Decrease by 1 step Increase by 1 step 1 0 0 1 Increase by 1 step Decrease by 1 step 1 0 1 0 Decrease by 1 step Decrease by 1 step Other Combinations Reserved Table 2 OCD adjust mode program hyuix DDR2 Device Operations amp Timing Diagram For proper operation of adjust mode WL RL 1 AL CL 1 clocks and tDS tDH should be met as the fol lowing timing diagram For input data pattern for adjustment DTS is a fixed order and not affected by MR addressing mode ie sequential or interleave OCD adjust mode OCD calibration mode exit aio ue a eo my Cor CK py ow pc gt WL DOS WR DOS in 10 Dri X Dra M D Q in Xen i ac Va do Figure 8 OCD adjust mode T Y DM Drive Mode Drive mode both Drive 1 and Drive 0 is used for controllers to measure DDR2 SDRAM Driver impedance In this mode all outputs are driven out tOIT after enter drive mode command and all output drivers are turned off tOIT after DCD calibration mode exit command as the foll
67. s Notes Output Timing Measurement Reference Level 0 5 VDDQ V 1 1 The VDDQ of the device under test is referenced Table 20 Output AC test conditions 4 3 2 Output DC Current Drive Symbol Parameter SSTI 18 Units Notes Output Minimum Source DC Current 13 4 1 3 4 Output Minimum Sink DC Current 13 4 mA 2 3 4 1 1 7 V Voyt 1420 mV Vout Vppo lou must be less than 21 Q for values of between and 280 mV 2 1 7 V Vout 280 mV must be less than 21 Q for values of between 0 V and 280 mV The dc value of applied to the receiving device is set to 4 values of and loi are based on the conditions given in Notes 1 2 They are used to test device drive current capability to ensure min plus a noise margin and max minus a noise margin are delivered to an SSTL_18 receiver The actual current values are derived by shifting the desired driver operating point see Section 3 3 along a 21 Q load line to define a convenient driver current for measurement e Table 21 Output DC current drive 58 hyuix DDR2 Device Operations amp Timing Diagram HEN 4 3 3 OCD default characteristics Description Parameter Min Nom Max Unit Notes Output impedance 12 6 18 23 4 Q 1 2 Output impedance step size for OCD
68. s pins AO A15 The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register 1 The mode register set command cycle time tMRD must be satisfied to com plete the write operation to the extended mode register 1 Mode register contents can be changed using the same com mand and clock cycle requirements during normal operation as long as all banks are in the precharge state AO is used for DLL enable or disable A1 is used for enabling a half strength output driver A3 A5 determines the additive latency 7 9 are used for OCD control A10 is used for DQS disable and A11 is used for RDQS enable A2 and are used for ODT setting DLL Enable Disable The DLL must be enabled for normal operation DLL enable is required during power up initialization and upon returning to normal operation after having the DLL disabled The DLL is automatically disabled when entering self refresh operation and is automatically re enabled upon exit of self refresh operation Any time the DLL is enabled and subsequently reset 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK param eters lau DDR2 Device Operations amp Timing Diagram
69. sued then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence If A10 is HIGH when the Read or Write com mand is issued then the auto precharge function is engaged During auto precharge a Read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is CAS latency CL clock cycles before the end of the read burst Auto precharge is also implemented during Write commands The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array This feature allows the precharge operation to be partially or completely hidden during burst read cycles dependent upon CAS latency thus improving system performance for random data access The RAS lock out circuit internally delays the Precharge operation until the array restore operation has been completed tRAS satisfied so that the auto precharge command may be issued with any read or write command Burst Read with Auto Precharge If A10 is HIGH when a Read Command is issued the Read with Auto Precharge function is engaged The DDR2 SDRAM starts an Auto Precharge operation on the rising edge which is AL BL 2 cycles later than the read with AP command if tRAS min and tRTP min are satisfied If tRAS min is not satisfied at the edge the start point of auto precharge operation
70. tCKE 12 The state of ODT does not affect the states described in this table The ODT function is not available during Self Refresh See section 1 2 2 4 13 The Power Down does not perform any refresh operations The duration of Power Down Mode is therefore limited by the refresh requirements out lined in section 1 2 2 14 CKE must be maintained HIGH while the SDRAM is in OCD calibration mode 15 X means don t care including floating around VREF in Self Refresh and Power Down However ODT must be driven HIGH or LOW in Power Down if the ODT fucntion is enabled Bit A2 or set to 1 EMR 1 16 Vref must be maintained during Self Refresh operation Table 7 Clock enable CKE truth table for synchronous transitions 2 3 Data Mask Truth Table Name Functional DM DQs Note Write enable L Valid 1 Write inhibit H X 1 1 Used to mask write data provided coincident with the corresponding data Table 8 Data mask truth table 51 hyuix DDR2 Device Operations amp Timing Diagram 3 Maximum DC Ratings 3 1 Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss 10V 23V V 1 3 VDDQ Voltage on VDDQ pin relative to Vss 05V 23V V 1 3 VDDL Voltage on VDDL pin relative to Vss 0 5V 2 3V V 1 3 Vw Voltage on any pin relative to Vss 0 5V 23V V 1 Storage Temperature 55 to 100
71. upon For E MR BA selects an Extended Mode Register 3 Burst reads or writes at BL 4 cannot be terminated or interrupted See sections Reads interrupted by a Read and Writes inter rupted by a Write in section 1 4 for details 4 The Power Down Mode does not perform any refresh operations The duration of Power Down is therefore limited by the refresh requirements outlined in section 1 2 2 5 The state of ODT does not affect the states described in this table The ODT function is not available during Self Refresh See section 1 2 2 4 6 X means or L but a defined logic level 7 Self refresh exit is asynchronous 8 VREF must be maintained during Self Refresh operation Table 6 Command truth table 50 hyuix DDR2 Device Operations amp Timing Diagram _ 2 2 Clock Enable Truth Table for Synchronous KE Command 3 2 3 Current State previous Cycle Current Cycle RAS CAS WE CS Action N Notes N 1 N L L X Maintain Power Down 11 13 15 Power Down L H DESELECT or NOP Power Down Exit 4 8 11 13 L L X Maintain Self Refresh 11 15 Self Refresh L H DESELECT or NOP Self Refresh Exit 4 5 9 16 Bank s Active H L DESELECT or NOP Active Power Down Entry 4 8 10 11 13 H L DESELECT or NOP Precharge Power Down Entry 4 8 10 11 13 All Banks Idle H L REFRESH Self Refresh Entry 6 9 11 13 H H Refer to the Command Truth Tabl
72. wed one reads interrupted by a read the other writes interrupted by a write with 4 bit burst boundry respectively The minimum CAS to CAS delay is defined by tCCD and is a minimum of 2 clocks for read or write cycles hyuix DDR2 Device Operations amp Timing Diagram 1 4 1 Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM In this operation the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command or any time during the RAS CAS delay time tRCD period The command is held for the time of the Additive Latency AL before it is issued inside the device The Read Latency RL is controlled by the sum of AL and the CAS latency CL Therefore if a user chooses to issue a R W command before the tRCDmin then AL greater than 0 must be written into the EMR 1 The Write Latency WL is always defined as RL 1 read latency 1 where read latency is defined as the sum of additive latency plus CAS latency RL AL CL Read or Write operations using AL allow seamless bursts refer to semaless operation timing diagram examples in Read burst and Wirte burst section Examples of posted CAS operation 1 0 1 2 3 4 5 6 7 8 9 10 n 12 ee CMD guo NE NE 7 DQS DQS e dm Fri Figure 16 Example 1 Re
73. wer Down tAONPD vi 4 mode timings to Internal be applied Term Res RIL Figure 13 ODT timing mode switch at entering power down mode lau DDR2 Device Operations amp Timing Diagram ODT timing mode switch at exiting power down mode TO T1 T4 T5 T6 T7 T8 T9 T10 T11 us tAXPD CKE VIH ac xiting trom Slow Active Power Down Mode or Precharge Power Down Mode Active amp Standby VIL ac s mode timings to tAOFD be applied Internal RTT Term Res ts Power Down ODT mode timings to tA FPDmax be applied Internal Term Res RTT y Active amp Standby ODT ViH ao mode timings to tAOND be applied 4 1 Internal RTT Term Res tIS ViH ad Power Down SET mode timings to _ AONPDmax be applied nternal RTT Term Res Figure 14 ODT timing mode switch at exiting power down mode hyuix DDR2 Device Operations amp Timing Diagram 1 3 Bank Activate Command The Bank Activate command is issued by holding CAS and WE HIGH with CS and RAS LOW at the rising edge of the clock The bank addresses BAO BA2 are used to select the desired bank The row address AO through A15 is used to determine which row to activate in the selected bank The
74. will be delayed until tRAS min is satisfied If tRTP min is not satisfied at the edge the start point of auto precharge operation will be delayed until tRTP min is satisfied In case the internal precharge is pushed out by tRTP tRP starts at the point where tRTP ends not at the next rising clock edge after this event So for BL 4 the minimum time from Read AP to the next Activate com mand becomes AL tRTP tRP tCK see example 2 for BL 8 the time from Read AP to the next Acti vate is AL 2 tRTP 1 where means rounded up to the next integer These equations change to AL tRP tCK avg and AL 2 tRTP tRP tCK avg respectively for DDR2 667 800 In any event internal precharge does not start earlier than two clocks after the last 4 bit prefetch A new bank activate command may be issued to the same bank if the following two conditions are satisfied simultaneously 1 The RAS precharge time has been satisfied from the clock at which the auto precharge begins 2 The RAS cycle time tRC from the previous bank activation has been satisfied 36 hyuix DDR2 Device Operations amp Timing Diagram TO T1 T2 T3 T4 5 6 emPEIXIXPXIriririrll Post CAS Bank A W NOP C NOP 82 Autoprecharge AL i i

Hynix HMP125U6EFR8C-S6 memory module

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