Elixir 1GB DDR2 SDRAM Unbuffered DIMM
Contents
1. Byte Description PER EDHY TAUS Note 3C AC 3C AC 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory DDR2 SDRAM 08 3 Number of Row Addresses on Assembly 14 OE 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Ranks 1 rank Height 30mm 60 6 Data Width of Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL 1 8V 05 9 DDR2 SDRAM Device Cycle Time at CL X 3 2 5 30 25 10 DDR2 SDRAM Device Access Time from Clock at CL X 0 45 0 40 45 40 11 DIMM Configuration Type Non parity ECC 00 12 Refresh Rate Type 7 8us self 82 13 Primary DDR2 SDRAM Width X8 08 14 Error Checking DDR2 SDRAM Device Width Undefined 00 15 Reserved Undefined 00 16 DDR2 SDRAM Device Attributes Burst Length Supported 4 8 0C 17 DDR2 SDRAM Device Attributes Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes CAS Latencies Supported 3 4 5 38 19 DIMM Mechanical Characteristics lt 4 1 mm 01 20 DDR2 SDRAM DIMM Type Information Regular UDIMM 133 35mm 02 21 DDR2 SDRAM Module Attributes Normal DIMM 00 22 DDR2 SDRAM Device Attributes General 07 23 Minimum Clock Cycle at CL X 1 3 75ns 3D 24 Maximum Data Access Time from Clock at CL X 1 0 5ns 50 25 Minimum Clock Cycle Time at CL X 2 5 0ns 50 26 Maximum Data Access Time from Clock at CL X 2 0 6ns 60 27 Minimum Row Precharg2. tAOND turn on delay 2 2 2 2 taon ODT turn on tAC min YAG ma tAC min AG men ns 2tCK 2tCK tAONPD ODT turn on Power down mode g in tAC max ac tAC max ns 1 1 tAOFD ODT turn off delay 2 5 2 5 2 5 2 5 taoF ODT turn off tAC min ui tAC min d ns tac 2 5tCK tac 2 5tCK tAOFPD ODT turn off Power down mode ns min 2 41 min 2 1 tANPD ODT to power down entry latency tAXPD power down exit latency Speed Grade Definition PC2 5300 PC2 6400 Symbol Parameter Unit Min Max Min Max Row Active Time 45 70 000 45 70 000 ns tRC Row Cycle Time 60 57 5 ns tRCD RAS to CAS delay 15 12 5 ns tRP Row Precharge Time 15 12 5 x ns REV 0 1 15 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 elixir Unbuffered DDR2 SDRAM DIMM Preliminary Edition Package Dimensions 512 1 Rank 64 8 DDR2 SDRAMs FRONT 13335 5 5 250 13135 Ss 12895 5 077 ON AL S ponn C N Detail A Detail 10 0 14 039 Q Drm 625 0 098 BACK 63 00 55 00 2 480 2 16
3. Ax RAS CAS WE resistors are 5 1 Ohms 5 5 Address and control resistors are 22 Ohms 5 SAO SA1 SA2 5 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 elixir Unbuffered DDR2 SDRAM DIMM Preliminary Edition Functional Block Diagram 1GB 2 Rank 64Mx8 DDR2 SDRAMs csi CS0 JM DQS4 M 0050 M DQS4 M DMO M DM4 M DM CS DOS DOS DM CS DOS DOS DM CS DQS 095 DM CS DOS DOS 00 N 100 00 DQ32 M 100 1 00 01 M 101 VO 1 0033 097 VO 1 DQ2 02 02 0034 N 2 1 02 N 103 DO D8 DQ35 N 103 04 103 D12 DQ4 N 104 4 0036 N 04 4 095 N 105 5 D
4. N 104 4 0029 N 5 5 105 5 DQ30 N 1 06 lO 6 DQe2 1 06 1 0 6 N 1 07 VO 7 0063 N 1 07 VO 7 BAO BA1 JA BAO BA1 SDRAMs 00 015 1 A0 A13 SDRAMs 00 015 VODs ED eal PD RAS JN RAS SDRAMs 00 015 VDDQ 00 015 CAS JN CAS SDRAMs 00 015 VDD 00 015 WE JN WE SDRAMs 00 015 VREF 22 e 00 015 CKEO SDRAMs 00 07 Vss 00 015 CKE1 SDRAMs 08 015 N ODT SDRAMs 00 07 ODT1 wN ODT SDRAMs 08 015 Notes 1 DQ to I O wiring may be changed within a byte Serial PD 2 DQ DQS DM CKE CS relationships are maintained as shown SCL 3 DQ DQS DGS resistors are 22 Ohms 5 WP At Wid SDA 4 Ax RAS CAS WE resistors 5 1 Ohms 5 5 Address and control resistors are 22 Ohms 5 SA0 SAT 2 REV 0 1 6 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect Part 1 of 2 512MB 64Mx64 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8 1 8V DDR2 SDRAMs with SPD elix Preliminary Edition r
5. M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 Unbuffered DDR2 SDRAM DIMM Ordering Information Preliminary Edition Part Number Speed Organization Leads Power Note M2Y51H64TU88DOB 3C 333MHz 3 00ns CL 5 DDR2 667 2 5300 M2Y51H64TU88D0B AC 400MHz 2 50ns CL 5 DDR2 800 PC2 6400 M2Y51H64TU88D6B 3C 333MHz 3 00ns CL 5 DDR2 667 2 5300 SUME M2Y51H64TU88D6B AC 400MHz 2 50ns CL 5 DDR2 800 2 6400 M2Y1GH64TU8HDOB 3C 333MHz 3 00ns CL 5 DDR2 667 2 5300 iod iuis M2Y1GH64TU8HDOB AC 400MHz 2 50ns CL 5 DDR2 800 PC2 6400 M2Y1GH64TU8HD6B 3C 333MHz 3 00ns CL 5 DDR2 667 2 5300 e M2Y1GH64TU8HD6B AC 400MHz 2 50ns CL 5 DDR2 800 2 6400 Pin Description ee Differential Clock Inputs 000 0063 Data input output CKEO CKE1 Clock Enable DQS0 DQS8 Bidirectional data strobes RAS Row Address Strobe DMO0 DM8 Input Data Mask High Data Strobes CAS Column Address Strobe DQS0 DQS8 Differential data strobes WE Write Enable Voo Power 1 8V CSO CS1 Chip Selects VREF Ref Voltage for SSTL_18 inputs A0 A9 A11 A13 Address Inputs VopsPp Serial EEPROM positive power supply A10 AP Column Address Input Auto precharge Vss Ground BAO BA1 SDRAM Bank Address Inputs SCL Serial Presence Detect Clock Input RESET Reset pin SDA Serial Presence Detect Data input output ODTO ODT1 Active termination control lines SA0 2 Serial Presence Detect Address Inputs NC No Connect Note ODT1 CKE1 and CS1 are
6. tps 0 10ns 0 05ns 10 05 35 Data Input Hold Time After Clock tpi 0 17ns 0 12ns 17 12 36 Write Recovery Time twa 15ns 3C 37 Internal Write to Read Command delay twtr 7 5ns 1E 38 Internal Read to Precharge delay tare 7 5ns 1E 39 Reserved Undefined 00 REV 0 1 9 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 elixir Unbuffered DDR2 SDRAM DIMM Preliminary Edition Serial Presence Detect Part 2 of 2 1GB 128Mx64 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8 4Banks 8K Refresh 1 8V DDR2 SDRAMs with SPD Serial PD Data Entry SPD Entry Value Description y Hexadecimal Note 3C AC 3C AC 00 The number below a decimal point of tRC and tRFC are 0 tRFC is less 40 Extension of Byte 41 tac and Byte 42 tarc than 256ns 30 The number below a 06 36 decimal point of tRC is 5 tRFC is less than 256ns 41 Minimum Core Cycle Time tac 60 ns 57 7ns 3C 39 42 Min Auto Refresh Command Cycle Time trrc 127 5ns 7F 43 Maximum Clock Cycle Time tcx 8 0ns 80 44 DQS DQ Skew Factor tpos 0 24ns 0 2 18 14 45 Read Data Hold Skew Factor tous 0 34ns 0 30 22 1E 46 PLL Relock Time Undefined 00 47 DT4R
7. 0 C lt Tease lt 85 C 7 8 7 8 us tolT OCD drive mode output delay 12 12 ns tCCD CAS to CAS tCK REV 0 1 14 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TUS88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module Tcase 0 85 C Vong 1 8V 0 1V Voo 1 8V 0 1V See AC Characteristics Part 2 of 2 Preliminary Edition elix PC2 5300 PC2 6400 Symbol Parameter Unit Min Max Min Max twR Write recovery time without Auto Precharge 15 15 ns WR Write recovery time with Auto Precharge tWR tCK tWR tCK tDAL Auto precharge write recovery precharge time WR tRP WR tRP tWTR Internal write to read command delay 7 5 7 5 ns tRTP Internal read to precharge command delay 7 5 7 5 ns tXSNR Exit self refresh to a Non read command 10 10 ns tXsRD Exit self refresh to a Read command 200 200 bp Exit precharge power down to any Non read 2 2 tXARD Exit active power down to read command 2 2 tXARDS Exit active power down read command 7 AL 8 AL minimum pulse width 3 3
8. Input Output Functional Description Symbol Type Polarity Function The positive line of the differential pair of system clock inputs which drives the input to CKO CK1 CK2 SSTL p the on DIMM PLL All the DDR2 SDRAM address and control inputs are sampled on the 9 rising edge of their associated clocks am E Negative The negative line of the differential pair of system clock inputs which drives the input to KO GKI C SSTL Edge theon DIMM PLL Activa Activates the SDRAM CK signal when high and deactivates the CK signal when low By CKEO CKE1 SSTL High deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode PEU Active Enables the associated SDRAM command decoder when low and disables the S0 CS1 SSTL Low command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue ee Active When sampled at the positive rising edge of the clock RAS CAS WE define the S CAS WE SSTL Low operation to be executed by the SDRAM VREF Supply Reference voltage for SSTL 18 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise Vona Supply immunit y ODT1 Input a On Die Termination control signals BAO BA1 SSTL Selects which SDRAM bank is to be active During a Bank Activate command cycle A0 A14 defines the row address RAO RA13 when sampled at the rising clock edge During a Read or Write command cycle A0 A9
9. is used to clock data into and out of the SPD EEPROM A resistor may be connected from the SCL bus time to V DD to act as a pull up Vopspp Supply Serial EEPROM positive power supply REV 0 1 4 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram 512 1 Rank 64Mx8 DDR2 SDRAMs CSO DQSO DQSO DMO DQO DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQs1 DQs1 DM1 DQ8 DQ9 0010 2011 0912 DQ13 DQ14 DQ15 DQS2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 20921 0922 DQ23 DQS3 DQSS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BAO BA1 1 RAS CAS WE CKEO ODTO Notes REV 0 1 08 2008 Preliminary Edition M DQS4 M M 5054 DM4 A 4 DM CS 5695 09 DM CS 0695 5095 N 4 100 2032 N 1 00 N 1 2033 N 1 01 N voa DQ34 N 2 N vos DO DQ35 N 1 03 04 N 04 2036 N 1 04 N vos DQ37 VO5 M 1796 Dass N 1 06 N 107 DQ39 N 107 M DQS5 M M DQS5 AA DM5 DM CS 5695 09 DM CS 5695 09 N 4 voo 2040 N 1 00 onl 2041 N 4 VO 1 N voa 2042 N 2 N
10. 1 SA2 140 DQ14 181 221 CK2 21 DQ10 62 102 141 0015 182 222 Vss 22 DQ11 63 A2 103 Vss 142 Vss 183 A1 223 DM6 23 Vss 64 Vop 104 DQS6 143 DQ20 184 Voo 224 NC 24 DQ16 KEY 105 DQS6 144 DQ21 KEY 225 Vss 25 DQ17 65 Vss 106 Vss 145 Vss 185 CKO 226 DQ54 26 Vss 66 Vss 107 DQ50 146 DM2 186 CKO 227 DQ55 27 DQS2 67 VDD 108 0051 147 187 VDD 228 Vss 28 DQS2 68 NC 109 Vss 148 Vss 188 A0 229 DQ60 29 Vss 69 VDD 110 DQ56 149 0022 189 Voo 230 DQ61 30 DQ18 70 A10 AP 111 DQ57 150 DQ23 190 BA1 231 Vss 31 DQ19 71 BAO 112 Vss 151 Vss 191 232 DM7 32 Vss 72 VDDQ 113 DQS7 152 0028 192 RAS 233 NC 33 0024 73 WE 114 DQS7 153 DQ29 193 cso 234 Vss 34 DQ25 74 CAS 115 Vss 154 Vss 194 235 00962 35 Vss 75 116 0058 155 DM3 195 ODTO 236 DQ63 36 DQS3 76 117 DQ59 156 NC 196 A13 237 Vss 37 DQS3 77 ODT1 NC 118 Vss 157 Vss 197 Voo 238 Vopspp 38 Vss 78 119 SDA 158 DQ30 198 Vss 239 SAO 39 DQ26 79 Vss 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 Vss 200 DQ37 41 Vss 81 DQ33 161 NC 201 Vss Note 1 NC No Connect 2 CS1 ODT1 and CKE1 Pins 76 77 and 171 are only support in 1GB module type REV 0 1 3 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 elixir Unbuffered DDR2 SDRAM DIMM Preliminary Edition
11. 2 ranks Height 30mm 61 6 Data Width of Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL 1 8V 05 9 DDR2 SDRAM Device Cycle Time at CL X 3 2 5 30 25 10 DDR2 SDRAM Device Access Time from Clock at CL X 0 45 0 40 45 40 11 DIMM Configuration Type Non parity ECC 00 12 Refresh Rate Type 7 8us self 82 13 Primary DDR2 SDRAM Width X8 08 14 Error Checking DDR2 SDRAM Device Width Undefined 00 15 Reserved Undefined 00 16 DDR2 SDRAM Device Attributes Burst Length Supported 4 8 0C 17 DDR2 SDRAM Device Attributes Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes CAS Latencies Supported 3 4 5 38 19 DIMM Mechanical Characteristics 4 1 mm 01 20 DDR2 SDRAM DIMM Type Information Regular UDIMM 133 35mm 02 21 DDR2 SDRAM Module Attributes Normal DIMM 00 22 DDR2 SDRAM Device Attributes General On ee 07 23 Minimum Clock Cycle at CL X 1 3 75ns 3D 24 Maximum Data Access Time from Clock at CL X 1 0 5ns 50 25 Minimum Clock Cycle Time at CL X 2 5 0ns 50 26 Maximum Data Access Time from Clock at CL X 2 0 6ns 60 27 Minimum Row Precharge Time tgp 15ns 12 5ns 3C 32 28 Minimum Row Active to Row Active delay tarp 7 5ns 1E 29 Minimum RAS to CAS delay taco 15ns 12 5ns 3C 32 30 Minimum RAS Pulse Width tras 45ns 31 Module Bank Density 512MB 80 32 Address and Command Setup Time Before Clock tis 0 2ns 0 17ns 20 17 33 Address and Command Hold Time After Clock tix 0 27ns 0 25ns 27 25 34 Data Input Setup Time Before Clock
12. 4W Delta Undefined 00 Thermal Resistance of DRAM Package from Top Case to 8 Ambient Psi DRAM ese m DRAM Case Temperature Rise from Ambient due to 9 Activate Precharge Mode Bits DTO Mode Bits Undefined o9 DRAM Case Temperature Rise from Ambient due to 90 Precharge Quiet Standby DT2N DT2Q Uniagtned 98 DRAM Case Temperature Rise from Ambient due to precharge Power Down DT2P 00 DRAM Case Temperature Rise from Ambient due to Active 52 Standby DT3N Undefined 00 DRAM Case Temperature Rise from Ambient due to Active 53 Power Down with Fast PDN Exit DT3P fast agenned M DRAM Case Temperature Rise from Ambient due to Active 54 Power Down with Slow PDN Exit DT3P slow o0 DRAM Case Temperature Rise from Ambient due to Page 55 Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Undefined 00 Mode Bit DRAM Case Temperature Rise from Ambient due to Burst f 56 Refresh DT5B Undefined 00 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto Precharge DT7 Undefined i Thermal Resistance of PLL Package from Top Case to 98 Ambient Psi T A PLL i Thermal Resistance of Register Package from Top Case 59 o Ambient Psi T A Register Undefined sg PLL Case Temperature Rise from Ambient due to PLL 60 Active DT PLL Active Undefined 29 Resister Case Temperature Rise from Ambient due to 61 Register Active Mode Bit DT Register Active Mode Bit MINIS 00 62 SPD Revisio
13. 5 SIDE J O C 3 18 Max E 0 125 Detail B 1 274 0 10 0 050 4 0 004 0 8 0 5 gt 0 031 0 02 000002 1 00 Pitch 0 039 0 059 0 004 Note All dimensions are typical with tolerances of 0 15 0 006 unless otherwise stated Units Millimeters Inches Note Device position is only for reference REV 0 1 16 08 2008 O NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice 512MB 64M x 64 1GB 128M x 64 Unbuffered DDR2 SDRAM DIMM Preliminary Edition Package Dimensions 1GB 2 Ranks 64Mx8 DDR2 SDRAMs M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B eli FRONT 13335 5 250 13135 7 5 171 12895 5 077 0000101010100 Drm rirmmmm mm rmm Detail A Detail B 10 0 0 394 L3 E L3 E E LI i E LI Ix 925 0 098 BACK 63 00 55 00 2 480 a 2 165 gt SIDE o M a Detail B 1 27 0 10 0 050 0 004 0 8 0 5 0 031 0 02 Pal 172000 1 00Pitch 0 039 0 059 0 004 Note All dimensions are typical with tolerances of 0 15 0 006 unless otherwise stated Units Mill
14. 64TU88DOB M2Y1GH64TU8HDOB M2Y51H64TU88D6B and M2Y1GH64TU8HD6B are 240 Pin Double Data Rate 2 DDR2 Synchronous DRAM Unbuffered Dual In Line Memory Module UDIMM organized as one rank 64Mx64 and two ranks 128Mx64 high speed memory array M2Y51H64TU88D0B and M2Y51H64TUS88D6B use eight 64Mx8 DDR2 SDRAMs M2Y1GH64TU8HDOB and M2Y1GH64TU8HD6B use sixteen 64Mx8 DDR2 SDRAMs These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR2 SDRAM DIMMs provide a high performance flexible 8 byte interface in a 5 25 long space saving footprint The DIMM is intended for use in applications operating up to 333MHz and 400MHz clock speeds and achieves high speed data transfer rates of up to 667MHz and 800MHz Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs A0 A13 and inputs BAO and BA1 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial 2 048 bit EEPROM using a standard protocol The first 128 bytes of serial PD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV 0 1 1 08 2008 O NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB
15. D TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit mA mA mA mA mA mA mA mA mA mA mA mA mA NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORR reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TUS88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module Tease 0 85 1 8V 0 1V Voo 1 8V 0 1V See AC Characteristics Part 1 of 2 Preliminary Edition elix PC2 5300 PC2 6400 Unit Symbol Parameter Min Max Min Max tAC DQ output access time from CK CK 0 45 0 45 0 40 0 40 ns tbasck DQS output access time from CK CK 0 40 0 40 0 35 0 35 ns tCH CK high level width 0 45 0 55 0 45 0 55 tcL CK low level width 0 45 0 55 0 45 0 55 tCK HP Minimum half clk period for any given cycle d kd tek defined by clk high tCH or clk low tcL time t CL tcL Clock Cycle Time 3 8 2 5 8 ns itis DQ and DM input setup time differential data 0 1 0 05 ris strobe tDH DQ DM input hold time differential data strobe 0 175 0 125 ns tIPW Input pul
16. M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 elixir Unbuffered DDR2 SDRAM DIMM Preliminary Edition 240pin Unbuffered DDR2 SDRAM MODULE Based on 64Mx8 DDR2 SDRAM D Die Features Performance PC2 5300 PC2 6400 Speed Sort 3C AC Unit DIMM CAS Latency 5 6 f CK Clock Frequency 333 400 MHz t CK Clock Cycle 3 2 5 ns f DQ DQ Burst Frequency 667 800 MHz Programmable Operation JEDEC Standard 240 pin Dual In Line Memory Module Device CAS Latency 3 4 5 64Mx64 and 128Mx64 DDR2 Unbuffered DIMM based on Burst Type Sequential or Interleave 64Mx8 DDR2 SDRAM D die Burst Length 4 8 Intended for 333MHz and 400MHz applications Operation Burst Read and Write Inputs and outputs are SSTL 18 compatible Auto Refresh CBR and Self Refresh Modes e 1 8V 0 1V Automatic and controlled precharge commands SDRAMs have 4 internal banks for concurrent operation 14 10 1 Addressing row column rank 512MB Differential clock inputs 14 10 2 Addressing row column rank 1GB Data is read or written on both clock edges 7 8 us Max Average Periodic Refresh Interval Bi directional data strobe with one clock cycle preamble and Serial Presence Detect one half clock post amble Gold contacts Address and control signals are fully synchronous to positive SDRAMs in 60 ball BGA Package clock edge RoHS compliance Description M2Y51H
17. Q37 N 05 5 N 1 0 6 DQ38 M 106 lO 6 DQ7 N 7 VO 7 DQ39 N 107 VO 7 DQS1 MW DQS5 A basi M DQS5 M DM1 A DM5 A DM CS Deas DOS DM CS DQS 095 DM CS DQS 095 DM CS DQS 095 N 100 00 DQ40 N 100 l O 0 N 4 101 01 DQ41 M VO 1 1 DQ10 02 702 DQ42 N 02 2 0011 N 1 03 D1 09 0043 N 1 03 05 103 D13 DQ12 N 04 1 0 4 DQ44 M 04 4 0013 A 105 105 DQ45 N 105 5 0014 N 1 06 1 0 6 DQ46 M 1 06 1 0 6 DQ15 N 107 7 DQ47 N 4 107 7 DQS2 A DQS6 M DQS2 M DQS6 DM2 DM6 A DM CS Bas DOS pM cS DOS DQS DM CS DOS DOS DM CS DQS 095 DQ16 N j 1 00 00 DQ48 N 100 1 00 DQ17 N 101 1 DQ49 101 1 0018 02 702 DQ50 N 02 1 02 DQi9 AN 103 D2 D10 DQ51 N 03 D6 103 D14 DQ20 N 04 1 0 4 DQ52 N 04 1 0 4 0021 A 5 5 DQ53 N 05 5 DQ22 M 1 06 1 06 DQ54 N 106 1 0 6 DQ23 N 107 Vo 7 DQ55 N 07 VO 7 DQS3 JM DQS7 M DQS3 M DQS7 M DM3 M DM7 M DM CS DQS 095 DM CS DQS 095 DM CS DOS DOS DM CS DQS 095 DQ24 N 100 100 DQ56 N 100 1 00 DQ25 M 1 1 DQ57 M 1 1 DQ26 N 1 02 2 pass N 1 02 2 DQ27 1 03 03 103 D11 DQ59 N D7 103 D15 DQ28 N 1 04 4 0060
18. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit mA mA mA mA mA mA mA mA mA mA mA mA mA NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 Unbuffered DDR2 SDRAM DIMM Operating Standby and Refresh Currents Tcase 0 85 Vooo 1 8V 0 1V 1GB 2 Ranks 64Mx8 DDR2 SDRAMs Symbol DDO DD1 DD2P DD2N DD2Q DD3PF DD3PS DD3N DDAW DD4R DD5 DD6 DD7 REV 0 1 08 2008 Parameter Condition Operating Current one bank active precharge tRC tRC MIN tCK tCK MIN DQ DM and DQS inputs changing twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank active read precharge Burst 2 tRC tRC MIN CL 2 5 tCK tCK MIN IOUT OmA address and control inputs changing once per clock cycle Precharge Power Down Standby Current all banks idle power down mode CKE lt VIL MAX MIN Idle Standby Current CS gt VIH MIN all banks idle gt MIN tCK MIN address and control inputs changing once per clock cycle Precharge Quiet Standby Current All banks idle CS is HIGH is HIGH tcx tc
19. defines the column address CA0 CA9 when sampled at the rising clock edge In addition to the column address AP is used to A9 invoke Autoprecharge operation at the end of the Burst Read or Write cycle If AP is A10 AP SSTL high autoprecharge is selected and BAO BA1 defines the bank to be precharged If AP A11 A13 is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with 1 to control which bank s to precharge If AP is high all 4 banks will be precharged regardless of the state of BAO BA1 If AP is low then BAO BA1 are used to define which bank to pre charge Active 000 0063 SSTL High Data and Check Bit Input Output pins VDD Vss Supply Power and ground for the DDR2 SDRAM input buffers and core logic Negative DQSO0 0058 and 5050 DOSS SSTL Positive Data strobe for input and output data Edge Active The data write masks associated with one data byte In Write mode DM operates as a DMO DM8 Input High byte mask by allowing input data to be written if it is low but blocks the write operation if 9 itis high In Read mode DM lines have no effect SA0 SA2 Address inputs Connected to either Vpp or Vss on the system board to configure the Serial Presence Detect EEPROM address SDA This bi directional pin is used to transfer data into or out of the SPD EEPROM A resistor must be connected from the SDA bus line to V DD to act as a pull up SCL This signal
20. e Time tgp 15ns 12 5ns 3C 32 28 Minimum Row Active to Row Active delay tarp 7 5ns 1E 29 Minimum RAS to CAS delay taco 19ns 12 5ns 3C 32 30 Minimum RAS Pulse Width tras 45ns 2D 31 Module Bank Density 512MB 80 32 Address and Command Setup Time Before Clock tis 0 2ns 0 17ns 20 17 33 Address and Command Hold Time After Clock tiu 0 27ns 0 25ns 27 25 34 Data Input Setup Time Before Clock tps 0 10ns 0 05ns 10 05 35 Data Input Hold Time After Clock tpi 0 17ns 0 12ns 17 12 36 Write Recovery Time twa 15ns 3C 37 Internal Write to Read Command delay twtr 7 5ns 1E 38 Internal Read to Precharge delay tare 7 5ns 1E 39 Reserved Undefined 00 REV 0 1 7 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 elixir Unbuffered DDR2 SDRAM DIMM Preliminary Edition Serial Presence Detect Part 2 of 2 512MB 64Mx64 1RANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8 1 8V DDR2 SDRAMs with SPD Serial PD Data Entry SPD Entry Value Byte Description y Hexadecimal Note 3C AC 3C AC 00 The number below a decimal point of tRC and tRFC are 0 tRFC is less 40 Extension of Byte 41 tac and Byte 42 tarc than 256ns 30 The number below a 06 36 decimal
21. e floating Active Power Down Current All banks open tCK MIN CKE is LOW Other control and address inputs are STABLE Data bus inputs are floating MRS A12 bit is set to low Fast Power down Exit Active Power Down Current All banks open tCK MIN CKE is LOW Other control and address inputs are STABLE Data bus inputs are floating MRS A12 bit is set to high Slow Power down Exit Active Standby Current one bank active precharge CS gt VIH MIN gt MIN tRC tRAS tCK MIN DQ DM and DQS inputs changing twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank Burst 2 writes continuous burst address and control inputs changing once per clock cycle DQ and DQS inputs changing twice per clock cycle CL 2 5 tCK MIN Operating Current one bank Burst 2 reads continuous burst address and control inputs changing once per clock cycle DQ and DQS outputs changing twice per clock cycle CL 2 5 tcK tCK MIN IOUT OMA Auto Refresh Current tRC tRFC MIN Self Refresh Current CKE lt 0 2V Operating Current four bank four bank interleaving with BL 4 address and control inputs randomly changing 50 of data changing at every transfer tRC tRC min loUT 12 Preliminary Edition PC2 5300 PC2 6400 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
22. imeters Inches Note Device position is only for reference REV 0 1 17 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 elixir Unbuffered DDR2 SDRAM DIMM Preliminary Edition Revision Log Rev Date Modification 0 1 08 2008 Preliminary Release REV 0 1 18 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORR reserves the right to change Products and Specifications without notice
23. k Other control and address inputs are stable Data bus inputs are floating Active Power Down Current All banks open tCK MIN CKE is LOW Other control and address inputs are STABLE Data bus inputs are floating MRS A12 bit is set to low Fast Power down Exit Active Power Down Current All banks open tCK MIN CKE is LOW Other control and address inputs are STABLE Data bus inputs are floating MRS A12 bit is set to high Slow Power down Exit Active Standby Current one bank active precharge CS gt VIH MIN gt VIH MIN tRC tRAS tCK MIN DQ DM and DQS inputs changing twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank Burst 2 writes continuous burst address and control inputs changing once per clock cycle DQ DQS inputs changing twice per clock cycle CL 2 5 tCK MIN Operating Current one bank Burst 2 reads continuous burst address and control inputs changing once per clock cycle DQ and DQS outputs changing twice per clock cycle CL 2 5 tcK tCK MIN IOUT OMA Auto Refresh Current tRC tRFC MIN Self Refresh Current CKE lt 0 2V Operating Current four bank four bank interleaving with BL 4 address and control inputs randomly changing 50 of data changing at every transfer tRC tRC min loUT 13 Preliminary Edition PC2 5300 PC2 6400 TB
24. n 1 3 13 63 Checksum for Byte 0 62 Checksum data 93 79 64 71 Manufacture s ID Code NANYA 7F7F7F0B00000000 72 255 Reserved Undefined REV 0 1 10 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 elixir Unbuffered DDR2 SDRAM DIMM Preliminary Edition Absolute Maximum Ratings Symbol Parameter Rating Units Vin Vout Voltage on I O pins relative to Vss 0 5 to 2 3 V Vpp Voltage on VDD supply relative to Vss 1 0 to 2 3 V VDDQ Voltage on VDDQ supply relative to Vss 0 5 to 2 3 V Note Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability DC operating Conditions Symbol Parameter Rating Units Note TcASE Operating Temperature Ambient 0 to 95 C 1 2 3 TsrG Storage Temperature Plastic 55 to 100 C IL Short Circuit Output Current 5 to 5 Note 1 Case temperature is measured at top and center side of DRAMs 2 tcAsE gt 85 C 3 9 us 3 All DRAM specification only support 0 C lt
25. only support in 1GB module type REV 0 1 2 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B s 512MB 64M 64 1GB 128M 64 elixir Unbuffered DDR2 SDRAM DIMM Preliminary Edition Pinout Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 VREF 42 NC 82 Vss 121 Vss 162 NC 202 DM4 2 Vss 43 NC 83 Das4 122 004 163 Vss 203 NC 3 DQO 44 Vss 84 DQS4 123 DQ5 164 NC 204 Vss 4 DQ1 45 NC 85 Vss 124 Vss 165 NC 205 DQ38 5 Vss 46 NC 86 DQ34 125 DMO 166 Vss 206 DQ39 6 DASO 47 Vss 87 DQ35 126 NC 167 NC 207 Vss 7 DQSO 48 NC 88 Vss 127 Vss 168 NC 208 0044 8 Vss 49 NC 89 DQ40 128 DQ6 169 Vss 209 DQ45 9 DQ2 50 Vss 90 DQ41 129 DQ7 170 210 Vss 10 003 51 91 Vss 130 Vss 171 CKE1 NC 211 DM5 11 Vss 52 CKEO 92 DQS5 131 0012 172 212 NC 12 DQ8 53 93 DQS5 132 DQ13 173 NC 213 Vss 13 DQ9 54 NC 94 Vss 133 Vss 174 NC 214 DQ46 14 Vss 55 NC 95 DQ42 134 DM1 175 215 DQ47 15 DAST 56 96 DQ43 135 NC 176 A12 216 Vss 16 DQS1 57 A11 97 Vss 136 Vss 177 A9 217 DQ52 17 Vss 58 A7 98 DQ48 137 CK1 178 Voo 218 DQ53 18 NC 59 99 0049 138 179 A8 219 Vss 19 NC 60 A5 100 Vss 139 Vss 180 A6 220 CK2 20 Vss 61 A4 10
26. op Case to 58 Ambient Psi T A PLL Undefined d Thermal Resistance of Register Package from Top Case 59 o Ambient Psi T A Register 09 PLL Case Temperature Rise from Ambient due to PLL 60 Active DT PLL Active Hndetined 00 Resister Case Temperature Rise from Ambient due to 61 Register Active Mode Bit DT Register Active Mode Bit unaetined us 62 SPD Revision 1 3 13 63 Checksum for Byte 0 62 Checksum data 92 78 64 71 Manufacture s ID Code NANYA 7F7F7F0B00000000 72 255 Reserved Undefined REV 0 1 8 08 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect Part 1 of 2 1GB 128Mx64 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8 1 8V DDR2 SDRAMs with SPD Preliminary Edition el IX r Byte Description SPD Entry Value PU ean Note 3C AC 3C AC 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type DDR2 SDRAM 08 3 Number of Row Addresses on Assembly 14 OE 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Ranks
27. point of tRC is 5 tRFC is less than 256ns 41 Minimum Core Cycle Time tac 60 ns 57 7ns 3C 39 42 Min Auto Refresh Command Cycle Time 127 5ns 7F 43 Maximum Clock Cycle Time 8 0ns 80 44 DQS DQ Skew Factor 0 24ns 0 2 18 14 45 Read Data Hold Skew Factor tous 0 34ns 0 30 22 1E 46 PLL Relock Time Undefined 00 47 DT4R4W Delta Undefined 00 Thermal Resistance of DRAM Package from Top Case to 8 Ambient Psi DRAM Undefined d DRAM Case Temperature Rise from Ambient due to 9 Activate Precharge Mode Bits DTO Mode Bits bibas 00 DRAM Case Temperature Rise from Ambient due to 90 Precharge Quiet Standby DT2N DT2Q Undefined m DRAM Case Temperature Rise from Ambient due to i precharge Power Down DT2P Undefined m DRAM Case Temperature Rise from Ambient due to Active 52 Standby DT3N Undefined 00 DRAM Case Temperature Rise from Ambient due to Active 53 Power Down with Fast PDN Exit DT3P fast denned oo DRAM Case Temperature Rise from Ambient due to Active 54 Power Down with Slow PDN Exit slow Undefined 00 DRAM Case Temperature Rise from Ambient due to Page 55 Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Undefined 00 Mode Bit DRAM Case Temperature Rise from Ambient due to Burst 56 Refresh DT5B Undefined 00 DRAM Case Temperature Rise from Ambient due to Bank d Interleave Reads with Auto Precharge DT7 Undefined 09 Thermal Resistance of PLL Package from T
28. se temperature shall not exceed the value specified in the component spec REV 0 1 11 08 2008 O NANYA TECHNOLOGY CORP NANYA TECHNOLOGY reserves the right to change Products and Specifications without notice M2Y51H64TU88DOB M2Y51H64TU88D6B M2Y1GH64TU8HDOB M2Y1GH64TU8HD6B 512MB 64M x 64 1GB 128M x 64 Unbuffered DDR2 SDRAM DIMM Operating Standby and Refresh Currents Tcase 0 85 1 8V 0 1V 512MB 1 Rank 64Mx8 DDR2 SDRAMs Symbol DDO DD1 DD2P DD2N DD2Q DD3PF DD3PS DD3N DDAW DD4R DD5 DD6 DD7 REV 0 1 08 2008 Parameter Condition Operating Current one bank active precharge tRC MIN tCK tCK MIN DQ DM and DQS inputs changing twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank active read precharge Burst 2 tRC tRC MIN CL 2 5 tCK MIN IOUT OmA address and control inputs changing once per clock cycle Precharge Power Down Standby Current all banks idle power down mode CKE lt VIL MAX MIN Idle Standby Current CS gt VIH MIN all banks idle gt MIN tCK MIN address and control inputs changing once per clock cycle Precharge Quiet Standby Current All banks idle CS is HIGH is HIGH tcx tck Other control and address inputs are stable Data bus inputs ar
29. se width 0 6 0 6 tDIPW DQ and DM input pulse width each input 0 35 0 35 tHZ Data out high impedance time from CK CK tACmax tACmax ns tLzipas DOS low impedance time from CK CK tACmin tACmax tACmin tACmax ns tLzipg low impedance time from CK CK 2tAc min tac max 2tacmin max ns DQS DQ skew DQS amp associated DQ signals 0 24 0 20 ns tQHS Data hold Skew Factor 0 34 0 3 ns tQH Data output hold time from DQS tOHS tos ns tpass Write command to 1st DQS latching transition 0 25 0 25 0 25 0 25 DGS input low high pulse width tDQSL H write cycle 0 35 0 35 tCK toss DQS falling edge to CK setup time 0 2 0 2 write cycle tDSH DQS falling edge hold time from CK 0 2 02 igi write cycle tMRD Mode register set command cycle time 2 2 twPsT Write postamble 0 40 0 60 0 40 0 60 twPRE X Write preamble 0 35 0 35 tH Address and control input hold time 275 250 ps 15 Address and control input setup time 200 175 ps tRPRE Read preamble 0 90 1 10 0 90 1 10 tRPST Read postamble 0 40 0 60 0 40 0 60 tRRD Active bank A to Active bank B command 7 5 7 5 ns Minimum time clocks remains ON after tIS tIS hg e asynchronously drops Low Average Periodic Refresh Interval 85 C lt Toase lt 95 C 39 us REFI Average Periodic Refresh Interval
30. tcAsE lt 85 C DC Electrical Characteristics and Operating Conditions Tease 0 85 1 8V 0 1V Voo 1 8V 0 1V See AC Characteristics Symbol Parameter Min Max Units Notes VDD Supply Voltage 1 7 1 9 V 1 VDDQ Supply Voltage 1 7 1 9 V 1 Vss Vssa Supply Voltage I O Supply Voltage 0 0 V VREF I O Reference Voltage 0 49VDDQ 0 51VDDQ V 1 2 VIH DC Input High Logic1 Voltage VREF 0 125 VDDQ 0 3 V 1 VIL DC Input Low LogicO Voltage 0 3 VREF 0 125 V 1 Note 1 Inputs are not recognized as valid until VREF stabilizes 2 VREF is expected to be equal to 0 5 V of the transmitting device and to track variations the DC level of the same Peak to peak noise on VREF may not exceed 2 of the DC value Environmental Parameters Symbol Parameter Rating Units Note Topr Module Operating Temperature Range ambient 0 to 55 C 3 Hopr Operating Humidity relative 10 to 90 Storage Temperature Plastic 55 to 100 C 1 HsTG Storage Humidity without condensation 5 to 95 96 1 Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 1 Stresses greater than those listed may cause permanent damage to the device This is a tress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Up to 9850 ft 3 The component maximum ca
31. vos D1 DQ43 N 1 03 D5 N vo4 DO44 N 4 N vos DQ45 N 1 05 N voe DQ46 N 1 06 N 107 DQ47 N 7 M base M DQS6 AA DM6 N 4 DM CS 5695 09 DM CS 0695 5095 N roo DO48 N 1 00 N 101 DQ49 VO 1 N voa DQ50 N 1 02 N vos D2 DQ51 N 1 03 D6 N vo4 DQ52 N 1 04 N vos DQ53 N VO5 N voe 2954 N 1 06 107 2955 M VO7 M DQS7 WM DQS7 DM7 N 4 DM CS 5695 09 DM CS DAQS 5095 N 4 voo DQ56 N 4 0 M4 101 DQ57 N 4 1 01 N voa pass N 1 02 N vos D3 2959 1 03 D7 N 4 DQ60 N 04 N vos DQ61 N 1 05 N 4 voe DQ62 N 1 06 N vo7 DQ63 N 107 2 SDRAMs 00 07 N AO0 A13 SDRAMs 00 07 V DDSPD e Serial PD 00 07 RAS SDRAMs 00 07 N CAS SDRAMs 00 07 V DD 20 07 _ WE SDRAMs 00 07 V REF e 00 07 N SDRAMS 00 07 Vss e 00 07 V ODT SDRAMS 00 07 1 DQ to I O wiring may be changed within a byte Serial PD 2 DQ DQS DM CKE CS relationships are maintained as shown SCL 3 DQ DQS DGS resistors are 22 Ohms 5 LM gt 4
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