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Elixir 2GB DDR3 Memory Module

1. M2F1G64CB88A4N BE 4D324632473634434238484 1344E2D424520 M2F1G64CB88A4N CG 4D324632473634434238484 1344E2D434720 M2F1G64CB88A4N DG 4D324632473634434238484 1344E2D444720 REV 0 1 06 2008 10 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice Byte Description SPD Entry Value a Note BE CG DG BE CG DG 61 Module thickness Max Standard 01 62 Raw Card ID reference Undefined 63 DRAM address mapping edge connector Nanya Technology 830B 64 116 Reserved Undefined 00 117 118 Module manufacture ID Undefined 00 119 125 Module information Undefined 00 126 127 CRC Undefined 00000000 128 145 Module part number Calculated Value ABEF 7909 6B97 146 Module die revision ASCII values 147 Module PCB revision Undefined 00 148 149 DRAM device manufacturer ID Undefined 00 150 175 Manufacturer reserved Nanya Technology 830B 176 255 Customer reserved Undefined SPD Note SPD Entry Value Serial PD Data Entry Hexadecimal M2F1G64CB88A4N M2F2G64CB8HA4N J 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SDRAM DIMM Preliminary Absolute Maximum DC Ratings Symbol Parameter Rating Units Vin Vout Voltage on I O pins relative to Vss 0 4 to 1 975 V Vpp Voltage on VDD supply relative to Vss 0 4 to 1 975 V VDDQ Voltage on VDDQ supply relative to Vss 0 4 to 1 975 V Note St
2. Unbuffered DDR3 SDRAM DIMM Preliminary Ordering Information Part Number Speed Organization Leads Power Note M2F1G64CB88A4N BE 533MHz 1 875ns CL 7 DDR3 1066 PC3 8500 M2F1G64CB88A4N CG 667MHz 1 5ns CL 9 DDR3 1333 PC3 10660 128Mx64 M2F1G64CB88A4N DG 800 MHz 1 25ns CL 9 DDR3 1600 PC3 12800 M2F2G64CB8HA4N BE 533MHz 1 875ns CL 7 DDR3 1066 PC3 8500 M2F2G64CB8HA4N CG 667MHz 1 5ns CL 9 DDR3 1333 PC3 10660 256Mx64 M2F2G64CB8HA4N DG 800 MHz 1 25ns CL 9 DDR3 1600 PC3 12800 Pin Description Pin Name Description Pin Name Description A0 A13 Address Inputs SCL Serial Presence Detect Clock Input BAO BA2 SDRAM Bank select SDA Serial Presence Detect Data input output RAS Row Address Strobe SA0 SA2 Serial Presence Detect Address Inputs CAS Column Address Strobe Voo SDRAM core power supply WE Write Enable Vopa SDRAM I O Driver power supply S0 S1 Chip Selects VREFDa SDRAM I O reference supply CKEO CKE1 Clock Enable VREFCA SDRAM command address reference supply ODTO0 ODT1 On die termination control lines Vss Ground DQO0 DQ63 Data input output Vopspp Serial EEPROM positive power supply oa SDRAM differential data strobes NC No Connect DMO0 DM7 Input Data Mask High Data Strobes Vir SDRAM I O termination supply aa Differential Clock Inputs RESET Set DRAMs to Know State Note CK1 CK1 Sl OTD1 and CKE1 are used for 2GB module only REV 0 1 06 2008 2 NANYA TECHNOLOGY CORP NANYA T
3. DM7 SAO SA2 SDA SCL Vopspp REV 0 1 06 2008 Type SSTL SSTL SSTL SSTL Supply Supply Supply SSTL SSTL SSTL SSTL Supply SSTL Input Supply Polarity Differential crossing Active High Active Low Active Low Active High Active High Differential crossing Active High Function CK and CK are differential clock inputs All the DDR3 SDRAM address control inputs are sampled on the crossing of positive edge of CK and negative edge of CK Output read data is reference to the crossing of CK and CK Activates the SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue This signal provides for external rank selection on systems with multiple ranks RAS CAS WE along with S define the command being entered Reference voltage for SSTL15 I O inputs Reference voltage for SSTL15 command address inputs Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity When high termination resistance is enabled for all DQ DQS DQS and DM pins assuming this function is enabled in the Mode Register 1 MR1 Selects which SDRAM bank is to be active During
4. This signal is used to clock data into and out of the SPD EEPROM A resistor may be connected from the SCL bus time to V DD to act as a pull up Power Supply for SPD EEPROM This supply is separate from the VDD VDDQ power plane EEPROM supply is operable from 3 0V to 3 6V 4 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Preliminary Functional Block Diagram 1GB 1 Rank 128Mx8 DDR3 SDRAMs SO Daso M pas4 DASO M DAS4 M DMO N DM4 _ DM CS DAQS pas DM CS DAQS Das Dao M 100 DQ32 100 pai N 101 pas3 M 101 Daz 4 102 pas4 02 Daz M 103 DO pass 4 1 03 D4 pa4 104 pase 04 Da5 M 105 DQ37 M 105 Das M 106 DQ38 M 1 06 DQ7 N 107 pasa 107 basi M pass M basi bass DMI N DM5 N DM CS DQS DAQS DM CS DQS Das Das VV 100 DQ40 1 00 pag 01 pDa41 4 1 01 DQ10 4 02 DQ42 M 02 DQ11 1 03 D1 DQ43 M 03 D5 DQ12 4 04 DQ44 104 DQ13 4 1 05 DQ45 M 105 DQ14 1 06
5. ns 7 5 6 3C 30 20 Minimum row Precharge delay tRPmin ns 13 125 13 5 11 25 69 6C 5A 21 Upper nibble for tRAS and tRC 1 1 11 22 Minimum Active to Precharge delay tRASmin ns 37 5 36 35 2C 20 18 23 Minimum Active to Active Refresh delay tRCmin ns 50 625 49 5 46 25 95 8C 72 24 Minimum refresh recovery delay tRFCmin LSB Combo bytes 24 25 70 25 Minimum refresh recovery delay tRFCmin MSB 110ns 03 26 Minimum internal Write to Read command delay tWTRmin 7 5ns 3C 27 Minimum internal Read to Precharge command delay 7 5ns 3C tRTPmin 28 Minimum four active window delay tFAWmin LSB Combo byte 28 29 01 00 29 Minimum four active window delay tFAWmin MSB 37 5ns 30ns 2C FO 3 RZQ 6 RZQ 7 30 SDRAM device output drivers suported DLL Off Mode Support 83 Extended Temperature Range ASR 31 SDRAM device thermal and refresh options ODTS PASR 8D 32 Module thermal sensor Non Thermal Sensor Support 33 SDRAM device type height lt 15mm OF 34 59 Reserved thickness lt 1mm 11 60 Module height nominal Raw Card B 01 REV 0 1 9 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect Part 2 of 2 2GB 256Mx64 2 Ranks UNBUFFERED DDR3 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 5V DDR3 SDRAMs with SPD Preliminary elixir
6. 2GB 256M x 64 elixir Unbuffered DDR3 SDRAM DIMM Preliminary erial Presence Detect Part 1 of 2 2GB 256Mx64 2 Ranks UNBUFFERED DDR3 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 5V DDR3 SDRAMs with SPD Serial PD Data Entry SPD Entry Value Byte Description i Hexadecimal Note BE CG DG BE CG DG CRC Covers Bytes 0 116 0 CRC range EEPROM bytes bytes used Total SPD Bytes 256 92 SPD Bytes Used 176 1 SPD revision Revision 0 8 08 2 DRAM device type DDR3 SDRAM 0B 3 Module type form factor UDIMM 02 4 SDRAM Device density and banks 8 banks 1Gb 02 5 SDRAM device row and column count 14 rows 10 columns 11 6 Reserved Undefined 00 7 Module ranks and device DQ count 2 ranks 8 bits 09 8 ECC tag and module memory Bus width Non ECC 64bits 03 9 Fine timebase dividend divisor in ps 2 5ps 52 10 Medium timebase dividend 1ns 01 11 Medium timebase divisor 8ns 08 12 Minimum SDRAM cycle time tCKmin ns 1 875 1 5 1 25 OF 0c 0A 13 Reserved Undefined 00 14 CAS latencies supported 6 7 8 6 8 9 5 6 7 8 9 10 1C 34 7E 15 CAS latencies supported Undefined 00 16 Minimum CAS latency time tAAmin ns 13 125 13 5 11 25 69 6C 5A 17 Minimum write recovery time tWRmin 15ns 78 18 Minimum CAS to CAS delay tRCDmin ns 13 125 13 5 11 25 69 6C 5A 19 Minimum Row Active to Row Active delay tRRDmin
7. DQS DOS high impedance time Reference from RL BL 2 tHZ DQS 225 ps DQS DQS differential input low pulse width tDQSL 0 4 0 6 tCK avg DQS DQS differential input high pulse width tDQSH 0 4 0 6 tCK avg DQS DQS rising edge to CK CK rising edge tDQSS 0 25 0 25 tCK avg DQS DQS falling edge setup time to CK CK rising edge tDSS 0 2 tCK avg DQS DQS falling edge hold time to CK CK rising edge tDSH 0 2 tCK avg REV 0 1 17 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Preliminary DDR3 1600 Parameter Symbol Min Max Units Command and Address Timing DLL locking time tDLLK 512 nCK Internal READ Command to PRECHARGE Command delay tRTP max 4nCK 7 5ns Delay from start of internal write transaction to internal read WTR max 4nCK 7 5ns 7 command WRITE recovery time tWR 15 ns Mode Register Set command cycle time tMRD 4 nCK Mode Register Set command update delay tMOD max 12nCK 15ns CAS to CAS command delay tCCD 4 nCK Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK avg nCK Multi Purpose Register Recovery Time tMPRR 1 ACTIVE to ACTIVE command period for 1KB page
8. 1 nCK Timing of PRE or PREA command to Power Down entry tPRPDEN 1 7 nCK Timing of RD RDA command to Power Down entry tRDPDEN RL 4 1 3 nCK beon command to Power Down entry BL8OTF BL8MRS WRPDEN WL 44 tWR tCK avg 7 nCK Timing of WRA command to Power Down entry BL8OTF 7 BL8MRS BC4OTF tWRAPDEN WL 4 WR 1 nCK Timing of WR command to Power Down entry BC4MRS tWRPDEN WL 2 tWR tCK avg nCK Timing of WRA command to Power Down entry BC4MRS tWRAPDEN WL 2 WR 1 nCK Timing of REF command to Power down entry tREFPDEN 1 nCK Timing of MRS command to Power Down entry tMRSPDEN tMOD min REV 0 1 18 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88AA4N M2F2G64CB8HA4N m 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SDRAM DIMM Preliminary DDR3 1600 Parameter Symbol Min Max Units ODT Timings oa high time without write command or with write command and ODTH4 4 7 nCK ODT high time with Write command and BL8 ODTH8 6 nCK Asynchronous RTT turn on delay Power Down with DLL frozen tAONPD 1 9 ns Asynchronous RTT turn off delay Power Down with DLL frozen tAOFPD 1 9 ns RTT turn on tAON 225 225 ps RTT_Nom and RTT_WR turn off time from ODTLoff reference tAOF 0 3 0 7 tCK avg RTT dynamic change skew tADC 0 3 0 7 tCK avg Write Leveling Timings F
9. Block Diagram 2GB 2 Rank 128Mx8 DDR3 SDRAMs Si S0 paso M pas4 M DASO M DAS M DMO DM4 M DM CS DAQS Das DM CS DAS DAQS DM CS DAQS Das DM CS Das Das Dao 4 00 o0 DQ32 1 00 00 pai 4 101 vO1 pas3 4 01 V01 paz 102 02 DQ34 02 VO 2 Da3 4 103 DO V0 3 D8 pass M 1 03 D4 VO3 D12 pa4 M 04 VO 4 pass 04 V0 4 Da5 M 05 05 DQ37 105 VO5 pas M 106 O6 pass M 06 06 DQ7 M 07 VO7 pase 07 VO7 DASI M DQS5 M DAST M Das5 M DM1 M DM5 M DM CS DAQS Das DM CS DAQS pas DM CS DAQS Das DM CS DQS DQS pas 00 voo DQ40 M 00 00 bag M 101 vO1 pa41 4 01 V01 DQ10 M 102 02 DQ42 M 102 V02 DQ11 103 D1 03 D9 DQ43 1 03 D5 VO3 D13 DQ12 N 04 VO 4 DQ44 N 104 V0 4 DQ13 N 105 05 DQ45 M 05 V
10. DQ46 M 06 pais 4 107 Da47 07 DQS2 pas DASZ DASE DM2 V DM6 N DM CS DQS DAQS DM CS DQS Das DQ16 4 1 00 pass oo pai7 M 01 pa4g M 01 Dais 02 paso 02 Daig M 03 D2 pasi 1 03 D6 DQ20 04 pas2 04 DQ21 M 1 05 DQ53 M 1 05 DQ22 M 06 pas4 106 DQ23 107 pass 07 DAS3 M pas7 M DAS3 M bas7 M DM3 M DM7 N DM CS DQS DAQS DM CS DQS Das DQ24 4 00 pases 00 pazs 1 01 DQ57 M 101 DQ26 4 02 pass M 02 DQ27 M 03 D3 DQ59 4 1 03 D7 DQ28 04 paso 04 DQ29 M 05 DQ61 M 105 DQ30 1 06 DQ62 M 06 DQ31 107 pass M 107 BA0 BA2 gt BA0 BA2 SDRAMs D0 D7 A0 A13 gt A0 A13 SDRAMs D0 D7 R one Vooso gt SPD RAS gt RAS SDRAMs D0 D7 Vool Vona DO D7 CAS gt CAS SDRAMs DO D7 Vreroa 00 D7 paa _s_ X WE gt WE SDRAMS D0 D7 Vss p DOD Vrerca e gt DO0 D7 CKE0 CKE SDRAMs D0 D7 ODTO gt ODT SDRAMs D0 D7 CKO CK SDRAMs D0 D7 CKO gt CK SDRAMs D0 D7 Serial PD SCL gt WPao ao o a2 SDA gt sho sh she REV 0 1 5 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Preliminary Functional
11. Write leveling setup time from rising CK CK crossing to E E rising DQS DQS crossing WES 245 195 ps Write leveling setup hold from rising CK CK crossing to z rising DQS DQS crossing WEN 245 195 ps Write leveling output delay tWLO 0 9 0 9 ns Write leveling output error tWLOE 0 2 0 2 ns REV 0 1 16 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Preliminary AC Timing Specifications for DDR3 SDRAM Devices Used on Module DDR3 1600 Parameter Symbol Min Max Units Clock Timing Minimum Clock Cycle time DLL off mode tCK DLL_OFF 8 ns Average high pulse width tCH avg 0 47 0 53 tCK avg Average low pulse width tCL avg 0 47 0 53 tCK avg Absolute Clock Period tCK abs tCK avg min tUlT per min tCK avg max tJIT per max ps Absolute clock high pulse width tCH abs 0 43 ps Absolute clock low pulse width tCL abs 0 43 ps Clock Period Jitter tJIT per 70 70 ps Clock Period Jitter during DLL locking period tJIT per lck 60 60 ps Cycle to Cycle Period Jitter tJIT cc 140 ps Cycle to Cycle Period Jitter during DLL locking period tJIT cc Ick 120 ps Duty Cycle Jitter tJIT duty ps Cumulative error
12. across 2 cycles tERR 2per 103 103 ps Cumulative error across 3 cycles tERR 3per 122 122 ps Cumulative error across 4 cycles tERR 4per 136 136 ps Cumulative error across 5 cycles tERR 5per 147 147 ps Cumulative error across 6 cycles tERR 6per 155 155 ps Cumulative error across 7 cycles tERR 7per 163 163 ps Cumulative error across 8 cycles tERR 8per 169 169 ps Cumulative error across 9 cycles tERR 9per 175 175 ps Cumulative error across 10 cycles tERR 10per 180 180 ps Cumulative error across n 11 50 cycles tERR nper een N Pree las eae ps Data Timing DQS DOS to DQ skew per group per access tDQSQ 100 ps DQ output hold time from DQS DQS tQH 0 38 tCK avg DQ low impedance time from CK CK tLZ DQ 450 225 ps DQ high impedance time from CK CK tHZ DQ 225 ps Data setup time to DQS DQS reference to Vih ac Vil ac levels tDS base TBD ps Data hold time to DQS DQS reference to Vih ac Vil ac levels tDH base TBD ps Data Strobe Timing DQS DQS differential READ Preamble tRPRE 0 9 tCK avg DQS DQS differential READ Postamble tRPST 0 3 tCK avg DQS DQS differential output high time tQSH 0 40 tCK avg DQS DQS differential output low time tQSL 0 40 tCK avg DQS DQS differential WRITE Preamble tWPRE 0 9 tCK avg DQS DQS differential WRITE Postamble tWPST 0 3 tCK avg DQS DQS rising dege output access time from rising CK CK tDQSCK 225 225 ps DQS DOS low impedance time Reference from RL 1 tLZ DQS 450 225 ps
13. 23 Vss 63 CK1 NC 104 Vss 143 DM2 183 Voo 224 DQ54 24 DQS2 64 CKI NC 105 DQ50 144 NC 184 CKO 225 DQ55 25 DQS2 65 Voo 106 DQ51 145 Vss 185 CKO 226 Vss 26 Vss 66 Vop 107 Vss 146 DQ22 186 VDD 227 DQ60 27 DQ18 67 VREFCA 108 DQ56 147 DQ23 187 NC 228 DQ61 28 DQ19 68 NC 109 DQ57 148 Vss 188 AO 229 Vss 29 Vss 69 Vop 110 Vss 149 DQ28 189 Vop 230 DM7 30 DQ24 70 A10 AP 111 DQs7 150 DQ29 190 BA1 231 NC 31 DQ25 71 BAO 112 DQS7 151 Vss 191 Vop 232 Vss 32 Vss 72 Vop 113 Vss 152 DM3 192 RAS 233 DQ62 33 DQs3 73 WE 114 DQ58 153 NC 193 S0 234 DQ63 34 DQS3 74 CAS 115 DQ59 154 Vss 194 Voo 235 Vss 35 Vss 75 Vop 116 Vss 155 DQ30 195 ODTO 236 Vopsep 36 DQ26 76 S1 NC 117 SAO 156 DQ31 196 A13 237 SA1 37 DQ27 77 ODT1 NC 118 SCL 157 Vss 197 Vop 238 SDA 38 Vss 78 Vop 119 SA2 158 NC 198 NC 239 Vss 39 NC 79 NC 120 Vit 159 NC 199 Vss 240 Vit 40 NC 80 Vss 160 Vss 200 DQ36 41 Vss 81 DQ32 161 NC 201 DQ37 Note 1 NC No Connect 2 Pin 63 64 76 77 and 169 CK1 CK1 Sl OTD1 and CKE1 are used for 2GB module only REV 0 1 3 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Preliminary Input Output Functional Description Symbol CKO CK1 CKO CK1 CKE0O CKE1 VREFDa VREFCA Vopa ODT0 ODT1 BAO BA2 AO A13 DQO DQ63 VDD VSS DQS0 DQS7 DQS0 DQS7 DMO
14. 3 1600 Unit lDDo Operating Current one bank activate Precharge TBD TBD TBD mA DD1 Operating Current one bank activate Read Precharge TBD TBD TBD mA DD2P 0 Precharge Power Down Current Fast Exit MRO0 bit A12 0 TBD TBD TBD mA DD2P 1 Precharge Power Down Current Slow Exit MRO bit A12 1 TBD TBD TBD mA DD2N Precharge Standby Current TBD TBD TBD mA I DD2Q Precharge Quiet Standby current TBD TBD TBD mA DD3P_ Active Power Down Current Always Fast Exit TBD TBD TBD mA DD3N Active Standby Current TBD TBD TBD mA DD4w Operating Current Burst Write TBD TBD TBD mA DD4R Operating Current Burst Read TBD TBD TBD mA DD5B Burst Refresh Current TBD TBD TBD mA DD6 Self Refresh Current Normal Temperature Range 0 85C TBD TBD TBD mA DD6ET Self Refresh Current Extended Temperature Range 0 95C TBD TBD TBD mA DD7 All Bank Interleave Read Current TBD TBD TBD mA Note Module IDD was calculated from component IDD It may differ from the actual measurement Operating Standby and Refresh Currents Toase 0 C 85 C Vona Voo 1 5V 0 075V 2GB 2 Ranks base on 128Mx8 DDR3 SDRAMs Symbol Parameter Condition DDR3 1066 DDR3 1333 DDR3 1600 Unit DDo Operating Current one bank activate Precharge TBD TBD TBD mA DD1 Operating Current one bank activate Read Precharge TBD TBD TBD mA DD2P 0 Precharge Power Down Current Fast Exit MRO bit A12 0 TBD TBD TBD mA DD2P 1 Pre
15. CT or REF command period tRC 50 625 49 5 3 46 25 ns ACT to PRE command period tRAS 37 5 9 tREFI 36 9 tREFI 35 9 tREFI ns CWL 5 tCK AVG Reserved Reserved 2 5 3 3 ns Ghs5 CWL 6 7 8 tCK AVG Reserved Reserved Reserved ns CWL 5 tCk AVG 2 5 3 3 2 5 3 3 2 5 3 3 ns CL 6 CWL 6 tCK AVG Reserved Reserved 1 875 lt 2 5 ns CWL 7 8 tCK AVG Reserved Reserved Reserved ns CWL 5 tCK AVG Reserved Reserved Reserved ns CWL 6 tCK AVG 1 875 lt 2 5 Reserved 1 875 lt 2 5 ns eea CWL 7 tCK AVG Reserved Reserved Reserved ns CWL 8 tCK AVG Reserved Reserved Reserved ns CWL 5 tCK AVG Reserved Reserved Reserved ns CWL 6 tCK AVG 1 875 lt 2 5 1 875 lt 2 5 1 875 lt 2 5 ns ae CWL 7 tCK AVG Reserved Reserved 1 5 lt 1 875 ns CWL 8 tCK AVG Reserved Reserved Reserved ns CWL 5 6 tCK AVG Reserved Reserved Reserved ns CL 9 CWL 7 tCK AVG Reserved 1 5 lt 1 875 1 5 lt 1 875 ns CWL 8 tCK AVG Reserved Reserved 1 25 lt 1 5 ns Supported CL settings 6 7 8 6 8 9 5 6 7 8 9 10 nCK Supported CWL Settings 5 6 5 6 7 5 6 7 8 nCK REV 0 1 13 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N m 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SDRAM DIMM Preliminar
16. D15 MPa ar ag A gt SDA CKO CK SDRAMs D0 D7 CKi CK SDRAMs D8 D15 REV 0 1 6 06 2008 sho sh she NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect Part 1 of 2 1GB Preliminary 128Mx64 1 Rank UNBUFFERED DDR3 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 5V DDR3 SDRAMs with SPD Serial PD Data Entry SPD Entry Value Byte Description y Hexadecimal Note BE CG DG BE CG DG CRC Covers Bytes 0 116 0 CRC range EEPROM bytes bytes used Total SPD Bytes 256 92 SPD Bytes Used 176 1 SPD revision Revision 0 8 08 2 DRAM device type DDR3 SDRAM 0B 3 Module type form factor UDIMM 02 4 SDRAM Device density and banks 8 banks 1Gb 02 5 SDRAM device row and column count 14 rows 10 columns 11 6 Reserved Undefined 00 7 Module ranks and device DQ count 1 ranks 8 bits 01 8 ECC tag and module memory Bus width Non ECC 64bits 03 9 Fine timebase dividend divisor in ps 2 5ps 52 10 Medium timebase dividend ins 01 11 Medium timebase divisor 8ns 08 12 Minimum SDRAM cycle time tCKmin ns 1 875 1 5 1 25 OF 0c 0A 13 Reserved Undefined 00 14 CAS latencies sup
17. ECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N J 1GB 128M x 64 2GB 256M x 64 el Unbuffered DDR3 SDRAM DIMM Preliminary Pinout Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 VREFDa 42 NC 82 DQ33 121 Vss 162 NC 202 Vss 2 Vss 43 NC 83 Vss 122 DQ4 163 Vss 203 DM4 3 DQO 44 Vss 84 DQAS4 123 DQ5 164 NC 204 NC 4 DQ1 45 NC 85 DQS4 124 Vss 165 NC 205 Vss 5 Vss 46 NC 86 Vss 125 DMO 166 Vss 206 DQ38 6 DASO 47 Vss 87 DQ34 126 NC 167 NC 207 DQ39 7 DQSO 48 NC 88 DQ35 127 Vss 168 RESET 208 Vss 8 Vss KEY 89 Vss 128 DQ6 KEY 209 DQ44 9 DQ2 49 NC 90 DQ40 129 DQ7 169 CKE1 NC 210 DQ45 10 DQ3 50 CKEO 91 DQ41 130 Vss 170 Voo 211 Vss 11 Vss 51 Vpop 92 Vss 131 DQ12 171 NC 212 DM5 12 DQ8 52 BA2 93 Dass 132 DQ13 172 NC 213 NC 13 DQ9 53 NC 94 DQS5 133 Vss 173 Voo 214 Vss 14 Vss 54 Vop 95 Vss 134 DM1 174 A12 BC 215 DQ46 15 Das1 55 A11 96 DQ42 135 NC 175 A9 216 DQ47 16 DQS1 56 A7 97 DQ43 136 Vss 176 Voo 217 Vss 17 Vss 57 Voo 98 Vss 137 DQ14 177 A8 218 DQ52 18 DQ10 58 A5 99 DQ48 138 DQ15 178 A6 219 DQ53 19 DQ11 59 A4 100 DQ49 139 Vss 179 Voo 220 Vss 20 Vss 60 Vop 101 Vss 140 DQ20 180 A3 221 DM6 21 DQ16 61 A2 102 DQs6 141 DQ21 181 Al 222 NC 22 DQ17 62 Voo 103 DQS6 142 Vss 182 Voo 223 Vss
18. ERR nper 1 0 68In n tUIT 1 0 68In n tUIT 1 0 68In n tUIT 1 0 68In n tJIT ps per min per max per min per max Data Timing DQS DOS to DQ skew per group per access tDQSQ 150 125 ps DQ output hold time from DQS DS tQH 0 38 0 38 tCK avg DQ low impedance time from CK CK tLZ DQ 600 300 500 250 ps DQ high impedance time from CK CK tHZ DQ 300 250 ps Tear time to DQS DQS reference to Vih ac tDS base 25 TBD ps pata hold time to DQS DQS reference to Vih ac Vil ac tDH base 100 TBD ps Data Strobe Timing DQS DQS differential READ Preamble tRPRE 0 9 0 9 tCK avg DQS DQS differential READ Postamble tRPST 0 3 0 3 tCK avg DQS DQS differential output high time tQSH 0 38 0 40 tCK avg DQS DQS differential output low time tQSL 0 38 0 40 tCK avg DQS DQS differential WRITE Preamble tWPRE 0 9 0 9 tCK avg DQS DQS differential WRITE Postamble tWPST 0 3 0 3 tCK avg a DQS rising dege output access time from rising CK tDascK 300 300 255 255 ps DQS DOS low impedance time Reference from RL 1 tLZ DQS 600 300 500 250 ps a8 DQS high impedance time Reference from RL tHZ DQS 7 300 250 ps DQS DQS differential input low pulse width tDQSL 0 4 0 6 0 4 0 6 tCK avg DQS DQS differential input high pulse width tDQSH 0 4 0 6 0 4 0 6 tCK avg DQS DQS rising edge to CK CK rising edge tDQSS 0 25 0 25 0 25 0 25 tCK avg DQS DQS falling edge setup time to CK CK rising edge tDSS 0 2 0 2 tCK avg DQS DQS
19. M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM elixir Preliminary 240pin Unbuffered DDR3 SDRAM MODULE Based on 128Mx8 DDR3 SDRAM A Die Features e Performance PC3 8500 PC3 10660 PC3 12800 Speed Sort BE CG DG Unit DIMM CAS Latency 7 9 9 fex Clock Frequency 533 667 800 MHz tek Clock Cycle 1 875 1 5 1 25 ns foa DQ Burst Frequency 1066 1333 1600 Mbps e JEDEC Standard 240 pin Dual In Line Memory Module e 128Mx64 and 256Mx64 DDR3 Unbuffered DIMM based on 64Mx8 DDR3 Elixir SDRAM e Intended for 533MHz 667MHz and 800MHz applications e Inputs and outputs are SSTL15 compatible e Voo Vona 1 5Volt 0 075Volt SDRAMs have 8 internal banks for concurrent operation e Differential clock inputs e Data is read or written on both clock edges 8 bit pre fetch e Two different termination values Rtt_Nom amp Rtt_WR e Extended operating temperature rage e Auto Self Refresh option e Automatic and controlled precharge commands e Programmable Operation DIMM CAS Latency 5 6 7 8 9 10 Burst Type Sequential amp Interleave Burst Length BC4 BL8 Operation Burst Read and Write e 14 10 1 Addressing row column rank 1GB e 14 10 2 Addressing row column rank 2GB e Serial Presence Detect e Gold contacts SDRAMs in 78 FBGA Package RoHS and Halogen Free compliance Description M2F1G64CB88A4N and M2F2G64CB8HA4N are 240 Pin Double Data Rate 3 DDR3 Sy
20. MM Package Dimensions 2GB 2 Ranks 128Mx8 DDR3 SDRAMs FRONT 133 35 0 15 Preliminary elixir SIDE Detail A lt lt _ __ Detail B lt lt 5 175 47 00 E fl cro COAT AUTTTATAT ATMA MGA NANA TT COTA 71 00 gt Pit BACK CCC ECC oe Detail A To ooon r O00 1 50 0 10 Units Millimeters Detail B gt 0 80 0 05 OO00000 1 00 Pitch Note Device position is only for reference REV 0 1 06 2008 21 4 00 Max 30 00 0 5 0 15 1 27 0 10 S NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N J 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SDRAM DIMM Preliminary Revision Log Rev Date Modification 0 1 06 2008 Preliminary Edition REV 0 1 22 06 2008 f NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice
21. O5 DQ14 4 06 06 DQ46 M 106 06 pais N 107 VO7 DQ47 M 107 VO7 bas2 M pas M DASZ M DQS6 M DM2 M DM6 M DM CS DAQS Das DM CS DAQS Das DM CS DAQS Das DM CS DAS pas DQ16 100 vO 0 DQ48 00 00 pai7 N 101 vO1 pa4g 01 V01 pais 102 02 paso M 02 VO 2 DQ19 M 103 D2 O3 D10 pasi 103 D6 VO3 p14 DQ20 N_ 04 VO 4 pas2 M 04 V0 4 DQ21 4 05 VO5 pDas3 M 05 VO5 DQ22 06 06 pas4 M 106 O6 DQ23 107 VO7 pass M 107 VO7 pas3 M pas7 M Das3 Das7 DM3 M DM7 M DM CS DAQS Das DM CS DAQS DQS DM CS DAQS Das DM CS DQS Das DQ24 100 00 pass 1 00 00 paz 01 vO1 DQ57 101 V01 DQ26 M 02 v o 2 pass 1 02 V0 2 DQ27 N 03 D3 O3 D11 pas9 M 103 D7 VO3 D15 DQ28 M 04 V04 paso 1 04 VO 4 DQ29 1 05 V05 past 105 05 paso M 1 06 06 DQ62 1 06 O6 DQ31 N4 107 VO7 DQ63 07 VO7 BAO BA2 gt BAO BA2 SDRAMs D0 D15 A0 A13 gt A0 A13 SDRAMs D0 D15 RAS RAS gt RAS gt RAS SDRAMs DO D15 hives E gt Pai CAS TAS SDRAMs D0 D15 VREFDO T gt D0 D15 WE gt WE SDRAMs D0 D15 Ves 4 DO DI5 Vrerca gt DO D15 CKE0 CKE SDRAMs D0 D7 CKE1 CKE SDRAMs D8 D15 ODTO gt ODT SDRAMs D0 D7 ODT1 gt ODT SDRAMs D8 D15 Serial PD CKO gt CK SDRAMs D0 D7 scL l CK1 gt CK SDRAMs D8
22. WL 4 tWR tCK a 7 nCK BL8MRS BC4OTF vg vg eee ec Pownentry WRAPDEN WL 4 WR 1 WL 4 WR 1 nCK Timing of WR command to Power Down entry BC4MRS tWRPDEN dai aay aah i tCK a 3 nCK ene command to Power Down entry WRAPDEN WL 24 WR 1 WL 24 WR 1 nCK Timing of REF command to Power down entry tREFPDEN 1 1 7 nCK Timing of MRS command to Power Down entry tMRSPDEN tMOD min tMOD min z REV 0 1 15 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N m 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR3 SDRAM DIMM Preliminary DDR3 1066 DDR3 1333 Parameter Symbol Min Max Min Max Units ODT Timings ODT high time without write command or with write _ _ command and BC4 oo i 4 mek ODT high time with Write command and BL8 ODTH8 6 6 nCK Pe dia RTT turn on delay Power Down with DLL tAONPD 1 9 9 ns Asynchronous RTT turn off delay Power Down with DLL tAOFPD 9 9 hs frozen RTT turn on tAON 300 300 250 250 ps RTT_Nom and RTT_WR turn off time from ODTLoff tAOF 03 0 7 0 3 0 7 tCK avg reference RTT dynamic change skew tADC 0 3 0 7 0 3 0 7 tCK avg Write Leveling Timings First DQS DQS rising edge after write leveling mode is iWLMRD 40 p 40 _ nCK programmed DQS DQS delay after write leveling mode is programmed tWLDQSEN 25 25 nCK
23. a Bank Activate command cycle Address input defines the row address RAO RA13 During a Read or Write command cycle Address input defines the column address In addition to the column address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BO and B1 to control which banks s to precharge If AP is high all banks will be precharged regardless of the state of BAO BA1 or BAZ If AP is low BAO BA1 and BA2 are used to define which bank to precahrge A12 BC is sampled during READ and WRITE commands to determine if burst chop on the fly will be performed High no burst chop Low burst chopped Data and Check Bit Input Output pins Power and ground for the DDR3 SDRAM input buffers and core logic Data strobe for input and output data DM is an input mask signal for write data Input data is masked when DM is sampled High coincident with that input data during a write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loadings These signals are tied at the system planar to either Vss or Vppspp to configure the serial SPD EEPROM address range This bi directional pin is used to transfer data into or out of the SPD EEPROM A external resistor must be connected from the SDA bus line to VDD to act as a pull up on the system board
24. bove the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Up to 9850 ft 3 The component maximum case temperature shall not exceed the value specified in the component spec Single Ended AC and DC Input Levels DDR3 1066 DDR3 1333 DDR3 1600 Symbol Parameter Units Note Min Max VIH DC DC input logic high Vref 0 100 VDD V 1 VIL DC DC input logic low VSS Vref 0 100 V 1 VIH AC AC input logic high Vref 0 175 V 1 VIL AC AC input logic low Vref 0 175 V 1 VrefDQ DC Reference Voltage for DQ DM inputs 0 49 VDD 0 51 VDD V 2 3 VrefCA DC Reference Voltage for ADD CMD inputs 0 49 VDD 0 51 VDD V 2 3 Note 1 For DQ and DM Vref VrefDQ For input only pins except RESET Vref VrefCA 2 The AC peak noise on Vref may not allow Vref to deviate from Vref DC by more than 1 VDD 3 For reference approx VDD 2 15mV REV 0 1 11 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Preliminary M2F1G64CB88A4N M2F2G64CB8HA4N Celi z e Operating Standby and Refresh Currents Toase 0 C 85 C Vooo Voo 1 5V 0 075V 1GB 1 Rank base on 128Mx8 DDR3 SDRAMs Symbol Parameter Condition DDR3 1066 DDR3 1333 DDR
25. charge Power Down Current Slow Exit MRO bit A12 1 TBD TBD TBD mA DD2N Precharge Standby Current TBD TBD TBD mA DD2Q Precharge Quiet Standby current TBD TBD TBD mA DpD3P Active Power Down Current Always Fast Exit TBD TBD TBD mA DD3N Active Standby Current TBD TBD TBD mA DD4w Operating Current Burst Write TBD TBD TBD mA DD4R Operating Current Burst Read TBD TBD TBD mA DD5B Burst Refresh Current TBD TBD TBD mA DD6 Self Refresh Current Normal Temperature Range 0 85C TBD TBD TBD mA DD6ET Self Refresh Current Extended Temperature Range 0 95C TBD TBD TBD mA DD7 All Bank Interleave Read Current TBD TBD TBD mA Note Module IDD was calculated from component IDD It may differ from the actual measurement REV 0 1 12 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N J 1GB 128M x 64 2GB 256M x 64 el Unbuffered DDR3 SDRAM DIMM Preliminary Speed Bins Speed Bin DDR3 1066 BE DDR3 1333 CG DDR3 1600 DG CL nRCD nRP 7 7 7 9 9 9 9 9 9 Unit Parameter Symbol Min Max Min Max Min Max Internal read command to first data tAA 13 125 20 13 5 20 11 25 20 ns ACT to internal read or write delay time tRCD 13 125 13 5 11 25 E ns PRE command period tRP 13 125 13 5 a 11 25 z ns ACT to A
26. e tZQinit 512 512 nCK Normal operation Full calibration time tZQoper 256 256 z nCK Normal operation Short calibration time tZQCS 64 64 nCK Reset Timing max 5nCK max 5nCK Exit Reset from CKE HIGH to a valid command tXPR tRFC min tRFC min 10ns 10ns Self Refresh Timings max 5nCK max 5nCK Exit Self Refresh to commands not requiring a locked DLL tXS tRFC min tRFC min 10ns 10ns Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK min tDLLK min nCK Minimum CKE low width for Self Refresh entry to exit tCKESR tCKE min p tCKE min 7 timing 1nCK 1nCK a a Self Refresh Entry SRE or icxsRE max 5nCK 10ns max 5nCK 10ns P E after Self Refresh Exit SRX or ICKSRX max 5nCK 10ns max 5nCK 10ns Power Down Timings Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not tXP max 3nCK 7 5ns max 3nCK 6ns requiring a locked DLL Slee a ere Se EE frozenito tXPDLL max 10nCK 24ns max 10nCK 24ns CKE minimum pulse width tCKE a a Command pass disable delay tCPDED 1 1 nCK Power Down Entry to Exit Timing tPD tCKE min 9 tREFI tCKE min 9 tREFI Timing of ACT command to Power Down entry tACTPDEN 1 1 nCK Timing of PRE or PREA command to Power Down entry tPRPDEN 1 1 7 nCK Timing of RD RDA command to Power Down entry tRDPDEN RL 4 1 RL 4 1 nCK Timing of WR command to Power Down entry BL8OTF WRPDEN WL 4 tWR tCK a E
27. falling edge hold time to CK CK rising edge tDSH 0 2 0 2 tCK avg REV 0 1 14 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Preliminary DDR3 1066 DDR3 1333 Parameter Symbol Min Max Min Max Units Command and Address Timing DLL locking time tDLLK 512 512 nCK ae READ Command to PRECHARGE Command tRTP max 4nCK 7 5ns max 4nCK 7 5ns T om of internal write transaction to internal WTR max 4nCK 7 5ns max 4nCK 7 5ns p WRITE recovery time tWR 15 15 z ns Mode Register Set command cycle time tMRD 4 4 nCK Mode Register Set command update delay tMOD max 12nCK 15ns max 12nCK 15ns CAS to CAS command delay tCCD 4 4 nCK Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK avg nCK Multi Purpose Register Recovery Time tMPRR 1 1 ACTIVE to ACTIVE command period for 1KB page size tRRD max 4nCK 7 5ns max 4nCK 6ns Four activate window for 1KB page size tFAW 37 5 z 30 E ns N ee setup time to CK CK referenced tIS base 125 _ 65 _ ps GEIN ie elias hold time to CK CK referenced to tIH base 200 140 _ ps Calibrating Timing Power up and RESET calibration tim
28. irst DQS DQS rising edge after write leveling mode is programmed tWLMRD 40 nCK DQS DQS delay after write leveling mode is programmed tWLDQSEN 25 nCK Write leveling setup time from rising CK CK crossing to rising DQS iWLS TBD 7 ps DQS crossing Write leveling setup hold from rising CK CK crossing to rising DQS iWLH TBD _ ps DQS crossing Write leveling output delay tWLO 0 7 5 ns Write leveling output error tWLOE 0 2 ns REV 0 1 19 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Package Dime nsions 1GB 1 Rank 128Mx8 DDR3 SDRAMs Preliminary FRONT 133 35 0 15 4 Hh A ooe 8 a a 71 00 i gt 5 00 gt Detail A g 250 o opot OOOO 1 50 0 10 Units Millimeters Note Device position is only for reference REV 0 1 06 2008 Detail B 0 80 0 05 OMUO000 p q 100 Pitch 20 2 70 Max 1 27 0 10 l NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88AA4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DI
29. nchronous DRAM Unbuffered Dual In Line Memory Module UDIMM organized as one rank 128Mx64 and two ranks 256Mx64 high speed memory array M2F1G64CB88A4N uses eight 128Mx8 DDR3 SDRAMs M2F2G64CB8HAAN uses sixteen 128Mx8 DDR3 SDRAMs These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR3 SDRAM DIMMs provide a high performance flexible 8 byte interface in a 5 25 long space saving footprint The DIMM is intended for use in applications operating up to 533 MHz 667MHz or 800MH7z clock speeds and achieves high speed data transfer rates of up to 1066Mbps 1333 Mbps or 1600 Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs AO A13 and I O inputs BAO BA1 and BA2 are using for the mode register set cycle The DIMM uses serial presence detect implemented via a serial 2 048 bit EEPROM using a standard IIC protocol The first 128 bytes of serial PD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV 0 1 06 2008 1 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64
30. ported 6 7 8 6 8 9 5 6 7 8 9 10 1C 34 7E 15 CAS latencies supported Undefined 00 16 Minimum CAS latency time tAAmin ns 13 125 13 5 11 25 69 6C 5A 17 Minimum write recovery time tWRmin 15ns 78 18 Minimum CAS to CAS delay tRCDmin ns 13 125 13 5 11 25 69 6C 5A 19 Minimum Row Active to Row Active delay tRRDmin ns 7 5 6 3C 30 20 Minimum row Precharge delay tRPmin ns 13 125 13 5 11 25 69 6C 5A 21 Upper nibble for tRAS and tRC 1 1 11 22 Minimum Active to Precharge delay tRASmin ns 37 5 36 35 2C 20 18 23 Minimum Active to Active Refresh delay tRCmin ns 50 625 49 5 46 25 95 8C 72 24 Minimum refresh recovery delay tRFCmin LSB Combo bytes 24 25 70 25 Minimum refresh recovery delay tRFCmin MSB 110ns 03 26 Minimum internal Write to Read command delay tWTRmin 7 5ns 3C 27 Minimum internal Read to Precharge command delay 7 5ns 3C tRTPmin 28 Minimum four active window delay tFAWmin LSB Combo byte 28 29 01 00 29 Minimum four active window delay tFAWmin MSB 37 5ns 30ns 2C FO RZQ 6 RZQ 7 30 SDRAM device output drivers suported DLL Off Mode Support 83 Extended Temperature Range ASR 31 SDRAM device thermal and refresh options ODTS PASP 8D 32 Module thermal sensor Non Thermal Sensor Support 33 SDRAM device type height lt 15mm OF 34 59 Reserved thickness lt 1mm 11 60 Module height nominal Raw Card A 00 REV 0 1 7 06 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Product
31. resses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability DC Electrical Characteristics and Operating Conditions Tease 0 C 85 C Vona 1 5V 0 075V Voo 1 5V 0 075V See AC Characteristics Symbol Parameter Min Max Units Notes VDD Supply Voltage 1 425 1 575 V 1 VDDQ I O Supply Voltage 1 425 1 575 V 1 VREF I O Reference Voltage 0 49VDDQ 0 51VDDQ V 1 2 Note 1 Inputs are not recognized as valid until VREF stabilizes 2 VREF is expected to be equal to 0 5 V DDQ of the transmitting device and to track variations in the DC level of the same Peak to peak noise on VREF may not exceed 2 of the DC value Environmental Parameters Symbol Parameter Rating Units Note Topr Module Operating Temperature Range ambient 0 to 55 C 3 Hopr Operating Humidity relative 10 to 90 1 TsTG Storage Temperature Plastic 50 to 100 C 1 HsTG Storage Humidity without condensation 5 to 95 1 PBAR Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a tress rating only and device functional operation at or a
32. s and Specifications without notice M2F1G64CB88A4N M2F2G64CB8HA4N 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect Part 2 of 2 1GB 128Mx64 1 Rank UNBUFFERED DDR3 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 5V DDR3 SDRAMs with SPD Preliminary M2F1G64CB88A4N BE 4D324631473634434238384 1344E2D424520 M2F1G64CB88A4N CG 4D324631473634434238384 1344E2D434720 M2F1G64CB88A4N DG 4D324631473634434238384 1344E2D444720 REV 0 1 06 2008 8 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice Byte Description SPD Entry vale iHexatiecinal Note BE CG DG BE CG DG 61 Module thickness Max Standard 00 62 Raw Card ID reference Undefined 63 DRAM address mapping edge connector Nanya Technology 830B 64 116 Reserved Undefined 00 117 118 Module manufacture ID Undefined 00 119 125 Module information Undefined 00 126 127 CRC Undefined 00000000 128 145 Module part number Calculated Value 227A FO5C E202 146 Module die revision ASCII values 147 Module PCB revision Undefined 00 148 149 DRAM device manufacturer ID Undefined 00 150 175 Manufacturer reserved Nanya Technology 830B 176 255 Customer reserved Undefined SPD Note SPD Entry Value Serial PD Data Entry Hexadecimal M2F1G64CB88AAN M2F2G64CB8HA4N fg 1GB 128M x 64
33. size tRRD max 4nCK 6ns Four activate window for 2KB page size tFAW 30 ns Command and Address setup time to CK CK referenced to Vih ac tIS base TBD _ ps Vil ac levels Command and Address hold time to CK CK referenced to Vih ac tlH base TBD _ ps Vil ac levels Calibrating Timing Power up and RESET calibration time tZQinit 512 nCK Normal operation Full calibration time tZQoper 256 nCK Normal operation Short calibration time tZQCS 64 nCK Reset Timing Exit Reset from CKE HIGH to a valid command tXPR e tad F Self Refresh Timings Exit Self Refresh to commands not requiring a locked DLL tXS We C min Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK min nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR ee a Valid Clock Requirement after Self Refresh Entry SRE or _ Power Down Entry PDE tCKSRE max 5nCK 10ns Valid Clock Requirement after Self Refresh Exit SRX or 7 Power Down Exit PDX or Reset Exit tCKSRX max 5nCK 10ns Power Down Timings Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL tXP max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL tXPDLL max 10nCK 24ns CKE minimum pulse width tCKE max 3nCK 5ns Command pass disable delay tCPDED 1 nCK Power Down Entry to Exit Timing tPD tCKE min 9 tREFI Timing of ACT command to Power Down entry tACTPDEN
34. y AC Timing Specifications for DDR3 SDRAM Devices Used on Module DDR3 1066 DDR3 1333 Parameter Symbol Min Max Min Max Units Clock Timing Minimum Clock Cycle time DLL off mode M 8 8 ns Average high pulse width tCH avg 0 47 0 53 0 47 0 53 tCK avg Average low pulse width tCL avg 0 47 0 53 0 47 0 53 tCK avg Absolute Clock Period tCK abs psami supenmas suNpenmn st Tiperymax P Absolute clock high pulse width tCH abs 0 43 0 43 ps Absolute clock low pulse width tCL abs 0 43 0 43 ps Clock Period Jitter tJIT per 90 90 80 80 ps Clock Period Jitter during DLL locking period tUIT per Ick 80 80 70 70 ps Cycle to Cycle Period Jitter tUIT cc 180 160 ps Cycle to Cycle Period Jitter during DLL locking period tuIT cc Ick 160 140 ps Duty Cycle Jitter tJIT duty ps Cumulative error across 2 cycles tERR 2per 132 132 118 118 ps Cumulative error across 3 cycles tERR 3per 157 157 140 140 ps Cumulative error across 4 cycles tERR 4per 175 175 155 155 ps Cumulative error across 5 cycles tERR 5per 188 188 168 168 ps Cumulative error across 6 cycles tERR 6per 200 200 177 177 ps Cumulative error across 7 cycles tERR 7per 209 209 186 186 ps Cumulative error across 8 cycles tERR 8per 217 217 193 193 ps Cumulative error across 9 cycles tERR 9per 224 224 200 200 ps Cumulative error across 10 cycles tERR 10per 231 231 205 205 ps tERR npr min tERR npr max tERR npr min tERR npr max Cumulative error across n 11 50 cycles t

Elixir 2GB DDR3 Memory Module

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