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Intel Xeon Wolfdale E3210

1. Testability Table 45 XOR Chain 13 Table 46 XOR Chain 14 E Chain 13 Pin Count Ball Chain 14 30 AB3 PEG2 0 61 PEG_TXN_8 31 AA13 PEG2 RXN 0 62 C6 PEG TXP 8 32 W12 PEG2 RXP 0 63 D5 PEG RXN 8 33 AP6 PEG2 TXN 15 64 E6 PEG RXP 8 34 PEG2 15 35 API1 PEG2_RXN_15 36 AP10 PEG2_RXP_15 Table 46 Chain 14 37 AT3 PEG2 TXN 14 Pin Count Ball Chain 14 38 AU2 PEG2 TXP 14 gt RSVD 39 AL PEG2_RXN_14 40 ALG PEG2_RXP_14 T 41 ARS PEG2 TXN 13 5 AKA REPE 42 PEG2_TXP_13 43 10 PEG2_RXN_13 i 44 ALII PEG2 RXP 13 45 PEG2 12 46 AR2 PEG2_TXP_12 7 ABIS RANG 47 PEG2_RXN_12 48 AK12 PEG2 RXP 12 ACE ERGO TN S 49 ANS PEG2 TXN 11 18 And RES 50 APA PEG2 TXP 11 a AGT 51 AHG PEG2_RXN_11 T 52 PEG2 RXP 11 a AHI Gr D 53 AM3 PEG2_TXN_10 3 54 AN2 PEG2_TXP_10 T T CE 55 AH10 PEG2 RXN 10 56 11 PEG2 10 17 5 PEG2 TXN 3 am PEG2 TXNL3 18 AF4 PEG2_TXP_3 58 AMG 19 AB12 PEG2 RXN 3 DS 20 AC13 PEG2 RXP 3 60 ne PES form 21 AD3 PEG2 TXN 2 el AKT 22 2 PEG2_TXP_2 62 AM 23 7 2 RXN 2 63 AEG PEG2_RXN_8 24 BAG PEG2_RXP_2 9 At PEGs nar 25 ACA PEG2 TXN 1
2. 260 9 2 DMIPVCCAP1 DMI Port VC Capability Register 1 260 9 3 DMIPVCCTL DMI Port VC ees 261 9 4 DMIVCORCAP DMI VCO Resource HH 261 9 5 DMIVCORCTLO DMI VCO Resource 1 262 9 6 DMIVCORSTS DMI VCO Resource Status sss mmn 263 9 7 DMIVCIRCAP DMI VC1 Resource Capability sess HH 263 9 8 DMIVCIRCTL1 DMI VC1 Resource 1 264 9 9 DMIVCIRSTS DMI Resource 265 9 10 DMILCAP DMI Link Capabilities 0000 265 9 11 DMILCTL DMI Link 1 sese senes 266 9 12 DMIESTS DMI Link Status 266 Functional 1 267 1021 Host Interface ui oce a erre ed e da eee 267 10 1 1 esee epe eter RAT D HIN RR E 267 10 1 2 5 000 chase aar UE Dese RS 267 10 1 3 FSB GTL Termination iiio n
3. Table 44 XOR Chain 12 Table 45 XOR Chain 13 js Chain 12 Bo dm Chain 13 10 P3 TXN 1 24 H13 PEG RXP 2 11 T7 DMI_RXP_1 25 D14 PEG TXN 1 12 T8 RXN 1 26 E15 PEG TXP 1 13 R7 DMI TXP 0 27 C14 PEG RXN 1 14 R6 TXN 0 28 B13 PEG RXP 1 15 N5 RXP 0 29 E17 PEG TXN 0 16 M4 DMI_RXN_O 30 D16 TXP 0 31 B15 PEG RXN 0 32 A16 PEG RXP 0 Table 45 XOR Chain 13 33 12 PEG TXN 15 Pin Ball 34 M1 PEG_TXP_15 35 N10 PEG_RXN_15 H21 RSVD 36 N8 PEG_RXP_15 37 K4 PEG TXN 14 1 AB 38 L5 PEG TXP 14 2 B7 PEG TXP_7 39 J2 PEG_RXN_14 3 H10 PEON 40 K3 PEG RXP 14 4 G10 41 H4 PEG_TXN_13 5 E9 PEG TXN 6 42 J5 PEG_TXP_13 6 D8 Peon 43 M8 PEG_RXN_13 7 L12 PEG RAN 6 44 M7 13 8 jin 45 G2 TXN 12 9 C10 PEG TANES 46 H1 PEG TXP 12 10 B9 PEG 3 47 L10 PEG RXN 12 11 ale PEG RAN 48 M11 PEG RXP 12 12 H12 PEGI TAFE D 49 E4 PEG TXN 11 13 ELI 50 F5 PEG TXP 11 i D10 PECATARI 51 K8 PEG RXN_11 15 MES PEG RANLA 52 K7 PEG RXP 11 16 N13 53 D3 PEG TXN 10 17 m ne 54 F3 TXP 10 18 BEL PEG Tar 55 C2 PEG_RXN_10 19 K13 PEG TOSS 56 D2 PEG RXP 10 20 L13 PEG RXP 3 ES BA PEG TXN_9 21 D12 PEG TXN 2 Ed Bs PEG TXP 9 22 E13 PEG TXP 2 EG PEG RXN 9 23 G13 PEG RXN 2 ES PEG RXP 9 325 intel
4. ds Gnade iei 303 30 XOR Chain 14 Functionality 2 0 enirn 316 31 XOR Chaim OUtpUts case re pecia re rada Late Ga ed Ue ke p Tae e Fre us 317 52 KOR Chali po PPP 318 33 XOR Chaim EU 319 Datasheet 11 34 XOR Chal 2 inn to IRR RR ERR FERRE REDI HER REX FRR 319 35 XOR skews PA UE ERU CR RES 319 36 XOR Chali 4 icc ERR E EUR EA ERES TR ET ee 320 37 XOR CHAIN kiss icta aser ra EORR tae a oa FA e be Fu tes 320 EP Neira 321 397 e morire TE 322 40 Leite REB 322 AT XOBR n NUR 323 42 XOR Chal 104 55 p rete recie hl RI CER VOCE RE AR RR RIDERE RE RU da 323 43 XOR Chaim Wisin csi rcx kr MORE TOR HU EE REB ERR YE EUER TE MER HUE RR BEAR E TEPORE ER TC RE R 324 XOR CHAIN 12 iicet ESAE S CREER T TRAE Tt 324 45 XOR Chain L3 cimanina E XX 325 46 XOR Chain 14 RE E ER RT X 326 12 Datasheet Revision History intel Revision Description Revision Date Number 001 e Initial release November 2007
5. 213 16 Direct Media Interface Register Address Map 259 17 Host Interface 2X and 1X Signal 268 18 Sample System Memory Dual Channel Symmetric Organization Mode 269 19 Sample System Memory Dual Channel Asymmetric Organization Mode with Intel Flex Memory Mode Enabled operose sa voa e eed bre Dean i 270 20 Sample System Memory Dual Channel Asymmetric Organization Mode with Intel Flex Memory Mode Disabled innsgne 270 21 Supported DIMM Module 271 22 Syndrome Bit orte kr EAE RAE 271 23 Absolute Minimum and Maximum 65 nemen 279 24 Current Consumption In SO ciet ter kr EE EK 281 25 Signal Groups aseo o corey orishas Ex DEUM P QU REP eden 283 26 JOBufter Supply Voltage cese exe eret RE EE 285 27 DC Characteristics 1 oit 286 28 Ballout Sorted 2 2910 4 4 4 402 2 2 21 21 1 1141 ene nnns 293 29 Ballout Sorted By Ball
6. Bit Access peraut Description Value 15 10 RO 00h Reserved Was Catastrophic Thermal Sensor I nterrupt Event WCTSIE 1 Indicates that a Catastrophic Thermal Sensor trip based on a higher to lower 9 RWC Ob nn temperature transition thru the trip point 0 No trip for this event Was Hot Thermal Sensor I nterrupt Event WHTSIE 1 Indicates that a Hot Thermal Sensor trip based on a higher to lower 8 RWC Ob i temperature transition thru the trip point 0 No trip for this event Was 0 Thermal Sensor Interrupt Event WAOTSI E 1 Indicates that an AuxO Thermal Sensor trip based on a higher to lower 7 RWC Ob in temperature transition thru the trip point 0 No trip for this event Software must write a 1 to clear this status bit 6 5 RO 00b Reserved Catastrophic Thermal Sensor I nterrupt Event CTSI E 1 Indicates that a Catastrophic Thermal Sensor trip event occurred based on a 4 RWC Ob ii lower to higher temperature transition thru the trip point 0 No trip for this event Software must write a 1 to clear this status bit Hot Thermal Sensor I nterrupt Event HTSI E 1 Indicates that a Hot Thermal Sensor trip event occurred based on a lower to 3 RWC Ob n higher temperature transition thru the trip point 0 No trip for this event Software must write 1 to clear this status bit AuxO Thermal Sensor Interrupt Event AOTSIE 1 Indicates that an 0 Thermal Sensor trip even
7. 1 2 4 222 118 5 2 26 CICYCTRKRD Channel 1 CYCTRK READ 2 2 04 22 4 2 118 5 2 27 CICKECTRL Channel 1 me 119 5 2 28 CIREFRCTRL Channel 1 DRAM Refresh Control 120 5 2 29 CIECCERRLOG Channel 1 ECC Error 100 2 121 5 2 30 CIODTCTRL Channel 1 ODT 122 5 2 31 EPCODRBO EP Channel 0 DRAM Rank Boundary Address 0 123 5 2 32 EPCODRB1 EP Channel 0 DRAM Rank Boundary Address 1 123 5 2 33 EPCODRB2 EP Channel 0 DRAM Rank Boundary Address 2 123 5 2 34 EPCODRB3 EP Channel 0 DRAM Rank Boundary Address 3 124 5 2 35 EPCODRAO1 EP Channel 0 DRAM Rank 0 1 124 5 2 36 EPCODRA23 EP Channel 0 DRAM Rank 2 3 Attribute 125 5 2 37 EPDCYCTRKWRTPRE EPD WRT PRE 2 22 4 125 5 2 38 EPDCYCTRKWRTACT EPD WRT 2 22 2 2 126 5 2 39 EPDCYCTRKWRTWR EPD CYCTRK 2 126 5 2 40 EPDCYCTRKWRTREF EPD CYCTRK WRT REF 1 2 127 5 2 41 EPDCYCTRKWRTRD EPD WRT READ
8. Bit Access Detault Description Value Detected Parity Error DPE This bit is set by the Secondary Side for a Type 1 15 RWC Ob Configuration Space header device whenever it receives a Poisoned Transaction Layer Packet regardless of the state of the Parity Error Response Enable bit in the Bridge Control Register Received System Error RSE This bit is set when the Secondary Side for a 14 RWC Ob Type 1 configuration space header device receives an ERR_FATAL or ERR_NONFATAL Received Master Abort RMA This bit is set when the Secondary Side for 13 RWC Ob Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Unsupported Request Completion Status Received Target Abort RTA This bit is set when the Secondary Side for 12 RWC Ob Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Completer Abort Completion Status Signaled Target Abort STA Not Applicable or Implemented Hardwired to 0 11 RO Ob The MCH does not generate Target Aborts the MCH will never complete a request using the Completer Abort Completion status 10 9 RO 00b DEVSELB Timing DEVT Not Applicable or Implemented Hardwired to 0 Master Data Parity Error SMDPE When set indicates that the MCH 8 RWC Ob received across the link upstream a Read Data Completion Poisoned Transaction Layer Packet EP 1 This bit can
9. 315 Tables slintelSPe Giti Gabi ais eee rc 19 2 Expansion Area Memory 1 39 3 Extended System BIOS Area Memory 2 2 39 4 System BIOS Area Memory 40 5 Transaction Address Ranges Compatible High 49 6 SMM Space 50 7 SMM Control Table 51 8 DRAM Controller Register Address Map 65 9 MCHBAR Register Address 98 10 DRAM Rank Attribute Register enn 104 11 00 55 Map creer bei et bens ci 141 12 Express Bridge Register Address Map 01 147 13 Function in ME Subsystem 3 0 Register Address 193 14 Mapped Register Address Map 204 15 Host Secondary PCI Express Bridge Register Address D6 FO
10. 22 2 0 0 022 106 5 2 10 COCYCTRKWR Channel 0 CYCTRK 7 4 4 107 5 2 11 COCYCTRKRD Channel 0 CYCTRK READ 11412 108 5 2 12 COCYCTRKREFR Channel 0 CYCTRK 4 108 5 2 13 COCKECTRL Channel 0 12 109 5 2 14 COREFRCTRL Channel 0 DRAM Refresh Control 110 5 2 15 COECCERRLOG Channel 0 ECC Error 09 112 5 2 16 COODTCTRL Channel 0 ODT 1 113 5 2 17 C1DRBO Channel 1 DRAM Rank Boundary Address 0 113 5 2 18 C1DRB1 Channel 1 DRAM Rank Boundary Address 1 114 5 2 19 C1DRB2 Channel 1 DRAM Rank Boundary Address 2 114 5 2 20 C1DRB3 Channel 1 DRAM Rank Boundary Address 3 115 5 2 21 CIDRAO1 Channel 1 DRAM Rank 0 1 115 5 2 22 C1DRA23 Channel 1 DRAM Rank 2 3 115 5 2 23 1 CYCTRK PCHG 20 116 5 2 24 CICYCTRKACT Channel 1 CYCTRK 117 5 2 25 CICYCTRKWR Channel 1 CYCTRK
11. 01110 E 169 6 31 MA Message Addtess eee 170 6 32 MD Message TE era 170 6 33 Express Capability 5 170 6 34 PE Express Capabilities 171 6 35 DCAP Device Capabilities sess eH memememen emnes nnns 171 6 36 DCTE Device Control ini get rear liodie ane 172 6 37 0575 hhina 173 6 38 320 Dee Seria Dunt tet Dx e de vu 174 6 39 JECTEPIDK CONTO 55 tri kets wen Rp E DERE 176 6 40 ESTS ELInk Status e er reete ie vk 178 6 41 SLOTCAP Slot 000 mmm 179 6 42 SEOTCTE SIOot Control cecinere tor hti 180 Datasheet 6 43 SLOTSTS Slot a 182 6 44 RCTE RO0E irte 183 6 45 RSTS ROOE Status oer oe RR EERERR EU PROMO ROGA RR UY RECUERDE ened 184 6 46 PELC PCI Express Le
12. LEM edad 267 10 1 4 FSB Dynamic Bus Inversion 00 1 memes 267 10 1 5 APIC Cluster Mode 2 268 10 2 System Memory Controller 0 0 2 0 0 2 6 nnn 269 10 2 1 System Memory Organization 269 10 2 1 1 Single Channel 269 10 2 1 2 Dual Channel 269 10 2 2 System Memory Technology 270 10 2 3 Error Checking and 271 10 3 PCI EXpress ERR 274 10 3 1 PCI Express Architecture 274 10 3 51 Transaction Layer exe LER UH RR RE RE FRU RR ee 274 10 3 1 2 Data LINK Layer T E EATER 274 10 3 1 3 Physical Layer iiri terere tee reve ea br reca reor epa br eie P a eee 274 10 4 Thermal Sensor nasieniem EEEE parte tuae katie le pe apex 275 10 4 1 PCI Device 0 FUNCHON Qood Lam EE Ee Ced d 275 10 4 2 MCHBAR Thermal Sensor t 275 10 5 Power Management e Fr Caco E
13. 5 1 13 MCHBAR MCH Memory Mapped Register Range Base B D F Type 0 0 0 PCI Address Offset 48 4Fh Default Value 0000000000000000h Access RO RW L Size 64 bits This is the base address for the MCH Memory Mapped Configuration space There is no physical memory within this 16KB window that can be addressed The 16 KB reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset the MCH MMIO Memory Mapped Configuration space is disabled and must be enabled by writing a 1 to MCHBAREN Dev 0 offset48h bit 0 All the bits in this register are locked in Intel TXT mode The register space contains memory control initialization timing and buffer strength registers clocking registers and power and thermal management registers The 16 KB space reserved by the MCHBAR register is not accessible during Intel TXT mode of operation or if the ME security lock is asserted MESMLCK ME SM lock at PCI device 0 function 0 offset FAh except for the following offset ranges 02B8h to 02BFh Channel 0 Throttle Counter Status Registers O6B8h to O6BFh Channel 1 Throttle Counter Status Registers OCDOh to OCFFh Thermal Sensor Control Registers 3000h to 3FFFh Unlocked registers for future expansion Default Bit Access Value Description 63 36 RO 0000000h Reserved MCH Memory Mapped Base Address MCHBAR This field corresponds to bits 35 14 of the base address MCH Memory Mapped configuration space BIO
14. MAIA WALSAS LSOH BSVEINd asvan sreg gaong amp vam aad1 UVESINLA uVaIOAING UVELAX9 HVEHOW NOTE Do not follow the UMA requirement 37 Datasheet m n tel System Address Map 3 1 Legacy Address Range This area is divided into the following address regions e 0 640 KB DOS Area 640 768 KB Legacy Video Buffer Area 768 896 KB in 16 KB sections total of 8 sections Expansion Area 896 960 KB in 16 KB sections total of 4 sections Extended System BIOS Area 960 KB 1 MB Memory System BIOS Area Figure 4 DOS Legacy Address Range 1 MB 000 FFFFh System BIOS Upper F h 64 KB 000 0000 960 KB 000 FFFFh Extended System BIOS Lower E h 64 KB 16 KB x 4 000E_0000 000D FFFFh Expansion Area 128 KB 16 KB x 8 000C 0000h 768 KB 000B FFFFh Legacy Video Area SMM Memory 128 KB 000A 0000h 0009 FFFFh 5595 DOS Area 0000_0000h 3 1 1 DOS Range 9 FFFFh The DOS area is 640 KB 0000 0000h 0009 FFFFh in size and is always mapped to the main memory controlled by the MCH 38 Datasheet m e System Address Map n Le 3 1 2 Expansion Area C 0000h D FFFFh This 128 KB ISA Expansion region 000C 0000h 000D FFFFh is divided into eight 16 KB segments Each segment can be assigned one of four Read Write states read only write onl
15. ppp DDR_B_MA_ DDR_A_DQ_ DDR B MA DDR B MA DDR B DQ 4 4 7 5 2 0 25 7 az c ae DDR B CK DDR B pbR B MA B Bs DDR A DQ DDR B DM B ck vss vss B DOL LB MAL _B_BS_ ADOL vss y pOL vss DDR_B_CKB DDR_B_DQ DDR B DQ DDR A DQ DDR A DQ DDR B DQ vss vss vss vss gps A DOL vss DDR_B_DQ DDR B DQ DDR A DQ DDR A DQ DDR B DDR B vss vss vss vss A DO sy B POL vss DDR B CK DDR B DQ DDR B DQ DDR B DQ vss vss S EE vss vss vss vss DDR B 09 00 DDR DM DDR B DQ DDR B DQ vss 8 vss B Do vss vss 4 vss 5 DDR A CK A DDR B DQ DDR DDR A DDR A DQ DDR 8 DQ DDR B DQ RSVD E E E RSVD 8 55 36 m 24 2 7 vcc cL DORA CKE DDR A RSVD vss CL vss PWROK RSTINB vss vcc cL RSVD VCC CL cL VCC CL VCC CL cL cL VCC CL CL VCC CL VcC CL VCC CL VCC CL VCC CL cL VCC CL VCC CL CL cL VCC CL VCC CL CL cL VcC CL RSVD vss vec vss vec vss vec vss vec vec vec vec cL RSVD vec vss vec vss vec vss vec vss vec vec vec CL vec vss vec vss vec vss vec vss vec vss vec vec CL vec vec vss vec vss vec vss vec vss vec vec vec CL vec vss vec vss vec vss vec vss vec vss vec vec CL vec vec vss vec vss vec vss vec vss vec vec vec vec vss v
16. 2 2 127 5 2 42 EPDCKECONFI GREG EPD Related 128 5 2 43 EPDREFCONFI G EP DRAM Refresh Configuration 129 5 2 44 TSC1 Thermal Sensor Control 1 00010 131 5 2 45 TSC2 Thermal Sensor Control 2 11 132 5 2 46 TSS Thermal Sensor Status sss memes 134 5 2 47 TSTTP Thermal Sensor Temperature Trip Point 135 5 2 48 TCO Thermal Calibration Offset 136 5 2 49 THERM1 Thermal Hardware 2 202 2 137 Datasheet 5 em 3 5 2 50 TIS Thermal Interrupt Status 137 5 2 51 TSMICMD Thermal SMI 139 5 2 52 PMSTS Power Management 140 5 3 Idi nm 141 5 3 1 EPESD EP Element Self 141 5 3 2 EPLE1D EP Link Entry 1 142 5 3 3 EPLEIA EP Link Entry 1 e 142 5 3 4 EPLE2D EP Link Entry 2 2 143 5 3 5 EPLE2A EP Link Entry 2 0 en 143 5 3 6 EPLE3D
17. 5 2 7 CODRA23 Channel 0 DRAM Rank 2 3 Attribute B D F Type 0 0 0 MCHBAR Address Offset 20A 20Bh Default Value 0000 Access RW L Size 16 bits See CODRAO1 register Default Bit Access Value Description Channel 0 DRAM Rank 3 Attributes CODRA3 This register defines DRAM pagesize number of banks for rank3 for given channel 15 8 RW L 00h See table in register description for programming This register is locked by ME stolen Memory lock Channel 0 DRAM Rank 2 Attributes CODRA2 This register defines DRAM pagesize number of banks for rank2 for given channel 7 0 RW L 00h uM See table in register description for programming This register is locked by ME stolen Memory lock 5 2 8 COCYCTRKPCHG Channel 0 CYCTRK PCHG B D F Type 0 0 0 MCHBAR Address Offset 250 251h Default Value 0000 Access RO RW Size 16 bits This is the Channel 0 CYCTRK Precharge registers Default Bit Access Value Description 15 11 RO 00000b Reserved Write PRE Delayed COsd cr pchg This field indicates the minimum 10 6 RW 000006 allowed spacing in DRAM clocks between the WRITE and PRE commands to the same rank bank This field corresponds to twp in the DDR Specification READ To PRE Delayed COsd cr rd pchg This field indicates the minimum 5 2 RW 0000b allowed spacing in DRAM clocks between the READ and PRE commands to the same rank bank PRE To PRE Delayed COsd cr pchg pchg This field indicate
18. 234 8 29 MSI CAPID Message Signaled Interrupts Capability 10 235 8 30 MC Message Control coiere temas need sre De EDRR LR Ra ERR ELE RE 235 8 31 MA Message Address 000001 eee nene e emen nnne 236 8 32 MD Message Data 2 1 2 42 2 4 4 44 ann ad nnn nd nnn nnn n 236 8 33 PE CAPL PCI Express Capability e 236 8 34 PE CAP PCI Express Capabilities mmm 237 8 35 DCAP Device Capabilities mememememe emen 237 8 36 DETL Devices Control tcr reiten tinent eee rinse nr REX RE ORT a RE Rand 238 8 37 DSTS DeViCe Status otto A A Herat 239 8 38 LCAP LINK Capabilities trt reor RAE EREEXE 240 8 39 LCTE Link Control eri ex DR ERREUR UE ve beanies ENUMERARE APER E RUPES 242 8 40 ES TS Elhk Status icu 244 8 41 SLOTCAP Slot 2 2020 emen memes 245 8 42 SLOTCTL Slot Control ente cen eet OR RT Ru e eR ORE Fa Re RR Re ge 246 8 43 SLOTSTS SIOt Status oes encender beta ad Pel de do nbl 248 8 44 RCTL ROOt Conttol rete i i x Te Du ue RR HR ERA
19. Ball Chain 9 6 AD36 DDR B DQ 57 Count 5 UM 7 AE35 DDR B 60 AP12 RSVD 8 AD39 DDR B DQ 56 9 AC34 DDR B DQ 63 1 AD33 DDR B DQSB 7 H 10 AG39 DDR B 00 6 2 AD35 DDR B DM 7 VU 11 AE38 DDR B DQ 51 3 AG38 DDR B DQSB 6 iin diia 12 AE33 DDR B 55 4 AG35 DDR_B_DM 6 iiir 13 AE39 DDR B DQ 50 5 AH42 DDR B DQSB 8 14 DDR B 52 6 40 DDR_B_DQSB_5 ils li 15 AH34 DDR B 48 7 AN36 DDR B DM 5 16 AH36 DDR B 53 8 AV38 DDR B DQSB 4 eere 17 AG33 DDR B DQ 49 9 AY40 DDR B DM 4 18 40 DDR 54 10 BA33 DDR B MA 13 E 19 AH43 DDR B DOS 8 11 BD31 DDR_B_RASB 20 AP39 DDR B 005 5 12 BB32 DDR B CASB 21 AP35 DDR B DQ 42 13 AY31 DDR_B_WEB 22 AN39 DDR B 46 14 AY18 DDR B MA 12 ee 23 AP36 DDR B 41 15 BA19 DDR B MA 11 ilicis 24 AV36 DDR B 44 16 BC18 DDR B MA 14 aS 25 AR34 DDR B 45 17 BB18 DDR B BS 2 26 AN40 DDR B 47 18 BB24 DDR_B_BS_0 27 AR36 DDR B DQ 40 19 AW23 DDR B BS 1 BS 28 AN33 DDR B DQ 43 29 AW39 DDR B DQS 4 30 AV39 DDR B DQ 38 31 AT40 DDR B DQ 35 32 AT38 DDR B DQ 34 33 40 DDR B DQ 39 34 AY39 DDR B DQ 32 Datasheet 323 intel 324 Testability Table 42 XOR Chain 10 Table 42 XOR Chain 10 Ball Chain 10 con Bang Chain 10 35 AW38 DDR_B
20. Datasheet 13 intel Intel 3200 and 3210 Chipset MCH Features 14 Processor Host Interface FSB Dual Core Intel Xeon Processor 3000 Series Quad Core Intel Xeon Processor 3200 Series 800 1067 1333 MT s 200 266 333 MHz FSB Hyper Threading Technology HT Technology FSB Dynamic Bus Inversion DBI 36 bit host bus addressing 12 deep I n Order Queue 1 deep Defer Queue GTL bus driver with integrated GTL termination resistors Supports cache Line Size of 64 bytes System Memory Interface One or two channels each channel consisting of 64 data lines Single or Dual Channel memory organization DDR2 800 667 frequencies Unbuffered ECC and non ECC DDR2 DIMMs Supports 1 Gb 512 Mb DDR2 8 GB maximum memory Direct Media Interface DMI Chip to chip connection interface to Intel 9 2 GB s point to point DMI to I CH9 1 GB s each direction 100 MHz reference clock shared with PCI Express graphics attach 32 bit downstream addressing Messaging and Error Handling PCI Express Interface 3210 MCH supports one x16 PCI Express port or two x8 PCI Express ports 3200 MCH supports one x8 PCI Express port Compatible with the PCI Express Base Specification Revision 1 1 Raw bit rate on data pins of 2 5 Gb s resulting in a real bandwidth per pair of 250 MB s Thermal Sensor Catastrophic Trip Point support Hot Trip Point support for SMI generation Power Management AC
21. pe POL M PCI Slot eee DOTCLK D1 USBCLK Ut PCICLK P1 P6 REFCLK R1 88 277 l n tel Functional Description b Datasheet m e Electrical Characteristics n tel 11 11 1 Table 23 Datasheet Electrical Characteristics This chapter contains the DC specifications for the MCH Absolute Minimum and Maximum Ratings Table 23 specifies the MCH absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time its reliability will be severely degraded or not function when returned to conditions within the functional operating condition limits Although the MCH contains protective circuitry to resist dam
22. 0 6 0 MMR 150 153h 00000000h RO RWO 32 bits This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element Default Bit Access Value Description Target Port Number TPN This field specifies the port number associated 31 24 RO 00h with the element targeted by this link entry Egress Port The target port number is with respect to the component that contains this element as specified by the target component ID Target Component ID TCI D This field identifies the physical or logical 2016 RWO oon component that is targeted by this link entry 15 2 RO 0000h Reserved Link Type LTYP This bit indicates that the link points to memory mapped 1 RO Ob space for RCRB The link address specifies the 64 bit base address of the target RCRB Link Valid LV 0 RWO Ob 0 Link Entry is not valid and will be ignored 1 Link Entry specifies a valid link 8 57 LE1A Link Entry 1 Address B D F Type Address Offset 158 15Fh Default Value Access Size 0 6 0 MMR 0000000000000000h RO RWO 64 bits This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element Bit Access Default Description Value 63 32 Ro 0000000 Reserved Link Address LA This field provides the memory mapped base address of 3112 RWO 000000 the RCRB that is the target
23. Device 6 contains the controls associated with the PCI Express root port that is the intended attach point for external devices In addition it also functions as the virtual PCI to PCI bridge The table below provides an address map of the D1 FO registers listed by address offset in ascending order This chapter provides a detailed bit description of the registers When reading the PCI Express conceptual registers such as this you may not get a valid value unless the register value is stable The PCI Express Specification defines two types of reserved bits Reserved and Preserved Reserved for future RW implementations software must preserve value read for writes to bits Reserved and Zero Reserved for future R WC S implementations software must use 0 for writes to bits Unless explicitly documented as Reserved and Zero all bits marked as reserved are part of the Reserved and Preserved type which have historically been the typical definition for Reserved Most if not all control bits in this device cannot be modified unless the link is down Software is required to first disable the link then program the registers and then re enable the link which will cause a full retrain with the new settings Host Secondary PCI Express Bridge Register Address Map D6 FO Sheet 1 of 3 Address Register Register Name Default Access Offset Symbol Value 0 1h VID1 Vendor Id
24. Dual Channel Modes Dual Channel Symmetric Mode This mode provides maximum performance on real applications Addresses are ping ponged between the channels after each cache line 64 byte boundary If there are two requests and the second request is to an address on the opposite channel from the first that request can be sent before data from the first request has returned If two consecutive cache lines are requested both may be retrieved simultaneously since they are guaranteed to be on opposite channels Dual channel symmetric mode is used when both Channel A and Channel B DIMMs are populated in any order with the total amount of memory in each channel being the same but the DRAM device technology and width may vary from one channel to the other Table 18 is a sample dual channel symmetric memory configuration showing the rank organization Sample System Memory Dual Channel Symmetric Organization Mode Rank ghanneio Address in Channel I ad ressin Channel 0 Channel 1 Rank 3 0 MB 2560 MB 0 MB 2560 MB Rank 2 256 MB 2560 MB 256 MB 2560 MB Rank 1 512 MB 2048 MB 512 MB 2048 MB Rank 0 512 MB 1024 MB 512 MB 1024 MB Dual Channel Asymmetric Mode with Intel Flex Memory Mode Enabled In this addressing mode the lowest DRAM memory is mapped to dual channel operation and the top most DRAM memory is mapped to single channel operation In this mode the system can run at one zone of dual ch
25. PCI Express Input PCI Express Output PCI Express Interface PEG RXN 15 0 PEG RXP 15 0 PCI Express Interface PEG TXN 15 0 PEG TXP 15 0 Analog PCI Express Compensation Signals EXP COMPO EXP COMPI Direct Media nterface Signal Groups DMI Input 3 0 RXN 3 0 DMI Output DMI 3 0 TXN 3 0 System Memory Int erface Signal Groups SSTL 1 8 Input Output DDR A DQ 63 0 DDR A DQS 7 0 DDR A DQSB 7 0 DDR B DQ 63 0 DDR B DQS 7 0 DDR B DQSB 7 0 DDR A CB 7 0 DDR A DQS 8 DDR A DQSB 8 DDR B CB 7 0 DDR B DQS 8 DDR B DQSB 8 SSTL 1 8 Output DDR A CK 5 0 DDR A CKB 5 0 DDR A CSB 3 0 DDR A CKE 3 0 DDR A ODT 3 0 DDR A MA 14 0 DDR A BS 2 0 DDR A RASB DDR A CASB DDR A WEB DDR A DM 7 0 DDR B CK 5 0 DDR B CKB 5 0 DDR B CSB 3 0 DDR B CKE 3 0 DDR B ODT 3 0 DDR B MA 14 0 DDR B BS 2 0 DDR B RASB DDR B CASB DDR B WEB DDR B DM 7 0 Reference and Comp Voltages DDR RCOMPXPD DDR RCOMPXPU DDR RCOMPYPD DDR RCOMPYPU DDR VREF Controller Link Sign al Groups CMOS 1 0 OD CL DATA CL CLK CMOS Input CL RSTB CL PWROK Analog Controller Link Reference Voltage CL VREF 283 m n tel Electrical Characteristics Table 25 Signal Groups Signal Type Signals Notes Clocks HCSL HPL CLKINP HPL CLKINN EXP CLKINP EXP CLKINN DPL REFCLKINN DPL REFCLKI NP Reset and Miscellaneous
26. 200 7 1 19 MID Message Signaled Interrupt 201 7 1 20 MC Message Signaled Interrupt Message 201 7 1 21 MA Message Signaled Interrupt Message 4 5 202 7 1 22 MUA Message Signaled Interrupt Upper Address Optional 202 7 1 23 MD Message Signaled Interrupt Message 4 2 202 7 1 24 HIDM HECI Interrupt Delivery 203 7 2 Memory Mapped Device Specific Registers 3 1 7 7 7 7 2 204 7 2 1 KTRxBR KT Receive Buffer 204 7 2 2 Transmit Holding 000 205 7 2 3 KTDLLR KT Divisor Latch LSB memes 205 7 2 4 KTIER KT Interrupt Enable memes 206 7 2 5 KTDLMR KT Divisor Latch MSB 206 7 2 6 KTIIR KT Interrupt Identification 111 1 207 7 2 7 FIFO Conttol 5 course 208 7 2 8 KTLCR KT Line Control 209 7 2 9 KTMCR KT Modem Control 0 0 0 0 meme emen enn 210 7 2 10 KTLSR KT Line Status A E E 211 7 211 KTMSR KT Modern Status
27. 40 System BI OS Area 0000h FFFFh This area is a single 64 KB segment 000 0000h 000F FFFFh This segment be assigned read and write attributes It is by default after reset Read Write disabled and cycles are forwarded to DMI Interface By manipulating the Read Write attributes the MCH can shadow BIOS into the main DRAM When disabled this segment is not remapped Non snooped accesses from PCI Express or DMI to this region are always sent to DRAM System BI OS Area Memory Segments Memory Segments Attributes Comments OF0000h OFFFFFh WE RE BIOS Area PAM Memory Area Details The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory Area The MCH does not handle IWB Implicit Write Back cycles targeting DMI Since all memory residing on DMI should be set as non cacheable there will normally not be IWB cycles targeting DMI However DMI becomes the default target for processor and DMI originated accesses to disabled segments of the PAM region If the MTRRs covering the PAM regions are set to WB or RD it is possible to get IWB cycles targeting DMI This may occur for processor originated cycles in a DP system and for DMI originated cycles to disabled PAM regions For example say that a particular PAM region is set for Read Disabled and the MTRR associated with this region is set to WB A DMI master generates a memory read targeting the PAM region A snoop i
28. Ballout and Package Information Table 29 MCH Ballout Sorted By Ball Ball Signal Name Ball Signal Name Ball Signal Name N24 FSB DB 42 M8 PEG RXN 13 K36 FSB REQB 3 N23 VSS M7 PEG RXP 13 K35 FSB DB 21 N22 VSS M6 VSS K34 FSB DB 24 N21 RSVD M4 DMI_RXN_O K33 VSS N19 VSS M3 VCCR_EXP K31 FSB DB 33 N18 RSVD M1 PEG TXP 15 K30 VSS N16 VSS L44 FSB_DB_6 K28 FSB_DB_40 N15 VCC N15 L42 FSB_DB_7 K27 VTT_FSB N13 PEG_RXP_4 L41 FSB DINVB 0 K25 VTT_FSB N12 RSVD L40 FSB AB 7 K24 FSB DB 46 N11 RSVD L39 FSB REQB 2 K23 VSS N10 PEG RXN 15 L38 VSS K22 RSVD N8 PEG RXP 15 L36 FSB DB 19 K21 RSVD N7 VSS L35 VSS K19 EXP SLR N6 VSS L34 FSB DB 27 K18 VSS N5 0 133 FSB DB 29 K16 VSS K16 4 VSS L31 VSS K15 VSS N2 DMI TXP 1 L30 FSB DB 36 K13 PEG RXN 3 M45 FSB DB 5 L28 FSB DB 41 K12 VSS M43 VSS L27 VTT FSB K11 PEG RXP 6 M42 FSB DB 3 L25 FSB DB 43 K10 VSS M40 FSB ADSTBB 0 L24 FSB DB 44 K8 PEG RXN 11 M39 VSS L23 VSS K7 PEG RXP 11 M38 FSB AB 4 L22 XORTEST K6 VSS M36 FSB AB 5 L21 VSS K4 PEG_TXN_14 M35 VSS L19 RSVD K3 PEG_RXP_14 M34 VSS L18 RSVD K1 VSS M33 VSS L16 VCC3 3 L16 J44 FSB DSTBPB 0 M31 FSB DB 31 L15 VSS J43 FSB DB 8 M30 FSB DB 35 L13 PEG RXP 3 J41 FSB DB 10 M28 VSS L12 PEG RXN 6 13 27 VTT_FSB L11 VSS 3 VSS M25 FSB DSTBNB 2 L10 PEG RXN 12 J2 PEG RXN 14 M24 VSS L8 V
29. RAE vss PEGLTAN 2 PEG RAPLI vss PEG TXP 1 vss PEG RXN 1 3 4 RSVD H15 PEG RXP 2 PEG RXP 5 vss PEG RXN 7 vss vss vss PEG_TXN_1 vccm exp PEG TARLI RSVD_G15 PEG_RXN_2 PEG_RXN_5 vss PEG_RXP_7 vss vss PEG_RXN_9 vss T vss vss vss vss vss vss PEG_RXP_9 vss PEG_TXP_1 PEGE TXB vss PEG_TXP_1 PEG_TXP_2 PEG_TXN_4 PEG_TXN_6 PEG_RXP_8 vss PEG vss PEG_TXN_1 vss PEG_TXN_2 vss PEG_TXP_4 PEG_TXP_6 vss PEG_RXN_8 vss PEG XN PEG 2 PEG RXN 1 PEG RXN 1 VCCR EXP PEG TXN 5 vss VCCR EXP PEG TXP 8 PEG TXN 8 vss RXN vss PEG RXN 0 PEG RXP 1 PEG TXP 3 PEG TXP 5 PEG TXP 7 PEG TXN 9 PEG 9 VSS NC VSS PEG_TXN_3 VSS PEG_TXN_7 vss VSS TEST2 15 14 13 12 n 10 9 8 7 6 5 4 3 2 1 Datasheet BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA lt 5 Ballout and Package I nformation Datasheet intel Table 28 MCH Table 28 MCH Table 28 MCH Ballout Sorted By Name v Ballout Sorted By Name Ballout Sorted Name Signal Name Ball Signal Name Ball Signal Name Ball ALLZTEST M21 DDR A DM 4 AU44 DDR A DQ 41 AN42 BSELO M22 DDR A DM 5 AN44 DDR A DQ 42 AL44 BSEL1 F21 DDR A DM 6 AE44 DDR_A_DQ_43 AL42 BSEL2 F18 DDR_A_DM_7 AB40 DDR_A_DQ_44 AP42 CL_CLK 14 DDR A DQ 0 BC4 DDR_A_DQ_45 AP45 CL_DATA 1
30. VC Arbitration Table Offset VCATO Indicates the location of the VC Arbitration Table This field contains the zero based offset of the table in 31 24 RO 00h DQWords 16 bytes from the base address of the Virtual Channel Capability Structure A value of 0 indicates that the table is not present due to fixed VC priority 23 0 RO 0000h Reserved 6 50 PVCCTL Port VC Control B D F Type 0 1 0 MMR Address Offset 10C 10Dh Default Value 0000h Access RO RW Size 16 bits Bit Access Berat Description Value 15 4 RO 000h Reserved VC Arbitration Select VCAS This field will be programmed by software to 3 1 RW 000b the only possible value as indicated the VC Arbitration Capability field Since there is no other VC supported than the default this field is reserved 0 RO Ob Reserved 186 Datasheet Host Primary PCI Express Bridge Registers D1 FO tel 6 51 VCORCAP VCO Resource Capability B D F Type 0 1 0 MMR Address Offset 110 113h Default Value 00000001 Access RO Size 32 bits Bit Access 1 Description 31 16 RO 0000h Reserved Reject Snoop Transactions RSNPT 0 Transactions with or without the No Snoop bit set within the Transaction 15 RO Ob Layer Packet header are allowed on this VC 1 When Set any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will be rejected as an Unsupporte
31. not FSB DINVB 3 0 are asserted such that the number of data bits driven electrically low low voltage within 1 0 the corresponding 16 bit group never exceeds 8 FSB_DINVB_ 3 i 13 01 4x FSB_DINVB_x Data Bits FSB DINVB 3 FSB DB 63 48 FSB DINVB 2 FSB DB 47 32 FSB DINVB 1 FSB DB 31 16 FSB DINVB 0 FSB DB 15 0 1 0 FSB DRDYB GTL Data Ready Asserted for each cycle that data is transferred 26 Datasheet Signal Description intel Signal Name Type Description FSB AB 35 3 1 0 GTL 2x Host Address Bus FSB AB 35 3 connect to the processor address bus During processor cycles the FSB AB 35 3 are inputs The MCH drives FSB AB 35 3 during snoop cycles on behalf of DMI and PCI Express initiators FSB AB 35 3 are transferred at 2x rate Note that the address is inverted on the processor bus The values are driven by the MCH between PWROK assertion and FSB CPURSTINB de assertion to allow processor configuration FSB ADSTBB 1 0 FSB DB 63 0 1 0 GTL 2x 1 0 GTL 4x Host Address Strobe The source synchronous strobes used to transfer FSB AB 31 3 and FSB REQB 4 0 at the 2x transfer rate Strobe Address Bits FSB ADSTBB 0 FSB AB 16 3 FSB REQB 4 0 FSB ADSTBB 1 FSB AB 31 17 Host Data These signals are connected to the processor data bus Data on FSB DB 63 0 is transferred at a 4x rate Note that the data signals may be inverted on the processor bus
32. 00010005h RO 144 147h ESD Element Self Description 02000100h RO RWO 150 153h LE1D Link Entry 1 Description 00000000h RO RWO 000000000 158 15Fh LE1A Link Entry 1 Address 0000000h RO RWO 000000000 218 21Fh PESSTS PCI Express Sequence Status 0000FFFh RO 6 1 VI D1 Vendor Identification B D F Type 0 1 0 PCI Address Offset 0 11 Default Value 8086h Access Size RO 16 bits This register combined with the Device Identification register uniquely identify any PCI device Default 4122 Bit Access Value Description 15 0 RO 8086h Vendor Identification VI D1 PCI standard identification for Intel Datasheet 149 Host Primary PCI Express Bridge Registers D1 FO 6 2 DI D1 Device Identification B D F Type 0 1 0 PCI Address Offset 2 3h Default Value 29F1h Access RO Size 16 bits This register combined with the Vendor Identification register uniquely identifies any PCI device Bit Access Default Description Value 15 8 RO 29h Device Identification Number DI D1 UB Identifier assigned to the device 1 virtual PCI to PCI bridge PCI Express port 7 4 RO Fh Device I dentification Number DID1 HW Identifier assigned to the i device 1 virtual PCI to PCI bridge PCI Express port 3 0 RO 1h Device Identification Number DI D1 LB Identifier assigned to the device 1 virtual PCI to PCI bridge PCI E
33. 2 pagesize number of banks for rank3 for given channel Channel 0 DRAM Rank 2 Attributes CODRA2 This register defines DRAM 7 0 RW 00h pagesize number of banks for rank2 for given channel 5 2 37 EPDCYCTRKWRTPRE EPD CYCTRK WRT PRE B D F Type 0 0 0 MCHBAR Address Offset 19 1 Default Value 0000h Access RW RO Size 16 bits EPD CYCTRK WRT PRE Status registers Default S Bit Access Value Description ACTTo PRE Delayed COsd cr act pchg This field indicates the minimum 15 11 RW 00000b allowed spacing in DRAM clocks between the ACT and PRE commands to the same rank bank Write To PRE Delayed COsd cr wr pchg This field indicates the minimum 10 6 RW 00000b allowed spacing in DRAM clocks between the WRITE and PRE commands to the same rank bank READ To PRE Delayed COsd cr rd pchg This field indicates the minimum 5 2 RW 0000b allowed spacing in DRAM clocks between the READ and PRE commands to the same rank bank 1 0 RO 00b Reserved Datasheet 125 DRAM Controller Registers DO FO 5 2 38 EPDCYCTRKWRTACT EPD CYCTRK WRT ACT B D F Type 0 0 0 MCHBAR Address Offset A1C A1Fh Default Value 000000008 Access RO RW Size 32 bits EPD CYCTRK WRT ACT Status registers 3 Default Bit Access Value Description 31 21 RO 000h Reserved ACT to ACT Delayed COsd cr act act This configuration register 20 17 RW 00006 indicates the minimum allowed spaci
34. 6 4 RO 000b priority VC LPVC group that has the lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration 3 RO Ob Reserved Extended VC Count EVCC Indicates the number of extended Virtual 2 0 RWO 001b Channels in addition to the default VC supported by the device The Private Virtual Channel is not included in this count 260 Datasheet m e Direct Media Interface DMI RCRB tel 9 3 DMIPVCCTL DMI Port VC Control B D F Type 0 0 0 DMIBAR Address Offset C Dh Default Value 0000 Access RO RW Size 16 bits Default ae Bit Access Value Description 15 4 RO 000h Reserved VC Arbitration Select VCAS This field will be programmed by software to 3 1 RW 000b the only possible value as indicated in the VC Arbitration Capability field See the PCI express specification for more details 0 RO Ob Reserved 9 4 DMI VCORCAP DMI VCO Resource Capability B D F Type 0 0 0 DMIBAR Address Offset 10 13h Default Value 00000001h Access RO Size 32 bits Default Bit Access Value Description 31 16 RO Os Reserved Reject Snoop Transactions REJ SNPT 0 Transactions with or without the No Snoop bit set within the TLP header are 15 RO Ob allowed on this VC 1 When Set any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will
35. 80 57 42 AW22 DDR_A_DQ_31 6 es DDR A DO_59 43 AT22 DDR A DQ 27 DDR A DO 60 44 AN22 DDR A DQ 26 8 TS DDR_A_DQ_63 45 AN19 DDR A DQ 24 3 AB3S DB athe 46 AV19 DDR A DQ 28 10 AD43 DDR_A_DQS_6 m EXPE DDR DOS 2 11 AC42 DDR_A_DQ_50 4B Bee DDR A DQ 18 12 AC39 DDR A DQ 55 dc DDR DQ 22 13 41 DDR A DQ 48 56 00 19 14 AD40 DDR_A_DQ_54 i DQ 17 15 AC45 DDR A DQ 51 DDR A DQ 23 16 AF42 DDR_A_DQ_52 ERIS DDR A 20 17 AF45 DDR_A_DQ_53 sd EDS DDR A 00 16 18 42 DDR_A_DQ_49 EE BEES DDR DQ 21 19 AL38 DDR A DQS 8 BATI DDR DOS 1 20 AM43 DDR_A_DQS_5 13 21 AL40 DDR_A_DQ_46 Bd DDR DQ 14 321 i n tel n Testability Table 38 XOR Chain 6 BLUR Ball Chain 6 Table 40 XOR Chain 8 Pin 59 BB11 DDR_A_DQ_15 Count Ball cana 60 BE12 DDR A DQ 11 AN13 RSVD 61 BD9 DDR A DQ 8 62 9 DDR A DQ 12 1 AG42 DDR_B_CB 2 63 BB12 DDR_A_DQ_10 2 AG44 DDR B CB 7 64 BB10 DDR A DQ 9 3 1 DDR B CB 6 65 DDR A DQS 0 4 AK45 DDR B CB 0 66 BB7 DDR A DQ 7 5 Aj 42 DDR B CB 4 67 BB8 DDR A DQ 2 6 40 DDR B CB 3 68 BE8 DDR A DQ 3 7 AJ44 DDR B CB 1 69 BD7 DDR A DQ 6 8 AK42 DDR_B_CB_5 70 BD4 DDR A DQ 1 9 BB34
36. Each bit location within this field corresponds to a Port Arbitration Capability defined below When more than one bit in this field is Set it indicates that the VC resource can be configured to provide different arbitration services Software selects among these capabilities by writing to the Port Arbitration Select field see below 7 0 RO Olh pit o Default 01b Non configurable hardware fixed arbitration scheme e g Round Robin RR Bit 1 Weighted Round Robin WRR arbitration with 32 phases Bit 2 WRR arbitration with 64 phases Bit 3 WRR arbitration with 128 phases Bit 4 Time based WRR with 128 phases Bit 5 WRR arbitration with 256 phases Bits 6 7 Reserved MCH default indicates Non configurable hardware fixed arbitration scheme Datasheet 253 Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 52 VCORCTL VCO Resource Control B D F Type 0 6 0 MMR Address Offset 114 117h Default Value 800000FFh Access RO RW Size 32 bits This register controls the resources associated with PCI Express Virtual Channel 0 Bit Access Berat Description Value VCO Enable VCOE For VCO this is hardwired to 1 and read only as VCO can 31 RO 1b never be disabled 30 27 RO Oh Reserved VCO I D VCOI D This field assigns a VC ID to the VC resource For VCO this is 26 24 RO 0909 hardwired to 0 and read only 23 20 RO 0000h Reserved Port Arbitr
37. Port VC Capability Register 1 00000000h RO 108 10Bh PVCCAP2 Port VC Capability Register 2 00000000h RO 10C 10Dh PVCCTL Port VC Control 0000h RO RW 110 113h VCORCAP VCO Resource Capability 00000000h RO 114 117h VCORCTL VCO Resource Control 800000FFh RO RW 11A 11Bh VCORSTS VCO Resource Status 0002h RO 140 143h RCLDECH Root Complex Link Declaration Enhanced 00010005h RO 144 147h ESD Element Self Description 03000100h RO RWO 150 153h LE1D Link Entry 1 Description 00000000h RO RWO 0000000000 158 15Fh LE1A Link Entry 1 Address 000000h RO RWO 8 1 VI D1 Vendor Identification B D F Type 0 6 0 PCI Address Offset 0 1 Default Value 8086 Access RO Size 16 bits This register combined with the Device Identification register uniquely identify any PCI device Default WESS Bit Access Value Description 15 0 RO 8086h Vendor Identification VI D1 PCI standard identification for Intel Datasheet 215 Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 2 DI D1 Device Identification B D F Type 0 6 0 PCI Address Offset 2 3h Default Value 29F9h Access RO Size 16 bits This register combined with the Vendor Identification register uniquely identifies any PCI device Bit Access Default Description Value 15 8 RO 29h Device Identification Number DI D1 UB Identifier assigned to the device 6 virtual
38. RW Ob Parity Error Response Enable PEREN Controls whether or not the Master Data Parity Error bit in the Secondary Status register is set when the MCH receives across the link upstream a Read Data Completion Poisoned Transaction Layer Packet 0 Master Data Parity Error bit in Secondary Status register can NOT be set 1 Master Data Parity Error bit in Secondary Status register CAN be set Datasheet 165 n tel Host Primary PCI Express Bridge Registers D1 FO 6 25 PM CAPID1 Power Management Capabilities B D F Type 0 1 0 PCI Address Offset 80 83h Default Value 8039001 Access RO Size 32 bits Bit Access petals Description Value PME Support PMES This field indicates the power states in which this device may indicate PME wake via PCI Express messaging DO D3hot amp D3cold This 31 27 RO 19h device is not required to do anything to support D3hot amp D3cold it simply must report that those states are supported Refer to the PCI Power Management 1 1 specification for encoding explanation and other power management details D2 Power State Support D2PSS Hardwired to 0 to indicate that the D2 26 RO 95 power management state is NOT supported D1 Power State Support D1PSS Hardwired to 0 to indicate that the D1 25 RO Ob power management state is NOT supported 24 22 RO 000b Auxiliary Current AUXC Hardwired to 0 to indicate that there are no 3 3Vaux au
39. RWC S RO 99 n tel DRAM Controller Registers DO FO 5 2 1 CHDECMI SC Channel Decode Misc B D F Type 0 0 0 MCHBAR Address Offset 111h Default Value 00h Access RW L Size 8 bits This register provides miscellaneous CHDEC MAGEN configuration bits Default ar Bit Access Value Description 7 RW L Ob Reserved Enhanced Mode Select ENHMODESEL 00 Swap Enabled for Bank Selects and Rank Selects 6 5 RW L 00b 01 XOR Enabled for Bank Selects and Rank Selects 10 Swap Enabled for Bank Selects only 11 XOR Enabled for Bank Select only This register is locked by ME stolen Memory lock 4 RW L Ob Channel 2 Enhanced Mode CH2 ENHMODE 3 RW L Ob Channel 1 Enhanced Mode CH1_ENHMODE 2 RW L Ob Channel 0 Enhanced Mode CHO_ENHMODE 1 RW L Ob Reserved EP Present EPPRSNT This bit indicates whether EP UMA is present in the 0 RW L Ob system or not This register is locked by ME stolen Memory lock 100 Datasheet m e DRAM Controller Registers DO FO n tel 5 2 2 Datasheet CODRBO Channel 0 DRAM Rank Boundary Address O B D F Type 0 0 0 MCHBAR Address Offset 200 2011 Default Value 0000h Access RO RW L Size 16 bits The DRAM Rank Boundary Registers define the upper boundary address of each DRAM rank with a granularity of 64MB Each rank has its own single word DRB register These registers are used to determine which chip select will be active for a given ad
40. This bit is a global enable bit for Device 0 and Device 6 for the 3210 MCH SERR messaging The MCH does not have an SERR signal The MCH communicates the SERR condition by sending an SERR message over DMI to the ICH 1 The is enabled to generate SERR messages over DMI for specific Device 0 error conditions that are individually enabled in the ERRCMD and 8 RW Ob DMIUEMSK registers The error status is reported in the ERRSTS PCISTS and DMIUEST registers 0 The SERR message is not generated by the MCH for Device 0 Note that this bit only controls SERR messaging for the Device 0 Device 1 has its own SERRE bits to control error reporting for error conditions occurring in that device The control bits are used in a logical OR manner to enable the SERR DMI message mechanism Address Data Stepping Enable ADSTEP Address data stepping is not 7 RO Ob implemented in the MCH and this bit is hardwired to 0 Writes to this bit position have no effect Parity Error Enable PERRE Controls whether or not the Master Data Parity 6 ay Ob Error bit in the PCI Status register can bet set 0 Master Data Parity Error bit in PCI Status register NOT be set 1 Master Data Parity Error bit in PCI Status register CAN be set 5 RO Ob Reserved Memory Write and I nvalidate Enable MWIE The will never issue 4 RO Ob memory write and invalidate commands This bit is therefore hardwired to 0 Writes to this bit position will have no effect
41. depending on the FSB DINVB 3 0 signals FSB DSTBPB 3 0 FSB DSTBNB 3 0 1 0 GTL 4x Differential Host Data Strobes The differential source synchronous strobes used to transfer FSB_DB_ 63 0 and FSB_DINVB_ 3 0 at the 4x transfer rate Named this way because they are not level sensitive Data is captured on the falling edge of both strobes Hence they are pseudo differential and not true differential Strobe Data Bits FSB DSTB PBN B FSB DB 63 48 HDINVB_3 FSB DSTB RBN B 2 FSB DB 47 32 HDINVB 2 FSB DSTB PBN B 1 FSB DB 31 16 HDINVB 1 FSB DSTB PBN B FSB DB 15 0 HDINVB 0 FSB HITB 1 0 GTL Hit Indicates that a caching agent holds an unmodified version of the requested line Also driven in conjunction with FSB_HITMB by the target to extend the snoop window FSB_HITMB 1 0 GTL Hit Modified Indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line Also driven in conjunction with FSB HITB to extend the snoop window FSB LOCKB GTL Host Lock All processor bus cycles sampled with the assertion of FSB_LOCKB and FSB_ADSB until the negation of FSB LOCKB must be atomic i e no DMI or PCI Express access to DRAM are allowed when FSB LOCKB is asserted by the processor FSB_REQB 4 0 1 0 GTL 2x Host Request Command Defines the attributes of the request FSB REQB 4 0 ar
42. n tel 3 9 1 Datasheet PCI Express 1 Address Mapping The can be programmed to direct non memory 1 0 accesses to the PCI Express bus interface when processor initiated 1 cycle addresses are within the PCI Express 1 address range This range is controlled via the 1 0 Base Address IOBASE and 1 0 Limit Address IOLIMIT registers in MCH Device 1 configuration space Address decoding for this range is based on the following concept The top 4 bits of the respective 1 0 Base and 1 0 Limit registers correspond to address bits A 15 12 of an address For the purpose of address decoding the assumes that lower 12 address bits A 11 0 of the I O base are zero and that address bits A 11 0 of the I O limit address are FFFh This forces the 1 0 address range alignment to 4 KB boundary and produces a size granularity of 4 KB The positively decodes 1 0 accesses to PCI Express I O address space as defined by the following equation O Base Address lt Processor I O Cycle Address lt 1 Limit Address The effective size of the range is programmed by the plug and play configuration software and it depends on the size of I O space claimed by the PCI Express device Note that the MCH Device 1 and or Device 6 I O address range registers defined above are used for all 1 0 space allocation for any devices requiring such a window on PCI Express The PCICMD1 register can disable the routing of I O cycles to PC
43. 0 3 0 PCI Address Offset 3Fh Default Value 00h Access RO Size 8 bits z Default m Bit Access Value Description 7 0 RO 00h Latency LAT Not implemented hardwired to O 7 1 19 HFS Host Firmware Status B D F Type 0 Address Offset 40 43h Default Value 00000000h Access RO Size 32 bits Default Bit Access Description 0000000 Firmware Status Host Access FS_HA Indicates current status of the 31 0 RO Oh firmware for the HECI controller This field is the host s read only access to the FS field in the ME Firmware Status AUX register 7 1 16 PID PCI Power Management Capability I D B D F Type 0 3 0 PCI Address Offset 50 51h Default Value 8 01 Access RO Size 16 bits Bit Access Baron Description Value Next Capability NEXT Indicates the location of the next capability item in 13 8 RO the list This is the Message Signaled Interrupts capability 7 0 RO 01 Cap ID CI D Indicates that this pointer is PCI power management Datasheet 199 Intel Manageability Engine Subsystem PCI D3 F0 F3 7 1 17 PC PCI Power Management Capabilities B D F Type 0 3 0 PCI Address Offset 52 53h Default Value C803h Access RO Size 16 bits Bit Access Defaut Description Value PME_ Support PSUP Indicates the states that can generate PME
44. 23 20 RW Oh E e active rank in a one hot manner 19 17 RW 000b CKE Pulse Width Requirement in Low Phase sdO cr cke pw safe This field indicates pulse width requirement in low phase 16 15 RO Oh Reserved EPDunit MPR Mode EPDMPR MPR Read Mode 1 MPR mode 14 RW Ob 0 Normal mode In MPR mode only read cycles must be issued by Firmware Page Results are ignored by DCS and just issues the read chip select EPDunit Power Down enable for ODT Rank EPDOAPDEN Configuration to enable the ODT ranks to dynamically enter power down 13 RW Ob 1 Enable active power down 0 Disable active power down EPDunit Power Down enable for Active Rank EPDAAPDEN Configuration to enable the active rank to dynamically enter power down 12 RW Ob 1 Enable active power down 0 Disable active power down 11 10 RO Oh Reserved 9 1 RW 0000000 Self Refresh Exit Count sdO cr slfrfsh exit cnt This field indicates the 00b Self refresh exit count Program to 255 128 Datasheet m DRAM Controller Registers DO FO n tel Bit Access Default Description Value Indicates Only 1 Rank Enabled sdO cr singledimmpop This field 0 RW Ob indicates the that only 1 rank is enabled This bit needs to be set if there is one active rank and no odt ranks or if there is one active rank and one ODT rank and they are the same rank 5 2 43 EPDREFCONFI G EP DRAM Refresh Config
45. 3 2 RO 00b Reserved Overrun Error OE This bit is cleared by hardware when the LSR register is 1 RO CR Ob being read by the Host The FW typically sets this bit but it is cleared by hardware when the host reads the LSR Data Ready DR Non FIFO Mode This bit is set when the FW writes to the RBR register and cleared by 0 RO Ob hardware when the RBR register is being Read by the Host FIFO Mode This bit is set by hardware when the RBR FIFO is not empty and cleared by hardware when the RBR FIFO is empty This bit is reset on Host System Reset or D3 gt D0 transition Datasheet 211 Intel Manageability Engine Subsystem PCI D3 FO F3 pee 1 KTMSR KT Modem Status B D F Type 0 3 3 KT MM IO Address Offset 6h Default Value 00h Access RO RO CR Size 8 bits The functionality of the Modem is emulated by the FW This register provides the status of the current state of the control lines from the modem Note Reset Host system Reset or 3 gt 00 transition Bit Access POMPE Description Value J RO Ob Data Carrier Detect DCD In Loop Back mode this bit is connected by hardware to the value of MCR bit 3 6 RO Ob Ring I ndicator In Loop Back mode this bit is connected by hardware to the value of MCR bit 2 5 RO Ob Data Set Ready DSR Loop Back mode this bit is connected by hardware to the value of MCR bit O 4 RO Ob Clear To Send CTS Loop Back mode this bit is co
46. 5 1 31 BSM Base of Stolen 2 4 2 ene 89 5 1 32 TSEGMB TSEG Memory Base menn nnn nnn 89 5 1 33 TOLUD Top of Low Usable 90 Datasheet 5 1 34 ERRSTS Error Status iii iei eine 91 5 1 35 ERRCMD Error Command anaes 93 5 1 36 SMICMD SMI eene 94 5 1 37 SKPD Scratchpad 0 11 senem sensere nnns 94 5 1 38 CAPIDO Capability Identifier cece mms 95 5 2 IMCHBAR PE 98 5 2 1 CHDECMISC Channel Decode 00001 1 100 5 2 2 CODRBO Channel 0 DRAM Rank Boundary Address 0 101 5 2 3 CODRB1 Channel 0 DRAM Rank Boundary Address 1 102 5 2 4 CODRB2 Channel 0 DRAM Rank Boundary Address 2 103 5 2 5 CODRB3 Channel 0 DRAM Rank Boundary Address 3 103 5 2 6 CODRAO1 Channel 0 DRAM Rank 0 1 104 5 2 7 CODRA23 Channel 0 DRAM Rank 2 3 105 5 2 8 COCYCTRKPCHG Channel 0 CYCTRK PCHG 105 5 2 9 COCYCTRKACT Channel 0 CYCTRK
47. Bit Access Default Description Value VCO Enable VCOE For VCO this is hardwired to 1 and read only as VCO can 31 RO 1b never be disabled 30 27 RO Oh Reserved VCO I D VCOI D Assigns a VC ID to the VC resource For VCO this is 26 24 RO 0909 hardwired to 0 and read only 23 20 RO 0000h Reserved Port Arbitration Select This field configures the VC resource to provide a particular Port Arbitration service This field is valid for RCRBs Root Ports that 00b support peer to peer traffic and Switch Ports but not for PCI Express Endpoint 19 17 RW 000 devices or Root Ports that do not support peer to peer traffic The permissible value of this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource 16 8 RO 00h Reserved TC VCO Map TCVCOM Indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 7 is set in this field TC7 is mapped to this VC resource When 7 1 RW 7Fh more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link 0 RO 1b TCO VCO Map TCOVCOM Traffic Class 0 is always routed to VCO 188 Datasheet m e Host Primary PCI
48. CC CDh SMICMD SMI Command 0000h RO RW DC DFh SKPD Scratchpad Data 00000000h RW 00000001C1 EO EBh CAPIDO Capability Identifier 064000010C RO 0009h Datasheet 66 DRAM Controller Registers DO FO 5 1 Configuration Register Details 5 1 1 VI D Vendor Identification B D F Type 0 0 0 PCI Address Offset O 1h Default Value 8086h Access RO Size 16 bits This register combined with the Device Identification register uniquely identifies any PCI device Default 4254 Bit Access Value Description 15 0 RO 8086h Vendor Identification Number VI D PCI standard identification for Intel 5 1 2 DI D Device dentification B D F Type 0 0 0 PCI Address Offset 2 3h Default Value 29FOh Access RO Size 16 bits This register combined with the Vendor Identification register uniquely identifies any PCI device fault 2 Bit Access 1 Description Device Identification Number DI D This field identifier assigned to the 15 0 RO PCI device Datasheet 67 n tel DRAM Controller Registers DO FO 5 1 3 PCI Command B D F Type 0 0 0 PCI Address Offset 4 5h Default Value 0006h Access RO RW Size 16 bits Since MCH Device 0 does not physically reside on PCI A many of the bits are not implemented Default Bit Access Value Description 15 9 RO 00h Reserved SERR Enable SERRE
49. Capability List CLIST This bit is hardwired to 1 to indicate to the configuration software that this device function implements a list of new 4 RO 1b capabilities A list of new capabilities is accessed via register CAPPTR at configuration address offset 34h Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the Capability Identification register resides 3 0 RO 0000b Reserved Datasheet 69 intel DRAM Controller Registers DO FO 5 1 5 RI D Revision Identification B D F Type 0 0 0 PCI Address Offset 8h Default Value See table below Access RO Size 8 bits This register contains the revision number of the Device 0 These bits are read only and writes to this register have no effect Default Bit Access Value Description Revision Identification Number RI D This is an 8 bit value that 7 0 RO See indicates the revision identification number for the Device 0 Refer to d description the Intel 3200 and 3210 Chipset Specification Update for the value of this register 5 1 6 CC Class Code B D F Type 0 0 0 PCI Address Offset 9 Default Value 0600001 Access RO Size 24 bits This register identifies the basic function of the device a more specific sub class and a register specific programming interface Bit Access Default Description Value 23 16 RO 06h Base Cla
50. Configuration cycles to the PCI Express PCI compatibility configuration space are routed to the PCI Express port device or associated link Datasheet MCH Register Description n tel Figure 10 4 4 1 Datasheet MCH Configuration Cycle Flow Chart DW Write to CONFIG ADDRESS with bit 31 1 Read Write to CONFIG_DATA MCH Generates Bus gt SEC BUS Devices 0 amp 1 Bus lt SUB BUS Functions 0 MCH Claims to PCI Express in MCH Dev 1 Device 0 Bus SECONDARYBUS in MCH Dev 1 Devices 1 amp Dev 1 Enabled amp Function 0 MCH Generates DMI Type 1 Configuration Cycle MCH Generates DMI Type 0 Configuration Cycle MCH Generates Type 0 Access to PCI Express MCH allows cycle to go to DMI resulting in Master Abort Yes MCH Claims I nternal Device Configuration Accesses The MCH decodes the Bus Number bits 23 16 and the Device Number fields of the CONFIG ADDRESS register If the Bus Number field of CONFIG ADDRESS is 0 the configuration cycle is targeting a PCI Bus 0 device If the targeted PCI Bus 0 device exists in the and is not disabled the configuration cycle is claimed by the appropriate device 61 m n tel MCH Register Description 4 4 2 4 4 2 1 4 4 2 2 62 Bridge Related Configur
51. Datasheet 179 intel Host Primary PCI Express Bridge Registers D1 FO Bit Access Derault Description Value MRL Sensor Present MSP When set to 1b this bit indicates that an MRL 2 RO Ob Sensor is implemented on the chassis for this slot Power Controller Present PCP When set to 1b this bit indicates that a 1 RO Ob software programmable Power Controller is implemented for this slot adapter depending on form factor 0 RO Ob Attention Button Present ABP When set to 1b this bit indicates that an Attention Button for this slot is electrically controlled by the chassis 6 42 SLOTCTL Slot Control B D F Type Address Offset Default Value Access Size 0 1 0 PCI B8 B9h 0000h RO RW 16 bits PCI Express Slot related registers Bit Access Default Value Description 15 13 RO 000b Reserved 12 RO Ob Data Link Layer State Changed Enable DLLSCE If the Data Link Layer Link Active capability is implemented when set to 1b this field enables software notification when Data Link Layer Link Active field is changed If the Data Link Layer Link Active capability is not implemented this bit is permitted to be read only with a value of Ob 11 RO Ob Electromechanical I nterlock Control EI C If an Electromechanical Interlock is implemented a write of 1b to this field causes the state of the interlock to toggle A wr
52. Functional Description D 47 32 DBI2 DSTBP2 DSTBN2 D 31 16 1 D 63 48 DBIS DSTBP3 DSTBN3 Signals Associated Clock or Strobe Signal Group ADS BNR BPRI DEFER BCLK DBSY DRDY HIT HITM 1X LOCK RS 2 0 TRDY RESET BRO 16 3 REQ 4 0 ADSTB 0 Ay HA 35 17 ADSTB 1 D 15 0 DBIO DSTBPO DSTBNO DSTBP1 DSTBN1 4X APIC Cluster Mode Support APIC Cluster mode support is required for backwards compatibility with existing software including various operating systems The MCH supports three types of interrupt re direction Physical Flat Logical Clustered Logical Datasheet Functional Description 10 2 10 2 1 10 2 1 1 10 2 1 2 10 2 1 2 1 Table 18 10 2 1 2 2 Datasheet intel System Memory Controller The system memory controller supports DDR2 protocol with two independent 64 bit wide channels each accessing one or two DIMMs It supports a maximum of two un buffered ECC or non ECC DDR2 DIMMs per channel thus allowing up to four device ranks per channel System Memory Organization Modes The system memory controller supports two memory organization modes Single Channel and Dual Channel Single Channel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B DIMMs are populated in any order but not both
53. If any of the following conditions are violated the results of SMM accesses are unpredictable and may cause the system to hang 1 The Compatible SMM space must not be set up as cacheable 2 High or TSEG SMM transaction address space must not overlap address space assigned to system DRAM or to any PCI devices including DMI Interface and PCI Express This is a BIOS responsibility 3 Both D OPEN and D CLOSE must not be set to 1 at the same time 4 When TSEG SMM space is enabled the TSEG space must not be reported to the OS as available DRAM This is a BIOS responsibility 5 Any address translated through the GMADR TLB must not target DRAM from A 0000 F FFFFh 3 7 3 SMM Space Combinations When High SMM is enabled G SMRAME 1 SMRAM 1 the Compatible SMM space is effectively disabled Processor originated accesses to the Compatible SMM space are forwarded to PCI Express otherwise they are forwarded to the DMI Interface PCI Express and DMI Interface originated accesses are never allowed to access SMM space Table 6 SMM Space Table Global Enable High Enable TSEG Enable Compatible High H TSEG T G SMRAME H SMRAM EN TSEG EN C Range Range Range 0 X X Disable Disable Disable 1 0 0 Enable Disable Disable 1 0 1 Enable Disable Enable 1 1 0 Disabled Enable Disable 1 1 1 Disabled Enable Enable 50 Datasheet System Address Map 3 7 4 Table 7 3 7 5 3
54. MRL Sensor Changed MSC If an MRL sensor is implemented this bit is set 2 RO Ob when a MRL Sensor state change is detected If an MRL sensor is not implemented this bit must not be set Power Fault Detected PFD If a Power Controller that supports power fault detection is implemented this bit is set when the Power Controller detects a power fault at this slot Note that depending on hardware capability it is possible that a power fault can be detected at any time independent of the Power Controller Control setting or the occupancy of the slot If power fault detection is not supported this bit must not be set Attention Button Pressed ABP If an Attention Button is implemented 0 RO Ob this bit is set when the attention button is pressed If an Attention Button is not supported this bit must not be set 182 Datasheet Host Primary PCI Express Bridge Registers D1 FO tel 6 44 RCTL Root Control B D F Type 0 1 0 PCI Address Offset BC BDh Default Value 0000h Access RO RW Size 16 bits This register allows control of PCI Express Root Complex specific parameters The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error reported in this device s Device Status register or when an error message is received across the link Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in
55. Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined 1 0 address range will be at the top of a 4 KB aligned address block Bit Access Description Value Address Limit IOLI MIT Corresponds to A 15 12 of the 1 0 address 7 4 RW Oh limit of device 1 Devices between this upper limit and OBASE1 will be passed to the PCI Express hierarchy associated with this device 3 0 RO Oh Reserved 156 Datasheet Host Primary PCI Express Bridge Registers D1 FO tel 6 14 SSTS1 Secondary Status B D F Type 0 1 0 PCI Address Offset 1E 1Fh Default Value 0000 Access RO RWC Size 16 bits SSTS1 is a 16 bit status register that reports the occurrence of error conditions associated with secondary side of the virtual PCI PCI bridge embedded within MCH Bit Access Derault Description Value Detected Parity Error DPE This bit is set by the Secondary Side for a Type 1 15 RWC Ob Configuration Space header device whenever it receives a Poisoned Transaction Layer Packet regardless of the state of the Parity Error Response Enable bit in the Bridge Control Register Received System Error RSE This bit is set when the Secondary Side for a 14 RWC Ob Type 1 configuration space header device receives an ERR_FATAL or ERR_NONFATAL Received Master Abort RMA This bit is set when the Secon
56. PMBASE and Pre fetchable Memory Limit PMLIMIT registers Conceptually address decoding for each range follows the same basic concept The top 12 bits of the respective Memory Base and Memory Limit registers correspond to address bits A 31 20 of a memory address For the purpose of address decoding the MCH assumes that address bits A 19 0 of the memory base are zero and that address bits A 19 0 of the memory limit address are FFFFFh This forces each memory address range to be aligned to 1MB boundary and to have a size granularity of 1 MB The MCH positively decodes memory accesses to PCI Express memory address space as defined by the following equations Memory Base Address Address Memory Limit Address Prefetchable Memory Base Address lt Address xPrefetchable Memory Limit Address The window size is programmed by the plug and play configuration software The window size depends on the size of memory claimed by the PCI Express device Normally these ranges will reside above the Top of Low Usable DRAM and below High BIOS and APIC address ranges They MUST reside above the top of low memory TOLUD if they reside below 4 GB and MUST reside above top of upper memory TOUUD if they reside above 4 GB or they will steal physical DRAM memory space It is essential to support a separate Pre fetchable range in order to apply USWC attribute from the processor point of view to that range The USWC attribute is used by the processor for write
57. Register Name Symbol Start End Value access RW L RW Thermal Sensor Control 1 TSC1 CD8 CD8 00h RS WC Thermal Sensor Control 2 TSC2 CD9 CD9 00h RO RW L Thermal Sensor Status TSS CDA CDA 00h RO E Sensor Temperature Trip TSTTP CDC CDF 00000000h RO RW RW L Thermal Calibration Offset TCO CE2 CE2 00h RW L K RW L RW L RO Hardware Throttle Control THERM1 CE4 CE4 00h RW L K TCO Fuses THERM3 CE6 CE6 00h RO RS WC Thermal Interrupt Status TIS CEA CEB 0000h RO RWC Thermal SMI Command TSMICMD CF1 CF1 00h RO RW Datasheet 275 intel 10 5 10 6 276 Functional Description Power Management Power Management Feature List ACPI 1 0b support ACPI SO S1 S5 CO C1 and C2 states Enhanced power management state transitions for increasing time processor spends in low power states PCI Express Link States LO LOs L2 L3 Ready L3 Clocking The MCH has a total of 3 PLLs providing many times that many internal clocks The PLLs are Host PLL Generates the main core clocks in the host clock domain Can also be used to generate memory core clocks Uses the Host clock H_CLKIN as a reference Memory 1 0 PLL Optionally generates low jitter clocks for memory 1 0 interface as opposed to from Host PLL Uses the Host FSB differential clock HPL_CLKINP HPL CLKINN as a reference Low jitter clock source from memory 1 0 PLL is required for DDR667 and higher frequencies PCI Express PLL Generates all PCI Expre
58. address range will be aligned to a 4 KB boundary Default Bit Access Value Description 7 4 RW Fh 1 Address Base I OBASE This field corresponds to A 15 12 of the 1 0 addresses passed by bridge 1 to PCI Express 3 0 RO Oh Reserved 8 13 I OLI MIT1 I O Limit Address B D F Type 0 6 0 PCI Address Offset 1Dh Default Value 00h Access RW RO Size 8 bits This register controls the processor to PCI Express 1 0 access routing based on the following formula IO BASE lt address xIO LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined 1 0 address range will be at the top of a 4 KB aligned address block Bit Access Description Value Address Limit 1 OLI MIT Corresponds to A 15 12 of the 1 0 address 7 4 RW Oh limit of device 6 Devices between this upper limit and 5 1 will be passed to the PCI Express hierarchy associated with this device 3 0 RO Oh Reserved 222 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 14 SSTS1 Secondary Status B D F Type Address Offset Default Value Access Size 0 6 0 PCI 1E 1Fh 0000h RO RWC 16 bits SSTS1 is a 16 bit status register that reports the occurrence of error conditions associated with secondary side of the virtual PCI PCI bridge embedded within MCH
59. ee eee 15 1 1 17 12 wees 20 1 2 1 iMoSElnterfdCe s cote 20 1 2 2 System Memory Interface 0 20 1 2 3 Direct Media Interface 66 21 1 2 4 Express Interface cec cetero keen e Rr Ded 22 1 2 5 E 23 1 2 6 Power eene nennen ne ene nn nnn 23 1 2 7 Thermal Sensor x actu eee a excitet eR ea noes ath aie nq E REA 23 2 Signal Description err obe ped eae las area rx Mt edna 25 2 1 Host interface Signals iere tai i ura RU 26 2 2 System Memory DDR2 Interface Signals 29 2 2 1 System Memory Channel A Interface 5 29 2 2 2 System Memory Channel B Interface 5 30 2 2 3 System Memory Miscellaneous Signals 31 2 3 PCI Express Interface 2 lt mind ea a Ene eh Ra a e He kae EIS 31 2 4 Controller L
60. vss vs AK7 VS AD38 vss VSS VsSS AD34_ VSS AR27 VSS AJ41 VSS AD27 VSS AR23 VSS 4 VSS AD25 VSS AR22 VSS AH45 VSS AD23 VSS AR21 VSS AH40 VSS AD21 VSS AR19 VSS AH39 VSS AD19 VSS AR15 VSS AH38 VSS AD13 VSS AR8 VSS AH35 VSS AD6 VSS AR7 VSS AH32 VSS AD1 VSS AR6 VSS AH27 VSS AC43 vss ARA vss 25 55 8 VSS AP43 VSS AH23 VSS AC35 vss AP38 VSS Vss VSS AP33 VSS AH12 VSS AC26 VSS AP30 VSS AH8 VSS AC24 VSS AP25 VSS 1 VSS AC22 VSS AP23 VSS AG36 VSS AC20 VSS AP22 VSS AG34 VSS AC14 VSS AP18 VSS AG26 VSS AC12 VSS AP13 VSS AG24 VSS AC8 VSS AP8 VSS AG22 VSS AC1 VSS AN38 VSS AG20 VSS AB45 VSS AN34 VSS AG13 VSS AB36 VSS AN23 VSS AG10 VSS AB33 vss vss aAG8 yss 27 VSS AN6 VSS AG7 VSS AB25 VSS AN4 VSS AG6 VSS AB23 VSS AM45 VSS AG4 VSS AB21 VSS AM24 VSS AF43 VSS AB19 VSS AM21 VSS AF27 VSS AA39 vss AM16 VSS AF25 VSS AA36 VSS AM1 VSS AF23 VSS AA34 VSS AL39 VSS AF21 VSS AA32 300 Datasheet Ballout and Package I nformation Datasheet intel Table 28 MCH Table 28 MCH Table 28 MCH Ballout Sorted By Name v Ballout Sorted By Name Ballout Sorted Name Signal Name Ball Signal Name Ball Signal Name Ball VSS AA26 VSS R8 VSS K40 VSS AA24 VSS R4 VSS K39 VSS AA22 VSS P45 VSS K33 VSS
61. 0 Do not generate GPE PME message when PME is received 2 RW Ob 1 Generate a GPE PME message when PME is received Assert_PMEGPE and Deassert_PMEGPE messages on DMI This enables the MCH to support PMEs on the PCI Express port under legacy OSs 1 RO Ob Reserved General Message GPE Enable GENGPE 0 Do not forward received GPE assert de assert messages 0 RW 0b 1 Forward received GPE assert de assert messages These general GPE message can be received via the PCI Express port from an external Intel device and will be subsequently forwarded to the ICH via Assert_GPE and Deassert GPE messages on DMI 184 Datasheet m e Host Primary PCI Express Bridge Registers D1 FO n tel 6 47 VCECH Virtual Channel Enhanced Capability Header B D F Type 0 1 0 MMR Address Offset 100 103h Default Value 14010002 Access RO Size 32 bits This register indicates PCI Express device Virtual Channel capabilities Extended capability structures for PCI Express devices are located in PCI Express extended configuration space and have different field definitions than standard PCI capability structures Bit Access Detault Description Value Pointer to Next Capability PNC The Link Declaration Capability is the next 31 20 RO 140h ec T in the PCI Express extended capabilities list 19 16 RO 1h PCI Express Virtual Channel Capability Version PCI EVCCV Hardwired to
62. 00h RO 19h SBUSN1 Secondary Bus Number 00h RW 1Ah SUBUSN1 Subordinate Bus Number 00h RW 1Ch 1 I O Base Address FOh RO RW 1Dh IOLIMITI Limit Address 00h RW RO 1E 1Fh SSTS1 Secondary Status 0000h RO RWC 147 intel Table 12 148 Host Primary PCI Express Bridge Registers D1 FO Express Bridge Register Address Map D1 FO Sheet 2 of 3 Address Register Default Offset Symbol Register Name Valle Access 20 21h MBASE1 Memory Base Address FFFOh RW RO 22 23h MLIMIT1 Memory Limit Address 0000h RW RO 24 25h 5 1 Prefetchable Memory Base Address FFF1h RW RO 26 27h PMLIMIT1 Prefetchable Memory Limit Address 0001h RO RW 28 2Bh PMBASEU1 Prefetchable Memory Base Address Upper 00000000h RW 2C 2Fh PMLIMITU1 Prefetchable Memory Limit Address Upper 00000000h RW 34h CAPPTR1 Capabilities Pointer 88h RO 3Ch INTRLINE1 Interrupt Line 00h RW 3Dh INTRPIN1 Interrupt Pin Olh RO 3E BCTRL1 Bridge Control 0000h RO RW 80 83h PM_CAPID1 Power Management Capabilities C8039001h RO 84 87h PM_CS1 Power Management Control Status 00000008h ae 88 8Bh SS CAPID Subsystem ID and Vendor ID Capabilities 0000800Dh RO 8C 8Fh SS Subsystem ID and Subsystem Vendor ID 00008086h RWO 90 91h MSI CAPID Message Signaled Interrupts Capability ID 005 RO 92 93h MC Message Contro
63. 1 The MCH is enabled to generate SERR messages which will be sent to the ICH for specific Device 1 error conditions generated detected on the primary side of the virtual PCI to PCI bridge not those received by the secondary side The status of SERRs generated is reported in the PCISTS1 register 7 RO Ob Reserved Parity Error Response Enable PERRE Controls whether or not the Master 6 RW Ob Data Parity Error bit in the PCI Status register can bet set 0 Master Data Parity Error bit in PCI Status register can NOT be set 1 Master Data Parity Error bit in PCI Status register CAN be set 5 3 RO Ob Reserved Bus Master Enable BME Controls the ability of the PCI Express port to forward Memory IO Read Write Requests in the upstream direction 0 This device is prevented from making memory or IO requests to its primary bus Note that according to PCI Specification as MSI interrupt messages are in band memory writes disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them from its secondary bus to its primary bus Upstream memory writes reads IO writes reads peer writes reads and MSIs will all be treated as illegal cycles 2 RW Ob Writes are forwarded to memory address C0000h with byte enables de asserted Reads will be forwarded to memory address 0000 and will return Unsupported Request status or Master abort in its completion packet 1 This device is allowed to issu
64. 1 20 MC Message Signaled I nterrupt Message Control B D F Type 0 3 0 PCI Address Offset 8E 8Fh Default Value 0080 Access RO RW Size 16 bits Bit Access Default Description Value 15 8 RO 00h Reserved J RO 1b 64 Bit Address Capable C64 Specifies whether capable of generating 64 bit messages 6 4 RO 000b Multiple Message Enable MME Not implemented hardwired to 0 3 1 RO 000b Multiple Message Capable MMC Not implemented hardwired to 0 MSI Enable MSIE If set MSI is enabled and traditional interrupt pins are not 0 RW Ob used to generate interrupts Datasheet 201 ntel Intel Manageability Engine Subsystem PCI D3 FO F3 7 1 21 MA Message Signaled I nterrupt Message Address B D F Type 0 Address Offset 90 93h Default Value 000000008 Access RW RO Size 32 bits E Default ice Bit Access Value Description 31 2 RW 0000000 Address ADDR Lower 32 bits of the system specified message address Oh always DW aligned 1 0 RO 00b Reserved 7 1 22 MUA Message Signaled I nterrupt Upper Address Optional B D F Type 0 3 0 PCI Address Offset 94 97h Default Value 00000000h Access RW Size 32 bits Default Bit Access Value Description 31 0 RW 0000000 Upper Address UADDR Upper 32 bits of the system specified message d Oh address This register is optional and only implemented if MC C64 1 7 1 23 MD M
65. 15 11 RO 11001b HECI can assert PME from any D state except D1 or D2 which are not supported by HECI 10 RO Ob D2 Support D2S The D2 state is not supported for the HECI host controller 9 RO Ob D1 Support D1S The D1 state is not supported for the HECI host controller 8 6 RO 000b Aux Current AUXC Reports the maximum Suspend well current required when the D3COLD state Device Specific Initialization DSI Indicates whether device specific 5 RO Ob initialization is required RO Ob Reserved RO Ob PME Clock PMEC Indicates that PCI clock is not required to generate PME 2 0 RO 011b Version VS Indicates support for Revision 1 2 of the PCI Power Management Specification 7 1 18 PMCS PCI Power Management Control And Status B D F Type 0 3 0 PCI Address Offset 54 55h Default Value 0008h Access RWC RO RW Size 16 bits Bit Access Default Description Value PME Status PMES The PME Status bit in HECI space can be set to 1 by ME FW performing a write into AUX register to set PMES C This bit is cleared by host processor writing a 1 to it m i 09 not clear this bit Host processor writes with value 0 have no effect on this bit This bit is reset to 0 by MRST 14 9 RO 000000b Reserved PME Enable PMEE This bit is read write under control of host SW It does not directly have an effect on PME events However this bit is shadowed into AUX space so ME FW can monitor it The ME FW is responsi
66. 258 25Ah COCYCTRKRD Channel 0 CYCTRK READ 000000h RO RW 25B 25Ch COCYCTRKREFR Channel 0 CYCTRK REFR 0000h RO RW 260 263h COCKECTRL Channel 0 CKE Control P AWL 269 26Eh COREFRCTRL Channel 0 DRAM Refresh 021830000C RW RO Control 30h 0000000000 280 287h COECCERRLOG Channel 0 ECC Error Log 000000h RO P RO 29C 29Fh COODTCTRL Channel 0 ODT Control 00000000h RO RW Channel 1 DRAM Rank 600 601h C1DRBO Boundary Address 0 0000h RW L RO Channel 1 DRAM Rank 602 603h C1DRB1 Boundary Address 1 0000h RO RW L Channel 1 DRAM Rank 604 605h C1DRB2 Boundary Address 2 0000h RW L RO Channel 1 DRAM Rank 606 607h C1DRB3 Boundary Address 3 0000h RW L RO 608 609h CIDRAO1 1 DRAM Rank 0 1 0000h RW L Attributes 60A 60Bh C1DRA23 nanne T DRAM RANKA d 0000h RW L Attributes 650 651h C1CYCTRKPCHG Channel 1 CYCTRK PCHG 0000h RW RO 652 655h C1CYCTRKACT Channel 1 CYCTRK ACT 00000000h RO RW 656 657h C1CYCTRKWR Channel 1 CYCTRK WR 0000h RW 98 Datasheet DRAM Controller Registers DO FO Table 9 Datasheet MCHBAR Register Address Map intel Address Default Offset Register Symbol Register Name Value Access 658 65 C1CYCTRKRD Channel 1 CYCTRK READ 000000h RW RO 660 663h CICKECTRL Channel 1 CKE Control 00000800h 52 669 66Eh CIREFRCTRL Channel 1 DRAM Refresh 021830000C RW RO Control 30h 0000000000 680 687h CIECCER
67. 26 PEG2 1 27 AALL PEG2 RXN_1 88 28 10 PEG2 1 29 1 PEG2 0 326 Datasheet
68. 3 1 375 V Controller Link I nterface VCC CL 1 25 V Supply Voltage with respect to VSS 0 3 1 375 V CMOS Interface 3 3 V CMOS Supply Voltage with respect to VCC3_3 vA 0 3 3 63 V NOTE 1 Possible damage to the MCH may occur if the MCH temperature exceeds 150 C Intel does not ensure functionality for parts that have exceeded temperatures above 150 C due to specification violation 280 Datasheet Electrical Characteristics intel 11 2 Current Consumption Table 24 shows the current consumption for the MCH in the Advanced Configuration and Power Interface ACPI SO state max values are determined on a per interface basis at the highest frequencies for each interface Sustained current values or Max current values cannot occur simultaneously on all interfaces Sustained Values are measured sustained RMS maximum current consumption and includes leakage estimates The measurements are made with fast silicon at 96 C Tcase temperature at the Max voltage listed in Table 26 The Max values are maximum theoretical pre silicon calculated values In some cases the Sustained measured values have exceeded the Max theoretical values Table 24 Current Consumption in SO Symbol Parameter Signal Names Sustained Max Unit Notes lues on V Core Supply Current Discrete vcc 6 06 7 27 A 1 2 DDR2 System Memory Interface lvcc_
69. 3 RO Ob Reserved Bus Master Enable BME The MCH is always enabled as a master on the 2 RO 1b backbone This bit is hardwired to a 1 Writes to this bit position have no effect Memory Access Enable MAE The MCH always allows access to main 1 RO 1b memory This bit is not implemented and is hardwired to 1 Writes to this bit position have no effect 0 RO Ob Access Enable I This bit is not implemented in the and is hardwired to a 0 Writes to this bit position have no effect 68 Datasheet DRAM Controller Registers DO FO n tel 5 1 4 PCISTS PCI Status B D F Type 0 0 0 PCI Address Offset 6 7h Default Value 0090 Access RO RWC Size 16 bits This status register reports the occurrence of error events on Device 0 s PCI interface Since the Device 0 does not physically reside on PCI A many of the bits are not implemented Bit Access Derault Description Value 15 RWC Ob Detected Parity Error DPE This bit is set when this Device receives a Poisoned TLP Signaled System Error SSE This bit is set to 1 when the MCH Device 0 generates an SERR message over DMI for any enabled Device 0 error condition 14 RWC Ob Device 0 error conditions are enabled in the PCICMD ERRCMD and DMIUEMSK registers Device 0 error flags are read reset from the PCISTS ERRSTS or DMIUEST registers Software clears this bit by writing a 1 to it Received Master
70. 4 AE26 VSS AD18 VCC AC8 VSS AE25 VCC AD17 VCC AC7 PEG2 RXN 5 4 AE24 VSS AD15 VCCR_EXP AC6 PEG2 5 7 AE23 VCC AD14 EXP2_CLKINN AC4 PEG2 TXN 1 7 AE22 VSS AD13 VSS AC3 VCCR EXP AE21 VCC AD12 PEG2 RXN 60 AC1 VSS AE20 VSS AD11 VCC_EXP AB45 VSS AE19 VCC AD10 VCC_EXP AB43 DDR_A_DQ_57 AE18 VCC AD8 VCC_EXP AB42 DDR_A_DQ_56 AE17 VCC AD7 VCC_EXP AB40 DDR_A_DM_7 AE15 VCCR_EXP AD6 VSS AB39 DDR A DQ 61 307 intel 308 Table 29 MCH Ballout Sorted By Ball Table 29 MCH Ballout Sorted By Ball Ballout and Package Information Table 29 MCH Ballout Sorted By Ball Ball Signal Name Ball Signal Name Ball Signal Name AB38 DDR B DQ 59 AA28 VCC W41 FSB RSB 1 AB36 VSS AA27 VCC W40 FSB_TRDYB AB35 FSB_AB_34 AA26 VSS 39 VSS AB34 FSB AB 29 AA25 VCC W38 FSB AB 22 AB33 VSS AA24 VSS W36 FSB AB 30 AB32 DDR B DQ 58 AA23 VCC W35 VSS AB31 VCC CL AA22 VSS W34 FSB AB 25 AB29 VCC CL AA21 VCC W33 FSB_AB_27 AB28 VCC AA20 VSS W32 RSVD AB27 VSS AA19 VCC W31 VSS W31 AB26 VCC AA18 VCC W29 VCC CL AB25 VSS AA17 VCC W28 VCC AB24 VCC AA15 VCCR EXP W27 VCC AB23 VSS AA14 VCCR EXP W26 VSS AB22 VCC AA13 PEG2 RXN 0 W25 VCC AB21 VSS AA12 VSS W24 VSS AB20 VCC AA11 PEG2_RXN_1 7 W23 VCC AB19 VSS AA10 PEG2_RXP_1 W W22 VSS AB18 VCC AA8 VSS W21 VCC AB17 VCC
71. ABP When set to 1b this bit indicates that an Attention Button for this slot is electrically controlled by the chassis 8 42 SLOTCTL Slot Control B D F Type Address Offset B8 B9h Default Value Access Size 0 6 0 PCI 0000h RO RW 16 bits PCI Express Slot related registers Bit Access Default Value Description 15 13 RO 000b Reserved 12 RO Ob Data Link Layer State Changed Enable DLLSCE If the Data Link Layer Link Active capability is implemented when set to 1b this field enables software notification when Data Link Layer Link Active field is changed If the Data Link Layer Link Active capability is not implemented this bit is permitted to be read only with a value of Ob 11 RO Ob Electromechanical I nterlock Control EI C If an Electromechanical Interlock is implemented a write of 1b to this field causes the state of the interlock to toggle A write of Ob to this field has no effect A read to this register always returns a O 10 246 RO Ob Power Controller Control PCC If a Power Controller is implemented this field when written sets the power state of the slot per the defined encodings Reads of this field must reflect the value from the latest write unless software issues a write without waiting for the previous command to complete in which case the read value is undefined Depending on the form factor the power is
72. AV27 DDR B DQS 8 AH43 DDR B CKB 5 AY34 DDR B DQ 28 AN24 DDR B DQSB 0 AT10 DDR CKE 0 BD17 DDR B DQ 29 AP24 DDR B DQSB 1 AR12 DDR B CKE 1 BD19 DDR B DQ 30 AT25 DDR B DQSB 2 AP16 DDR B CKE 2 BB17 DDR B DQ 31 AP27 DDR B DQSB 3 AR24 DDR B CKE 3 BA17 DDR B DQ 32 AY39 DDR B DQSB 4 AV38 Datasheet Ballout and Package I nformation Datasheet intel Table 28 MCH Table 28 MCH Table 28 MCH Ballout Sorted By Name v Ballout Sorted By Name Ballout Sorted Name Signal Name Ball Signal Name Ball Signal Name Ball DDR_B_DQSB_5 AP40 DMI_RXP_3 V7 FSB AB 30 W36 DDR B DQSB 6 AG38 TXN 0 R6 FSB AB 31 AA33 DDR B DQSB 7 AD33 DMI TXN 1 P3 FSB AB 32 AA35 DDR B DQSB 8 AH42 DMI_TXN_2 T1 FSB AB 33 40 DDR_B_MA_0 AY22 DMI_TXN_3 V11 FSB AB 34 AB35 DDR B MA 1 BC22 DMI TXP 0 R7 FSB AB 35 AA38 DDR B MA 2 BB22 DMI TXP 1 N2 FSB ACCVREF D27 DDR B MA 3 BA21 DMI TXP 2 R2 FSB ADSB U44 DDR_B_MA_4 BD21 DMI_TXP_3 V10 FSB ADSTBB 0 M40 DDR B MA 5 BB21 EXP CLKINN D18 FSB ADSTBB 1 V34 DDR_B_MA_6 BB20 EXP_CLKINP D19 FSB_BNRB U42 DDR_B_MA_7 AY19 EXP_COMPI R10 FSB_BPRIB H38 DDR_B_MA_8 BE20 EXP_COMPO T10 FSB_BREQOB w44 DDR B MA 9 BB19 EXP SLR K19 FSB CPURSTB D35 DDR B MA 10 AW24 EXP2 CLKINN AD14 FSB DB 0 P42 DDR B MA 11 BA19 EXP2 CLKINP AE14 FSB DB 1 N41 DDR B MA 12 AY18 EXP2 4 AN10 FSB DB 2 N44 DDR B MA 13 BA33 EXP2 COMPO 7 A
73. Access Value Description 15 2 RO 0000h Reserved VCO Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling 1 RO lb This bit indicates the status of the process of Flow Control initialization It is set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL Down state It is cleared when the link successfully exits the FC INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Ob Reserved 8 54 RCLDECH Root Complex Link Declaration Enhanced B D F Type 0 6 0 MMR Address Offset 140 143h Default Value 00010005 Access RO Size 32 bits This capability declares links from this element PCI Express to other elements of the root complex component to which it belongs See PCI Express specification for link topology declaration requirements Bit Access Bera Description Value Pointer to Next Capability PNC This is the last capability in the PCI Express 31 20 RO pou extended capabilities list 19 16 RO 1h Link Declaration Capability Version LDCV Hardwired to 1 to indicate i compliances with the 1 1 version of the PCI Express specification 15 0 RO 0005h Extended Capability I D ECI D Value of 0005h identifies this linked list item capability structure
74. Applicable or Implemented Hardwired to 0 6 RO Ob Reserved 5 RO Ob 66 60MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 4 RO 1b Capabilities List CAPL Indicates that a capabilities list is present Hardwired to 1 INTA Status INTAS Indicates that an interrupt message is pending 3 RO Ob internally to the device Only PME sources feed into this status bit not PCI INTA INTD assert and de assert messages The INTA Assertion Disable bit PCI CMD1 10 has no effect on this bit 2 0 RO 000b Reserved 152 Datasheet m e Host Primary PCI Express Bridge Registers D1 FO n tel 6 5 RI D1 Revision dentification B D F Type 0 1 0 PCI Address Offset 8h Default Value see table below Access RO Size 8 bits This register contains the revision number of the MCH device 1 These bits are read only and writes to this register have no effect Bit Access Derault Description Value Revision Identification Number RI D1 This is an 8 bit value that 7 0 RO see indicates the revision identification number for the MCH Device 0 Refer to the description Intel 3200 and 3210 Chipset Specification Update for the value of this register 6 6 CC1 Class Code B D F Type 0 1 0 PCI Address Offset 9 Bh Default Value 0604008 Access RO Size 24 bits This register identifies the basic function of the device a more specific sub class and a register specific programm
75. Bridge Control B D F Type 0 1 0 PCI Address Offset 3E 3Fh Default Value 0000h Access RO RW Size 16 bits This register provides extensions to the PCICMD1 register that are specific to PCI PCI bridges The BCTRL provides additional control for the secondary interface as well as some bits that affect the overall behavior of the virtual Host PCI Express bridge embedded within MCH Bit Access Beran Description Value 15 12 RO Oh Reserved 11 RO Ob Discard Timer SERR Enable DTSERRE Not Applicable or Implemented Hardwired to 0 Discard Timer Status DTSTS Not Applicable or Implemented Hardwired to 10 RO Ob 0 164 Datasheet m Host Primary PCI Express Bridge Registers D1 FO tel Bit Access Default Value Description RO Ob Secondary Discard Timer SDT Not Applicable or Implemented Hardwired to 0 RO Ob Primary Discard Timer PDT Not Applicable or Implemented Hardwired to 0 RO Ob Fast Back to Back Enable FB2BEN Not Applicable or Implemented Hardwired to 0 RW Ob Secondary Bus Reset SRESET Setting this bit triggers a hot reset on the corresponding PCI Express Port This will force the LTSSM to transition to the Hot Reset state via Recovery from LO LOs or L1 states RO Ob Master Abort Mode MAMODE Does not apply to PCI Express Hardwired to 0 RW Ob VGA 16 bit Decode VGA16D Enables the PCI to PCI bridge to pro
76. Chipset Specification Update for the value 7 1 5 CC Class B D F Type Address Offset Default Value Access Size Code 0 3 0 PCI 9 Bh 0C8001h RO 24 bits Bit Default A 5 eces Value 23 16 RO Och Base Class Code BCC Indicates the base class code of the HECI host controller device 15 8 RO 80h Sub Class Code SCC Indicates the sub class code of the HECI host controller device 7 0 RO Olh Programming Interface PI Indicates the programming interface of the HECI host controller device Datasheet 195 m n tel Intel Manageability Engine Subsystem PCI D3 FO F3 7 1 6 CLS Cache Line Size B D F Type 0 3 0 PCI Address Offset Ch Default Value 00h Access RO Size 8 bits Default Bit Access Value Description 7 0 RO 00h Cache Line Size CLS Not implemented hardwired to O MLT Master Latency Timer B D F Type 0 3 0 PCI Address Offset Dh Default Value 00h Access RO Size 8 bits 5 Default Bit Access Value Description 7 0 RO 00h Master Latency Timer MLT Not implemented hardwired to 0 7 1 8 HTYPE Header Type B D F Type 0 Address Offset Default Value 80h Access RO Size 8 bits 5 Default Bit Access Value Description Multi Function Device MFD Indicates the HECI host controller is part of a D RO
77. Config Header Oh Located By PCI Express Base Address Maman As with PCI devices each device is selected based on decoded address information that is provided as a part of the address portion of Configuration Request packets A PCI Express device will decode all address information fields bus device function and extended address numbers to provide access to the correct register To access this space steps 1 2 3 are done only once by BIOS 1 Use the PCI compatible configuration mechanism to enable the PCI Express enhanced configuration mechanism by writing 1 to bit 0 of the PCIEXBAR register 2 Use the PCI compatible configuration mechanism to write an appropriate PCI Express base address into the PCIEXBAR register 3 Calculate the host address of the register you wish to set using PCI Express base bus number 1 MB device number 32KB function number 4 KB 1 B offset within the function host address 4 Use a memory write or memory read cycle to the calculated host address to write or read that register 4 4 Routing Configuration Accesses 60 The MCH supports two PCI related interfaces DMI and PCI Express The MCH is responsible for routing PCI and PCI Express configuration cycles to the appropriate device that is an integrated part of the MCH or to one of these two interfaces Configuration cycles to the ICH internal devices and Primary PCI including downstream devices are routed to the ICH via DMI
78. DDR A DQSB 2 AY15 DDR A CKE 2 BB25 DDR A DQ 31 AW22 DDR A DQSB 3 AV21 DDR A CKE 3 BC24 DDR A DQ 32 AV42 DDR_A_DQSB_4_ AT42 DDR A CSB 0 40 DDR A DQ 33 AU43 DDR A DQSB 5 AM42 DDR A CSB 1 BD42 DDR A DQ 34 AR44 DDR A DQSB 6 AD42 DDR A CSB 2 BB39 DDR A DQ 35 AR42 DDR_A_DQSB_7 AA44 DDR_A_CSB_3 AY43 DDR_A_DQ_36 AW42 DDR DQSB 8 AL36 DDR A DM 0 BB5 DDR A DQ 37 AU41 DDR_A_MA_0 BC36 DDR_A_DM_1 BC10 DDR_A_DQ_38 AR41 DDR_A_MA_1 BB31 DDR_A_DM_2 14 DDR_A_DQ_39 AR40 DDR A MA 2 BB30 DDR A DM 3 AP21 DDR A DQ 40 AN41 DDR_A_MA_3 BB29 293 intel 294 Table 28 Ballout Sorted By Name MCH Table 28 Ballout Sorted By Name MCH Table 28 Ballout Sorted By Name MCH Ballout and Package Information Signal Name Ball Signal Name Ball Signal Name Ball DDR A MA 4 BA29 DDR B CSB 0 BA31 DDR B DQ 33 AW38 DDR A MA 5 BB28 DDR B CSB 1 BB35 DDR B DQ 34 AT38 DDR A MA 6 BD29 DDR B CSB 2 BC32 DDR B DQ 35 AT40 DDR_A_MA_7 AY27 DDR B CSB 3 BA35 DDR B DQ 36 AY38 DDR A MA 8 BC28 DDR B DM O0 AY8 DDR B DQ 37 AW36 DDR A MA 9 BA27 DDR B DM 1 AT13 DDR B DQ 38 AV39 DDR A MA 10 BD37 DDR B DM 2 AW16 DDR B DQ 39 AV40 DDR_A_MA_11 BD27 DDR_B_DM_3 AY25 DDR B DQ 40 AR36 DDR A MA 12 BB27 DDR B DM 4 AY40 DDR B DQ 41 AP36 DDR A MA 13 BA42 DDR B DM 5 AN36 DDR B DQ 42 AP35 DDR
79. DDR B ODT 1 71 BC4 DDR A DQ 0 10 BD33 DDR B ODT O 72 BB4 DDR A DQ 5 11 BB35 DDR_B_CSB_1 73 BD3 DDR_A_DQ_4 12 BA31 DDR_B_CSB_0 13 AV30 DDR B CKB 0 Table 39 Chain 7 nid 2 15 AW33 DDR_B_CKB 2 Pin Count Ball Chain 7 16 AR28 DDR B CK 1 F18 BSEL2 17 AP28 DDR B CKB 1 18 AV33 DDR B CK 2 1 AW44 DDR_A_ODT_3 19 BB21 DDR B MA 5 2 AY43 DDR_A_CSB 3 20 BB22 DDR 2 3 BA41 DDR A ODT 2 21 BD21 DDR B 4 4 BB39 DDR A CSB 2 22 BC22 DDR MA 1 5 AV31 DDR A CK 3 23 AW24 DDR B MA 10 6 AT31 DDR A CKB 3 24 BB20 DDR B MA 6 7 AT36 DDR A CKB 5 25 BB19 DDR B 9 8 AT35 DDR A CK 5 26 BE20 DDR B MA 8 9 AN27 DDR A CK 4 27 BA21 DDR B MA 3 10 AM27 DDR A CKB 4 28 AY19 DDR B MA 7 11 BC24 DDR A CKE 3 29 BD17 DDR E 0 12 25 DDR A 2 30 AY22 DOR E WS 31 BD19 DDR B CKE 1 32 AR24 DDR B DQSB 3 33 AY25 DDR B DM 3 34 AP16 DDR B DQSB 2 322 Datasheet Testability tel Table 40 XOR Chain 8 Pin Ball 4 Chain 8 Table 42 XOR Chain 10 Count Pin T Chai 35 AW16 DDR B DM 2 Count Ball ain 10 36 AR12 DDR B DQSB 1 EIS 37 AT13 DDR B DM 1 38 AT10 DDR B DQSB 0 PIT DDR B 05 7 39 AY8 DDR B DM 2 PUT DDR B DQ 62 3 AB32 DDR B DQ 58 4 AB38 DDR B DQ 59 Table 41 XOR Chain 9 B DO 5 AE34 DDR B DQ 61
80. DDR_A_CKE_2 BE32 VCC DDR BC43 VSS BB24 DDR_B_BS_0 BE30 VSS BC42 DDR_RCOMPYPD BB23 RSVD BE28 VCC_DDR BC40 RSVD BB22 DDR B MA 2 BE26 VSS BC38 VCC DDR BB21 DDR B MA 5 BE24 VCC DDR BC37 DDR A BS 0 BB20 DDR B MA 6 BE23 VSS BC36 DDR_A MA 0 BB19 DDR B MA 9 BE22 VCC_DDR BC34 VCC_DDR BB18 DDR_B_BS_2 BE20 DDR_B_MA 8 BC32 DDR_B_CSB_2 BB17 DDR_B_CKE_2 BE18 VSS BC30 VCC_DDR BB16 DDR_A_DQ_18 BE16 DDR_A_DQ_19 BC28 DDR_A_MA_8 BB15 DDR A DQ 23 BE14 VSS BC26 VCC_DDR BB14 DDR A DQ 17 BE12 DDR A DQ 11 BC24 DDR A CKE 3 BB13 DDR A DQ 21 BE10 VSS BC23 VCC DDR BB12 DDR A DQ 10 BE8 DDR A DQ 3 BC22 DDR B MA 1 11 DDR_A_DQ_15 BE6 VSS BC20 VCC DDR BB10 DDR A DQ 9 BE4 4 75 BC18 DDR_B_MA_14 BB8 DDR A DQ 2 BE3 VSS 16 55 7 DDR_A_DQ_7 BE2 NC 14 DDR_A_DM_2 BB5 DDR A DM 0 1 5 1 12 VSS BB4 DDR_A_DQ_5 BD45 NC BC10 DDR_A_DM_1 BB3 VSS_BB3 BD44 VCC_CKDDR 9 DDR_A_DQ_13 BB2 VSS BD43 VCC_CKDDR BC8 VSS BA42 DDR_A_MA_13 BD42 DDR A CSB 1 BC6 DDR A DQSB 0 BA41 DDR_A_ODT_2 BD39 DDR_A_WEB BC4 DDR A DQ 0 40 DDR A CSB 0 BD37 DDR A MA 10 BC3 VSS BA37 RSVD BD35 RSVD BC2 RSVD BA35 DDR B CSB 3 BD33 DDR B ODT O BC1 VSS BA33 DDR B MA 13 BD31 DDR B RASB BB44 RSVD BA31 DDR_B_CSB_0 BD29 DDR_A_MA_6 BB43 DDR_A_ODT_0 BA29 DDR_A_MA_4 BD27 DDR A MA 11 BB42 DDR_RCOMPYPU BA27 DDR_A_MA_9 BD25 DDR_A_CKE_0 BB41 DDR_A_CASB BA25 DDR_A_MA_14 BD21 DDR B MA 4 BB39 DDR A CSB 2 BA21 DDR B MA 3 BD19 DDR B CKE 1 BB38 DDR A RASB BA19 DDR B MA 11 BD17 DDR B CKE 0 BB36 DDR A BS 1 B
81. DRAM memory above 4 GB that is usable by the operating system Configuration software must set this value to TOM minus all EP stolen memory if reclaim is disabled If reclaim is enabled this value must be set to bits 19 0 are assumed to be 000 0000h for the purposes of address comparison The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than 4 GB All the Bits in this register are locked in Intel TXT mode 88 Datasheet m e DRAM Controller Registers DO FO n tel 5 1 31 BSM Base of Stolen Memory B D F Type 0 0 0 PCI Address Offset A4 A7h Default Value 00000000h Access RW L RO Size 32 bits This register contains the base address of stolen DRAM memory BIOS determines the base of stolen memory by subtracting the stolen memory size PCI Device 0 offset 52 bits 6 4 from TOLUD PCI Device 0 offset BO bits 15 04 Note This register is locked and becomes Read Only when the D LCK bit in the SMRAM register is set Default Bit Access Value Description Base of Stolen Memory BSM This register contains bits 31 to 20 of the base address of stolen DRAM memory BIOS determines the base of stolen memory by subtracting the stolen memory size PCI Device 0 offset 52h bits 6 4 from 31 20 RW L 000h TOLUD PCI Device 0 offset BOh bits 15 4 NOTE This register is locked and
82. Datasheet Subordinate Bus Number registers of its PCI to PCI bridges to determine if the configuration access is meant for Primary PCI or some other downstream PCI bus or PCI Express link Configuration accesses that are forwarded to the ICH9 but remain unclaimed by any device or bridge will result in a master abort 1 Mapped Registers The contains two registers that reside in the processor 1 0 address space the Configuration Address CONFIG ADDRESS Register and the Configuration Data CONFIG DATA Register The Configuration Address Register enables disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window CONFIG_ADDRESS Configuration Address Register Address OCF8h Accessed as a DW Default Value 00000000h Access R W Size 32 bits CONFIG_ADDRESS is a 32 bit register that can be accessed only as a DW A Byte or Word reference will pass through the Configuration Address Register and DMI onto the Primary PCI bus as an I O cycle The CONFIG_ADDRESS register contains the Bus Number Device Number Function Number and Register Number for which a subsequent configuration access is intended z Access amp oe Bit Default Description Configuration Enable CFGE R W 31 0 Disable Ob 0 Enable 30 24 Reserved Bus Number If the Bus Number is programmed to the target of the Configuration Cycle is a PCI Bus 0 a
83. Datasheet intel Intel Manageability Engine Subsystem PCI D3 F0 F3 This chapter provides the registers for Device 3 D3 Functions 0 FO and 3 F3 Function ME Subsystem D3 FO Device 3 contains registers for the Intel Manageability Engine The table below lists the PCI configuration registers in order of ascending offset address The following sections describe Device 3 configuration registers only HECI Function in ME Subsystem D3 FO Register Address Map Address Default Offset Symbol Register Name Value Access 0 3h ID Identifiers 29F48086h RO 4 5h CMD Command 0000h RO RW 6 7h STS Device Status 0010h RO 8h RID Revision ID see register RO description 9 Bh Class Code 0C8001h RO Ch CLS Cache Line Size 00h RO Dh MLT Master Latency Timer 00h RO Eh HTYPE Header Type 80h RO 0000000000 10 17h MBAR MMIO Base Address 000004h RO RW 2C 2Fh SS Sub System Identifiers 00000000h RWO 34h CAP Capabilities Pointer 50h RO 3C 3Dh INTR Interrupt Information 0100h RO RW 3Eh MGNT Minimum Grant 00h RO 3Fh MLAT Maximum Latency 00h RO 40 43h HFS Host Firmware Status 00000000h RO 50 51h PID PCI Power Management Capability ID 8 01 RO 52 53h PC PCI Power Management Capabilities C803h RO PCI Power Management Control And RWC RO 54 55h PMCS Status 0008h RW 8C 8Dh MID Message Signaled Interrupt Identifiers 0005h
84. Default Value 0001h Access RO RW Size 16 bits This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express prefetchable memory access routing based on the following formula PREFETCHABLE MEMORY BASE address PREFETCHABLE MEMORY LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC i e prefetchable from the processor perspective Bit Access Default Value Description 15 4 RW 000h Prefetchable Memory Address Limit PMLI MI T This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express 3 0 64 bit Address Support This field indicates that the upper 32 bits of the RO 1h prefetchable memory region limit address are contained in the Prefetchable Memory Base Limit Address register
85. EP Link Entry Description sss mme 144 5 3 7 EPEE3A EP Link Entry 3 Address ooi reete nnn ien 145 Host Primary PCI Express Bridge Registers D1 FO 147 61 VIDI Vendor Identification ei eme era ted ret eda eee me esae bina e AEE ek 149 6 2 DID1 Device 1 4 Iesse enemies 150 6 3 PGICMDI PGI Command inire E ut be 150 6 4 PGISTST PCI 5 ERN R EMPIRE M buna ead 152 6 5 RID1 Revision Identification 153 6 6 CClI Class Code oe er cx Ma IMP e RH 153 67 CRT Cache Wine SZC vinci ui erret exin E RENE 154 6 8 HbDRI Header texte RO EM Ee eae ed 154 6 9 PBUSN1 Primary Bus ens 154 6 10 SBUSN1 Secondary Bus 1 6 emen 155 6 11 SUBUSN1 Subordinate Bus 1 1 1 155 6 12 5 1 1 Base 5 gt eis ases eee ree eed a e se ele xd Fa e eb doen 156 6 13 IOLIMIT1 1 O Limit 00 ene 156 6 14 SSTS1 Secondary Status ci restet is bue ere ree ce ior lege Le p LE
86. MB solutions require changes to compatible SMRAM handlers code to properly execute above 1 MB DMI Interface and PCI Express masters are not allowed to access the SMM space SMM Space Definition SMM space is defined by its addressed SMM space and its DRAM SMM space The addressed SMM space is defined as the range of bus addresses used by the processor to access SMM space DRAM SMM space is defined as the range of physical DRAM memory locations containing the SMM code SMM space can be accessed at one of three transaction address ranges Compatible High and TSEG The Compatible and TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space is the same address range Since the High SMM space is remapped the addressed and DRAM SMM space is a different address range Note that the High DRAM space is the same as the Compatible Transaction Address space Table 5 describes three unique address ranges Compatible Transaction Address High Transaction Address TSEG Transaction Address Transaction Address Ranges Compatible High and TSEG SMM Space Enabled Transaction Address Space DRAM Space DRAM Compatible 000A 0000h to 000B FFFFh 000A 0000h to 000B FFFFh High FEDA 0000h to FEDB FFFFh 000A 0000h to 000B FFFFh TSEG TOLUD STOLEN TSEG to TOLUD STOLEN TOLUD STOLEN TSEG to TOLUD STOLEN 49 m n tel System Address Map 3 7 2 SMM Space Restrictions
87. Name AT6 DDR RCOMPVOH AP34 RSVD AN18 DDR B DQS 2 AT4 PEG2 TXP 13 4 AP33 VSS AN16 DDR B DQ 20 AT3 PEG2 TXN 14 AP31 DDR B CKB 3 15 DDR B DQ 14 1 VSS AP30 VSS AN13 RSVD AR44 DDR_A_DQ_34 AP28 DDR B CKB 1 AN12 RSVD AR42 DDR_A_DQ_35 AP27 DDR B DQ 31 AN11 RSVD AR41 DDR_A_DQ_38 AP25 VSS ANIO EXP2 9 AR40 DDR_A_DQ_39 AP24 DDR B DQ 29 AN8 2 COMPO AR39 VSS AP23 VSS AN7 VSS AR38 VSS AP22 VSS AN6 VSS AR36 DDR B DQ 40 AP21 DDR A DM 3 5 PEG2 TXN 114 AR35 VSS AP19 DDR B DQ 18 ANA VSS AR34 DDR B DQ 45 AP18 VSS AN2 PEG2 TXP 10 7 AR33 DDR A CKB 0 AP16 DDR B DQSB 2 AM45 VSS AR31 DDR_B_CK_3 AP15 DDR B DQ 15 AM43 DDR A DQS 5 AR30 VSS AP13 VSS AM42 DDR_A_DQSB_5 AR28 DDR_B_CK_1 AP12 RSVD AM32 RSVD AR27 VSS AP11 PEG2 RXN 15 AM30 VCC CL AR25 DDR B DQS 3 AP10 2 15 7 AM28 DDR A CKB 1 AR24 DDR B DQSB 3 AP8 VSS AM27 DDR A CKB 4 AR23 VSS 2 TXP 15 9 AM25 RSVD AR22 VSS AP6 PEG2 TXN 15 9 AM24 VSS AR21 VSS AP4 PEG2 TXP 11 7 AM23 VCC CL AR19 VSS AP3 VCCR EXP AM22 VCC CL AR18 DDR B DQ 23 AP1 PEG2 TXN 12 4 AM21 VSS AR16 DDR B DQ 21 AN44 DDR A DM 5 19 PWROK 15 VSS AN42 DDR A DQ 41 AM18 RSTINB AR13 DDR_B_DQS 1 AN41 DDR A DQ 40 16 VSS AR12 DDR B DQSB 1 AN40 DDR B DQ 47 AM14 RSVD AR11 DDR B DQ 6 AN39 DDR B DQ 46 AMA PEG2 TXP 9 AR10 VCCAPLL EXP2 AN38 VSS 2 TXN 10 77 AR8 VSS AN36 DDR B DM 5 AMI VSS AR7 VSS AN35 DDR A CB 1 AL44 DDR A DQ 42 AR6 VSS AN34 VSS AL
88. Offset Default Value Access Size 0 1 0 PCI AA ABh 0000h RO RWC 16 bits This register provides the reflects status corresponding to controls in the Device Control register The error reporting bits are in reference to errors detected by this device not errors messages received across the link Bit Access Default Value Description 15 6 RO 000h Reserved RO Ob Transactions Pending TP 0 All pending transactions including completions for any outstanding non posted requests on any used virtual channel have been completed 1 Indicates that the device has transaction s pending including completions for any outstanding non posted requests for all used Traffic Classes RO Ob Reserved RWC Ob Unsupported Request Detected URD When set this bit indicates that the Device received an Unsupported Request Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register Additionally the Non Fatal Error Detected bit or the Fatal Error Detected bit is set according to the setting of the Unsupported Request Error Severity bit In production systems setting the Fatal Error Detected bit is not an option as support for AER will not be reported RWC Ob Fatal Error Detected FED When set this bit indicates that fatal error s were detected Errors are logged in this register regardless of whether error re
89. PCI Express 32 bit downstream addressing APIC and MSI interrupt messaging support Will send Intel defined End Of Interrupt broadcast message when initiated by the processor Message Signaled Interrupt MSI messages SMI SCI and SERR error indication 21 intel PCI Express Interface 22 Introduction The 3210 MCH supports either two PCI Express 8 lane x8 ports or one PCI Express 16 lane x16 port Figure 1 shows two PCI Express 8 lane x8 ports support of one PCI Express 16 lane x16 port is not shown in figure The 3200 MCH supports one 8 lane x8 PCI Express port see Figure 2 The 3200 3210 MCHs do not support PCI Express graphics The PCI Express ports are intended for external device attach The PCI Express ports are compliant to the PCI Express Base Specification revision 1 1 The x8 ports operate at a frequency of 2 5 Gb s on each lane while employing 8b 10b encoding and support a maximum theoretical bandwidth of 4 0 GB s in each direction The PCI Express interface includes For the 3210 MCH either two 8 lane PCI Express ports or one 16 lane PCI Express port compatible to the PCI Express Base Specification Revision 1 1 For the 3200 MCH one 8 lane PCI Express port compatible to the PCI Express Base Specification Revision 1 1 PCI Express frequency of 1 25 GHz resulting in 2 5 Gb s each direction per lane Raw bit rate on the data pins of 2 5 Gb s resulting in a real bandwidth per pair
90. Rank 3 populated 0 Rank 3 not populated This register is locked by ME stolen Memory lock 23 RW L Ob Rank 2 Population sd1_cr_rankpop2 1 Rank 2 populated 0 Rank 2 not populated This register is locked by ME stolen Memory lock 22 RW L Ob Rank 1 Population sd1_cr_rankpop1 1 Rank 1 populated 0 Rank 1 not populated This register is locked by ME stolen Memory lock 21 RW L Ob Rank 0 Population sd1_cr_rankpop0O 1 Rank 0 populated 0 Rank 0 not populated This register is locked by ME stolen Memory lock 20 RW L Ob Pulse Width Requirement Low Phase sd1_cr_cke_pw_Ih_safe 19 17 RW 000b This field indicates pulse width requirement in low phase This field Corresponds to low the DDR Specification Enable CKE Toggle for PDN Entry Exit sd1_cr_pdn_enable This bit RW Ob indicates that the toggling of CKEs for PDN entry exit is enabled 15 14 RO 00b Reserved Minimum Powerdown Exit to Non Read Command Spacing 541 cr txp This field indicates the minimum number of clocks to wait following assertion of CKE before issuing a non read command dad RW 0010b 1010 1111 Reserved 0010 1001 2 9 clocks 0000 0001 Reserved 0000000 Self Refresh Exit Count sd1_cr_slfrfsh_ exit_cnt This configuration 9 1 RW 00b register indicates the Self refresh exit count Program to 255 Corresponds to txsnr txsrp in the DDR Specification
91. Rank Read Read Delayed COsd cr rdsr rd This field indicates 7 4 RW 0000b the minimum allowed spacing in DRAM clocks between two READ commands to the same rank Different Ranks Read To Read Delayed COsd cr rddr rd This field 3 0 RW 0000b indicates the minimum allowed spacing in DRAM clocks between two READ commands to different ranks This field corresponds to tgp pp 5 2 12 COCYCTRKREFR Channel 0 CYCTRK REFR B D F Type 0 0 0 MCHBAR Address Offset 25B 25Ch Default Value 0000h Access RO RW Size 16 bits Channel 0 CYCTRK Refresh registers Default Bit Access Value Description 15 13 RO 000b Reserved Same Rank PALL to REF Delayed COsd cr pchgall rfsh This field 12 9 RW 00006 indicates the minimum allowed spacing in DRAM clocks between the PRE ALL and REF commands to the same rank 0000000 Same Rank REF to REF Delayed COsd cr rfsh rfsh This field indicates 8 0 RW 00b the minimum allowed spacing in DRAM clocks between two REF commands to same ranks 108 Datasheet DRAM Controller Registers DO FO n tel 5 2 13 COCKECTRL Channel 0 CKE Control B D F Type 0 0 0 MCHBAR Address Offset 260 263h Default Value 00000800 Access RW RW L RO Size 32 bits This register provides CKE controls for Channel 0 Bit Access Description Value 31 28 RO 00006 Reserved Start the Self Refresh Exit Sequence sdO cr srcstart This
92. Reporting of this condition via SMI messaging is disabled For systems that do not support ECC this bit must be disabled 5 1 37 SKPD Scratchpad Data B D F Type 0 0 0 PCI Address Offset DC DFh Default Value 00000000h Access RW Size 32 bits This register holds 32 writable bits with no functionality behind them It is for the convenience of BIOS drivers Bit Access peraut Description Value 31 0 RW E Scratchpad Data SKPD 1 DWord of data storage 94 Datasheet DRAM Controller Registers DO FO n tel 5 1 38 CAPI DO Capability I dentifier B D F Type 0 0 0 PCI Address Offset EO EBh Default Value 00000001C1064000010C0009h Access RO Size 96 bits BIOS Optimal Default Oh This register provides control of bits in this register are only required for customer visible component differentiation Bit Access Derault Description Value 95 78 RO Os Reserved Dual Channel Disable DCD Disables dual channel operation 0 Dual channel operation allowed 77 RO Ob 1 Only single channel operation allowed Only channel 0 will operate channel 1 will be turned off and tristated to save power This setting hardwires the rank population field for channel 1 to zero MCHBAR offset 660h bits 20 23 2 DIMMS per Channel Disable 2DPCD Allows Dual Channel operation but only supports 1 DIMM per channel 76 RO Ob 0 2 DIMMs per channel Enabled 1 2 DIMMs per ch
93. Since the FW emulates the modem the Host communicates to the FW via this register Register has impact on hardware when the Loopback mode is on Note Reset Host system Reset D3 gt D0 transition Bit Access peraulg Description Value 7 5 RO 000b Reserved Loop Back Mode LBM When set by Host this bit indicates that the serial 4 RW Ob port is in loop Back mode This means that the data that is transmitted by the host should be received Helps in debug of the interface Output 2 OUT2 This bit has no affect on hardware in normal mode In loop 3 RW Ob back mode the value of this bit is written by hardware to Modem Status Register bit 7 Output 1 OUT1 This bit has no affect on hardware in normal mode In loop 2 RW Ob back mode the value of this bit is written by hardware to Modem Status Register bit 6 Request to Send Out RTSO This bit has no affect on hardware in normal 1 RW Ob mode In loopback mode the value of this bit is written by hardware to Modem Status Register bit 4 Data Terminal Ready Out DRTO This bit has no affect on hardware in 0 RW Ob normal mode In loopback mode the value in this bit is written by hardware to Modem Status Register Bit 5 210 Datasheet Intel Manageability Engine Subsystem PCI D3 FO F3 tel 7 2 10 KTLSR KT Line Status B D F Type 0 3 3 KT MM IO Address Offset 5h Default Value 00h Access R
94. TBP vss FSB_DB_60 FSB_DB_58 vss VIT_FSB NC vss FSB DB 18 FSB DB 55 FSB DB 56 FSESDINVB FSB DB 62 VIT FSB VIT FSB TEST3 NC VSS VSS FSB_DB_49 vss VSS VIT FSB 45 44 43 42 4i 40 39 38 37 36 35 34 33 32 31 Datasheet BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA c Ballout and Package I nformation Figure 13 BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA MCH Ballout Diagram Top View Middle Columns 30 16 intel 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vss DDR vss DDR vss DDR DDR B MA vss DDR A DDR A MA DDR A MA DDR A CKE DDR B MA DDR B DDR B CKE eo Ae 0 740 PU DDR DOREA MAS VCC_DDR CKE vcc DDR B MA VCC_DDR DDR P MA vss DDR A MA MA A MA A MA A ss A 8 ss Rsvp pon amp va va s va pon 85 DDR_A_DQ_ 2 3 5 12 2 72 0 2 5 6 9 2 22 18 DDR_A_MA_ DDR_A_MA_ DDR_A_MA_ DDR_B_MA_ DDR_B_MA_ DDR_B_CKE 4 9 14 3 11 3 DDR_B_CK_ DDR_B_CKB DDR_A_MA_ DDR B DM
95. VSS_D22 D22 VSS D34 VSS_D24 D24 VSS D29 VSS_F22 F22 VSS D23 VSS_H16 H16 VSS D17 VSS_K16 K16 vss 015 VSS M5 5 vss JDB vsswai 3 VSS D11 VIT FSB M27 VSS D7 VIT FSB L27 VSS D4 VTT_FSB K27 VSS C45 VIT FSB K25 VSS C43 VIT FSB H28 VSS C38 VIT FSB H27 VSS C34 VIT FSB H25 VSS C30 VIT FSB G28 VSS C22 VIT FSB G27 vss 00 625 VSS C9 VIT FSB F30 vss C3 F28 VSS Cl VTT_FSB F27 VSS B44 VTT_FSB F25 VSS B29 VTT_FSB E33 VSS A43 VTT_FSB E31 VSS A40 VTT_FSB E29 VSS A36 VIT FSB D33 VSS A34 VIT FSB D32 VSS A26 VIT FSB D31 VSS A22 VIT FSB D30 VSS A18 VIT FSB C32 VSS A14 VIT FSB B33 vss AO VITFSB 83 VSS A6 VIT FSB A32 VSS A3 VIT FSB A30 VSS A24 A24 XORTEST L22 VSS AW2 AW2 22 2 VSS AY3 AY3 VSS B17 B17 VSS B21 B21 302 Datasheet Ballout and Package I nformation Datasheet intel Table 29 MCH Table 29 MCH Table 29 MCH Ballout Sorted By Ball Ballout Sorted By Ball Ballout Sorted By Ball Ball Signal Name Ball Signal Name Ball Signal Name BE45 TESTO BD7 DDR A DQ 6 BB31 DDR A MA 1 BE44 VCC CKDDR BD4 DDR A DQ 1 BB30 DDR A MA 2 BE43 VCC_CKDDR BD3 DDR_A_DQ 4 BB29 DDR_A_MA_3 BE40 VCC_DDR BD2 VSS BB28 DDR_A_MA_5 BE38 VSS BD1 NC BB27 DDR_A_MA_12 BE36 VCC_DDR BC45 VCC_CKDDR BB26 DDR_A_BS 2 BE34 VSS BC44 VCC_CKDDR BB25
96. a cold reset is Power Good Reset as defined in the PCI Express Specification R WSC Read Write Self Clear bit s These bits can be read and written When the bit is 1 hardware may clear the bit to 0 based upon internal events possibly sooner than any subsequent read could retrieve a 1 R WSC L Read Write Self Clear Lockable bit s These bits can be read and written When the bit is 1 hardware may clear the bit to 0 based upon internal events possibly sooner than any subsequent read could retrieve a 1 Additionally there is a bit which may or may not be a bit marked R W L that when set prohibits this bit field from being writeable bit field becomes Read Only R WO Write Once bit s Once written bits with this attribute become Read Only These bits can only be cleared by a Reset Write Only Whose bits may be written but will always return zeros when read They are used for write side effects Any data written to these registers cannot be retrieved Datasheet m e MCH Register Description tel 4 2 Configuration Process and Registers 4 2 1 Platform Configuration Structure The DMI physically connects the MCH and the Intel ICH9 thus from a configuration standpoint the DMI is logically PCI bus 0 As a result all devices internal to the and the ICH appear to be on PCI bus O Note ICHO9 internal LAN controller does not appear on bus 0 it appear
97. again until the driver services the earlier one Default Bit Access Value Description 15 8 RO 00h Reserved 64 bit Address Capable 64AC Hardwired to 0 to indicate that the function 7 RO Ob does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64 bit memory address Multiple Message Enable MME System software programs this field to indicate the actual number of messages allocated to this device This number 6 4 BW 000b will be equal to or less than the number actually requested The encoding is the same as for the MMC field below Multiple Message Capable MMC System software reads this field to determine the number of messages being requested by this device The value of 3 1 RO 0006 0000 equates to 1 message requested 000 1 message requested All other encodings are reserved MSI Enable MSI EN Controls the ability of this device to generate MSIs 0 RW Ob 0 OMSI will not be generated 1 MSI will be generated when we receive PME messages INTA will not be generated and INTA Status PCISTS1 3 will not be set Datasheet 169 intel Host Primary PCI Express Bridge Registers D1 FO 6 31 MA Message Address B D F Type 0 1 0 PCI Address Offset 94 97h Default Value 00000000h Access RO RW Size 32 bits 4 Default uen Bit Access Value Description 0000000 Message Address MA Used by system so
98. and writeable Bit Default Access Description Value 7 6 RO 00b Reserved 5 4 RW L 00b 01 OFOOOO OFFFFF Attribute HIENABLE This field controls the steering of read and write cycles that address the BIOS area from OF0000h to OFFFFFh 00 DRAM Disabled All accesses are directed to DMI Read Only All reads are sent to DRAM writes are forwarded to DMI 10 Write Only All writes are sent to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 3 0 RO Oh Reserved 78 Datasheet DRAM Controller Registers DO FO n tel 5 1 18 PAM1 Programmable Attribute Map 1 B D F Type 0 0 0 PCI Address Offset 91h Default Value 00 Access RO RW L Size 8 bits This register controls the read write and shadowing attributes of the BIOS areas from 0CO0000h OC7FFFh Default 4 22 Bit Access Value Description 7 6 RO 00b Reserved 0C4000h OC7FFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from 0CA4000h to OC7FFFh 00 DRAM Disabled Accesses are directed to DMI 5 4 RW L 00b 01 Only All reads serviced by DRAM All writes are forwarded to 10 Write Only All writes are sent to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This r
99. at 2Ch Datasheet 161 m n tel Host Primary PCI Express Bridge Registers D1 FO 6 19 PMBASEU1 Prefetchable Memory Base Address Upper B D F Type 0 1 0 PCI Address Offset 28 2Bh Default Value 000000001 Access RW Size 32 bits The functionality associated with this register is present in the PCI Express design implementation This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express prefetchable memory access routing based on the following formula PREFETCHABLE MEMORY BASE lt address xPREFETCHABLE MEMORY LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1MB boundary Bit Access perault Description Value 0000000 Prefetchable Memory Base Address MBASEU Corresponds to A 63 32 of 31 0 RW Oh the lower limit of the prefetchable memory range that will be passed to PCI Express 162 Datasheet m e Host Primary PCI Express Bridge Registers D1 FO n tel 6 20 PMLI MI TU1 Pref
100. be avoided If an even number of bits greater than two flipped there will be an even number of 1s in the syndrome but that even number could be zero such that detection of this scenario is not ensured If the syndrome contains a nonzero number of 1s it cannot be distinguished from scenario 4 above It is possible for odd number of bits greater than one to flip between the time the data is written and the time it is read back This scenario will always be detected but the resulting syndrome could appear to be a multi bit error treated similarly to scenario 4 or it could be misinterpreted as a single bit error indistinguishable from scenario 2 The data cannot be corrected though if it appears to be a single bit error the algorithm will flip the bit that corresponds to the syndrome generated thus an additional bit may be corrupted Fortunately soft error rates are low enough that it is extremely unlikely that there would be more than one soft error in the same QWord so scenarios 5 and 6 are very rare 273 10 3 10 3 1 10 3 1 1 10 3 1 2 10 3 1 3 274 PCI Express See Section 1 2 for a list of PCI Express features and the PCI Express specification for further details This MCH is part of a PCI Express root complex This means it connects a host processor memory subsystem to a PCI Express hierarchy The control registers for this functionality are located in Device 1 and Device 6 configuration space and
101. be rejected as an Unsupported Request 14 8 RO 00h Reserved Port Arbitration Capability PAC Having only bit 0 set indicates that the 7 0 RO 01h only supported arbitration scheme for this VC is non configurable hardware fixed Datasheet 261 Direct Media I nterface DMI RCRB 9 5 DMI VCORCTLO DMI VCO Resource Control B D F Type 0 0 0 DMIBAR Address Offset 14 17h Default Value 800000FFh Access RO RW Size 32 bits This register controls the resources associated with PCI Express Virtual Channel 0 Bit Access rerun Description Value Virtual Channel 0 Enable VCOE For VCO this is hardwired to 1 and read 31 RO 1b only as VCO can never be disabled 30 27 RO Oh Reserved Virtual Channel 0 I D VCOI D Assigns a VC ID to the VC resource For VCO 26727 RO 0005 this is hardwired to 0 and read only 23 20 RO Oh Reserved Port Arbitration Select PAS This field configures the VC resource to provide a particular Port Arbitration service Valid value for this field is a number 19 17 RW 000b corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource Because only bit 0 of that field is asserted This field will always be programmed to 1 16 8 RO 000h Reserved Traffic Class Virtual Channel 0 Map TCVCOM This field indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond
102. bit 7 of this register 6 0 RW L 00h The fuses cannot be programmed Vie this register Once this register has been overwritten by software the values of the TCO fuses can be read using the Therm3 register Note for TCO operation While this is a seven bit field the 7th bit is sign extended to 9 bits for TCO operation The range of 00 to 3fh corresponds to 0 0000 0000 to 0 0011 1111 The range of 41h to 7Fh corresponds to 1 1100 001 i e negative 3Fh to 1 1111 1111 i e negative 1 respectively 136 Datasheet m e DRAM Controller Registers DO FO n tel 5 2 49 THERM1 Thermal Hardware Protection B D F Type 0 0 0 MCHBAR Address Offset CE4h Default Value 00h Access RW L RO RW L K Size 8 bits All bits in this register are reset to their defaults by PLTRST Bit Default Access Description Value 7 4 RO Ob Reserved Halt on Catastrophic HOC RW L Ob 0 Continue to toggle clocks when the catastrophic sensor trips 1 All clocks are disabled when the catastrophic sensor trips A system reset is required to bring the system out of a halt from the thermal sensor 2 1 RW L K Ob RO 00b Reserved Hardware Throttling Lock Bit HTL This bit locks bits 7 0 of this register The register bits are unlocked 1 The register bits are locked It may only be set to a 0 by a hardware reset Writing a 0 to this bit has no effect 5 2 50 Datasheet TI S Therma
103. cL DDR 09 DDR_A DQ FDDR A DQ psg vss FSB AB 35 vss FSB AB 32 vss FSB AB 31 vss vcc cL DDR DQ DDR A DQ 3 VSS 58 FSB BREQO DO nsp 1 FSB_TRDYB vss FSB AB 22 FSB AB 30 vss FSB AB 25 FSB AB 27 RSVD VSS W31 vss FSB AB 28 FSB HITMB vss FSB AB 24 FSB AB 23 vss FSB AB 26 FSB ADSTB vss RSVD CL FSB ADSB FSB BNRB FSB DRDYB FSB LOCKB vss FSB_DBSYB FsB AB 17 FSB_DEFER Ag 20 FSB AB 18 vss FSB AB 19 RSVD vss VCCAUX FSB RSB 0 FSB HITB FSB RSB 2 VSS FSB_AB_14 VSS FSB_AB_10 FSB_AB_16 VSS RSVD vss FSB_AB_21 FSB_DB_O VSS FSB_DB_2 FSB_DB_4 FSB_DB_1 FSB_AB_9 FSB_AB_11 FSB_AB_13 FSB_AB_8 VSS FSB AB 12 FSB DB 28 FSB DB 30 FSB DB 5 vss FSB_DB_3 FOR vss FSB_AB_4 FSB_AB_5 vss vss vss FSB_DB_31 FSB_DB_6 FsB_DB_7 FSB_DINVB FSB_REQB_ vss FSB_DB_19 vss FSB_DB_27 FSB_DB_29 vss vss FSB DSTBN sg 15 vss vss FSB AB 6 FSB_REQB_ rsg 21 rsg 24 vss FSB DB 33 FSB DSTBP esp FSB DB 10 FSB DB 12 vss FSB_DB_9 vss FSB_REQB_ FSB_BPRIB vss vss F5B DSTBP pg 25 FSB DB 34 FSB DB 13 FSB DB 11 FSB_REQB_ vss FSB_DB_20 FSB DB 22 FSB_DB_23 5 05 8 vss vss vss FSB_AB_3 FSB_DB_14 VSS FSB_DB_17 FSB_DB_16 VSS FSB DB 48 VSS FSB DB 26 FSB DB 32 FSB DB 15 rsB DB 50 F5B DINVB FSB DB 61 FSB DB 63 VIT FSB VIT FSB FSB DB 52 FSB DB 53 vss FSB DS IBN FSB DB 57 FSB DB 54 DB 59 FSB_CPURS vss VTT FSB VIT FSB VIT FSB vss FSBAREQB vss FSB DB 51 FOB ADO
104. case the read value is undefined If the indicator is electrically controlled by chassis the indicator is controlled directly by the downstream port through 7 6 RO 00b implementation specific mechanisms 00 Reserved 01 On 10 Blink 11 Off If the Attention Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b 5 4 RO 00b Reserved 3 RW Ob Presence Detect Changed Enable PDCE When set to 1b this bit enables software notification on a presence detect changed event MRL Sensor Changed Enable MSCE When set to 1b this bit enables software notification on a MRL sensor changed event 2 RO Ob Default value of this field is Ob If the MRL Sensor Present field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Power Fault Detected Enable PFDE When set to 1b this bit enables 1 RO Ob software notification on a power fault event Default value of this field is Ob If Power Fault detection is not supported this bit is permitted to be read only with a value of 06 0 RO Ob Button Pressed Enable ABPE When set to 1b this bit enables software notification on an attention button pressed event Datasheet 247 n tel Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 43 SLOTSTS Slot Status B D F Type 0 6 0 PCI Address Offset BA BBh Default Value 0000h Acces
105. combining Note that the MCH Device 1 memory range registers described above are used to allocate memory address space for any PCI Express devices sitting on PCI Express that require such a window The PCI CMD1 register can override the routing of memory accesses to PCI Express In other words the memory access enable bit must be set in the device 1 PCICMD1 register to enable the memory base limit and pre fetchable base limit windows For the MCH the upper PMUBASE1 PMULIMIT1 registers have been implemented for PCI Express Spec compliance The MCH locates MMIO space above 4 GB using these registers Datasheet System Address Map 3 7 Note 3 7 1 Table 5 Datasheet intel System Management Mode SMM System Management Mode uses main memory for System Management RAM SMM RAM The MCH supports Compatible SMRAM C SMRAM High Segment HSEG and Top of Memory Segment TSEG System Management RAM space provides a memory area that is available for the SMI handlers and code and data storage This memory resource is normally hidden from the system OS so that the processor has immediate access to this memory space upon entry to SMM MCH provides three SMRAM options Below 1 MB option that supports compatible SMI handlers Above 1 MB option that allows new SMI handlers to execute with write back cacheable SMRAM Optional TSEG area of 1 MB 2 MB or 8 MB in size The TSEG area lies below stolen memory The above 1
106. disabled and hidden 1 Bus 0 Device 3 Function 0 is enabled and visible If this MCH does not have ME capability CAPIDO 57 1 then Device 3 Function 0 is disabled and hidden independent of the state of this bit Datasheet m e DRAM Controller Registers DO FO n tel Bit Access Default Description Value 5 2 RO Os Reserved PCI Express Port DIEN 1 RW L 1b 0 Bus 0 Device 1 Function 0 is disabled and hidden Bus 0 Device 1 Function 0 is enabled and visible 0 RO 1b Host Bridge DOEN Bus 0 Device 0 Function 0 may not be disabled and is therefore hardwired to 1 5 1 15 PCI EXBAR PCI Express Register Range Base Address Datasheet B D F Type 0 0 0 PCI Address Offset 60 67h Default Value 00000000E0000000h Access RO RW L RW L K Size 64 bits This is the base address for the PCI Express configuration space This window of addresses contains the 4 KB of configuration space for each PCI Express device that can potentially be part of the PCI Express Hierarchy associated with the MCH There is not actual physical memory within this window of up to 256 MB that can be addressed The actual length is determined by a field in this register Each PCI Express Hierarchy requires a PCI Express BASE register The MCH supports one PCI Express hierarchy The region reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset this register is disabled a
107. element Egress Port for this link entry 11 0 RO 000h Reserved Datasheet 88 257 e n tel Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 258 Datasheet Direct Media Interface DMI RCRB intel 9 Direct Media I nterface DMI RCRB This Root Complex Register Block RCRB controls the 9 serial interconnect The base address of this space is programmed DMI BAR in DO FO configuration space Table 16 provides an address map of the DMI registers listed by address offset in ascending order Note IMPORTANT All RCRB register space needs to remain organized as shown here Table 16 Direct Media I nterface Register Address Map Address Register Default Offset Symbol Register Name Value Access DMI Virtual Channel Enhanced 0 3h DMIVCECH Capability 04010002h RO 4 7h DMIPVCCAP1 DMI Port VC Capability Register 1 00000001h RWO RO C Dh DMIPVCCTL DMI Port VC Control 0000h RO RW 10 13h DMIVCORCAP DMI VCO Resource Capability 00000001h RO 14 17h DMIVCORCTLO DMI VCO Resource Control 800000FFh RO RW 1A 1Bh DMIVCORSTS DMI VCO Resource Status 0002h RO 1C 1Fh DMIVCIRCAP DMI VC1 Resource Capability 00008001h RO 20 23h DMIVC1RCTL1 DMI VC1 Resource Control 01000000h RW RO 26 27h DMIVCIRSTS DMI VC1 Resource Status 0002h RO 84 87h DMILCAP DMI Link Capabilities 00012C41h RO RWO 88 89h DMILCTL DMI Link Control
108. element Value of 00h indicates to configuration software that this is the default egress port Component ID CI D Identifies the physical component that contains this Root Complex Element 23 16 RWO 00h BI OS Requirement Must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS Number of Link Entries NLE Indicates the number of link entries following the Element Self Description This field reports 3 two each for PCI Express and 15 8 RO 03h one for DMI Note For the 3200 MCH the field reports 2 link entries one each for PCI Express and DMI 7 4 RO Oh Reserved Element ET Indicates the type of the Root Complex Element Value of 3 0 RO 1h 1h represents a port to system memory Datasheet 141 intel DRAM Controller Registers DO FO 5 3 2 EPLE1D EP Link Entry 1 Description B D F Type 0 0 0 PXPEPBAR Address Offset 50 53h Default Value 01000000h Access RO RWO Size 32 bits This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element Default Pr Bit Access Value Description Target Port Number TPN Specifies the port number associated with the 31 24 RO 01h element targeted by this link entry DMI The target port number is with respect to the component that contains this element as spec
109. field indicates 27 RW Ob eR the request to start the self refresh exit sequence CKE Pulse Width Requirement in High Phase sdO cr cke pw hl safe 26 24 RW 000b This field indicates pulse width requirement in high phase This field corresponds to high in the DDR specification Rank 3 Population sdO cr rankpop3 23 RW L Ob 1 Rank 3 populated 0 Rank 3 not populated This register is locked by ME stolen Memory lock Rank 2 Population sd0_cr_rankpop2 22 RW L Ob 1 Rank 2 populated 0 Rank 2 not populated This register is locked by ME stolen Memory lock Rank 1 Population sdO cr rankpop1 21 RW L Ob 1 Rank 1 populated 0 Rank 1 not populated This register is locked by ME stolen Memory lock Rank 0 Population sdO cr rankpopO 1 Rank lated 20 RW L Ob BITS C papae 0 Rank 0 not populated This register is locked by ME stolen Memory lock CKE Pulse Width Requirement in Low Phase sdO cr cke pw safe 19 17 RW 000b This configuration register indicates pulse width requirement in low phase This field corresponds to low in the DDR specification 16 RW Ob Enable CKE Toggle for PDN Entry Exit sdO cr pdn enable This bit indicates that the toggling of CKEs for PDN entry exit is enabled 15 14 RO 00b Reserved Minimum Powerdown exit to Non Read command spacing sdO cr txp This field indicates the minimum number of clocks to wait following assertion of CKE before issuing a non read co
110. is 1 Both received if enabled by BCTRL1 1 and internally detected error messages do not affect this field Received Master Abort Status RMAS Not Applicable or Implemented 13 RO Ob Hardwired to 0 The concept of a master abort does not exist on primary side of this device Received Target Abort Status RTAS Not Applicable or Implemented 12 RO Ob Hardwired to 0 The concept of a target abort does not exist on primary side of this device Signaled Target Abort Status STAS Not Applicable or Implemented 11 RO Ob Hardwired to 0 The concept of a target abort does not exist on primary side of this device DEVSELB Timing DEVT This device is not the subtractively decoded device 10 9 RO 00b on bus 0 This bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode Master Data Parity Error PMDPE Because the primary side of the PCI Express s virtual peer to peer bridge is integrated with the MCH functionality there is no scenario where this bit will get set Because hardware will never set this bit it is impossible for software to have an opportunity to clear this bit or 8 RO Ob otherwise test that it is implemented The PCI specification defines it as a R WC but for our implementation an RO definition behaves the same way and will meet all Microsoft testing requirements This bit can only be set when the Parity Error Enable bit in the PCI Command register is set RO Ob Fast Back to Back FB2B Not
111. management hardware before starting Channel 0 self refresh 0 RWC S Ob exit sequence initiated by a power management exit Cleared by the BIOS by writing a 1 in a warm reset Reset asserted while PWROK is asserted exit sequence 0 Channel 0 not guaranteed to be in Self Refresh 1 Channel 0 in Self Refresh 140 Datasheet DRAM Controller Registers DO FO n tel Table 11 EPBAR Address Map Address Register x Default Offset Symbol Register Name Value Access 44 47h EPESD EP Element Self Description 00000201h RO RWO 50 53h EPLE1D EP Link Entry 1 Description 01000000h RO RWO 00000000000 58 5 EPLE1A EP Link Entry 1 Address 00000h RO RWO 60 63h EPLE2D EP Link Entry 2 Description 02000002h RO RWO 00000000000 68 6Fh EPLE2A EP Link Entry 2 Address 08000h RO 60 63h EPLE3D EP Link Entry 3 Description 03000002h RO RWO 00000000000 68 6Fh EPLE3A EP Link Entry 3 Address 08000h RO 5 3 1 EPESD EP Element Self Description B D F Type 0 0 0 PXPEPBAR Address Offset 44 47h Default Value 00000201 Access RO RWO Size 32 bits This register provides information about the root complex element containing this Link Declaration Capability Default Value Description Port Number PN This field specifies the port number associated with this 31 24 RO 00h element with respect to the component that contains this
112. mapped space On reset the Root Complex configuration space is disabled and must be enabled by writing a 1 to DMI BAREN Dev O offset 68h bit 0 All the Bits in this register are locked in Intel TXT mode Default Bit Access Value Description 63 36 RO 0000000h Reserved DMI Base Address DMIBAR This field corresponds to bits 35 12 of the base address DMI configuration space BIOS will program this register resulting in a base address for a 4 KB block of contiguous memory address 35 12 RW L 000000h space This register ensures that a naturally aligned 4KB space is allocated within the first 64 GB of addressable memory space System Software uses this base address to program the DMI register set All the Bits in this register are locked in Intel TXT mode 11 1 RO 000h Reserved DMI BAR Enable DMI BAREN 0 DMIBAR is disabled and does not claim any memory 0 RW L Ob 1 DMIBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT Datasheet 77 m n tel DRAM Controller Registers DO FO 5 1 17 PAMO Programmable Attribute Map O B D F Type 0 0 0 PCI Address Offset 90h Default Value 00h Access RO RW L Size 8 bits This register controls the read write and shadowing attributes of the BIOS area from OF0000h OFFFFFh The allows programmable memory attributes 13 Legacy memory segments of various sizes in the 768 KB to 1 MB address
113. multi function device Header Layout HL ndicates that the host controller uses a target 6 0 RO 0000000b device layout 196 Datasheet m e Intel Manageability Engine Subsystem PCI D3 FO F3 n tel 7 1 9 MBAR HECI MMI O Base Address B D F Type 0 3 0 PCI Address Offset 10 17h Default Value 0000000000000004h Access RO RW Size 64 bits Default Bit Access Description 0000000 63 4 RW 0000000 Base Address BA Base address of register memory space Oh 3 RO Ob Prefetchable PF Indicates that this range is not pre fetchable 2 1 RO 10b Type TP Indicates that this range can be mapped anywhere in 64 bit address space 0 RO Ob Resource Type Indicator RTE Indicates a request for register memory space 7 1 10 SS Sub System Identifiers B D F Type 0 3 0 PCI Address Offset 2C 2Fh Default Value 00000000h Access RWO Size 32 bits Default a Bit Access Value Description Subsystem ID SSID Indicates the sub system identifier This field should be 31 16 RWO 0000h programmed by BIOS during boot up Once written this register becomes Read Only This field can only be cleared by PLTRST Subsystem Vendor 1 SSVID Indicates the sub system vendor identifier 15 0 RWO 0000h This field should be programmed by BIOS during boot up Once written this register becomes Read Only This field can only be cleared by
114. of 250 MB s given the 8b 10b encoding used to transmit data across this interface Maximum theoretical realized bandwidth on the interface of 4 GB s in each direction simultaneously for an aggregate of 8 GB s when x16 PCI Express Enhanced Addressing Mechanism allows for accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Supports traditional PCI style traffic asynchronous snooped PCI ordering Hierarchical PCI compliant configuration mechanism for downstream devices i e normal PCI 2 3 Configuration space as a PCI to PCI bridge Supports static lane numbering reversal This method of lane reversal is controlled by a Hardware Reset strap and reverses both the receivers and transmitters for all lanes e g TX 15 2 TX 0 RX 15 gt RX 0 This method is transparent to all external devices and is different than lane reversal as defined in the PCI Express Specification In particular link initialization is not affected by static lane reversal Datasheet Introduction 1 2 5 1 2 6 1 2 7 Datasheet MCH Clocking Differential host clock of 200 266 333 MHz Supports FSB transfer rates of 800 1066 1333 MT s Differential memory clocks of 333 400 533 MHz Supports memory transfer rates of DDR2 667 and DDR2 800 The PCI Express PLL of 100 MHz Serial Reference Clock generates the PCI Express core clock of 250 MHz All of the
115. only be set when the Parity Error Enable bit in the Bridge Control register is set RO Ob Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 6 RO Ob Reserved 5 RO Ob 66 60 MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 4 0 RO 00h Reserved Datasheet 223 intel Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 15 MBASE1 Memory Base Address B D F Type 0 6 0 PCI Address Offset 20 21h Default Value FFFOh Access RW RO Size 16 bits This register controls the processor to PCI Express non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary Bit Access Para Description Value 15 4 RW FFFh Memory Address Base MBASE Corresponds to A 31 20 of the lower limit of the memory range that will be passed to Express 3 0 RO Oh Reserved 224 Datasheet m e Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH on
116. read value is undefined 9 8 RO 00b 00 Reserved 01 On 10 Blink 11 Off If the Power Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 006 Attention I ndicator Control AIC If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state Reads of this field must reflect the value from the latest write unless software issues a write without waiting for the previous command to complete in which case the read value is undefined If the indicator is electrically controlled by chassis the indicator is controlled directly by the downstream port through 7 6 RO 00b implementation specific mechanisms 00 Reserved 01 On 10 Blink 11 Off If the Attention Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b 5 4 RO 00b Reserved 3 RW Ob Presence Detect Changed Enable PDCE When set to 1b this bit enables software notification on a presence detect changed event MRL Sensor Changed Enable MSCE When set to 1b this bit enables software notification on a MRL sensor changed event 2 RO Ob Default value of this field is Ob If the MRL Sensor Present field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Power Fault Detected Enable PFDE When set to 1b this bit enables 1 RO Ob software notifica
117. reversal lanes 15 8 are active and lanes 7 0 are powered down Primary PCI Express Port Disable PEPD 0 There is a PCI Express Port on this Device 1 and associated memory spaces are accessible 1 There is no PCI Express Port on this MCH Device 1 and associated memory 44 RO Ob and 1 0 spaces are disabled by hardwiring the DIEN field bit 1 of the Device Enable register DEVEN Dev 0 Offset 54h In addition Next_Pointer 00h and IO cannot decode to the PCI Express interface From a Physical Layer perspective all 16 lanes are powered down and the link does not attempt to train Secondary PCI Express Port X16 Disable PE2X16D 0 Capable of x16 PCI Express1 Port 1 Not Capable of x16 PCI Express1 port instead PCI Express1 is limited to x8 43 RO Ob and below This causes PCI Express1 port to enable and train logical lanes 7 0 only Logical lanes 15 8 are powered down and the Max Link Width field of the Link Capability register reports x8 instead of x16 In the case of x8 lane reversal lanes 15 8 are active and lanes 7 0 are powered down Secondary PCI Express Port Disable PE2PD 0 There is a secondary PCI Express Port on this Device 6 and associated memory spaces are accessible 1 There is no secondary PCI Express Port on this MCH Device 6 and 42 RO Ob associated memory and 10 spaces are disabled by hardwiring the D6EN field bit 13 of the Device Enable register DEVEN Dev 0 Offset 54h All 16 lane
118. set 15 14 RW 00b 00 1 01 2 10 3 11 4 Refresh Counter Time Out Value REFTI MEOUT Program this field with a value that will provide 7 8 us at mclk frequency 0011000 at various memory clock frequencies this results in the following values 13 0 RW 0110000 b 400 Mhz gt C30 hex Default Value 533 Mhz gt 104B hex 666 Mhz gt 1450 hex 5 2 29 C1ECCERRLOG Channel 1 ECC Error Log B D F Type 0 0 0 MCHBAR Address Offset 680 687h Default Value 0000000000000000h Access RO P RO Size 64 bits This register is used to store the error status information in ECC enabled configurations along with the error syndrome and the rank bank row column address information of the address block of main memory of which an error single bit or multi bit error has occurred Note that the address fields represent the address of the first single or the first multiple bit error occurrence after the error flag bits in the ERRSTS register have been cleared by software A multiple bit error will overwrite a single bit error Once the error flag bits are set as a result of an error this bit field is locked and does not change as a result of a new error until the error flag is cleared by software Same is the case with error syndrome field but the following priority needs to be followed if more than one error occurs on one or more of the 4 QWs MERR on QWO MERR on QW1 MERR on QW2 MERR on QW3 CERR on QWO CERR on QW1 CERR on QW2 CERR on QW3 Default
119. set to 1 a memory read data transfer had an uncorrectable multiple bit error When this bit is set the address channel number and device number that caused the error are RWC S Ob logged in the register Once this bit is set the fields are locked until the processor clears this bit by writing a 1 Software uses bits 1 0 to detect whether the logged error address is for Single or Multiple bit error This bit is reset on PWROK Single bit DRAM ECC Error Flag DSERR If this bit is set to 1 a memory read data transfer had a single bit correctable error and the corrected data was sent for the access When this bit is set the address and device number that caused the error are logged in the DEAP register Once this bit is set the DEAP DERRSYN and DERRDST fields are locked to further single bit error updates until the processor clears this bit by writing a 1 A multiple bit error that occurs after this bit is set will overwrite the DEAP and DERRSYN fields with the multiple bit error signature and the DMERR bit will also be set A single bit error that occurs after a multi bit error will set this bit but will not overwrite the other fields This bit is reset on PWROK IR 0 RWC S Ob 92 Datasheet DRAM Controller Registers DO FO n tel 5 1 35 ERRCMD Error Command B D F Type 0 0 0 PCI Address Offset CA CBh Default Value 0000 Access RW RO Size 16 bits This register controls th
120. tel Bit Access Berat Description Value Common Clock Configuration CCC 0 Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock 6 RW Ob 1 Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock The state of this bit affects the LOs Exit Latency reported in LCAP 14 12 and the N FTS value advertised during link training Retrain Link RL 0 Normal operation 1 Full Link retraining is initiated by directing the Physical Layer LTSSM from LO LOs or L1 states to the Recovery state This bit always returns 0 when read 5 RW SC Ob This bit is cleared automatically no need to write a 0 It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register If the LTSSM is not already in Recovery or Configuration the resulting Link training must use the modified values If the LTSSM is already in Recovery or Configuration the modified values are not required to affect the Link training that s already in progress Link Disable LD 0 Normal operation 1 Link is disabled Forces the LTSSM to transition to the Disabled state via 4 RW Ob Recovery from LO LOs or L1 states Link retraining happens automatically on 0 to 1 transition just like when coming out of reset Writes to this bit are immediate
121. to TC values 7 1 RW 7Fh For example when bit 7 is set in this field TC7 is mapped to this VC resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link Traffic Class 0 Virtual Channel 0 Map TCOVCOM Traffic Class 0 is always 0 RO 1b routed to VCO 262 Datasheet Direct Media Interface DMI RCRB tel 9 6 DMI VCORSTS DMI VCO Resource Status B D F Type 0 0 0 DMIBAR Address Offset 1A 1Bh Default Value 0002 Access RO Size 16 bits This register reports the Virtual Channel specific status Bit Access Description Value 15 2 RO 0000h Reserved Virtual Channel 0 Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control initialization It is set 1 RO 1b by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state BIOS Requirement Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that V
122. to the scheduler and the dref high flag is set 17 16 RW 00b 00 3 01 4 10 5 11 6 DRAM Refresh Low Watermark REFLOWWM When the refresh count exceeds this level a refresh request is launched to the scheduler and the dref_low flag is set 15 14 RW 00b 00 1 01 22 10 3 11 4 Refresh Counter Time Out Value REFTI MEOUT Program this field with a value that will provide 7 8 us at the memory clock frequency 13 0 T 00110000 At various mclk frequencies this results in the following values 110000b 400 Mhz gt C30 hex Default Value 533 Mhz gt 104B hex 666 Mhz gt 1450 hex Datasheet 111 n tel DRAM Controller Registers DO FO 5 2 15 COECCERRLOG Channel 0 ECC Error Log B D F Type 0 0 0 MCHBAR Address Offset 280 287h Default Value 0000000000000000h Access RO P RO Size 64 bits This register is used to store the error status information in ECC enabled configurations along with the error syndrome and the rank bank row column address information of the address block of main memory of which an error single bit or multi bit error has occurred Note that the address fields represent the address of the first single or the first multiple bit error occurrence after the error flag bits in the ERRSTS register have been cleared by software A multiple bit error will overwrite a single bit error Once the error flag bits are set as a result of an error this bit field
123. turned on off either to the slot or within the adapter Note that in some cases the power controller may autonomously remove slot power or not respond to a power up request based on a detected fault condition independent of the Power Controller Control setting 0 Power On 1 Power Off If the Power Controller Implemented field in the Slot Capabilities register is set to Ob then writes to this field have no effect and the read value of this field is undefined Datasheet m e Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel Bit Access Default Description Value Power I ndicator Control PIC If a Power Indicator is implemented writes to this field set the Power Indicator to the written state Reads of this field must reflect the value from the latest write unless software issues a write without waiting for the previous command to complete in which case the read value is undefined 9 8 RO 00b 00 Reserved 01 On 10 Blink 11 Off If the Power Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 006 Attention I ndicator Control AIC If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state Reads of this field must reflect the value from the latest write unless software issues a write without waiting for the previous command to complete in which
124. wm Bit Access Value Description 63 48 RO P 0000h Error Column Address ERRCOL Row address of the address block of main memory of which an error single bit or multi bit error has occurred 47 32 RO P 0000h Error Row Address ERRROW Row address of the address block of main memory of which an error single bit or multi bit error has occurred Error Bank Address ERRBANK Rank address of the address block of main 31 29 RO P 000b 4 Moe memory of which an error single bit or multi bit error has occurred Datasheet 121 intel DRAM Controller Registers DO FO Bit Access Defaut Description Value Error Rank Address ERRRANK Rank address of the address block of main memory of which an error single bit or multi bit error has occurred zs ob 00 rank 0 DIMMO ae SNMP g 01 rank 1 DIMMO 10 rank 2 DIMM1 11 rank 3 DIMM1 26 24 RO Oh Reserved 23 16 RO P 00h Error Syndrome ERRSYND Syndrome that describes the set of bits associated with the first failing quadword 15 2 RO Oh Reserved Multiple Bit Error Status MERRSTS This bit is set when an uncorrectable multiple bit error occurs on a memory read data transfer When this bit is set 1 RO P Ob the address that caused the error and the error syndrome are also logged and they are locked until this bit is cleared This bit is cleared when it receives an indication that the processor has cleared th
125. 0 Ballout and Package Information MCH Ballout Diagram Top View Left Columns 45 31 45 44 43 42 40 39 38 37 36 35 34 33 32 31 TESTO VCC_CKDDR VCC_CKDDR VCC DDR VSS VCC DDR VSS VCC DDR NC VCC _ PPR A CSB DDR WE DDR AMA ODT RAS CKDDR VCC vss DDR RCOM RSVD vec_ppr PPR_ABS_ DDR_A_MA_ VCC_DDR DDR B CSB Rsvp 008 ODT DDR RCOM DDR A CAS DDR A CSB DDR A RAS DDR A BS DDR B CSB DDR DDR ODT DDR B CAS DDR o PYPU B d B 1 T LI E B 1 DDR_A_MA_ DDR_A_ODT DDR A CSB REUS DDR B CSB DDR MA DDR B CSB AT 2 0 22 13 DDR_A_ODT B DQ DDR B DDR B WE VCC DDR 8 vss vss DR A ODT DDR A DQ DDR B DQ B DQ DDR_B_DQ_ DDR_B_CK_ DDR_B_CKB 36 vS E 33 7 ves 5 vss DDR_A_DQ DQ DDR B DQ DO DDR B DQ DDR A DDR B CK DDR A CK vss vss az 39 38 SB a ap ux vss d ae os DDR A DM DDR_A_DQ_ DDR_A_DQ_ a 33 37 Wes DDR DQ DDR_B_DQ_ mE DDR_B_DQ_ DDR_A_CKB DDR_A_CK_ DDR_A_CK_ DDR_A_CK_ DDR_A_CKB 54 SB a 35 34 25 5 2 0 3 00 DDR_A_DQ_ DDR A DDR_B_DQ DDR_B_D
126. 0 sampled on these pins determines the expected frequency of CMOS the bus PWROK 1 0 Power OK When asserted PWROK is an indication to the MCH SSTL that core power has been stable for at least 10 us ICH SYNCB HVCMOS I CH Sync This signal synchronizes the with the ICH ALLZTEST All 2 Test This signal is used for chipset Bed of Nails testing to GTL execute All Z Test It is used as output for XOR Chain testing XORTEST XOR Chain Test This signal is used for chipset Bed of Nails GTL testing to execute XOR Chain Test In Circuit Test These pins should be connected to test points on the motherboard They are internally shorted to the package 1 0 ground and can be used to determine if the corner balls on the TEST 3 0 A MCH are correctly soldered down to the motherboard These pins should NOT connect to ground on the motherboard If TEST 3 0 are not going to be used they should be left as no connects 2 6 Direct Media I nterface Signal Name Type Description DMI_RXP_ 3 0 Direct Media nterface Receive differential pair MCH DMI_RXN_ 3 0 DMI ICH serial interface input DMI TXP 3 0 Direct Media Interface Transmit differential pair TX DMI_TXN_ 3 0 DMI MCH ICH serial interface output Datasheet 33 intel 2 7 34 Signal Description Power and Grounds Name Voltage Description VCC 1 25 V Core Power VTT 1 1 V 1 2 V Processor System Bus Power VC
127. 0 0 MCHBAR 608 609h 0000h RW L 16 bits of this register is detailed in the description for CODRAOI register Bit Access Value Description 15 8 RW L 00h 7 0 RW L 00h Channel 1 DRAM Rank 1 Attributes CIDRA1 See CODRAI register This register is locked by ME stolen Memory lock Channel 1 DRAM 0 Attributes CIDRAO See CODRAO register This register is locked by ME stolen Memory lock 5 2 22 B D F Type Address Offset Default Value Access Size C1DRA23 Channel 1 DRAM Rank 2 3 Attributes 0 0 0 MCHBAR 60A 60Bh 0000h RW L 16 bits The operation of this register is detailed the description for CODRAOI register Default PH Value Access Description 15 8 RW L 00h 7 0 RW L 00h Channel 1 DRAM Rank 3 Attributes C1DRA3 See CODRA3 register This register is locked by ME stolen Memory lock Channel 1 DRAM Rank 2 Attributes CIDRA2 See CODRA2 register This register is locked by ME stolen Memory lock Datasheet 115 m n tel DRAM Controller Registers DO FO 5 2 23 CICYCTRKPCHG Channel 1 PCHG B D F Type 0 0 0 MCHBAR Address Offset 650 651h Default Value 0000h Access RW RO Size 16 bits Channel 1 CYCTRK Precharge registers s Default Bit Access Value Description 15 11 RO 00000b Reserved Write To PRE Delayed Clsd cr pchg This field indicate
128. 0 RO Ob 0 9 RO Ob Secondary Discard Timer SDT Not Applicable or Implemented Hardwired to 0 8 RO Ob Primary Discard Timer PDT Not Applicable or Implemented Hardwired to 0 Fast Back to Back Enable FB2BEN Not Applicable Implemented 7 RO Ob Hardwired to 0 Secondary Bus Reset SRESET Setting this bit triggers a hot reset on the 6 RW Ob corresponding PCI Express Port This will force the LTSSM to transition to the Hot Reset state via Recovery from LO LOs or L1 states 5 RO Ob Master Abort Mode MAMODE Does not apply to PCI Express Hardwired to 0 VGA 16 bit Decode VGA16D Enables the PCI to PCI bridge to provide 16 bit decoding of VGA 1 0 address precluding the decoding of alias addresses every 1 KB This bit only has meaning if bit 3 VGA Enable of this register is also 4 RW Ob set to 1 enabling VGA I O decoding and forwarding by the bridge 0 Execute 10 bit address decodes on VGA I O accesses 1 Execute 16 bit address decodes on VGA 1 0 accesses VGA Enable VGAEN Controls the routing of processor initiated transactions 3 RW Ob targeting VGA compatible 1 and memory address ranges See the VGAEN MDAP table in device 0 offset 97h 0 ISA Enable I SAEN Needed to exclude legacy resource decode to route ISA resources to legacy decode path Modifies the response by the to an 1 0 access issued by the processor that target ISA I O addresses This applies only to I O addresses that are enabled by the IOBAS
129. 0 RW Ob Indicates Only 1 DIMM Populated sd1 cr singledimmpop This field indicates the that only 1 DIMM is populated Datasheet 119 n tel DRAM Controller Registers DO FO 5 2 28 C1LREFRCTRL Channel 1 DRAM Refresh Control B D F Type 0 0 0 MCHBAR Address Offset 669 66Eh Default Value 021830000 30 Access RW RO Size 48 bits This register provides the settings to configure the DRAM refresh controller Bit Access Default Description Value 47 42 RO 00h Reserved Direct Rcomp Quiet Window DI RQUI ET This configuration setting 41 37 RW 10000b indicates the amount of refresh tick events to wait before the service of rcomp request in non default mode of independent rank refresh Indirect Rcomp Quiet Window INDI RQUI ET This configuration setting 36 32 RW 11000b indicates the amount of refresh tick events to wait before the service of rcomp request in non default mode of independent rank refresh Rcomp Wait RCOMPWAIT This configuration setting indicates the amount 31 27 RW 00110b of refresh tick events to wait before the service of rcomp request in non default mode of independent rank refresh 26 RO Ob Reserved Refresh Counter Enable REFCNTEN This bit is used to enable the refresh counter to count during times that DRAM is not in self refresh but refreshes are not enabled Such a condition may occur due to need to reprogram DIMMs following DRAM controller switch Thi
130. 0000h RW RO 8A 8Bh DMILSTS DMI Link Status 0001h RO Datasheet 259 intel Direct Media I nterface DMI RCRB 9 1 DMI VCECH DMI Virtual Channel Enhanced Capability B D F Type 0 0 0 DMIBAR Address Offset 0 3h Default Value 04010002h Access RO Size 32 bits This register indicates DMI Virtual Channel capabilities Bit Access peraulg Description Value Pointer to Next Capability PNC This field contains the offset to the next 31 20 RO 040h PCI Express capability structure in the linked list of capabilities Link Declaration Capability PCI Express Virtual Channel Capability Version PCI EVCCV Hardwired to 1 to indicate compliances with the 1 1 version of the PCI Express 19 16 RO specification Note This version does not change for 2 0 compliance 15 0 RO 0002h Extended Capability I D ECI D Value of 0002 h identifies this linked list item capability structure as being for Express Virtual Channel registers 9 2 DMI PVCCAP1 DMI Port VC Capability Register 1 B D F Type 0 0 0 DMIBAR Address Offset 4 7h Default Value 000000018 Access RWO RO Size 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port Bit Access Derault Description Value 31 7 RO 0000000h Reserved Low Priority Extended VC Count LPEVCC Indicates the number of extended Virtual Channels in addition to the default VC belonging to the low
131. 0h Reserved Extended Synch EXTSYNC 7 RW Ob 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and when in the Recovery state 6 3 RO Oh Reserved 2 RW Ob Far End Digital Loopback FEDLB Active State Power Management Support ASPMS This field controls the level of active state power management supported on the given link b 00 Disabled 1 0 Rs o0 01 LOs Entry Supported 10 Reserved 11 LOs and L1 Entry Supported 9 12 DMI LSTS DMI Link Status B D F Type 0 0 0 DMI BAR Address Offset 8A 8Bh Default Value 0001h Access RO Size 16 bits This register indicates DMI status Bit Access Description Value 15 4 RO Os Reserved Negotiated Speed NSPD This field indicates negotiated link speed 3 0 RO 1h 1h 2 5 Gb s All other encodings are reserved 266 88 Datasheet Functional Description 10 Functional Description 10 1 Host I nterface The MCH supports Dual Core Intel Xeon Processor 3000 Series and Quad Core Processor 3200 Series processors The cache line size is 64 bytes Source Intel Xeon ntel synchronous transfer is used for the address and data signals The address signals are double pumped and a new address can be generated every other bus clock At 200 267 333MHz bus clock the address signals run at 667MT s The data is quad pumped and an entire 64B cache line can be transferred in two bus cl
132. 1 to indicate compliances with the 1 1 version of the Express specification 15 0 RO 0002h Extended Capability I D ECI D Value of 0002 h identifies this linked list item capability structure as being for Express Virtual Channel registers 6 48 PVCCAP1 Port VC Capability Register 1 B D F Type 0 1 0 MMR Address Offset 104 107h Default Value 00000000h Access RO Size 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port Bit Access Derauit Description Value 31 7 RO 00000h Reserved Low Priority Extended VC Count LPEVCC Indicates the number of extended Virtual Channels in addition to the default VC belonging to the low 6 4 RO 000b priority VC LPVC group that has the lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration 3 RO Ob Reserved 2 0 RO 000b Extended VC Count EVCC Indicates the number of extended Virtual Channels in addition to the default VC supported by the device Datasheet 185 m n tel Host Primary PCI Express Bridge Registers D1 FO 6 49 PVCCAP2 Port VC Capability Register 2 B D F Type 0 1 0 MMR Address Offset 108 10Bh Default Value 00000000h Access RO Size 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port Default Bit Access Value Description
133. 2 RO 00b Reserved 5 RO Ob Direct Catastrophic Comparator Read DCCR This bit reads the output of 1 RO Ob the Catastrophic comparator directly without latching via the Thermometer mode circuit Used for testing Direct Hot Comparator Read DHCR This bit reads the output of the Hot 0 RO Ob comparator directly without latching via the Thermometer mode circuit Used for testing 134 Datasheet DRAM Controller Registers DO FO n tel 5 2 47 TSTTP Thermal Sensor Temperature Trip Point B D F Type 0 0 0 MCHBAR Address Offset CDC CDFh Default Value 00000000h Access RO RW RW L Size 32 bits This register provides the following Sets the target values for the trip points in thermometer mode See also TST Direct DAC Connect Test Enable Reports the relative thermal sensor temperature All bits in this register are reset to their defaults by MPWROK Bit Access Derault Description Value Relative Temperature RELT In Thermometer mode the RELT field of this register report the relative temperature of the thermal sensor Provides a two s complement value of the thermal sensor relative to the Hot Trip Point Temperature above the Hot Trip Point will be positive 31 24 RO 00h TR and HTPS can both vary between 0 and 255 But RELT will be clipped between 127 to keep it an 8 bit number See also TSS Thermometer mode Output Valid In the Analog mode the RELT field reports HTPS value 2
134. 23 20 RO Oh Reserved Port Arbitration Select PAS This field configures the VC resource to provide a particular Port Arbitration service Valid value for this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource 16 8 RO 000h Reserved Traffic Class Virtual Channel 1 Map TCVC1M This field indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values 7 1 RW 00h For example when bit 7 is set in this field TC7 is mapped to this VC resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource To remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link Traffic Class 0 Virtual Channel 1 TCOVC1M Traffic Class 0 is always routed to VCO 19 17 RW 000b 264 Datasheet m e Direct Media I nterface DMI RCRB tel 9 9 DMI VCIRSTS DMI VC1 Resource Status B D F Type 0 0 0 DMI BAR Address Offset 26 27h Default Value 0002h Access RO Size 16 bits This register reports the Virtual Channel specific status Default Bit Access Value Description 15 2 RO 0000h Reserved Virtual Channel 1 Negotiation Pending VC1NP 1 RO lb 0 The VC nego
135. 3 16 RW 00h AuxO Trip point setting AOTPS Sets the target for the Aux0 trip point Hot Trip Point Setting HTPS Sets the target value for the Hot trip point RIWL om Lockable via TCO bit 7 Catastrophic Trip Point Setting CTPS Sets the target for the Catastrophic 7 0 RW L 00h trip point See also TST Direct DAC Connect Test Enable Lockable via TCO bit 7 Datasheet 135 DRAM Controller Registers DO FO 5 2 48 TCO Thermal Calibration Offset B D F Type 0 0 0 MCHBAR Address Offset CE2h Default Value 00 Access RW L K RW L Size 8 bits Bit 7 reset to it s default by PLTRST Bits 6 0 reset to their defaults by MPWROK Bit Access Default Description Value Lock Bit for Catastrophic LBC This bit when written to a 1 locks the Catastrophic programming interface including bits 7 0 of this register and bits 7 RW L K Ob 15 0 of TSTTP bits 1 7 of TSC 1 bits 3 0 of TSC 2 bits 4 0 of TSC 3 and bits 0 7 of TST This bit may only be set to a O by a hardware reset PLTRST Writing a 0 to this bit has no effect Calibration Offset CO This field contains the current calibration offset for the Thermal Sensor DAC inputs The calibration offset is a twos complement signed number which is added to the temperature counter value to help generate the final value going to the thermal sensor DAC This field is Read Write and can be modified by Software unless locked by setting
136. 39001h RO 84 87h PM_CS1 Power Management Control Status 00000008h pu 88 8 SS CAPID Subsystem ID and Vendor ID Capabilities 0000800Dh RO 8C 8Fh SS Subsystem ID and Subsystem Vendor ID 00008086h RWO 90 91h MSI CAPID Message Signaled Interrupts Capability ID 005 RO 92 93h MC Message Control 0000h RW RO 94 97h MA Message Address 00000000h RO RW 98 99h MD Message Data 0000h RW 0 1 CAPL PCI Express Capability List 0010h RO A2 A3h PE_CAP PCI Express Capabilities 0142h RO RWO A4 A7h DCAP Device Capabilities 00008000h RO A8 A9h DCTL Device Control 0000h RW RO AA ABh DSTS Device Status 0000h RO RWC AC AFh LCAP Link Capabilities 03214D01h RO RWO BO B1h LCTL Link Control 0000h je ee B2 hB3 LSTS Link Status 1000h RWC RO B4 B7h SLOTCAP Slot Capabilities 00040000h RWO RO B8 B9h SLOTCTL Slot Control 0000h RO RW BA BBh SLOTSTS Slot Status 0000h RO RWC BC BDh RCTL Root Control 0000h RO RW C0O C3h RSTS Root Status 00000000h RO RWC Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only intel Table 15 Host Secondary PCI Express Bridge Register Address Map D6 FO Sheet 3 of 3 Address Register Default Offset Symbol Register Name Value Access EC EFh PELC PCI Express Legacy Control 00000000h RO RW 100 103h VCECH Virtual Channel Enhanced Capability 14010002h RO Header 104 107h PVCCAP1
137. 42 DDR_A_DQ_43 AR5 PEG2 TXN 13 AN33 DDR B DQ 43 AL41 DDR_A_DQ_47 AR4 VSS AN31 RSVD AL40 DDR_A_DQ_46 AR2 PEG2 TXP 12 7 AN30 RSVD AL39 VSS AP45 DDR_A_DQ_45 AN28 DDR_A_CK_1 AL38 DDR_A_DQS 8 AP43 VSS AN27 DDR A CK 4 AL36 DDR A DQSB 8 AP42 DDR A DQ 44 AN25 RSVD AL35 VSS AP40 DDR_B_DQSB_5 AN24 DDR B DQ 28 AL34 DDR A CB 5 AP39 DDR B DQS 5 AN23 VSS AL33 DDR A CB 0 AP38 VSS AN22 DDR A DQ 26 AL30 VCC CL AP36 DDR B DQ 41 AN21 DDR A DQ 30 AL28 RSVD AP35 DDR B DQ 42 AN19 DDR A DQ 24 AL27 VCC CL 305 intel Table 29 MCH Ballout Sorted By Ball Table 29 MCH Ballout Sorted By Ball Ballout and Package Information Table 29 MCH Ballout Sorted By Ball 306 Ball Signal Name Ball Signal Name Ball Signal Name AL25 VCC_CL AJ29 VCC CL AH11 PEG2 RXP 10 AL24 VCC CL AJ28 VCC CL AH10 PEG2 RXN 10 AL23 VCC CL AJ27 VCC CL AH8 VSS AL22 VCC CL AJ26 VCC CL AH7 PEG2 RXP 11 7 AL21 VCC CL AJ25 VCC CL AH6 PEG2 RXN 11 AL19 VCC CL AJ24 VCC CL AH4 PEG2 TXP 5 47 AL18 VCC CL AJ23 VCC CL AH3 PEG2 TXN 6 7 AL16 VCC CL AJ22 VCC CL AH1 VSS AL13 CL PWROK AJ21 VCC CL AG44 DDR_B_CB_7 AL12 VSS AJ20 VCC CL AG42 DDR B CB 2 AL11 PEG2 13 7 AJ19 VCC CL AG41 DDR_B_CB_6 ALIO PEG2 RXN 13 7 18 VCC CL AG40 DDR B CB 3 8 vss A7 VCC CL AG39 DDR B DQS 6 AL7 PEG2
138. 5 DDR A DQ 1 BD4 DDR A DQ 46 AL40 CL_PWROK AL13 DDR A DQ 2 BB8 DDR_A_DQ_47 AL41 CL_RSTB AG11 DDR A DQ 3 BE8 DDR_A_DQ_48 AE41 CL_VREF AG14 DDR_A_DQ 4 BD3 DDR_A_DQ_49 AE42 DDR_A_BS_0 BC37 DDR_A_DQ_5 BB4 DDR_A_DQ_50 AC42 DDR_A_BS_1 BB36 DDR_A_DQ 6 BD7 DDR_A_DQ_51 AC45 DDR_A_BS 2 BB26 DDR_A_DQ_7 BB7 DDR_A_DQ_52 AF42 DDR_A_CASB BB41 DDR A DQ 8 BD9 DDR A DQ 53 AF45 DDR_A_CB_0 AL33 DDR A DQ 9 BB10 DDR A DQ 54 AD40 DDR_A_CB_1 AN35 DDR_A_DQ_10 BB12 DDR_A_DQ_55 AC39 DDR A CB 2 AK38 DDR A DQ 11 BE12 DDR A DQ 56 AB42 DDR_A_CB_3 AK35 DDR A DQ 12 BA9 DDR A DQ 57 AB43 DDR A CB 4 AK33 DDR A DQ 13 9 DDR_A_DQ_58 42 DDR A CB 5 AL34 DDR A DQ 14 BD11 DDR A DQ 59 W42 DDR_A_CB_6 AK34 DDR_A_DQ_15 BB11 DDR_A_DQ_60 AC40 DDR_A_CB_7 AK39 DDR_A_DQ_16 BD13 DDR_A_DQ_61 AB39 DDR_A_CK_0 AT33 DDR_A_DQ_17 BB14 DDR A DQ 62 41 DDR_A_CK_1 AN28 DDR_A_DQ_18 BB16 DDR A DQ 63 45 DDR_A_CK_2 AT34 DDR_A_DQ_19 BE16 DDR A DQS 0 BA6 DDR A CK 3 AV31 DDR A DQ 20 BA13 DDR A DQS 1 BA11 DDR A CK 4 AN27 DDR A DQ 21 BB13 DDR A DQS 2 BA15 DDR_A_CK_5 AT35 DDR_A_DQ_22 BD15 DDR_A_DQS 3 AT21 DDR A CKB 0 AR33 DDR A DQ 23 BB15 DDR_A_DQS 4 AT43 DDR_A_CKB_1 AM28 DDR 24 19 DDR A DQS 5 AM43 DDR A CKB 2 AV35 DDR A DQ 25 AY21 DDR A DQS 6 AD43 DDR A CKB 3 AT31 DDR A DQ 26 AN22 DDR A DQS 7 42 DDR_A_CKB 4 AM27 DDR A DQ 27 AT22 DDR A DQS 8 AL38 DDR A CKB 5 AT36 DDR A DQ 28 AV19 DDR A DQSB 0 BC6 DDR A 0 BD25 DDR A DQ 29 AW19 DDR A DQSB 1 AY11 DDR A CKE 1 AY24 DDR A DQ 30 AN21
139. 56 LE1D Link Entry 1 Description B D F Type 0 1 0 MMR Address Offset 150 153h Default Value 000000008 Access RO RWO Size 32 bits This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element Bit Access perault Description Value Target Port Number TPN Specifies the port number associated with the 31 24 RO 00h element targeted by this link entry Egress Port The target port number is with i respect to the component that contains this element as specified by the target component ID 23 16 RWO 00h Target Component D TCI D Identifies the physical or logical component that is targeted by this link entry 15 2 RO 0000h Reserved 1 RO Ob Link Type LTYP Indicates that the link points to memory mapped space for RCRB The link address specifies the 64 bit base address of the target RCRB Link Valid LV 0 RWO Ob 0 Link Entry is not valid and will be ignored 1 Link Entry specifies a valid link 190 Datasheet m e Host Primary PCI Express Bridge Registers D1 FO n tel 6 57 LE1A Link Entry 1 Address B D F Type 0 1 0 MMR Address Offset 158 15Fh Default Value 0000000000000000h Access RO RWO Size 64 bits This register provides the second part of a Link Entry which declares an internal link to another Root Complex Element Bit Access Description Value 63 32 RO Reserve
140. 7 2 2 CMD COMMANG itt ep exeun E O rm eee 194 7 123 SIS DevVice Status n apu RT ERRKPESKESRENOE HERI RIS 195 7 3 4 RIDSREVISION ID eee estem rre es ae ee nct e ven E Ud Se 195 PMS CC Class COC Gris Em 195 71 6 5 line SiZ e ea ica P chen 196 7 1 7 MLT Master Latency Timer 196 7 1 8 ei ror Lie pe bas 196 7 1 9 MBAR HECI MMIO Base 197 7 1 10 SS Sub System Identifiers 00001550 ea ene 197 7 1 11 CAP Capabilities Pointer ori en vats eens LI ER RE Ru aes 198 7 1 12 INTR Interrupt 1 emnes 198 7 1 13 MGNT Minimum 50011 198 7 1 14 MLAT Maximum 2 199 7 3 15 5 cete tete e ere REPRE RYAN ERR RU CER dads 199 7 1 16 PID PCI Power Management Capability 10 199 7 1 17 PC PCI Power Management Capabilities 200 7 1 18 PMCS PCI Power Management Control And
141. 7 4 RW Oh register indicates the minimum allowed spacing in DRAM clocks between two WRITE commands to different ranks This field corresponds to twr wr in the DDR Specification 7 READ WRTE Delay COsd cr rd wr This field indicates the minimum 3 0 RW Oh allowed spacing in DRAM clocks between the READ and WRITE commands This field corresponds to trp wg Datasheet 107 DRAM Controller Registers DO FO 5 2 11 COCYCTRKRD Channel O CYCTRK READ B D F Type 0 0 0 MCHBAR Address Offset 258 25Ah Default Value 0000008 Access RO RW Size 24 bits Channel 0 CYCTRK RD registers Bit Access Besse Description Value 23 21 RO 000b Reserved Min ACT To READ Delayed COsd_cr_act_rd This field indicates the 20 17 RW Oh minimum allowed spacing in DRAM clocks between the ACT and READ commands to the same rank bank This field corresponds to in the DDR specification 7 Same Rank Write READ Delayed COsd_cr_wrsr_rd This field indicates the minimum allowed spacing DRAM clocks between the WRITE and READ 16 12 RW 000099 commands to the same rank This field corresponds to twrp in the DDR specification Different Ranks Write To READ Delayed COsd cr wrdr rd This field 11 8 RW 0000b indicates the minimum allowed spacing in DRAM clocks between the WRITE and READ commands to different ranks This field corresponds to pp in the DDR specification 7 Same
142. 7 6 3 7 7 Datasheet intel SMM Control Combinations The G_SMRAME bit provides a global enable for all SMM memory The D_OPEN bit allows software to write to the SMM ranges without being in SMM mode BIOS software can use this bit to initialize SMM code at powerup The D_LCK bit limits the SMM range access to only SMM mode accesses The D_CLS bit causes SMM both CSEG and TSEG data accesses to be forwarded to the DMI Interface or PCI Express The SMM software can use this bit to write to video memory while running SMM code out of DRAM SMM Control Table usa monks i maaa Data Mode Access Access 0 x X x x Disable Disable 1 0 X 0 0 Disable Disable 1 0 0 0 1 Enable Enable 1 0 0 1 Enable 1 0 1 0 1 Enable Disable 1 0 1 1 Invalid Invalid 1 1 X x 0 Disable Disable 1 ii 0 x 1 Enable Enable 1 1 1 1 Enable Disable SMM Space Decode and Transaction Handling Only the processor is allowed to access SMM space PCI Express and DMI Interface originated transactions are not allowed to SMM space Processor WB Transaction to an Enabled SMM Address Space Processor Writeback transactions REQa 1 0 to enabled SMM Address Space must be written to the associated SMM DRAM even though D_OPEN 0 and the transaction is not performed in SMM mode This ensures SMM space cache coherency when cacheable extended SMM space is used SMM Acc
143. 7 vss 8 Note 4y 8 Note 4 3 Note 47 vss 2 Note 47 EXP2_CLKIN PEG2_RXN PEG2_TXP_ PEG2_TXN VCCR EXP vss EO ORA _ Vcc EXP ExP vss T NGA r MORE ay vss PEG2 PEG2_RXP_ PEG2_RXN PEG2_RXN_ PEG2_RXP PEG2 TXN VCCR EXP ves 3 Note 47 4 Note 4j 4 Note 47 Ne 5 Note 47 5 Note 47 1 Note ay VCCR EXP i VCC_EXT_P PEG2_RXN PEG2 TXP PEG2 vec VCCR_EXP XT PEG _ vcc EXP vcc ExP vcc ExP vec_exe FG Gy Gente AT PEG2_RXN PEG2_RXN_ PEG2_RXP PEG2_RXN_ PEG2_RXP VCCR EXP VCCR EXP o Note 47 xe 1 Note 4y 1 Note 47 vss 2 Note 47 2 Note ay VCC EXP VEG EXP VCC EXP VCC EXP VCC EXP VCCR EXP vss vss EXP VCC EXP VCC EXP vss VCC EXP VCC EXP VCC EXP VCCR EXP VCCR ExP VSS RSVD DMI_TXN_3 DMI_TXP_3 VSS DMI_RXN_3 vcc ExP vcc Exe VCC EXP VCC EXP VCC EXP VCC EXP VCCR EXP VCCR_EXP VSS RSVD VSS EXP_COMPO DMI_RXN_1 DMI_RXP_1 vss vcc ExP vcc EXP DMI_TXN_2 VSS vss VSS EXP_COMPI VSS 0 DMI_TXN_O DMI_RXN_2 VSS DMI_TXP_2 VSS DMI_RXP_2 DMI_TXN_1 VSS VCC N15 PEG RXP 4 RSVD RSVD FEGSRAN T PEG RAS vss vss DMI RXP 0 vss DMI_TXP_1 VSS M15 PEG RXN 4 vss vss PEG_RXN_1 PEG_RXP_1 vss DMI_RXN_O VCCR_EXP PEG_TXP_1 vss PEG_RXP_3 PEG_RXN_6 vss PEG_RXN_1 vss vss vss PEG TAE vss PEG_TAN 1 vss PEG_RXN_3 vss PEG_RXP_6 vss PEG_RXN 1
144. 8 RWO 1b 0 The PCI Express Link associated with this port is connected to an integrated component or is disabled 1 The PCI Express Link associated with this port is connected to a slot Device Port Type DPT Hardwired to 4h to indicate root port of PCI Express 7 4 RO 4h Root Complex 3 0 RO 2h PCI Express Capability Version PCI ECV Hardwired to 2h to indicate compliance to the Express Capabilities Register Expansion 8 35 DCAP Device Capabilities B D F Type 0 6 0 PCI Address Offset A4 A7h Default Value 00008000 Access RO Size 32 bits This register indicates PCI Express device capabilities Default Bit Access Value Description 31 16 RO 0000h Reserved Role Based Error Reporting RBER This bit indicates that this device 15 RO 1b implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1 1 specification 14 6 RO 000h Reserved Extended Tag Field Supported ETFS Hardwired to indicate support for 5 5 RO Ob bit Tags as Requestor Phantom Functions Supported PFS Not Applicable or Implemented 4 3 RO 00b Hardwired to 0 Max Payload Size MPS Hardwired to indicate 128B max supported payload 2 0 RO 000b A for Transaction Layer Packets TLP Datasheet 237 Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only DCTL Device Control B D F Type Address Offset Default V
145. A MA 14 BA25 DDR B DM 6 AG35 DDR B DQ 43 AN33 DDR ODT 0 BB43 DDR B DM 7 AD35 DDR B DQ 44 AV36 DDR A ODT 1 AY41 DDR_B_DQ_0 AW8 DDR_B_DQ_45 AR34 DDR_A_ODT_2 BA41 DDR B DQ 1 AY7 DDR B DQ 46 AN39 DDR A ODT 3 AW44 DDR_B_DQ 2 AT11 DDR B DQ 47 AN40 DDR_A_RASB BB38 DDR_B_DQ 3 AT12 DDR B DQ 48 AH34 DDR A WEB BD39 DDR B DQ 4 AV8 DDR B DQ 49 AG33 DDR B BS 0 BB24 DDR B DQ 5 AW6 DDR B DQ 50 AE39 DDR B BS 1 AW23 DDR B DQ 6 AR11 DDR B DQ 51 AE38 DDR B BS 2 BB18 DDR B DQ 7 AW11 DDR B DQ 52 AH33 DDR B CASB BB32 DDR B DQ 8 AY12 DDR B DQ 53 AH36 DDR B CB 0 AK45 DDR_B_DQ 9 AY13 DDR_B_DQ_54 AE40 DDR_B_CB_1 AJ 44 DDR_B_DQ_10 AT15 DDR_B_DQ_55 AE33 DDR_B_CB_2 AG42 DDR_B_DQ_11 AV15 DDR_B_DQ_56 AD39 DDR_B_CB_3 AG40 DDR_B_DQ_12 AW12 DDR_B_DQ_57 AD36 DDR_B_CB_4 42 DDR B DQ 13 AW13 DDR B DQ 58 AB32 DDR B CB 5 AK42 DDR B DQ 14 AN15 DDR B DQ 59 AB38 DDR B CB 6 AG41 DDR_B_DQ_15 AP15 DDR_B_DQ_60 AE35 DDR_B_CB_7 AG44 DDR_B_DQ_16 AY16 DDR B DQ 61 AE34 DDR B CK 0 AW30 DDR B DQ 17 AV16 DDR B DQ 62 AC36 DDR B CK 1 AR28 DDR B DQ 18 AP19 DDR B DQ 63 AC34 DDR_B_CK_2 AV33 DDR_B_DQ_19 AT19 DDR_B_DQS_0 AW10 DDR_B_CK_3 AR31 DDR B DQ 20 AN16 DDR B DQS 1 AR13 DDR B CK 4 AY30 DDR B DQ 21 AR16 DDR B DQS 2 AN18 DDR B CK 5 AW34 DDR B DQ 22 AT18 DDR B DQS 3 AR25 DDR B CKB 0 AV30 DDR B DQ 23 AR18 DDR B DQS 4 AW39 DDR B CKB 1 AP28 DDR B DQ 24 AW25 DDR B DQS 5 AP39 DDR B CKB 2 AW33 DDR B DQ 25 AV25 DDR B DQS 6 AG39 DDR B CKB 3 AP31 DDR B DQ 26 AT27 DDR B DQS 7 AC33 DDR B CKB 4 AY28 DDR B DQ 27
146. A17 DDR B CKE 3 BD15 DDR A DQ 22 BB35 DDR B CSB 1 BA15 DDR A DQS 2 BD13 DDR A DQ 16 BB34 DDR_B_ODT_1 BA13 DDR A DQ 20 BD11 DDR A DQ 14 BB33 DDR B ODT 2 11 DDR_A_DQS 1 BD9 DDR A DQ 8 BB32 DDR B CASB BA9 DDR A DQ 12 303 intel 304 Table 29 MCH Ballout Sorted By Ball Table 29 MCH Ballout Sorted By Ball Ballout and Package Information Table 29 MCH Ballout Sorted By Ball Ball Signal Name Ball Signal Name Ball Signal Name BA6 DDR A DQS 0 AW31 VSS AV13 VSS BA5 VSS BA5 AW30 DDR B CK O0 AV12 VSS BA4 VSS_BA4 AW28 VSS AV11 VSS AY45 VCC_DDR AW27 VSS AV10 VSS AY43 DDR_A_CSB_3 AW25 DDR_B_DQ_24 AV8 DDR_B_DQ 4 AY41 DDR_A_ODT_1 AW24 DDR_B_MA_10 AV7 DDR_VREF AY40 DDR B DM 4 AW23 DDR B BS 1 AV6 VSS AY39 DDR B DQ 32 AW22 DDR A DQ 31 AVA VSS AY38 DDR B DQ 36 AW21 VSS AV3 VSS AY36 VSS AW19 DDR A DQ 29 1 VSS AY35 DDR_B_ODT_3 AW18 VSS AU44 DDR_A_DM_4 AY34 DDR_B_CKB_5 AW16 DDR_B_DM_2 AU43 DDR A DQ 33 AY33 VSS AW15 VSS AU41 DDR A DQ 37 AY31 DDR B WEB AW13 DDR B DQ 13 AU5 VCCA_EXP2 AY30 DDR_B_CK_4 AW12 DDR_B_DQ_12 AU3 VSS AY28 DDR_B_CKB_4 AW11 DDR B DQ 7 AU2 PEG2 TXP 14 4 AY27 DDR_A_MA_7 AW10 DDR_B_DQS_0 AT45 VSS AY25 DDR_B_DM_3 AW8 DDR_B_DQ_0 AT43 DDR_A_DQS 4 AY24 DDR_A_CKE_1 AW7 vss AT42 DDR_A_DQSB 4 AY23 VCC_DDR AW6 DDR B DQ 5 AT40 DDR_B_
147. AA20 VSS P32 VSS K30 VSS AA12 VSS P27 vss K23 VSS AA8 VSS P25 VSS K18 VSS Y43 VSS P24 VSS K15 VSS Y27 VSS P23 VSS K12 VSS Y25 VSS P22 VSS K10 VSS Y23 VSS P18 VSS K6 VSS Y21 VSS P14 VSS K1 VSS Y19 VSS P1 VSS 13 VSS W39 VSS N35 VSS H43 VSS W35 VSS N27 VSS H40 VSS W26 VSS N23 VSS H36 VSS W24 VSS N22 VSS H35 VSS W22 VSS N19 VSS H23 VSS W20 VSS N16 VSS H22 VSS W14 VSS N7 VSS H19 VSS W13 VSS N6 VSS H18 VSS W6 VSS N4 VSS H11 VSS V45 VSS M43 VSS H8 VSS V40 VSS M39 VSS H7 VSS V36 VSS M35 VSS H6 VSS V33 VSS M34 VSS G39 VSS V27 VSS M33 VSS G33 VSS V25 VSS M28 VSS G31 VSS V23 VSS M24 VSS G23 VSS V21 VSS M23 VSS G18 VSS V19 VSS M18 VSS G11 VSS V13 VSS M12 VSS G8 VSS V8 VSS M10 VSS G7 VSS T43 VSS M6 VSS G4 VSS T35 VSS L38 VSS F45 VSS T32 VSS L35 VSS F40 VSS T13 VSS L31 VSS F36 VSS T11 VSS L23 VSS F34 VSS T6 VSS L21 VSS F24 VSS R40 VSS L15 VSS F23 VSS R38 VSS L11 VSS F16 VSS R34 VSS L8 VSS F15 VSS R21 VSS L7 VSS F13 VSS R13 VSS L6 VSS F12 VSS R12 VSS L4 VSS F11 VSS R11 VSS K45 VSS F10 301 m n tel Ballout and Package Information Table 28 MCH Table 28 MCH Ballout Sorted By Name v Ballout Sorted By Name Signal Name Ball Signal Name Ball VSS F8 VSS_BA4 BA4 VSS F6 VSS_BA5 BA5 VSS F1 VSS_BB3 BB3 VSS E21 VSS C23 C23 VSS E19 VSS C24 C24 VSS E5 VSS D21 D21 VSS D42
148. AA7 PEG2 RXN 2 7 W20 VSS AB15 VCC AAG PEG2_RXP_2 4 W19 VCC AB14 VCCR_EXP AAS VCC_EXP W18 VCC AB13 VCC EXT PLL AAA VCC EXP W17 VCC AB12 PEG2 RXN 7 AA2 VCC EXP W15 VCCR EXP AB11 VCC EXP Y45 DDR_A_DQ 63 W14 VSS AB10 VCC_EXP Y43 VSS W13 VSS AB8 VCC EXP Y42 DDR A DQ 58 W12 PEG2 0 7 AB7 VCC EXP Y29 VCC CL W11 VCC EXP AB6 VCC EXP Y28 VCC W10 VCC EXP ABA VCC EXP Y27 VSS W8 VCC EXP AB3 PEG2 TXP 0 Y26 VCC W7 VCC_EXP AB1 PEG2 TXN 0 9 Y25 VSS W6 VSS AA44 DDR A DQSB 7 Y24 VCC W5 VCC_EXP 42 DDR A DQS 7 Y23 VSS WA VCC EXP 41 DDR A DQ 62 Y22 VCC W2 VCC EXP 40 5 33 Y21 VSS 45 VSS AA39 VSS Y20 VCC V43 FSB AB 28 AA38 FSB AB 35 Y19 VSS 42 FSB_HITMB AA36 VSS Y18 VCC V40 VSS AA35 FSB AB 32 Y17 VCC v39 FSB AB 24 AA34 VSS YA VCC EXP V38 FSB_AB_23 AA33 FSB_AB_31 Y3 VCC_EXP V36 VSS AA32 VSS Y1 VCC_EXP V35 FSB AB 26 AA31 VCC CL W44 FSB BREQOB V34 FSB ADSTBB 1 AA29 VCC CL W42 DDR A DQ 59 V33 VSS Datasheet Ballout and Package I nformation Datasheet intel Table 29 MCH Table 29 MCH Table 29 MCH Ballout Sorted By Ball Ballout Sorted By Ball Ballout Sorted By Ball Ball Signal Name Ball Signal Name Ball Signal Name V32 RSVD U2 VCC_EXP R16 VCC V31 VCC CL T45 FSB LOCKB R13 VSS V29 VCC_CL T43 VSS R12 VSS V28 VCC T42 FSB_DBSYB R11 VSS V27 VSS T40 FSB_AB_17 R10 EXP_COMPI V26 VCC T39
149. AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA intel Figure 14 BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB 292 Ballout and Package Information MCH Ballout Diagram Top View Left Columns 15 1 15 14 13 12 n 10 9 8 7 6 5 4 3 2 1 vss vss DDR_A_DQ_ vss vss NC TESTI DDR DQ DDR A DQ DDR DQ DDR A DQ DDR DQ DDR DQ DDR A DQ es iE 22 16 14 8 6 1 4 DDR A DM DDR A DM DDR A 00 DDR A DQ DDR A DQ 5 vss A Po vss 5 vss RSVD vss DQ DDR A DDR DDR A A DO DDR DQ DDR DQ DDR A DM DDR A DQ vss Ves 23 17 21 16 15 9 2 7 20 5 E DDR DQ DDR A 00 DDR A DQ DDR A DQ DDR A DQ ES 00 st A po so vss_BA5 VSS 4 DDR A DQ DDR B DQ DDR B DDR DDR B DM DDR RCOM DDR RCOM SB 2 z 78 77 SB 1 55 207 PXPD PXPU 55_ VSS AYI DDR DQ DDR B DDR B DDR DDR B DQ DDR B DQ vss B PO B DQ PIE B DQ vss vss VSS AW2 DDR B DQ vss vss vss vss DDR_B_DO_ ppg vss vss vss vss PEG2 TXP VCCA EXP2 vss aa iNote A DDR_B_DQ_ DDR_B_
150. Abort Status RMAS This bit is set when the MCH 13 RWC Ob generates a DMI request that receives an Unsupported Request completion packet Software clears this bit by writing a 1 to it Received Target Abort Status RTAS This bit is set when the MCH 12 RWC Ob generates a DMI request that receives a Completer Abort completion packet Software clears this bit by writing a 1 to it Signaled Target Abort Status STAS The MCH will not generate a Target 11 RO Ob Abort DMI completion packet or Special Cycle This bit is not implemented in the and is hardwired to a 0 Writes to this bit position have no effect DEVSEL Timing DEVT These bits are hardwired to 00 Writes to these bit 10 9 RO 00b positions have no affect Device 0 does not physically connect to PCI A These bits are set to 00 fast decode so that optimum DEVSEL timing for PCI A is not limited by the MCH Master Data Parity Error Detected DPD This bit is set when DMI received 8 RWC Ob a Poisoned completion from ICH u This bit can only be set when the Parity Error Enable bit in the PCI Command register is set Fast Back to Back FB2B This bit is hardwired to 1 Writes to these bit 7 RO 1b positions have no effect Device 0 does not physically connect to PCI This bit is set to 1 indicating fast back to back capability so that the optimum setting for PCI A is not limited by the MCH 6 RO Ob Reserved RO Ob 66 MHz Capable Does not apply to PCI Express Hardwired to 0
151. B 7 0 DDR B DQS 7 0 and DDR B DQSB 7 0 signals 6 Crossing voltage defined as instantaneous voltage when rising edge of BCLKO equals falling edge of BCLK1 7 is the statistical average of the measured by the oscilloscope 8 The crossing point must meet the absolute and relative crossing point specifications simultaneously Refer to the appropriate processor datasheet for further information 88 Datasheet m e Ballout and Package I nformation n tel 12 Ballout and Package I nformation This chapter provides the ballout and package dimensions for the MCH 12 1 Ballout Information Figure 12 Figure 13 and Figure 14 provide the MCH ballout as viewed from the top side of the package Table 28 provides a ballout list arranged alphabetically by signal name Table 29 provides a ballout list arranged numerically by ball number Note Notes for Figure 12 Figure 13 Figure 14 Table 28 and Table 29 1 Balls that are listed as RSVD are reserved 2 Some balls marked as reserved RSVD are used in XOR testing See Chapter 13 for details 3 Balls that are listed as NC are No Connects 4 PEG2 RXN 15 0 PEG2 RXP 15 0 PEG2 TXN 15 0 PEG2 TXP 15 0 EXP2 COMPO and EXP2 COMPI are NCs on the Intel 3200 MCH Datasheet 289 intel Figure 12 BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA 29
152. B AB 30 26 T38 FSB AB 20 Table 35 Chain 27 v35 FSB_AB_26 Ex 28 w33 FSB AB 27 Count Ball Chain 3 29 w38 FSB AB 22 NES 30 V34 FSB ADSTBB 1 31 AA33 FSB_AB_31 1 D41 FSB DSTBNB 3 a2 T36 FSB AB 18 2 C40 FSB DSTBPB 3 33 AB35 FSB AB 34 3 B37 FSB DINVB 3 34 BASS FSB_AB_32 4 E40 FSB DINVB 1 319 intel Testability Table 35 XOR Chain 3 Table 36 XOR Chain 4 Rane Ball Chain 3 2 Ball Chain 4 5 T39 FSB_DEFERB 22 AN28 DDR_A_CK_1 6 R44 FSB RSB 0 23 AR33 DDR_A_CKB_0 7 041 FSB_DRDYB 24 AM28 DDR_A_CKB_1 8 42 FSB_DBSYB 25 BD29 DDR A MA 6 9 R41 FSB RSB 2 26 BB31 DDR A MA 1 10 N28 FSB DINVB 2 27 BB28 DDR A MA 5 11 141 FSB DINVB 0 28 BC28 DDR A MA 8 12 W44 FSB_BREQOB 29 AY27 DDR_A_MA_7 13 044 FSB_ADSB 30 AY24 DDR_A_CKE_0 31 BB25 DDR A CKE 1 32 AV21 DDR A DQSB 3 Table 36 XOR Chain 4 33 AP21 DDR A DM 3 le 34 AY15 DDR A DQSB 2 35 BC14 DDR_A_DM_2 ANI RSVD 36 AY11 DDR A DQSB 1 37 BC10 DDR A DM 1 1 AK35 DB SER 38 BC6 DDR A DQSB 0 2 AL33 DDR A CB 0 36 EHE DM 0 3 AK34 DDR A CB 6 4 AK33 DDR A CB 4 5 AK39 DDR A CB 7 Table 37 Chain 5 6 AN35 DDR A CB 1 Bin 7 AL34 DDR_A_CB_5 Count Ball nee 8 AK38 DDR_A_CB_2 AM14 RSVD 9 1 DDR_A_ODT_1 10 BB39 DDR A CSB 1 1 44 DDR A DQSB 7 11 BD42 DDR A CSB 0 2 AB40 DDR_A_DM_7 12 BD37 DDR_A_
153. B D F Type 0 0 0 PCI Address Offset 2C 2Dh Default Value 0000 Access RWO Size 16 bits This value is used to identify the vendor of the subsystem Default Bit Access Value Description Subsystem Vendor ID SUBVID This field should be programmed during 15 0 RWO 0000h boot up to indicate the vendor of the system board After it has been written once it becomes read only 5 1 10 SI D Subsystem Identification B D F Type 0 0 0 PCI Address Offset 2E 2Fh Default Value 0000 Access RWO Size 16 bits This value is used to identify a particular subsystem Default Bit Access Value Description Subsystem ID SUBI D This field should be programmed during BIOS 1570 RWO eee initialization After it has been written once it becomes read only Datasheet 71 intel DRAM Controller Registers DO FO 5 1 11 CAPPTR Capabilities Pointer B D F Type 0 0 0 PCI Address Offset 34h Default Value EOh Access RO Size 8 bits The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list Default Pr Bit Access Value Description Capabilities Pointer CAPPTR Pointer to the offset of the first capability ID 7 0 RO EOh register block In this case the first capability is the product specific Capability Identifier CAPIDO 5 1 12 PXPEPBAR PCI Express Egress Port Base Address B D F Type 0 0 0 PCI Address Off
154. B9 PEG TXP 5 C42 FSB DB 51 B7 PEG TXP 7 C40 FSB DSTBPB 3 B4 PEG_TXN_9 C38 VSS B3 PEG TXP 9 C37 FSB DB 60 B2 VSS C36 FSB DB 58 B1 NC C34 VSS A45 TEST3 C32 VTT FSB 44 C30 VSS A43 VSS C28 FSB_SCOMPB A40 VSS C26 FSB_RCOMP A38 FSB_DB_49 C24 VSS_C24 A36 VSS C23 VSS C23 A34 VSS C22 VSS A32 VTT FSB C20 VSS A30 VTT_FSB C18 VCC C18 A28 FSB SWING C16 VCCR EXP A26 VSS C14 PEG RXN 1 A24 VSS A24 C12 VCCR EXP A23 VCC3 3 C10 PEG TXN 5 A22 VSS C9 VSS A20 VCCAPLL EXP C8 VCCR EXP A18 VSS C6 PEG TXP 8 A16 PEG RXP O C4 PEG TXN 8 A14 VSS C3 VSS A12 PEG TXN 3 C2 PEG RXN 10 A10 VSS C1 VSS A8 PEG_TXN_7 B45 NC A6 VSS B44 VSS A3 VSS B43 FSB_DB_18 A2 TEST2 B42 FSB_DB_55 pe B37 FSB_DINVB_3 B35 FSB_DB_62 Ballout and Package Information Datasheet Ballout and Package I nformation 12 2 Figure 15 intel Package Information The MCH is available in a 40 mm 1 57 in x 40 mm 1 57 in Flip Chip Ball Grid Array FC BGA package with an integrated heat spreader IHS and 1300 solder balls Figure 15 shows the package dimensions MCH Package Drawing IEW PKG Datasheet 313 n tel Ballout and Package Information 314 Datasheet Testability 13 13 1 Figure 16 Datasheet intel Testability In the MCH testability for Automated Test Equipment ATE board level testing has been imp
155. B_11 52 G44 FSB_DB_13 53 H42 FSB_DB_9 54 FSB DB 8 55 H45 FSB DB 12 56 L42 FSB DB 7 57 M45 FSB DB 5 58 M42 FSB DB 3 59 L44 FSB DB 6 60 J41 FSB_DB_10 61 P42 FSB_DB_0 62 N41 FSB_DB_1 63 N42 FSB_DB_4 64 N44 FSB_DB_2 Datasheet Testability Datasheet intel Table 33 XOR Chain 1 Table 33 XOR Chain 1 SE Pin Count Ball Chain 1 Count Ball Chain 1 35 v38 FSB AB 23 L22 XORTEST 36 AB34 FSB_AB_29 37 v39 FSB AB 24 t H33 38 40 FSB AB 33 K42 FSB_AB_15 39 V43 FSB AB 28 oy FSB_REQB_1 40 AA38 FSB_AB_35 4 K36 FSB_REQB 3 5 F43 FSB AB 3 6 M36 FSB AB 5 Table 34 XOR Chain 2 7 K38 FSB_AB_6 Pin 8 M38 FSB AB 4 Count Ball Chain 2 9 140 FSB 7 16 ICH SYNCB 10 C44 FSB REQB 0 11 M40 FSB ADSTBB 0 1 G34 FSB DSTBNB 1 12 N40 FSB_AB_9 2 H34 FSB_DSTBPB_1 13 L39 FSB REQB 2 3 W41 FSB RSB 1 14 N36 FSB AB 8 4 R42 FSB HITB 15 N39 FSB AB 11 5 W40 FSB_TRDYB 16 N38 FSB_AB_13 6 V42 FSB_HITMB 17 R35 FSB AB 16 7 M25 FSB DSTBNB 2 18 N34 FSB AB 12 8 N25 FSB DSTBPB 2 19 R39 FSB AB 14 9 K43 FSB DSTBNB 0 20 R36 FSB AB 10 10 J44 FSB_DSTBPB_0 21 T34 FSB_AB_19 11 T45 FSB_LOCKB 22 P43 FSB AB 21 12 042 FSB_BNRB 23 T40 FSB_AB_17 13 H38 FSB_BPRIB 24 W34 FSB AB 25 14 D35 FSB CPURSTB 25 W36 FS
156. Bit Access Value Description 0000000 63 28 RO 00h Reserved 27 20 RO 00h Bus Number BUSN 19 15 RO 00001b Device Number DEVN Target for this link is PCI Express port Devicel 14 12 RO 000b Function Number FUNN 11 0 RO 000h Reserved Datasheet 143 DRAM Controller Registers DO FO 5 3 6 EPLE3D EP Link Entry 3 Description B D F Type 0 0 0 PXPEPBAR Address Offset 70 73h Default Value 03000002 Access RO RWO Size 32 bits This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element Default Bit Access Value Description Target Port Number TPN Specifies the port number associated with the 31 24 RO 03h element targeted by this link entry PCI Express The target port number is with respect to the component that contains this element as specified by the target component ID Target Component I D TCI D Identifies the physical or logical component that is targeted by this link entry A value of 0 is reserved Component IDs start at 1 This value is a mirror of the value in the Component ID field of all elements 23 16 RWO 00h in this component BI OS Requirement Must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS 15 2 RO 0000h Reserved Link Type LTYP Indicates that the link points to configuration space of the 1 RO 1b integrate
157. C EXP 1 25 V PCI Express and DMI Power VCC DDR 1 8V DDR2 System Memory Power VCC CKDDR 1 8V DDR2 System Clock Memory Power VCC3 3 3 3 V 3 3 V CMOS Power VCCAPLL EXP 1 25 V Primary PCI Express PLL Analog Power VCCAPLL EXP2 1 25 V Secondary PCI Express PLL Analog Power VCCA hplL 1 25 V Host PLL Analog Power VCCA mpl 1 25 V System Memory PLL Analog Power VCCABG EXP 3 3 V PCI Express Analog Power VCC CL 1 25 V Controller Link Aux Power VSS Ov Ground 55 Datasheet m e System Address Map n tel 3 System Address Map The supports 64 GB 36 bit of host address space and 64 KB 3 of addressable space There is a programmable memory address space under the 1 MB region which is divided into regions which can be individually controlled with programmable attributes such as Disable Read Write Write Only or Read Only Attribute programming is described in the Register Description section This section focuses on how the memory space is partitioned and what the separate memory regions are used for O address space has simpler mapping and is explained near the end of this section The MCH supports PCI Express upper pre fetchable base limit registers This allows the PCI Express unit to claim accesses above 36 bit complying with the PCI Express Specification Addressing of greater than 8 GB is allowed on either the DMI Interface or PCI Express interface The MCH supports a maximum of 8 GB of DRAM No DRAM memory wil
158. CI CSR register and changes to this bit may be configured by the H PCI CSR register to generate 2 RW Ob ME MSI MEM 0 HECI is blocked from generating MSI to the host processor Note that this bit does not block HECI accesses to ME UMA i e writes or reads to the host and ME circular buffers through the read window and write window registers still cause ME backbone transactions to ME UMA 10 RW Ob Memory Space Enable MSE Controls access to the HECI host controller s memory mapped register space 0 RO Ob Reserved 194 Datasheet Intel Manageability Engine Subsystem PCI D3 FO F3 7 1 3 STS Device Status B D F Type Address Offset Default Value Access Size 0 6 7 0010h RO 16 bits ntel Bit Default Access Value 15 5 RO Oh Reserved RO 1b Capabilities List CL Indicates the presence of a capabilities list hardwired to 1 RO Ob Interrupt Status 1S Indicates the interrupt status of the device 1 Asserted 2 0 7 1 4 RO 000b Reserved RI D Revision ID B D F Type Address Offset Default Value Access Size 0 3 0 PCI 8h see table below RO 8 bits Bit Default Access Value 7 0 RO See Description of this register Revision I D RI D This field indicates stepping of the HECI host controller Refer to the Intel 3200 and 3210
159. CI Express 1 1 spec 14 6 RO 000h Reserved 5 RO Ob Extended Tag Field Supported ETFS Hardwired to indicate support for 5 bit Tags as a Requestor Phantom Functions Supported PFS Not Applicable or Implemented 4 3 RO 00b Hardwired to 0 2 0 RO 000b Max Payload Size MPS Hardwired to indicate 128B max supported payload for Transaction Layer Packets TLP Datasheet 171 Host Primary PCI Express Bridge Registers D1 FO DCTL Device Control B D F Type Address Offset Default Value Access Size 0 1 0 PCI 8 9 0000h RW RO 16 bits This register provides control for PCI Express device specific capabilities The error reporting enable bits are in reference to errors detected by this device not error messages received across the link The reporting of error messages ERR CORR ERR NONFATAL ERR FATAL received by Root Port is controlled exclusively by Root Port Command Register Bit Access Default Value Description 15 8 7 5 RO RW Oh 000b Reserved Max Payload Size MPS 000 128B max supported payload for Transaction Layer Packets TLP As a receiver the Device must handle TLPs as large as the set value as transmitter the Device must not generate TLPs exceeding the set value All other encodings are reserved Hardware will actually ignore this field It is writeable only to support compliance testing RO Ob Reserved R
160. Complements ALLES SSTL 1 8 p 29 Signal Description intel 2 2 2 System Memory Channel Interface Signals Signal Name Type Description B DDR CK SDRAM Differential Clocks SSTL 1 8 DDR2 Three per DIMM DDR B CKB SDRAM Inverted Differential Clocks SSTL 1 8 DDR2 Three per DIMM DDR B CSB 3 0 DDR2 Device Rank 3 2 1 and O Chip Select SSTL 1 8 DDR2 Clock Enable DDR B CKE 3 0 il 3 0 SSTL 1 8 1 per Device Rank 2 DDR B ODT 3 0 DDR2 Device Rank 3 2 1 and 0 On Die SSTL 1 8 Termination DDR B MA 14 0 SSTL 1 8 DDR2 Address Signals 14 0 DDR B BS 2 0 DDR2 Bank Select d dE SSTL 1 8 DDR_B_RASB SSTL 1 8 DDR2 Row Address Select signal DDR B CASB SSTL 1 8 DDR2 Column Address Select signal DDR_B_WEB d DDR2 Write Enable signal SSTL 1 8 8 DDR_B_DQ 63 0 V9 DDR2 Data Lines R SSTL 1 8 DDR_B_CB 7 0 VO ECC Check Byte wie a SSTL 1 8 yt DDR_B_DM 7 0 2 DDR2 Data Mask SSTL 1 8 DDR_B_DQS 8 0 DDR2 Data Strobes S s SSTL 1 8 DDR B DQSB 8 0 Io DDR2 Data Strobe Complements al SSTL 1 8 R Datasheet Signal Description 2 2 3 2 3 Datasheet System Memory Miscellaneous Signals Signal Name Type Description 1 0 DDR_RCOMPXPD A System Memory Pull down RCOMP 1 0 DDR_RCOMPXPU A System Memory Pull up RCOMP 1 0 DDR_RCOMPYPD A System Memor
161. D Deed 157 6 15 MBASE1 Memory Base Address sss 158 6 16 MLIMIT1 Memory Limit Address sss 159 6 17 PMBASE1 Prefetchable Memory Base Address 160 6 18 PMLIMIT1 Prefetchable Memory Limit Address sss 161 6 19 PMBASEU1 Prefetchable Memory Base Address 162 6 20 PMLIMITU1 Prefetchable Memory Limit Address Upper 163 6 21 CAPPTR1 Capabilities Pointer 21 6 163 6 22 INTRLINE1 Interrupt e eminens 164 6 23 INTRPINI Interrupt iere rrr otn Pee tr er ete khe oxi pibe bere E Ene et 164 6 24 BCTRL1 Bridge Control ese irrien en ideen E sene memes sess 164 6 25 PM CAPID1 Power Management 166 6 26 PM CS1 Power Management Control Status 167 6 27 SS CAPID Subsystem ID and Vendor ID Capabilities 168 6 28 SS Subsystem ID and Subsystem Vendor 10 168 6 29 MSI CAPID Message Signaled Interrupts Capability 10 169 6 30 MC Message
162. D31 VCC AA28 VCC C18 C18 CL AD29 VCC AA27 VCC CKDDR BE44 VCC_CL AC31 VCC AA25 VCC_CKDDR BE43 VCC_CL AC29 VCC AA23 VCC_CKDDR BD44 VCC_CL AB31 VCC AA21 VCC CKDDR BD43 CL AB29 VCC AA19 VCC CKDDR BC45 VCC CL AA31 VCC AA18 VCC CKDDR BC44 VCC_CL AA29 VCC AA17 VCC CL VCC CL Y29 VCC Y28 VCC CL AM30 VCC CL W29 VCC Y26 VCC_CL AM23 VCC_CL V29 Datasheet Ballout and Package I nformation Datasheet intel Table 28 MCH Table 28 MCH Table 28 MCH Ballout Sorted By Name v Ballout Sorted By Name Ballout Sorted Name Signal Name Ball Signal Name Ball Signal Name Ball VCC DDR BE40 VCC_EXP T3 VSS BE26 VCC DDR BE36 VCC EXT PLL AB13 VSS BE23 VCC DDR BE32 VCC N15 N15 VSS BE18 VCC DDR BE28 VCC3 3 A23 VSS BE14 VCC DDR BE24 VCC3 3 G16 G16 VSS BE10 VCC_DDR BE22 VCC3 3 L16 L16 VSS BE6 VCC_DDR BC38 VCCA_EXP D20 VSS BE3 VCC DDR BC34 VCCA EXP2 AU5 VSS BD2 VCC DDR BC30 VCCA HPL D26 VSS BC43 VCC DDR BC26 VCCA HPL D25 VSS BC16 VCC DDR BC23 VCCA MPL B27 VSS BC12 VCC DDR BC20 VCCAPLL EXP A20 VSS BC8 VCC DDR AY45 VCCAPLL EXP2 AR10 VSS BC3 VCC DDR AY23 VCCAUX U29 VSS 1 VCC_E25 E25 VCCAUX T31 VSS BB2 VCC EXP AD11 VCCAUX R30 VSS AY36 VCC EXP AD10 VCCAUX R28 VSS AY33 VCC EXP AD8 VCCAUX R27 vss AY10 VCC_EXP AD7 VCCAUX R25 vss AW40 VCC_EXP AB11 VCCAUX R24 VSS AW35 VCC EXP AB10 VCCAUX R23 V
163. DB FFFFh eene 45 3 3 3 FSB Interrupt Memory Space FEEO 0000 FEEF 45 3 3 4 High BIOS isti DH 45 3 4 Main Memory Address Space 4 GB to 46 3 4 1 Memory Re claim 11 mmm eene 47 3 4 2 Memory 47 3 5 PCI Express Configuration Address Space 47 3 6 PCI Express Address 5 1 1 esee nemen 48 3 7 System Management Mode 5 1 702 2 0 2 2 2 2 40404 4 4 4141444 4 4 nnn 49 3 7 1 SMM Space Definition 00011 tees meme 49 3 7 2 SMM Space Restrictions iced eder gerer edere dire Ru PE ede 50 3 7 3 SMM Space 00 emen enn 50 3 7 4 SMM Control Combinations secorrir re anden mmm meme nnn 51 3 7 5 SMM Space Decode and Transaction Handling 51 3 7 6 Processor WB Transaction to an Enabled SMM Address 51 Datasheet 3 ntel 3 7 7 SMM Access Through 01 A eres 51 3 8 Memory Shadowilhg uiro trek ter pase 52 3 9 Address Spaces scott e e De v
164. DM 50 Vss DDR RCOM DDR RCOM PEG2 PEG2_TXN_ 10 21 3 2 SB 0 PVOL PVOH 13 Note 4 14 Note 4 DDR_B_DQ DDR_B_DQ DQ VCCAPLL E PEG2 vss 581 58 vss vss vss 13 Note 4 VSS 12 Note 4 DDR_B_DQ_ PEG2_RXN_ PEG2_RXP PEG2_TXP_ PEG2_TXN_ PEG2_TXP PEG2_TXN 15 vss RSVD 15 Note 47 15 Note 4 vss 15 Note 4 15 Note 4 11 Note 4 VCCR EXP 12 Note 4 DDR_B_DQ EXP2_COMP EXP2 COMP PEG2 TXP ag RSVD Baye RSVD 1 Note 4 O Note 4 ven yaa 11 Note 4 vas 10 Note 4 PEG2_TXP_ PEG2_TXN RSV 9 Note 47 10 Note 4 yes PEG2 PEG2_RXN PEG2 RXN PEG2_RXP_ PEG2_TXN PEG2 TXP EL PRO use 13 Note 4 13 Note 4 us 14 Note 4 14 Note 4 9 Note ay Wes 8 Note 47 PEG2_RXN_ PEG2_RXP PEG2_TXP PEG2_TXN CL DATA BEGAN eS vss vss vss vss vss _ a PEG2_TXN_ ves PEG2_TXP_ 7 Note 4 6 Note 4j PEG2 RXN PEG2 PEG2_RXN PEG2 PEG2_RXN PEG2_TXP_ PEG2_TXN cr cL 9 Note 4 vss 10 Note 4 10 Note 4 vss 11 Note 4 11 Note 4 5 Note 47 6 Note 4y vas PEG2_RXP PEG2_TXN PEG2 TXP vec CL_VREF vss MOREM CLLRSTB vss vss vss vss Pear vss NOU ay PEG2_TXP PEG2_TXN 3 Note 4y VCCR EXP 4 Note 47 EXP2_CLKIN 2 PEG2_RXN_ PEG2_RXP PEG2_RXP_ PEG2_RXN_ PEG2_TXN PEG2 TXP VCCR EXP P 6 Note 47 vss 7 Note 4j 7 Note 4
165. DQ_35 AY22 DDR B MA 0 AWA VSS AT39 VSS AY21 DDR A DQ 25 AW2 VSS AW2 AT38 DDR B DQ 34 AY19 DDR B MA 7 AV45 vss AT36 DDR_A_CKB_5 AY18 DDR_B_MA_12 AV43 vss AT35 DDR_A_CK_5 AY16 DDR B DQ 16 AV42 DDR_A_DQ_32 AT34 DDR_A_CK_2 AY15 DDR A DQSB 2 AV40 DDR_B_DQ_39 AT33 DDR_A_CK_0 AY13 DDR_B_DQ_9 AV39 DDR_B_DQ_38 AT31 DDR_A_CKB_3 AY12 DDR_B_DQ 8 AV38 DDR_B_DQSB 4 AT30 VSS AY11 DDR A DQSB 1 AV36 DDR B DQ 44 AT28 VSS AY10 VSS AV35 DDR_A_CKB_2 AT27 DDR B DQ 26 AY8 DDR B DM O AV34 VSS AT25 DDR B DQ 30 AY7 DDR B DQ 1 AV33 DDR_B_CK_2 AT24 VSS AY6 DDR_RCOMPXPD AV31 DDR_A_CK_3 AT23 VSS AY5 DDR_RCOMPXPU AV30 DDR B CKB 0 AT22 DDR A DQ 27 AY3 VSS AY3 AV28 VSS AT21 DDR A DQS 3 AY1 VSS AY1 AV27 DDR B DQ 27 AT19 DDR B DQ 19 AW44 DDR_A_ODT_3 AV25 DDR B DQ 25 AT18 DDR B DQ 22 AW42 DDR A DQ 36 AV24 VSS AT16 VSS AWAO VSS AV23 VSS AT15 DDR B DQ 10 AW39 DDR B DQS 4 AV22 VSS AT13 DDR B DM 1 AW38 DDR B DQ 33 AV21 DDR A DQSB 3 AT12 DDR B DQ 3 AW36 DDR B DQ 37 AV19 DDR A DQ 28 AT11 DDR B DQ 2 AW35 VSS AV18 VSS AT10 DDR B DQSB 0 AW34 DDR_B_CK_5 AV16 DDR_B_DQ_17 AT8 VSS AW33 DDR_B_CKB_2 AV15 DDR_B_DQ_11 AT7 DDR_RCOMPVOL Datasheet Ballout and Package I nformation Datasheet intel Table 29 MCH Table 29 MCH Table 29 MCH Ballout Sorted By Ball Ballout Sorted By Ball Ballout Sorted By Ball Ball Signal Name Ball Signal Name Ball Signal
166. Default Value 00h Access RW V RO V Size 8 bits This implements the KT Interrupt Enable register Host access to this address depends on the state of the DLAB bit KTLCR 7 It must be O to access this register The bits enable specific events to interrupt the Host See bit specific definition Note Reset Host System Reset or D3 gt DO transition Bit Access Berat Description Value 7 4 RO V Oh Reserved 3 RW V Ob MSR 1 ER2 When set this bit enables bits in Modem Status register to cause an interrupt to host LSR I ER1 When set this bit enables bits in Receiver Line Status Register to 2 RW V Ob cause an Interrupt to Host THR 1 When set this bit enables interrupt to be sent to Host when the 1 RW V Ob tranmit Holding register is empty DR I ERO When set Received Data Ready or Receive FIFO Timeout 0 RW V Ob interrupts are enabled to be sent to Host 7 2 5 KTDLMR KT Divisor Latch MSB B D F Type 0 3 3 KT MM IO Address Offset 1h Default Value 00h Access RW V Size 8 bits Host can Read Write to this register only when the DLAB bit KTLCR 7 is 1 When this bit is 0 Host accesses the KTIER This is the standard Serial interface s Divisor Latch register s MSB This register is only for software compatibility and does not affect performance of the hardware Note Reset Host System Reset or D3 gt D0 transition Bit Access BOFMHE Description Value 7 0 RW V 00h Divisor Latch MSB DLM Implements
167. Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to Ob 20 RO Ob Data Link Layer Link Active Reporting Capable DLLLARC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob 19 RO Ob Surprise Down Error Reporting Capable SDERC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of detecting and reporting a Surprise Down error condition For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob 18 RO Ob Clock Power Management CPM A value of 1b in this bit indicates that the component tolerates the removal of any reference clock s when the link is in the L1 and L2 3 Ready link states A value of Ob indicates the component does not have this capability and that reference clock s must not be removed in these link states This capability is applicable only in form factors that support clock request CLKREQ capability For a multi function device each function indicates its capability independently Power Management configuration software must only permit reference clock removal if all functions of the multif
168. E message can be received via the PCI Express port from an external Intel device and will be subsequently forwarded to the ICH via Assert_GPE and Deassert GPE messages on DMI 250 Datasheet m Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 47 VCECH Virtual Channel Enhanced Capability Header B D F Type 0 6 0 MMR Address Offset 100 103h Default Value 14010002 Access RO Size 32 bits This register indicates PCI Express device Virtual Channel capabilities Extended capability structures for PCI Express devices are located in PCI Express extended configuration space and have different field definitions than standard PCI capability structures Bit Access Detault Description Value Pointer to Next Capability PNC The Link Declaration Capability is the next 31 20 RO 140h A E in the PCI Express extended capabilities list 19 16 RO 1h PCI Express Virtual Channel Capability Version PCI EVCCV Hardwired to 1 to indicate compliances with the 1 1 version of the Express specification 15 0 RO 0002h Extended Capability ID ECI D Value of 0002h identifies this linked list item capability structure as being for Express Virtual Channel registers 8 48 PVCCAP1 Port VC Capability Register 1 B D F Type 0 6 0 MMR Address Offset 104 107h Default Value 00000000h Access RO Size 32 bits This register d
169. E and IOLIMIT registers 2 RW Ob 0 All addresses defined by the IOBASE and IOLIMIT for processor 1 0 transactions will be mapped to PCI Express 1 will not forward to PCI Express any 1 0 transactions addressing the last 768 bytes in each 1 KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers Datasheet 231 intel Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only Bit Access Default Description Value SERR Enable SERREN 0 No forwarding of error messages from secondary side to primary side that 1 RW Ob could result in an SERR 1 ERR_COR ERR_NONFATAL and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register Parity Error Response Enable PEREN Controls whether or not the Master Data Parity Error bit in the Secondary Status register is set when the MCH 0 RW Ob receives across the link upstream a Read Data Completion Poisoned Transaction Layer Packet 0 Master Data Parity Error bit in Secondary Status register can NOT be set 1 Master Data Parity Error bit in Secondary Status register CAN be set 8 25 PM CAPID1 Power Management Capabilities B D F Type 0 6 0 PCI Address Offset 80 838 Default Value C8039001h Access RO Size 32 bits Default Bit Access Value Description PME Support PMES This field indicates the po
170. Express Bridge Registers D1 FO n tel 6 53 VCORSTS VCO Resource Status B D F Type 0 1 0 MMR Address Offset 11A 11Bh Default Value 0002 Access RO Size 16 bits This register reports the Virtual Channel specific status Default c iu Bit Access Value Description 15 2 RO 0000h Reserved VCO Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling 1 RO lb This bit indicates the status of the process of Flow Control initialization It is set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL Down state It is cleared when the link successfully exits the FC INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Ob Reserved 6 54 RCLDECH Root Complex Link Declaration Enhanced B D F Type 0 1 0 MMR Address Offset 140 143h Default Value 00010005 Access RO Size 32 bits This capability declares links from this element PCI Express to other elements of the root complex component to which it belongs See PCI Express specification for link topology declaration requirements Bit Access Bera Description Value Pointer to Next Capability PNC This is the last capability in the PCI Express 31 20 RO pou extended cap
171. FSB_DEFERB R8 VSS V25 VSS T38 FSB_AB_20 R7 TXP 0 V24 VCC T36 FSB_AB_18 R6 DMI TXN 0 V23 VSS T35 VSS R5 DMI_RXN_2 V22 VCC T34 FSB_AB_19 R4 VSS V21 VSS T33 RSVD R2 DMI_TXP_2 V20 VCC T32 VSS P45 VSS V19 VSS T31 VCCAUX P43 FSB_AB 21 V18 VCC 15 VCCR_EXP P42 FSB DB 0 V17 VCC T14 VCCR EXP P32 VSS V15 VCCR EXP T13 VSS P30 HPL CLKINN V14 VCCR EXP T12 RSVD P28 HPL CLKINP V13 VSS T11 VSS P27 VSS V12 RSVD T10 EXP COMPO P25 VSS 11 DMI_TXN_3 T8 DMI_RXN_1 P24 VSS V10 DMI TXP 3 T7 1 P23 VSS V8 VSS T6 VSS P22 VSS V7 3 T4 VCC_EXP P21 RSVD V6 DMI_RXN_3 T3 VCC_EXP P19 RSVD_P19 v4 VCC_EXP DMI_TXN_2 P18 VSS VCC_EXP R44 FSB RSB 0 P16 ICH SYNCB V1 VCC EXP R42 FSB HITB P14 VSS U44 FSB_ADSB R41 FSB RSB 2 P4 RXP 2 U42 FSB BNRB RAO VSS P3 DMI TXN 1 U41 FSB_DRDYB R39 FSB AB 14 P1 VSS U29 VCCAUX R38 VSS N44 FSB DB 2 U28 VCC R36 FSB_AB_10 N42 FSB DB 4 U27 VCC R35 FSB_AB_16 N41 FSB DB 1 U26 VCC R34 VSS N40 FSB_AB_9 U25 VCC R33 RSVD N39 FSB_AB_11 U24 VCC R30 VCCAUX N38 FSB_AB_13 U23 VCC R28 VCCAUX N36 FSB AB 8 U22 VCC R27 VCCAUX N35 VSS U21 VCC R25 VCCAUX N34 FSB AB 12 U20 VCC R24 VCCAUX N33 FSB DB 28 U19 VCC R23 VCCAUX N31 FSB_DB_30 U18 VCC R22 RSVD N30 FSB_DB_37 U17 VCC R21 VSS N28 FSB DINVB 2 U5 VCC_EXP R19 RSVD N27 VSS U4 VCC_EXP R18 VCC N25 FSB DSTBPB 2 309 intel 310 Table 29 MCH Ballout Sorted By Ball Table 29 MCH Ballout Sorted By Ball
172. G2 RSVD L19 PEG2 RXN 8 7 AEG PEG2 TXP 5 9 AH4 RSVD K22 PEG2 RXN 9 7 AH13 PEG2 TXP 6 7 AJ2 RSVD K21 PEG2 RXN 10 7 AH10 PEG2 TXP 7 AK4 RSVD H21 PEG2_RXN_11 7 AH6 PEG2 TXP 8 9 AL2 RSVD G22 PEG2 RXN 12 7 PEG2 TXP 9 7 AMA RSVD F19 PEG2 RXN 13 47 AL10 PEG2 TXP 10 7 2 RSVD B19 PEG2 RXN 14 7 417 2 TXP 11 7 RSVD GI15 G15 PEG2 RXN 15 7 1 PEG2 TXP 12 97 2 RSVD H15 H15 PEG2 RXP 07 wi2 PEG2 TXP 13 7 AT4 RSVD 19 M19 PEG2 1 4 AA10 PEG2 TXP 1447 AU2 RSVD P19 P19 PEG2 RXP 2 7 AAG PEG2 15 47 7 621 PEG2 3 AC13 PWROK AM19 TESTO BE45 PEG2 4 11 RSTINB AM18 5 1 1 PEG2 5 177 AC6 RSVD L18 TEST2 A2 PEG2 6 7 AE13 RSVD BC2 TEST3 A45 PEG2 7 AE10 RSVD AP34 VCC AH26 PEG2 8 7 AE7 RSVD AP12 VCC AH24 PEG2 9 7 AG12 RSVD AN31 VCC AH22 PEG2 10 7 11 RSVD AN30 VCC AH20 PEG2 1147 AH7 RSVD AN25 VCC AH19 PEG2_RXP_12 12 RSVD AN13 VCC AH18 PEG2 13 7 11 RSVD AN12 VCC 17 PEG2 RXP 1447 AL6 RSVD AM32 VCC AG27 PEG2 15 7 10 RSVD AM25 VCC AG25 PEG2 TXN 0 AB1 RSVD AM14 VCC AG23 PEG2 1 ACA RSVD AL28 VCC AG21 PEG2_TXN_2 9 AD3 RSVD AH28 VCC AG19 PEG2 AE5 RSVD AG32 VCC AG18 PEG2 TXN 4 AF1 RSVD AG28 VCC AG17 PEG2_TXN_5 7 AG5 RSVD AD32 VCC AG15 PEG2 TXN 6 97 AH3 RSVD W32 VCC AF28 PEG2 TXN 7 7 Aj5 RSVD V32 VCC AF26 PEG2 TXN 8
173. I Express 88 53 54 System Address Map Datasheet m e MCH Register Description n tel 4 Datasheet MCH Register Description The MCH contains two sets of software accessible registers accessed via the Host processor 1 0 address space Control registers and internal configuration registers Control registers I O mapped into the processor 1 0 space which control access to PCI and PCI Express configuration space see Chapter 6 nternal configuration registers residing within the MCH are partitioned into two logical device register sets logical since they reside within a single physical device The first register set is dedicated to Host Bridge functionality i e DRAM configuration other chipset operating parameters and optional features The second register block is dedicated to Host to PCI Express Bridge functions controls PCI Express interface configurations and operating parameters The MCH internal registers 1 O Mapped Configuration and PCI Express Extended Configuration registers are accessible by the processor The registers that reside within the lower 256 bytes of each device can be accessed as Byte Word 16 bit or DWord 32 bit quantities with the exception of CONFIG ADDRESS which can only be accessed as a DWord All multi byte numeric fields use little endian ordering i e lower addresses contain the least significant parts of the field Registers that reside in bytes 256 throu
174. I from the device 15 0 RW 0000h When the device must generate an interrupt request it writes a 32 bit value to the memory address specified in the MA register The upper 16 bits are always set to 0 The lower 16 bits are supplied by this register 8 33 PE CAPL PCI Express Capability List B D F Type 0 6 0 PCI Address Offset 0 1 Default Value 0010h Access RO Size 16 bits This register enumerates the PCI Express capability structure Default c Bit Access Value Description Pointer to Next Capability PNC This value terminates the capabilities list 15 8 RO 00h The Virtual Channel capability and any other PCI Express specific capabilities that are reported via this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space 7 0 RO 10h Capability ID CID Identifies this linked list item capability structure as being for PCI Express registers 236 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 34 PE CAP PCI Express Capabilities B D F Type 0 6 0 PCI Address Offset A2 A3h Default Value 0142 Access RO RWO Size 16 bits This register indicates PCI Express device capabilities Bit Access Derauit Description Value 15 14 RO 00b Reserved 13 9 RO 00h Interrupt Message Number IMN Not Applicable or Implemented Hardwired to 0 Slot Implemented SI
175. IO writes reads peer writes reads and MSIs will all be treated as illegal cycles 2 RW Ob Writes are forwarded to memory address C0000h with byte enables de asserted Reads will be forwarded to memory address 0000 and will return Unsupported Request status or Master abort in its completion packet 1 This device is allowed to issue requests to its primary bus Completions for previously issued memory read requests on the primary bus will be issued when the data is available This bit does not affect forwarding of Completions from the primary interface to the secondary interface Memory Access Enable MAE 1 RW Ob 0 All of device 6 s memory space is disabled 1 Enable the Memory and Pre fetchable memory address ranges defined in the MBASE1 MLIMIT1 PMBASE1 and PMLIMIT1 registers 10 Access Enable I OAE 0 RW Ob 0 All of device 6 s I O space is disabled 1 Enable the I O address range defined in the 5 1 and IOLIMIT1 registers Datasheet 217 Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 4 PCI STS1 PCI Status B D F Type 0 6 0 PCI Address Offset 6 7h Default Value 0010h Access RO RWC Size 16 bits This register reports the occurrence of error conditions associated with primary side of the virtual Host PCI Express bridge embedded within the MCH Bit Access Default Description Value Detected Parity Err
176. IU Software semaphore bit After a full MCH RESET a read to this bit returns a O After the first read subsequent reads will return a 1 A write of a 1 to this bit will reset the next read value to 0 Writing a 0 to this bit has no effect Software can poll this bit until it reads a 0 and will then own the usage of the thermal sensor 0 RS WC Ob This bit has no other effect on the hardware and is only used as a semaphore among various independent software threads that may need to use the thermal sensor Software that reads this register but does not intend to claim exclusive access of the thermal sensor must write a one to this bit if it reads a 0 in order to allow other software threads to claim it See also THERM3 bit 7 and IUB which are independent additional semaphore bits 5 2 45 TSC2 Thermal Sensor Control 2 B D F Type 0 0 0 MCHBAR Address Offset CD9h Default Value 00h Access RO RW L Size 8 bits This register controls the operation of the thermal sensor All bits in this register are reset to their defaults by MPWROK Bit Access Default Description Value 7 4 RO Oh Reserved 132 Datasheet m DRAM Controller Registers DO FO n tel Bit Access Default Description Value Thermometer Mode Enable and Rate TE If analog thermal sensor mode is not enabled by setting these bits to 0000b these bits enable the thermometer mode functions and set the Thermometer controller rate When the Th
177. MA_10 3 AD42 DDR A DQSB 6 13 BB43 DDR A ODT 0 4 44 DDR_A_DM_6 14 BC36 DDR A MA 0 5 AL36 DDR A DQSB 8 15 BA27 DDR A MA 9 6 AM42 DDR_A_DQSB_5 16 BB30 DDR A MA 2 7 AN44 DDR_A_DM_5 17 BB29 DDR A MA 3 8 AT42 DDR A DQSB 4 18 BA29 DDR A MA 4 9 AU44 DDR A DM 4 19 AV35 DDR A CKB 2 10 BA42 DDR A MA 13 20 AT34 DDR A CK 2 11 BB41 DDR_A_CASB 21 AT33 DDR_A_CK_0 12 BD39 DDR_A_WEB 320 Datasheet Testability Datasheet intel Table 37 XOR Chain 5 Table 38 XOR Chain 6 Chain 5 2 Ball Chain 6 18 BB36 DDR A BS 1 22 AN41 DDR_A_DQ_40 14 BB38 DDR_A_RASB 23 AN42 DDR_A_DQ_41 15 BC37 DDR A BS 0 24 2 DDR_A_DQ_44 16 BA25 DDR_A_MA_14 25 AL41 DDR A DQ 47 17 BD27 DDR A MA 11 26 AP45 DDR_A_DQ_45 18 BB26 DDR A BS 2 27 AL42 DDR_A_DQ_43 19 BB27 DDR_A_MA_12 28 144 DDR_A_DQ_42 20 AK15 CL_DATA 29 AT43 DDR A DQS 4 21 AK14 CL_CLK 30 AUA3 DDR A DQ 33 31 041 DDR A 37 32 AV42 DDR A DQ 32 Table 38 XOR Chain 6 33 ARAT DDR A DQ 38 EG 34 40 DDR_A_DQ_39 35 44 DDR_A_DQ_34 pel BSELI 36 AW42 DDR_A_DQ_36 37 AR42 DDR_A_DQ_35 1 n DDR ALBUS 7 38 AT21 DDR A DQS 3 2 bi DBRZACBO SB 39 AY21 DDR A DQ 25 3 AAMI DDR A DO 62 40 AW19 DDR_A_DQ 29 4 42 DDR_A_DQ_56 aT ANGT DDR A 30 3 AES
178. MI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 5 1 24 LAC Legacy Access Control B D F Type 0 0 0 PCI Address Offset 97h Default Value 00 Access RW L RO Size 8 bits This 8 bit register controls a fixed DRAM hole from 15 16 MB Bit Access Default Description Value Hole Enable HEN This field enables a memory hole in DRAM space The DRAM that lies behind this space is not remapped 7 RW L Ob 0 No memory hole 1 Memory hole from 15 MB to 16 MB This bit is Intel TXT lockable 6 0 RO Os Reserved 84 Datasheet DRAM Controller Registers DO FO n tel 5 1 25 REMAPBASE Remap Base Address Register B D F Type 0 0 0 PCI Address Offset 98 99h Default Value O3FFh Access RO RW L Size 16 bits Default Bit Access Valla Description 15 10 RO 000000b Reserved Remap Base Address 35 26 REMAPBASE The value in this register defines the lower boundary of the Remap window The Remap window is inclusive of this address In the decoder A 25 0 of the Remap Base Address are assumed to be Os Thus the bottom of the defined memory range will be aligned 9 0 RW L 3FFh to a 64MB boundary When the value in this register is greater than the value programmed into the Remap Limit register the Remap window is disabled These bits are Intel TXT lockable or ME stolen Memory lockable 5 1 26 REMAPLI MI
179. N8 FSB DB 3 M42 DDR B MA 14 BC18 FSB AB 3 F43 FSB DB 4 N42 DDR B ODT O BD33 FSB AB 4 M38 FSB DB 5 M45 DDR B ODT 1 BB34 FSB AB 5 M36 FSB DB 6 L44 DDR B ODT 2 BB33 FSB AB 6 K38 FSB DB 7 L42 DDR B ODT 3 AY35 FSB AB 7 L40 FSB DB 8 143 DDR_B_RASB BD31 FSB_AB 8 N36 FSB_DB_9 H42 DDR_B_WEB AY31 FSB_AB 9 N40 FSB_DB_10 141 DDR RCOMPVOH _ AT6 FSB AB 10 R36 FSB DB 11 G42 DDR RCOMPVOL AT7 FSB AB 11 N39 FSB DB 12 H45 DDR RCOMPXPD 6 FSB AB 12 N34 FSB DB 13 G44 DDR RCOMPXPU AY5 FSB AB 13 N38 FSB DB 14 F41 DDR_RCOMPYPD BC42 FSB_AB_14 R39 FSB_DB_15 E42 DDR_RCOMPYPU BB42 FSB_AB_15 K42 FSB_DB_16 F38 DDR_VREF AV7 FSB_AB_16 R35 FSB_DB_17 F39 RSVD BB44 FSB_AB_17 T40 FSB_DB_18 B43 RSVD BD35 FSB_AB_18 T36 FSB_DB_19 L36 RSVD BC40 FSB_AB_19 T34 FSB_DB_20 G38 RSVD BA37 FSB_AB_20 T38 FSB_DB_21 K35 RSVD AN11 FSB AB 21 P43 FSB DB 22 G36 RSVD BB23 FSB AB 22 38 FSB DB 23 G35 DMI_RXN_O M4 FSB AB 23 V38 FSB_DB_24 K34 DMI_RXN_1 T8 FSB_AB_24 v39 FSB_DB_25 H33 DMI_RXN_2 R5 FSB_AB_25 W34 FSB_DB_26 F33 DMI_RXN_3 V6 FSB_AB_26 v35 FSB_DB_27 L34 DMI 0 5 FSB AB 27 33 FSB DB 28 N33 DMI RXP 1 T7 FSB AB 28 V43 FSB DB 29 L33 DMI 2 P4 FSB_AB_29 AB34 FSB_DB_30 N31 295 intel 296 Ballout and Package Information Table 28 MCH Table 28 MCH Table 28 MCH Ballout Sorted By Name v Ballout Sorted By Name Ba
180. O RO CR Size 8 bits This register provides status information of the data transfer to the Host Error indication etc are provided by the hardware HW firmware FW to the host via this register Note Reset Host system reset or D3 gt D0 transition Bit Access Derault Description Value 7 RO Ob RX FIFO Error RXFER This bit is cleared in non FIFO mode Bit is connected to the BI bit in FIFO mode 6 RO Ob Transmit Shift Register Empty TEMT This bit is connected by hardware to bit 5 THRE of this register Transmit Holding Register Empty THRE The bit is always set when the mode FIFO Non FIFO is changed by the Host This bit is active only when the THR operation is enabled by the FW This bit has acts differently in the different modes 5 RO Ob Non FIFO Mode This bit is cleared by hardware when the Host writes to the THR registers and set by hardware when the FW reads the THR register FIFO Mode This bit is set by hardware when the THR FIFO is empty and cleared by hardware when the THR FIFO is not empty This bit is reset on Host system reset or 03 gt 00 transition Break I nterrupt BI This bit is cleared by hardware when the LSR register is being read by the Host This bit is set by hardware in two cases 4 RO CR Ob FIFO Mode The FW sets the BI bit by setting the SBI bit in the KTRIVR register See KT AUX registers Non FIFO Mode the FW sets the BI bit by setting the BIA bit in the KTRxBR register see KT AUX registers
181. O V Oh KTTHR KT Transmit Holding 00h WO Oh KTDLLR KT Divisor Latch LSB 00h RW V 1h KTI ER KT Interrupt Enable 00h RW V RO V 1h KTDLMR KT Divisor Latch MSB 00h RW V 2h KTIIR KT Interrupt Identification Olh RO 2h KTFCR KT FIFO Control 00h WO 3h KTLCR KT Line Control 03h RW 4h KTMCR KT Modem Control 00h RO RW 5h KTLSR KT Line Status 00h RO RO CR 6h KTMSR KT Modem Status 00h RO RO CR 7h KTSCR KT Scratch 00h RW 7 2 1 KTRxBR KT Receive Buffer B D F Type 0 3 3 KT MM IO Address Offset Oh Default Value 00h Access RO V Size 8 bits This implements the KT Receiver Data register Host access to this address depends on the state of the DLAB bit KTLCR 7 It must be 0 to access the KTRxBR RxBR Host reads this register when FW provides it the receive data in non FIFO mode In FIFO mode host reads to this register translate into a read from ME memory RBR FIFO Note Reset Host System Reset or D3 gt D0 transition Bit Access Default Description Value 7 0 RO V 00h Receiver Buffer Register RBR Implements the Data register of the Serial Interface If the Host does read it reads from the Receive Data Buffer 204 Datasheet m e Intel Manageability Engine Subsystem PCI D3 FO F3 n tel 7 2 2 KTTHR KT Transmit Holding B D F Type 0 3 3 KT MM IO Address Offset Oh Default Value 00h Access WO Size 8 bits This implements the KT Transmit Data register Host access to this address
182. P Ob the address that caused the error and the error syndrome are also logged and they are locked until this bit is cleared This bit is cleared when it receives an indication that the processor has cleared the corresponding bit in the ERRSTS register Correctable Error Status CERRSTS This bit is set when a correctable single bit error occurs on a memory read data transfer When this bit is set the address that caused the error and the error syndrome are also logged and they 0 RO P Ob are locked to further single bit errors until this bit is cleared But a multiple bit error that occurs after this bit is set will over write the address error syndrome info This bit is cleared when it receives an indication that the processor has cleared the corresponding bit in the ERRSTS register 112 Datasheet m e DRAM Controller Registers DO FO n tel 5 2 16 COODTCTRL Channel 0 ODT Control B D F Type 0 0 0 MCHBAR Address Offset 29C 29Fh Default Value 00000000h Access RO RW Size 32 bits This register provides ODT controls Default Bit Access Description 31 12 RO 00000h Reserved DRAM ODT for Read Commands sdO cr odt duration rd Specifies the 11 8 RW Oh duration in MDCLKs to assert DRAM ODT for Read Commands The Async value should be used when the Dynamic Powerdown bit is set Else use the Sync value DRAM ODT for Write Commands sdO cr odt d
183. PCI to PCI bridge PCI Express port 7 4 RO Fh Device Identification Number DI D1 HW Identifier assigned to the device 6 virtual PCI to PCI bridge PCI Express port 3 0 RO 9h Device Identification Number DI D1 LB Identifier assigned to the i device 6 virtual PCI to PCI bridge PCI Express port 8 3 PCI CMD1 PCI Command B D F Type 0 6 0 PCI Address Offset 4 5h Default Value 0000h Access RO RW Size 16 bits Default Bit Access Value Description 15 11 RO 00h Reserved I Assertion Disable INTAAD 0 This device is permitted to generate INTA interrupt messages 1 This device is prevented from generating interrupt messages Any INTA 10 RW Ob interrupts already asserted must be de asserted when this bit is This bit only affects interrupts generated by the device PCI INTA from a PME event controlled by this command register It does not affect upstream MSIs upstream PCI INTA INTD assert and deassert messages Fast Back to Back Enable FB2B Not Applicable or Implemented Hardwired 9 RO Ob to 0 216 Datasheet m e Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel Bit Access Default Description Value SERR Message Enable SERRE1 This bit controls Device 6 SERR messaging The MCH communicates the SERR condition by sending a SERR message to the ICH This bit when set enables reporting of non fatal an
184. PI Revision 2 0 compatible power management Supports processor states CO C2 Supports System states SO S1 and S5 Supports processor Thermal Management 2 Package FC BGA 40 mm x 40 mm package size 1300 balls located in a non grid pattern Datasheet Introduction te j 1 Introduction The Intel 3200 and 3210 Chipsets are designed for use with the Dual Core Intel Xeon Processor 3000 Series and Quad Core Intel Xeon Processor 3200 Series in server platforms The chipset contains two components 3210 3100 MCH for the host bridge and 1 0 Controller Hub 9 ICH9 for the 1 subsystem The 9 is the ninth generation 1 0 Controller Hub and provides a multitude of I O related functions Figure 1 and Figure 2 show example system block diagrams for the Intel 3200 and 3210 Chipsets This document is the datasheet for the Intel 3200 and 3210 Memory Controller Hub MCH Topics covered include signal description system memory map PCI register description a description of the MCH interfaces and major functional units electrical characteristics ballout definitions and package characteristics Note Unless otherwise specified 9 refers to the Intel 828011B ICH9 and Intel 82801IR ICH9R I O Controller Hub 9 components Note The term 9 refers to the ICH9 and ICH9R components Note In this document all references to MCH apply to both 3200 MCH and 3210 MCH unless otherwi
185. PLTRST Datasheet 197 ntel Intel Manageability Engine Subsystem PCI D3 FO F3 7 1 11 CAP Capabilities Pointer B D F Type 0 3 0 PCI Address Offset 34h Default Value 50h Access RO Size 8 bits Default its Bit Access Value Description 7 0 RO 50h Capability Pointer CP Indicates the first capability pointer offset It points to the power management capability offset 7 1 12 I NTR I nterrupt Information B D F Type 0 3 0 PCI Address Offset 3C 3Dh Default Value 0100h Access RO RW Size 16 bits Default Pr Bit Access Value Description Interrupt Pin I PIN This field indicates the interrupt pin the host 15 8 RO 01h controller uses The value of O1h selects INTA interrupt pin Note As HECI is an internal device in the MCH the INTA pin is implemented as an INTA message to the ICH Interrupt Line ILI NE Software written value to indicate which interrupt line 7 0 RW 00h vector the interrupt is connected to No hardware action is taken on this register 7 1 13 MGNT Minimum Grant B D F Type 0 3 0 PCI Address Offset 3Eh Default Value 00h Access RO Size 8 bits Default er Bit Access Value Description 7 0 RO 00h Grant GNT Not implemented hardwired to 0 198 Datasheet m e Intel Manageability Engine Subsystem PCI D3 FO F3 n tel 7 1 14 MLAT Maximum Latency B D F Type
186. Port Base Address re td RO RW L 48 4Fh MCHBAR E Memory Mapped Register Range aaa RO RW L 54 57h DEVEN Device Enable 000023DBh RO RW L 60 67h PCIEXBAR ee Register Range Base 1 L 68 6Fh DMIBAR Register Range Base RO RW L 90h PAMO Programmable Attribute Map 0 00h RO RW L 91h PAM1 Programmable Attribute Map 1 00h RO RW L 92h PAM2 Programmable Attribute Map 2 00h RO RW L 93h PAM3 Programmable Attribute Map 3 00h RO RW L 94h PAMA Programmable Attribute Map 4 00h RO RW L 65 intel DRAM Controller Registers DO FO Table 8 DRAM Controller Register Address Map Address Register Default Offset Symbol Register Name Value Access 95h PAM5 Programmable Attribute Map 5 00h RO RW L 96h PAM6 Programmable Attribute Map 6 00h RO RW L 97h LAC Legacy Access Control 00h RW 2 98 99 REMAPBASE Remap Base Address Register 03FFh RO RW L 9A 9Bh REMAPLIMIT Remap Limit Address Register 0000h RO RW L RO RW L 9Dh SMRAM System Management RAM Control 02h RW RW L K 9Eh ESMRAMC Extended System Management RAM 38h RW L RWC Control RO 0 1 of Memory 0001h RO RW L A2 A3h TOUUD Top of Upper Usable Dram 0000h RW L A4 A7h BSM Base of Stolen Memory 00000000h RW L RO AC AFh TSEGMB TSEG Memory Base 00000000h RO RW L BO B1h TOLUD Top of Low Usable DRAM 0010h RW L RO C8 C9h ERRSTS Error Status 0000h RWC S RO CA CBh ERRCMD Error Command 0000h RW RO
187. Q_ DDR_A_CKB DDR B CK 34 77 35 E 39 VSS 55 0 VSS 4507 0 aa DDR_A_DQ DDR_A_DQ DDR B DQ DDR_B_DQ DDR B B DDR B CKB 45777 vss 74 5 55 VSS abo u RD VSS T DDR_A_DM DDR_A_DQ_ DDR_A_DQ_ DDR_B_DQ_ DDR_B_DQ_ DDR_B_DM DDR_A_CB_ DDR_B_DQ_ 25 41 40 47 46 55 5 1 NSS 43 Rove DDR_A_DQ DDR_A_DQ vss ss 5 RSVD DDR_A_DQ_ DDR DQ DO vss DDR 00 DDR_A_DQ Ves DDR_A_CB_ DDR_A_CB_ a2 43 47 46 58 SB 8 5 0 DDR B CB vss DDR B CB DDR DDR_A_CB_ vss DDR_A_CB_ DDR_A_CB_ DDR_A_CB_ vss 0 5 7 2 3 6 4 s DDR B CB DDR B CB vss 1 4 DDR B DDR DDR DQ DDR B DQ B vss E Sas vss vss vss vss DOL E vss VcC CL DDR B CB DDR B CB B CB DDR B CB DDR DDR B DM DDR B DQ B p E ss ES vss 8 vss B02 VCC CL DDR A DQ DDR DQ A vss rz DDR DDR_A_DQ_ DDR_A_DQ_ DDR_B_DQ_ DDR_B_DQ_ DDR_B_DQ DDR DQ DDR_B_DQ_ DDR_B_DQ 26 9 77 E 5407 56 Sr VSS 50 55 55 DDR A DQ DDR A B DQ DDR B DQ DDR B DM DDR B DQ vss at Sas vss vss 8885 RSVD VcC CL DDR A DQ DDR DQ DDR DDR A 00 DDR DQ DDR B DQ DDR DQ A Po vss Pe ue vss B DO vss sy vss VcC CL DDR A DQ DDR A 00 DDR A DM DDR DDR 8 00 DDR DQ vss a vss FSB_AB_34 FSB_AB_29 vss DOL vcc
188. R Ro CR LO Ra FELD CR 276 10 6 ClOCKING p PE PC 276 Electrical Characteristics a eee a ud A ee Ue ER Ya 279 11 1 Absolute Minimum and Maximum Ratings sss 279 11 2 Current Consumption inae rien reet tos siege cope gr e vidas 281 11 3 Signal Groups s 282 11 4 Buffer Supply DC Characteristics 285 11 4 1 1 0 Buffer Supply Voltages ce mem 285 11 4 2 General DC Characteristics sss 286 Ballout and Package 2 7 7 289 12 Ballout Information ire metere leg nui RU E E Ded 289 12 2 Package linformatiOn ctp tein the pix me ing Fer 313 Datasheet 9 10 13 Testability ed ed 315 13 1 XOR Test Mode 1 1 2 ee ee enne nnn 315 13 2 XOR Chain 3 311106 e eme eene ense ean nan 316 13 3 XOR 1 ee enda ena aaa aane ee 317 13 4 KOR CHAINS d E ortu ad Puro rc EE Dad wetness 318 Datasheet Figures 1 Intel 3210 Chipset System Diag
189. RA registers describes the page size of a pair of ranks Channel and rank map Ranko 1 208h 209h ChO Rank2 3 20Ah 20Bh Ch1 0 1 608h 609h Ch1 Rank2 3 60Ah 60Bh DRA 6 0 00 means cfgO DRA 6 0 01 means cfg1 DRA 6 0 09 means cfg9 and so on DRA 7 indicates whether it s an 8 bank config or not DRA 7 0 means 4 bank DRA 7 1 means 8 bank Table 10 DRAM Rank Attribute Register Programming i Page Config Tech DDRx Depth Width Row Col Bank Row Size Size 0 256Mb 2 32M 8 13 10 2 256 MB 8k 1 256Mb 2 16M 16 13 9 2 128 MB 4k 2 512Mb 2 64M 8 14 10 2 512 MB 8k 3 512Mb 2 32M 16 13 10 2 256 MB 8k 4 512Mb 3 64M 8 13 10 3 512 MB 8k 5 512Mb 3 32M 16 12 10 3 256 MB 8k 6 1 Gb 2 3 128M 8 14 10 3 1 8k 7 1 Gb 2 3 64M 16 13 10 3 512 MB 8k Default A Bit Access Value Description Channel 0 DRAM Rank 1 Attributes CODRA1 This register defines DRAM pagesize number of banks for rank1 for given channel 15 8 RW L 00h P pi See table in register description for programming This register is locked by ME stolen Memory lock Channel 0 DRAM 0 Attributes CODRAO This register defines DRAM page size number of banks for rankO for given channel 7 0 RW L 00h See table in register description for programming This register is locked by ME stolen Memory lock 104 Datasheet m e DRAM Controller Registers DO FO n tel
190. RLOG Channel 1 ECC Error Log 000000h RO P RO 69C 69Fh C1ODTCTRL Channel 1 ODT Control 00000000h RO RW A00 A01h EPCODRBO EP Channel O DRAM Rank 0000h RW RO Boundary Address 0 A02 A03h EPCODRB1 EP Channel O DRAM Rang 0000h RW RO Boundary Address 1 A04 A05h EPCODRB2 EP Channel O DRAM Rank 0000h RW RO Boundary Address 2 A06 A07h EPCODRB3 EF Canne DRAM Rank 0000h RW RO Boundary Address 3 A08 A09h EPCODRAO1 EP Cannes RAP 0000h RW Attribute AOA AOBh EPCODRA23 Channel O DRAM Rank 2 3 0000h RW Attribute A19 A1Ah EPDCYCTRKWRTPRE EPD CYCTRK WRT PRE 0000h RW RO A1C A1Fh EPDCYCTRKWRTACT EPD CYCTRK WRT ACT 00000000h RO RW A20 A21h EPDCYCTRKWRTWR EPD CYCTRK WRT WR 0000h RW RO A22 A23h EPDCYCTRKWRTREF EPD CYCTRK WRT REF 0000h RO RW A24 A26h EPDCYCTRKWRTRD EPD CYCTRK WRT READ 000000h RW A28 A2Ch EPDCKECONFIGREG EPD CKE related configuration 00E0000000 RW registers h A30 A33h EPDREFCONFIG EP DRAM Refresh Configuration 40000C30h RW RO RW L RW CD8h 5 1 Thermal Sensor Control 1 00h RS WC CD9h TSC2 Thermal Sensor Control 2 00h RO RW L CDAh TSS Thermal Sensor Status 00h RO Thermal Sensor Temperature RO RW CDC CDFh TSTTP Trip Point 00000000h RW L CE2h TCO Thermal Calibration Offset 00h RW L K RW L RW L RO CE4h THERM1 Thermal Hardware Protection 00h RW L K CEA CEBh TIS Thermal Interrupt Status 0000h RO RWC CF1 CF1h TSMICMD Thermal SMI Command 00h RO RW F14 F17h PMSTS Power Management Status 00000000h
191. RO Message Signaled Interrupt Message 8E 8Fh MC Control 0080h RO RW Message Signaled Interrupt Message 90 93h MA Address 00000000h RW RO E Message Signaled Interrupt Upper 94 97h MUA Address Optional 00000000h RW 98 99h MD Message Signaled Interrupt Message 0000h RW Data AOh HIDM HECI Interrupt Delivery Mode 00h RW 193 n tel Intel Manageability Engine Subsystem PCI D3 F0 F3 7 1 1 ID I dentifiers B D F Type 0 3 0 PCI Address Offset 0 3h Default Value 29F48086h Access RO Size 32 bits Bit Access perau t Description Value 31 16 RO 29F4h Device I D DI D Device ID DID This field indicates what device number assigned by Intel Vendor ID VI D Vendor I D VI D This field indicates Intel is the vendor assigned by the PCI SIG 15 0 RO 8086h 7 1 2 CMD Command B D F Type 0 3 0 PCI Address Offset 4 5h Default Value 0000h Access RO RW Size 16 bits Bit Access Default Description Value 15 11 RO 00000b Reserved Interrupt Disable 10 Disables this device from generating PCI line based interrupts This bit does not have any effect on MSI operation 9 3 RO 00h Reserved Bus Master Enable BME Controls the HECI host controller s ability to act as a system memory master for data transfers When this bit is cleared HECI bus master activity stops and any active DMA engines return to an idle condition This bit is made visible to firmware through the H P
192. RSVD V12 VCC AF24 297 intel 298 Ballout and Package Information Table 28 MCH Table 28 MCH Table 28 MCH Ballout Sorted By Name v Ballout Sorted By Name Ballout Sorted By Name Signal Name Ball Signal Name Ball Signal Name Ball AF22 VCC Y24 VCC_CL AM22 VCC AF20 VCC Y22 VCC_CL AL30 VCC AF18 VCC Y20 VCC_CL AL27 VCC AF17 VCC Y18 VCC_CL AL25 VCC AE28 VCC Y17 VCC_CL AL24 VCC AE27 VCC W28 VCC_CL AL23 5 W27 VCC_CL AL22 VCC AE23 VCC W25 VCC_CL AL21 VCC AE21 VCC W23 VCC_CL AL19 VCC AE19 VCC W21 VCC CL AL18 VCC AE18 VCC W19 VCC CL AL16 VCC AE17 VCC W18 VCC CL AK31 VCC AD28 VCC W17 VCC CL AJ29 VCC AD26 VCC V28 VCC CL AJ28 VCC AD24 VCC V26 VCC CL AJ27 VCC AD22 VCC V24 VCC CL AJ26 VCC AD20 VCC V22 VCC_CL AJ25 VCC AD18 VCC V20 VCC_CL AJ 24 VCC AD17 VCC V18 VCC CL AJ23 VCC AC28 VCC V17 VCC CL AJ22 VCC AC27 VCC U28 VCC CL AJ21 VCC AC25 VCC U27 VCC CL AJ20 VCC AC23 VCC U26 VCC_CL AJ19 21 025 VCC_CL AJ18 VCC AC19 VCC U24 VCC CL AJ17 AC18 023 VCC_CL AH31 17 022 VCC_CL AH29 VCC AB28 VCC U21 VCC_CL AH15 VCC AB26 VCC U20 VCC_CL AH14 VCC AB24 VCC U19 VCC_CL AG31 22 018 VCC_CL AG29 VCC AB20 VCC U17 VCC CL AF29 VCC AB18 VCC R18 VCC CL AE31 VCC AB17 VCC R16 VCC CL AE29 VCC AB15 VCC B25 B25 VCC CL A
193. RW Oh allowed spacing in DRAM clocks between the ACT and WRITE commands to the same rank bank This field corresponds to tncp wr in the DDR Specification Same Rank Write To Write Delayed Cl1sd cr wrsr wr This field register 11 8 RW Oh indicates the minimum allowed spacing in DRAM clocks between two WRITE commands to the same rank Different Rank Write to Write Delay C1sd cr wrdr wr This field 7 4 RW Oh indicates the minimum allowed spacing in DRAM clocks between two WRITE i commands to different ranks This field corresponds to twr wg the DDR Specification 7 READ Delay 15 This field indicates the minimum 3 0 RW Oh allowed spacing in DRAM clocks between the READ and WRITE commands This field corresponds to tap 5 2 26 CICYCTRKRD Channel 1 CYCTRK READ B D F Type 0 0 0 MCHBAR Address Offset 658 65Ah Default Value 000000h Access RW RO Size 24 bits Channel 1 CYCTRK READ registers Default eer Bit Access Value Description 23 21 RO Oh Reserved Min ACT To READ Delayed 15 cr act rd This field indicates the 20 17 RW Oh minimum allowed spacing in DRAM clocks between the ACT and READ commands to the same rank bank This field Corresponds to in the DDR Specification 7 Same Rank Write READ Delayed C1sd_cr_wrsr_rd This field indicates the minimum allowed spacing in DRAM clocks between the WRITE and READ 16 12 RW om commands to the same rank This fie
194. RXN 14 9 AJ5 PEG2 TXN 7 9 AG38 DDR B DQSB 6 ALG PEG2 14 4 4 VSS AG36 VSS AL5 PEG2 TXN 9 2 PEG2 TXP 6 9 AG35 DDR B DM 6 AL4 VSS AH45 VSS AG34 VSS AL2 PEG2 TXP 8 9 AH43 DDR B DQS 8 AG33 DDR B DQ 49 AK45 DDR_B_CB_0 AH42 DDR_B_DQSB 8 AG32 RSVD AK43 VSS AH40 VSS AG31 VCC_CL AK42 DDR B CB 5 AH39 VSS AG29 VCC CL AK40 VSS AH38 VSS AG28 RSVD AK39 DDR A CB 7 AH36 DDR B DQ 53 AG27 VCC AK38 DDR A CB 2 AH35 VSS AG26 VSS AK36 VSS AH34 DDR B DQ 48 AG25 VCC AK35 DDR A CB 3 AH33 DDR B DQ 52 AG24 VSS AK34 DDR A CB 6 AH32 VSS AG23 VCC AK33 DDR A CB 4 AH31 VCC CL AG22 VSS AK32 VSS AH29 VCC CL AG21 VCC AK31 VCC_CL AH28 RSVD AG20 VSS AK15 CL_DATA AH27 VSS AG19 VCC AK14 CL_CLK AH26 VCC AG18 VCC AK13 PEG2 RXN 12 7 AH25 VSS AG17 VCC AK12 PEG2_RXP_12 7 AH24 VCC 15 VCC AK11 VSS AH23 VSS AG14 CL VREF AK10 VSS AH22 VCC AG13 VSS AK8 VSS AH21 VSS 12 PEG2 9 7 VSS AH20 VCC AG11 CL RSTB AK6 VSS AH19 VCC AG10 VSS AK4 PEG2 TXP 7 AH18 VCC AG8 VSS AK3 VCCR_EXP AH17 VCC AG7 VSS AK1 PEG2 8 9 AH15 VCC CL AG6 VSS 44 DDR B CB 1 AH14 VCC CL 5 PEG2 TXN 5 4 AJ42 DDR B CB 4 AH13 PEG2 RXN 9 AG4 VSS AJ41 VSS AH12 VSS AG2 PEG2 4 Datasheet Ballout and Package I nformation Datasheet intel Table 29 MCH Table 29 MCH Table 29 MCH Ballout Sorted By Bal
195. S 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and when in the Recovery state 7 RW Ob This mode provides external devices e g logic analyzers monitoring the Link time to achieve bit and symbol lock before the link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns 176 Datasheet Host Primary PCI Express Bridge Registers D1 FO tel Bit Access Default Value Description RW Ob Common Clock Configuration CCC 0 Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock 1 Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock The state of this bit affects the LOs Exit Latency reported in LCAP 14 12 and the N_FTS value advertised during link training RW SC Ob Retrain Link RL 0 Normal operation 1 Full Link retraining is initiated by directing the Physical Layer LTSSM from LO LOs or L1 states to the Recovery state This bit always returns 0 when read This bit is cleared automatically no need to write a 0 It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register If th
196. S will program this register resulting in a base address for a 16 KB block of 35 14 RW L 000000h contiguous memory address space This register ensures that a naturally aligned 16 KB space is allocated within the first 64 GB of addressable memory space System Software uses this base address to program the MCH Memory Mapped register set All the bits in this register are locked in Intel TXT mode 13 1 RO 0000h Reserved MCHBAR Enable MCHBAREN 0 MCHBAR is disabled and does not claim any memory 0 RW L Ob 1 MCHBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT Datasheet 73 DRAM Controller Registers DO FO DEVEN Device Enable B D F Type Address Offset Default Value Access Size 0 0 0 PCI 54 57h 000023DBh RO RW L 32 bits Allows for enabling disabling of PCI devices and functions that are within the MCH The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register All the bits in this register are Intel TXT Lockable Bit Access Default Value Description 31 14 RO 00000h Reserved 13 RW L 1b PE1 Enable D6EN 0 Bus 0 Device 6 is disabled and hidden 1 Bus 1 Device 6 is enabled and visible NOTE This bit description only applies to the 3210 MCH in dual x8 mode For the 3200 MCH this bit is reserved 12 11 RO 00
197. SE PMULIMIT PCI Express port upper prefetchable memory access window OBASE1 IOLIMIT1 PCI Express port I O access window Datasheet 35 36 intel System Address Map Device 3 ME Control Device 6 Function 0 Intel 3210 MCH only MBASE1 MLIMIT1 PCI Express port non prefetchable memory access window PMBASE1 PMLIMIT1 PCI Express port prefetchable memory access window PMUBASE PMULIMIT PCI Express port upper prefetchable memory access window OBASE 1 IOLIMITI1 PCI Express port I O access window The rules for the above programmable ranges are 1 ALL of these ranges MUST be unique NON OVERLAPPING It is the BIOS or system designers responsibility to limit memory population so that adequate PCI PCI Express High BIOS and PCI Express Memory Mapped space and APIC memory space can be allocated In the case of overlapping ranges with memory the memory decode will be given priority This is an Intel Trusted Execution Technology requirement It is necessary to get Intel TET protection checks avoiding potential attacks There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges 4 Accesses to overlapped ranges may produce indeterminate results The only peer to peer cycles allowed below the top of Low Usable memory register TOLUD are DMI Interface to PCI Express range writes Figure 3 represents system memory address map in a si
198. SEG size is set to 1 MB Stolen Memory Size set to 2 MB BIOS knows the OS requires 1 GB of PCI space BIOS also knows the range from FECO 0000h to FFFF FFFFh is not usable by the system This 20 MB range at the very top of addressable memory space is lost to APIC and Intel TXT According to the above equation TOLUD is originally calculated to 4 GB 1 0000 0000h The system memory requirements are 4GB max addressable space 1GB PCI space 35 MB lost memory 3 GB 35 MB minimum granularity ECBO 0000h Since ECBO 0000h PCI and other system requirements is less than 1 0000 0000h TOLUD should be programmed to ECBh These bits are Intel TXT lockable Default PREM Bit Access Value Description Top of Low Usable DRAM TOLUD This register contains bits 31 20 of an address one byte above the maximum DRAM memory below 4GB that is usable by the operating system Address bits 31 20 programmed to 01h implies a minimum memory size of 1 MB Configuration software must set this value to the smaller of the following 2 choices maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory Address bits 19 0 are assumed to be 0_0000h for the purposes of address comparison The Host interface positively decodes an address 15 4 RW L 001h towards DRAM if the incoming address is less than the value programmed in this register Note that the Top of Low Usable DRAM is the lowest address ab
199. SS AW31 VCC EXP AB8 VCCR EXP AP3 VSS AW28 VCC EXP AB7 VCCR EXP AK3 VSS AW27 VCC EXP AB6 VCCR EXP AF3 VSS AW21 VCC EXP ABA VCCR EXP AE15 VSS AW18 VCC_EXP AA5 VCCR_EXP AD15 VSS AW15 VCC_EXP AA4 VCCR_EXP AC15 VSS AW7 VCC EXP AA2 VCCR EXP AC3 VSS AWA VCC EXP Y4 VCCR_EXP AB14 VSS AV45 VCC_EXP Y3 VCCR_EXP AA15 VSS AV43 VCC_EXP Y1 VCCR_EXP AA14 VSS AV34 VCC_EXP Wil VCCR_EXP W15 VSS AV28 VCC EXP W10 VCCR EXP V15 VSS AV24 VCC EXP ws VCCR_EXP V14 VSS AV23 VCC EXP W7 VCCR_EXP T15 VSS AV22 VCC_EXP w5 VCCR_EXP T14 VSS AV18 VCC_EXP WA VCCR EXP M3 VSS AV13 VCC EXP W2 VCCR_EXP H3 vss AV12 VCC_EXP V4 VCCR_EXP C16 vss AV11 VCC_EXP VCCR_EXP C12 VSS AV10 VCC EXP V1 VCCR EXP C8 VSS AV6 VCC EXP U5 VSS B2 VSS AVA VCC EXP U4 VSS BE38 VSS AV3 VCC_EXP U2 VSS BE34 VSS AV1 VCC EXP T4 VSS BE30 VSS AU3 299 m n tel Ballout and Package Information Table 28 MCH Table 28 MCH Table 28 MCH Ballout Sorted By Name v Ballout Sorted By Name Ballout Sorted By Name Signal Name Ball Signal Name Ball Signal Name Ball VSS AT45 VSS AL35 VSS AF19 VSS AT39 VSS AL12 VSS AE36 VSS AT30 VSS AL8 VSS AE32 VSS AT28 VSS AL4 VSS AE26 VSS AT24 VSS AK43 VSS AE24 VSS AT23 VSS AK40 VSS AE22 VSS AT16 VSS AK36 VSS AE20 VSS AT8 VSS AK32 VSS AE12 VSS AT1 VSS AK11 VSS AE8 VSS AR39 VSS AK10 VSS AE4 VSS AR38 VSS AK8 VSS AD45
200. SS H45 FSB DB 12 M23 VSS L7 VSS H43 VSS M22 BSELO L6 VSS H42 FSB DB 9 M21 ALLZTEST L5 PEG TXP 14 H40 VSS M19 RSVD_M19 L4 VSS H39 FSB_REQB 4 M18 VSS L2 PEG TXN 15 H38 FSB BPRIB M16 RSVD K45 vss H36 VSS M15 VSS_M15 K43 FSB DSTBNB 0 H35 VSS M13 PEG RXN 4 K42 FSB AB 15 H34 FSB DSTBPB 1 M12 VSS K40 VSS H33 FSB DB 25 M11 PEG RXP 12 K39 VSS H31 FSB DB 34 M10 VSS K38 FSB AB 6 H30 FSB DB 39 Datasheet Ballout and Package I nformation Datasheet intel Table 29 MCH Table 29 MCH Table 29 MCH Ballout Sorted By Ball Ballout Sorted By Ball Ballout Sorted By Ball Ball Signal Name Ball Signal Name Ball Signal Name H28 VTT FSB 11 55 VTT_FSB H27 VTT_FSB G10 PEG_RXP_7 E31 VTT_FSB H25 VTT_FSB G8 VSS E29 VTT_FSB H24 FSB_DB_45 G7 VSS E27 FSB_DVREF H23 VSS G6 PEG_RXN_9 E25 VCC_E25 H22 VSS G4 VSS E21 VSS H21 RSVD G2 PEG_TXN_12 E19 VSS H19 VSS F45 VSS E17 PEG TXN O H18 VSS F43 FSB AB 3 E15 PEG TXP 1 H16 VSS 16 41 FSB DB 14 E13 PEG TXP 2 H15 RSVD H15 F40 VSS E11 PEG TXN 4 H13 PEG RXP 2 F39 FSB DB 17 E9 PEG TXN 6 H12 PEG RXP 5 F38 FSB DB 16 E6 PEG RXP 8 H11 VSS F36 VSS E5 VSS H10 PEG RXN 7 F35 FSB DB 48 E4 PEG_TXN_11 H8 VSS F34 VSS D44 FSB_DB_52 H7 VSS F33 FSB_DB_26 D43 FSB_DB_53 H6 VSS F31 FSB DB 32 D42 VSS H4 PEG_TXN_13 F30 VTT_FSB D41 FSB_DSTBNB_3 H3 VCCR_EXP F28 VTT_FSB D39 FSB_DB_57 H1 PEG_
201. Signal Groups CMOS Input EXP SLR PWROK RSTINB CMOS Output ICH SYNCB O Buffer Supply Voltages System Bus Input Supply Voltage VIL FSB 1 25 V PCI Express VCC EXP Supply Voltages 3 3 V PCI Express Analog Supply VCCA_EXP Voltage 1 8 V DDR2 Supply VCC DDR Voltage 1 8 V DDR2 Clock VCC CKDDR Supply Voltage 1 25 V MCH Core Supply Voltage Mee 1 25 V Controller Supply Voltage 3 3 V CMOS Supply VCC3 3 Voltage PLL Analog Supply VCCA_HPLL VCCAPLL_EXP VCCA_MPLL Voltages NOTES 1 CB_7 0 DQS 8 and DQSB 8 ECC signals are only for DDR2 284 Datasheet Electrical Characteristics 11 4 11 4 1 Table 26 Datasheet Buffer Supply and DC Characteristics Buffer Supply Voltages intel The 1 0 buffer supply voltage is measured at the package pins The tolerances shown in Table 26 are inclusive of all noise from DC up to 20 MHz In the lab the voltage rails should be measured with a bandwidth limited oscilloscope with a roll off of 3 dB decade above 20 MHz under all operating conditions Table 26 indicates which supplies are connected directly to a voltage regulator or to a filtered voltage rail For voltages that are connected to a filter they should me measured at the input of the filter If the recommended platform decoupling guidelines cannot be met the system designer will have to make tradeoffs between t
202. System Error on Fatal Error Enable SEFEE Controls the Root Complex s response to fatal errors 2 RW Ob 0 No SERR generated on receipt of fatal error 1 Indicates that an SERR should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself System Error on Non Fatal Uncorrectable Error Enable SENFUEE Controls the Root Complex s response to non fatal errors 1 RW Ob 0 SERR generated on receipt of non fatal error 1 Indicates that an SERR should be generated if a non fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself System Error on Correctable Error Enable SECEE Controls the Root Complex s response to correctable errors 0 RW Ob 0 No SERR generated on receipt of correctable error 1 Indicates that an SERR should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself Datasheet 249 Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 45 RSTS Root Status B D F Type 0 6 0 PCI Address Offset CO C3h Default Value 000000008 Access RO RWC Size 32 bits This register provides information about PCI Express Root Complex specific parameters Bit Access Default Description Val
203. T Remap Limit Address Register B D F Type 0 0 0 PCI Address Offset 9A 9Bh Default Value 0000h Access RO RW L Size 16 bits Default iens Bit Access Value Description 15 10 RO 000000b Reserved Remap Limit Address 35 26 REMAPLMT The value in this register defines the upper boundary of the Remap window The Remap window is inclusive of this address In the decoder A 25 0 of the remap limit address are assumed to be Fs Thus the top of the defined range will be one less than a 9 0 RW L 000h 64 MB boundary When the value in this register is less than the value programmed into the Remap Base register the Remap window is disabled These Bits are Intel TXT lockable or ME stolen Memory lockable Datasheet 85 n tel DRAM Controller Registers DO FO 5 1 27 SMRAM System Management RAM Control B D F Type 0 0 0 PCI Address Offset 9Dh Default Value 02h Access RO RW L RW RW L K Size 8 bits The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated The Open Close and Lock bits function only when G_SMRAME bit is set to a 1 Also the OPEN bit must be reset before the LOCK bit is set Bit Access Derault Description Value 7 RO Ob Reserved SMM Space Open D_ OPEN When D_OPEN 1 and D_LCK 0 the SMM space 6 RW L Ob DRAM is made visible even when SMM decode is not active This is intended to help BIOS initialize SMM space Software
204. T1 1 O Limit Address cece cece cece aa eene 222 8 14 SSTS1 Secondary dann ERR MERE UM ax daa 223 8 15 MBASE1 Memory Base Address sse nee enne 224 8 16 MLIMIT1 Memory Limit Address sss meme eene 225 8 17 PMBASE1 Prefetchable Memory Base Address 226 8 18 PMLIMIT1 Prefetchable Memory Limit 01111 227 8 19 PMBASEU1 Prefetchable Memory Base Address 228 8 20 PMLIMITU1 Prefetchable Memory Limit Address Upper 229 8 21 CAPPTR1 Capabilities Pointer 0 230 8 22 INTRLINE1 Interrupt 230 8 23 INTRPINI Interrupt errare her tret eka nr ree ce erben rbi e 230 8 24 BCIRLI Bridge Control eite de on teeter teed RARE RR TERR ERE teresa 231 8 25 PM CAPID1 Power Management 232 8 26 PM CS1 Power Management Control Status 233 8 27 SS CAPID Subsystem ID and Vendor ID Capabilities 234 8 28 SS Subsystem ID and Subsystem Vendor 10
205. TXP_12 F27 VTT_FSB D38 FSB DB 54 G44 FSB DB 13 F25 VIT FSB D36 FSB DB 59 G42 FSB_DB_11 F24 VSS D35 FSB_CPURSTB G40 FSB REQB 1 F23 VSS D34 VSS G39 VSS F22 VSS F22 D33 VTT FSB G38 FSB DB 20 F21 BSEL1 D32 VTT_FSB G36 FSB DB 22 F19 RSVD D31 VTT FSB G35 FSB DB 23 F18 BSEL2 D30 VTT FSB G34 FSB DSTBNB 1 F16 VSS D29 VSS G33 VSS F15 VSS D28 FSB SCOMP G31 VSS F13 VSS D27 FSB ACCVREF G30 FSB DB 38 F12 VSS D26 VCCA HPL G28 VTT FSB F11 VSS D25 VCCA HPL G27 VTT FSB F10 VSS D24 VSS D24 G25 VTT FSB F8 VSS D23 VSS G24 FSB DB 47 F7 PEG RXP 9 D22 VSS D22 G23 VSS F6 VSS D21 VSS D21 G22 RSVD F5 PEG TXP 11 D20 VCCA EXP G21 TCEN F3 PEG TXP 10 D19 EXP CLKINP G19 RSVD F1 VSS D18 EXP CLKINN G18 VSS E42 FSB DB 15 D17 VSS G16 VCC3 3 G16 E41 FSB DB 50 D16 PEG TXP 0 G15 RSVD_G15 E40 FSB_DINVB_1 D15 VSS G13 PEG RXN 2 E37 FSB DB 61 D14 PEG TXN 1 G12 PEG RXN 5 E35 FSB DB 63 D13 VSS 311 intel 312 Table 29 MCH Ballout Sorted By Ball Table 29 MCH Ballout Sorted By Ball Ball Signal Name Ball Signal Name D12 PEG TXN 2 B33 VIT FSB D11 VSS B31 VIT FSB D10 PEG TXP 4 B29 VSS D8 PEG TXP 6 B27 VCCA MPL D7 VSS B25 VCC B25 D5 PEG RXN 8 B21 VSS B21 D4 VSS B19 RSVD D3 PEG TXN 10 B17 VSS B17 D2 PEG RXP 10 B15 PEG RXN O C45 VSS B13 PEG RXP 1 C44 FSB REQB 0 B11 PEG TXP 3 C43 VSS
206. This address space is reported by the system firmware to the operating system There is a register PCIEXBAR that defines the base address for the block of addresses below 4 GB for the configuration space associated with busses devices and functions that are potentially a part of the PCI Express root complex hierarchy In the PCIEXBAR register there exists controls to limit the size of this reserved memory mapped space 256 MB is the amount of address space required to reserve space for every bus device and function that could possibly exist Options for 128 MB and 64 MB exist in order to free up those addresses for other uses In these cases the number of busses and all of their associated devices and functions are limited to 128 or 64 busses respectively The PCI Express Configuration Transaction Header includes an additional 4 bits ExtendedRegisterAddress 3 0 between the Function Number and Register Address fields to provide indexing into the 4 KB of configuration space allocated to each potential device For PCI Compatible Configuration Requests the Extended Register Address field must be all zeros 59 intel MCH Register Description Figure 9 Memory Map to PCI Express Device Configuration Space FFFFFFFh FFFFFh FFFh Device 31 Function 7 PCI Express Extended Configuration Space 1FFFFFh PCI Device 1 Funci n Compatible Config Space FFFFFh PCI Compatible Device
207. W Ob Unsupported Request Reporting Enable URRE When set this bit allows signaling ERR_NONFATAL ERR_FATAL or ERR_CORR to the Root Control register when detecting an unmasked Unsupported Request UR An ERR_CORR is signaled when an unmasked Advisory Non Fatal UR is received An ERR_FATAL or ERR_NONFATAL is sent to the Root Control register when an uncorrectable non Advisory UR is received with the severity bit set in the Uncorrectable Error Severity register RW Ob Fatal Error Reporting Enable FERE When set this bit enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting RW Ob Non Fatal Error Reporting Enable NERE When set this bit enables signaling of ERR_NONFATAL to the Rool Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting RW Ob Correctable Error Reporting Enable CERE When set this bit enables signaling of ERR_CORR to the Root Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting 172 Datasheet Host Primary PCI Express Bridge Registers D1 FO n tel 6 37 DSTS Device Status B D F Type Address
208. Write Clear bit s These bits can be read Internal events may set this bit A write of 1 clears sets to 0 the corresponding bit s and a write of 0 has no effect R WC S Read Write Clear Sticky bit s These bits can be read Internal events may set this bit A write of 1 clears sets to 0 the corresponding bit s and a write of 0 has no effect Bits are not cleared by warm reset but will be reset with a cold complete reset for PCI Express related bits a cold reset is Power Good Reset as defined in the PCI Express Specification R W L Read Write Lockable bit s These bits can be read and written Additionally there is a bit which may or may not be a bit marked R W L that when set prohibits this bit field from being writeable bit field becomes Read Only R W K Read Write Key bit s These bits can be read and written by software Additionally this bit when set prohibits some other bit field s from being writeable bit fields become Read Only R W L Read Write Lockable bit s These bits can be read and written Additionally there is a bit which may or may not be a bit marked R W L that when set prohibits this bit field from being writeable bit field becomes Read Only R W S Read Write Sticky bit s These bits can be read and written Bits are not cleared by warm reset but will be reset with a cold complete reset for PCI Express related bits
209. X 8 8 1 14 10 4 8K 1GB 1Gb 128M X 8 8 1 14 10 8 8K 1GB 512Mb 64M X 8 16 2 14 10 4 8K DDR2 E 667 and 2GB 1Gb 128M X 8 16 2 14 10 8 8K 800 512MB 512Mb 64M X 8 9 1 14 10 4 8K F 1GB 1Gb 128M X 8 9 1 14 10 8 8K 1GB 512Mb 64M X 8 18 2 14 10 4 8K G 2GB 1Gb 128M X 8 18 2 14 10 8 8K 10 2 3 Error Checking and Correction Table 22 is used to calculate the syndrome Numbers in parentheses indicate the data content of that bit position For example bit position 36 holds the data originally in data bit 32 Table 22 Syndrome Bit Values Datasheet Syndrome Byte 1C 0 A2 1 51 2 E 3 94 4 68 5 43 6 Fl 7 C1 8 2A 9 15 10 EO 11 49 12 86 13 34 14 15 271 intel Table 22 272 Syndrome Bit Values Syndrome Byte 2C 16 A4 17 52 18 DO 19 98 20 61 21 83 22 2F 23 C2 24 4A 25 25 26 D 27 89 28 16 29 38 30 F2 31 4C 32 A8 33 54 34 F8 35 B 36 91 37 62 38 23 39 40 41 45 42 8F 43 BO 44 19 45 26 46 32 47 8C 48 Al 49 58 50 4F 51 70 52 92 53 Functional Description Datasheet m e Functional Description n tel Table 22 Datasheet Syndrome Bit Values Syndrome Byte 64 54 13 55 C8 56 1A 57 85 58 59 7 60 29 61 46 62 31 63 Every data bit appears in eith
210. XN 3 K13 PEG TXP 0 D16 FSB DEFERB T39 PEG RXN 4 M13 PEG TXP 1 E15 FSB DINVB 0 141 RXN 5 G12 PEG TXP 2 E13 FSB DINVB 1 E40 PEG RXN 6 L12 PEG TXP 3 B11 FSB_DINVB_2 N28 PEG_RXN_7 H10 PEG_TXP_4 D10 FSB_DINVB_3 B37 PEG_RXN_8 D5 PEG_TXP_5 B9 FSB_DRDYB U41 PEG_RXN_9 G6 PEG_TXP_6 D8 FSB DSTBNB 0 K43 PEG RXN 10 C2 PEG TXP 7 B7 FSB DSTBNB 1 G34 PEG RXN 11 K8 PEG TXP 8 C6 FSB DSTBNB 2 M25 PEG RXN 12 L10 PEG TXP 9 B3 FSB DSTBNB 3 D41 PEG_RXN_13 M8 PEG_TXP_10 F3 FSB DSTBPB 0 144 RXN 14 12 11 5 Datasheet Ballout and Package I nformation Datasheet intel Table 28 MCH Table 28 MCH Table 28 MCH Ballout Sorted By Name v Ballout Sorted By Name Ballout Sorted Name Signal Name Ball Signal Name Ball Signal Name Ball PEG TXP 12 H1 PEG2 TXN 9 AL5 RSVD T33 PEG TXP 13 PEG2 1047 RSVD T12 PEG TXP 14 L5 PEG2 TXN 1147 5 RSVD R33 PEG TXP 15 M1 PEG2 TXN 1247 RSVD R22 PEG2 0 U 1 PEG2 TXN 13 97 5 RSVD R19 PEG2 RXN 1 97 AA11 PEG2 TXN 1447 RSVD P21 PEG2 RXN 27 7 PEG2 15 97 AP6 RSVD N21 PEG2 RXN 7 AB12 PEG2 TXP 0 AB3 RSVD N18 PEG2 RXN 4 97 AC10 PEG2 TXP 1 AD4 RSVD N12 PEG2 RXN 5 4 ACT PEG2 TXP 2 7 AE2 RSVD N11 PEG2 RXN 6 7 AD12 PEG2 TXP 3 9 AF4 RSVD M16 PEG2 RXN 7 7 AE11 PEG2 TXP 4 9 A
211. _DQ 33 71 AR11 DDR_B_DQ 6 36 AW36 DDR B DQ 37 72 AT12 DDR B DQ 3 37 AY38 DDR B DQ 36 73 AV8 DDR B DQ 4 38 AR25 DDR B DQS 3 39 AV27 DDR B DQ 27 40 27 DDR DQ 31 Table 43 XOR Chain 11 41 AT25 DDR B DQ 30 E m Per 42 AT27 DDR_B_DQ 26 43 AW25 DDR B DQ 24 L18 RSVD 44 AP24 DDR_B_DQ 29 ANDA DDR DQ 28 1 AY35 DDR B ODT 3 m WEE DDR B DQ 25 2 BA35 DDR B CSB 3 as ARIS DDR B DOS 2 3 BB33 DDR B ODT 2 48 Amp DDR DQ 19 4 BC32 DDR B CSB 2 m PTT DDR DQ 18 5 AY34 DDR_B_CKB_5 50 AN16 DDR_B_DQ 20 6 AW34 DDR B CK_3 ei AE DDR B DQ 22 7 AY28 DDR_B_CKB_4 52 AR18 DDR B DQ 23 8 AY30 DOR ES AVIC DDR B DQ 17 9 AP31 DDR_B_CKB_3 DDR B DQ 21 10 AR31 DDR B CK 3 EE NT DDR B DG 16 11 BA17 DDR B CKE 3 S6 PS DDR B DOS 1 12 BB17 DDR B CKE 2 57 AV15 DDR B DQ 11 58 AT15 DDR B DQ 10 Table 44 Chain 12 59 AW13 DDR B DQ 13 Bin Ball 60 15 DDR B DQ 14 Count 5 61 AY13 DDR B DQ 9 M22 BSELO 62 AW12 DDR B DQ 12 63 AP15 DDR B DQ 15 1 V10 DMI_TXP_3 64 AY12 DDR_B_DQ 8 2 vii DMI_TXN_3 65 AW10 DDR B DQS 0 3 v7 3 66 AW8 DDR DQ 0 4 V6 DMI_RXN_3 67 11 DDR_B_DQ 2 5 R2 DMI_TXP_2 68 AW11 DDR B DQ 7 6 Ti DMI_TXN_2 69 DDR B DQ 1 7 P4 2 70 AW6 DDR B DQ 5 8 R5 DMI_RXN_2 9 N2 DMI_TXP_1 Datasheet Testability Datasheet intel
212. _TXP_ 15 0 PCIE supports a maximum width of x8 The upper 8 lanes are used for 3210 MCH only static lane reversal For the 3200 MCH these signals are No Connects EXP_COMPO Primary PCI Express Output Current Compensation 31 Signal Description Signal Name Type Description Primary PCI Express Input Current Compensation EXP2 COMPO Secondary PCI Express Output Current Compensation 3210 MCH only A This signal is a No Connect for the 3200 MCH EXP2_COMPI Secondary PCI Express Input Current Compensation 3210 MCH only A This signal is a No Connect for the 3200 MCH 2 4 Controller Link I nterface Signals Signal Name Type Description CL DATA me Controller Link Data Bi directional 5 CL_CLK Ve Controller Link Clock Bi directional 5 CL_VREF Controller Link VREF CMOS CL_RST CMOS Controller Link Reset Active low 2 5 Clocks Reset and Miscellaneous Signal Name Type Description HPL CLKINP Differential Host Clock In These pins receive a differential HPL CLKI NN CMOS host clock from the external clock synthesizer This clock is used by all of the logic that is the Host clock domain Differential Primary PCI Express Clock In These pins EXP CLKINP receive a differential 100 MHZ Serial Reference clock from the EXP CLKINN CMOS external clock synthesizer This clock is used to gener
213. abilities list 19 16 RO 1h Link Declaration Capability Version LDCV Hardwired to 1 to indicate i compliances with the 1 1 version of the PCI Express specification 15 0 RO 0005h Extended Capability I D ECI D Value of 0005h identifies this linked list item capability structure as being for PCI Express Link Declaration Capability Datasheet 189 Host Primary PCI Express Bridge Registers D1 FO 6 55 ESD Element Self Description B D F Type 0 1 0 MMR Address Offset 144 147h Default Value 02000100h Access RO RWO Size 32 bits This register provides information about the root complex element containing this Link Declaration Capability Bit Access Default Description Value Port Number PN Specifies the port number associated with this element 31 24 RO 02h with respect to the component that contains this element This port number value is utilized by the egress port of the component to provide arbitration to this Root Complex Element 23 16 RWO 00h Component I D CI D Identifies the physical component that contains this Root Complex Element Number of Link Entries NLE Indicates the number of link entries following 15 8 RO Olh the Element Self Description This field reports 1 to Egress port only as we don t report any peer to peer capabilities in our topology 7 4 RO Oh Reserved 3 0 RO Oh Element Type ET Indicates Configuration Space Element 6
214. above clocks are capable of tolerating Spread Spectrum clocking Host memory and PCI Express PLLs are disabled until PWROK is asserted Power Management Power Management support includes SMRAM space remapping to 0000 128 KB Supports extended SMRAM space above 256 MB and cacheable cacheability controlled by processor ACPI Rev 1 0b compatible power management Supports processor states CO C1 and C2 Supports System states SO S1 and S5 Supports processor Thermal Management 2 TM2 Supports Manageability states MO M1 S5 Moff S5 Moff M1 Thermal Sensor MCH Thermal Sensor support includes Catastrophic Trip Point support for emergency clock gating for the MCH Hot Trip Point support for SMI generation 88 23 24 Introduction Datasheet Signal Description intel 2 Signal Description This chapter provides a detailed description of MCH signals The signals are arranged in functional groups according to their associated interface The following notations are used to describe the signal type Signal Type Description PCI Express PCI Express interface signals These signals are compatible with PCI Express 1 1 Signaling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Differential voltage spec D D 2 1 2 Vmax Single ended maximum 1 25 V Single ended minimum 0 V DMI Direct Media Interface signals These signals are co
215. age from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Absolute Minimum and Maximum Ratings Symbol Parameter Min Max Unit Notes Tstorage Storage Temperature 55 150 1 1 25 V Core Supply Voltage with respect to VSS 0 3 1 375 V VCC Host I nterface 800 1066 1333 MHz System Bus Input Voltage with respect to VSS 1 25 V Host PLL Analog Supply Voltage with respect to VSS VIT FSB 0 3 132 V VCCA HPLL 0 3 1 375 V System Memory Interface DDR2 667 800 MHz 1 8 V DDR2 System Memory Supply Voltage VCC DDR with respect to VSS 0 3 a0 Y 1 8 V DDR2 Clock System Memory Supply VCC EKDDR Voltage with respect to VSS s 49 M VCCA MPLL 1 25 V System Memory PLL Analog Supply 0 3 1 375 v Voltage with respect to VSS 279 n tel Electrical Characteristics Table 23 Absolute Minimum and Maximum Ratings Symbol Parameter Min Max Unit Notes PCI Express DMI Interface 1 25 V PCI Express and DMI Supply NCC Voltage with respect to VSS 0 3 1 375 V 3 3 V PCI Express Analog Supply Voltage with respect to VSS 1 25 V Primary PCI Express PLL Analog Supply Voltage with respect to VSS 1 25 V Secondary PCI Express PLL Analog Supply Voltage with respect to VSS VCCA EXP 0 3 3 63 V VCCAPLL EXP 0 3 1 375 V VCCAPLL EXP2 0
216. alue Access Size 0 6 0 PCI 8 0000h RW RO 16 bits This register provides control for PCI Express device specific capabilities The error reporting enable bits are in reference to errors detected by this device not error messages received across the link The reporting of error messages ERR CORR ERR NONFATAL ERR FATAL received by Root Port is controlled exclusively by Root Port Command Register Bit Access Default Value Description 15 8 7 5 RO RW Oh 000b Reserved Max Payload Size MPS 000 128B max supported payload for Transaction Layer Packets TLP As a receiver the Device must handle TLPs as large as the set value as transmitter the Device must not generate TLPs exceeding the set value All other encodings are reserved Hardware will actually ignore this field It is writeable only to support compliance testing RO Ob Reserved RW Ob Unsupported Request Reporting Enable URRE When set this bit allows signaling ERR_NONFATAL ERR_FATAL or ERR_CORR to the Root Control register when detecting an unmasked Unsupported Request UR An ERR_CORR is signaled when an unmasked Advisory Non Fatal UR is received An ERR_FATAL or ERR_NONFATAL is sent to the Root Control register when an uncorrectable non Advisory UR is received with the severity bit set in the Uncorrectable Error Severity register RW Ob Fatal Error Reporting Enable FERE Wh
217. alue of this field depends on the common Clock Configuration bit LCTL 6 11 10 RWO 11b Active State Link PM Support ASLPMS The MCH supports ASPM LOs and L1 9 4 RO 10h Max Link Width MLW This field indicates the maximum number of lanes supported for this link 08h x8 10h x16 For the 3210 MCH with dual 8 lane x8 configuration the value of 10h is reserved The supported maximum lane size is 8 lanes x8 for this link For the 3200 MCH the value of 10h is reserved The supported maximum lane size is 8 lanes x8 for this link 3 0 RWO 1h Max Link Speed MLS Supported Link Speed This field indicates the supported Link speed s of the associated Port 0001b 2 5GT s Link speed supported All other encodings are reserved Datasheet 175 Host Primary PCI Express Bridge Registers D1 FO LCTL Link Control B D F Type Address Offset Default Value Access Size 0 1 0 PCI BO B1h 0000h RO RW RW SC 16 bits This register allows control of PCI Express link Bit Access Berat Description Value 15 12 RO 0000b Reserved Link Autonomous Bandwidth I nterrupt Enable When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set 11 RW Ob This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of S
218. annel disabled This setting hardwires bits 2 and 3 of the rank population field for each channel to zero MCHBAR offset 260h bits 22 23 for channel 0 and MCHBAR offset 660h bits 22 23 for channel 1 75 RO Ob Chipset I ntel TXT disable LTDIS Chipset Intel TXT disable 74 75 RO 00b Reserved 72 RO Ob Agent Presence Disable APD 71 RO Ob Circuit Breaker Disable CBD Multiprocessor Disable MD 70 RO Ob 0 MCH capable of Multiple Processors 1 MCH capable of uni processor only 69 RO Ob FAN Speed Control Disable FSCD 68 RO Ob EastFork Disable EFD 67 65 RO 000b Reserved 64 62 RO 111b Reserved 61 58 RO 0000b Reserved ME Disable MED 57 RO Ob 0 ME feature is enabled 1 ME feature is disabled 56 RO 1b Reserved 55 51 RO Os Reserved 50 49 RO 11b Reserved VT d Disable VTDD 48 RO Ob 0 Enable VT d 1 Disable VT d 47 RO Ob Reserved Datasheet 95 intel DRAM Controller Registers DO FO Bit Access Default Description Value 46 RO 1b Reserved Primary PCI Express Port x16 Disable PEX16D 0 Capable of x16 PCI Express Port 1 Not Capable of x16 PCI Express port instead PCI Express is limited to x8 45 RO Ob and below This causes PCI Express port to enable and train logical lanes 7 0 only Logical lanes 15 8 are powered down and the Max Link Width field of the Link Capability register reports x8 instead of x16 In the case of x8 lane
219. annel mode and one zone of single channel mode simultaneously across the whole memory array This mode is used when Intel Flex Memory Mode is enabled and both Channel A and Channel B DIMMs are populated in any order with the total amount of memory in each channel being different 269 intel Table 19 10 2 1 2 3 Table 20 10 2 2 270 Functional Description Table 19 is a sample dual channel asymmetric memory configuration showing the rank organization with Intel Flex Memory Mode Enabled Sample System Memory Dual Channel Asymmetric Organization Mode with I ntel Flex Memory Mode Enabled Channel 0 Cumulative top Channel 1 Cumulative top Rank obulalion address in opulation address in populasi Channel 0 Popu Channel 1 Rank 3 0 MB 2048 MB 0 MB 2304 MB Rank 2 0 MB 2048 MB 256 MB 2304 MB Rank 1 512 MB 2048 MB 512 MB 2048 MB Rank 0 512 MB 1024 MB 512 MB 1024 MB Dual Channel Asymmetric Mode with I ntel Flex Memory Mode Disabled In this addressing mode addresses start in channel 0 and stay there until the end of the highest rank in channel 0 and then addresses continue from the bottom of channel 1 to the top This mode is used when Intel Flex Memory Mode is disabled and both Channel A and Channel B DIMMs are populated in any order with the total amount of memory in each channel being different Table 20 is a sample dual channel asymmetric memory configuration showing the rank or
220. anticipated that this capability will never be used However it is necessary because Microsoft will test for its presence Default A Bit Access Value Description 31 16 RO 0000h Reserved 15 8 RO 80h Pointer to Next Capability PNC This contains a pointer to the next item in the capabilities list which is the Power Management capability 7 0 RO ODh Capability ID CI D Value of ODh identifies this linked list item capability structure as being for SSID SSVID registers in PCI to PCI Bridge 8 28 SS Subsystem ID and Subsystem Vendor ID B D F Type 0 6 0 PCI Address Offset 8C 8Fh Default Value 00008086 Access RWO Size 32 bits System BIOS can be used as the mechanism for loading the SSID SVID values These values must be preserved through power management transitions and a hardware reset Bit Access Description Value 31 16 RWO 0000h Subsystem ID SSID Identifies the particular subsystem and is assigned by the vendor Subsystem Vendor I D SSVI D Identifies the manufacturer of the subsystem 15 0 RWO 8086h and is the same as the vendor ID which is assigned by the PCI Special Interest Group 234 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 29 MSI D Message Signaled Interrupts Capability I D B D F Type 0 6 0 PCI Address Offset 90 91h Default Value 005 Access RO Size 16 bits When a
221. apable of up to FSB 800 27 24 RO 1h CAPID Version CAPI DV This field has the value 0001b to identify the first revision of the CAPID register definition 23 16 RO OCh CAPI D Length CAPI DL This field has the value OCh to indicate the structure length 12 bytes Next Capability Pointer NCP This field is hardwired to 00h indicating the 15 8 RO 00h end of the capabilities linked list 7 0 RO 09h Capability I dentifier CAP ID This field has the value 1001b to identify the CAP ID assigned by the PCI SIG for vendor dependent capability pointers Datasheet 97 intel DRAM Controller Registers DO FO Table 9 MCHBAR Register Address Map Address Default Offset Register Symbol Register Name Valine Access 111h CHDECMISC Channel Decode Misc 00h RW L Channel 0 DRAM Rank 200 2018 CODRBO Boundary Address 0 0000h RO RW L Channel 0 DRAM Rank 202 203h CODRB1 Boundary Address 1 0000h RW L RO Channel 0 DRAM Rank 204 205h CODRB2 Boundary Address 2 0000h RW L RO Channel 0 DRAM Rank 206 207h CODRB3 Boundary Address 3 0000h RO RW L 208 209h CODRAO1 cnannel ORAM Rarik 0 1 0000h RW L Attribute 20A CODRA23 Cnannel Rank 2 3 0000h RW L Attribute 250 251h COCYCTRKPCHG Channel 0 CYCTRK PCHG 0000h RO RW 252 255h COCYCTRKACT Channel 0 CYCTRK ACT 00000000h RW RO 256 257h COCYCTRKWR Channel 0 CYCTRK WR 0000h RW
222. as being for PCI Express Link Declaration Capability Datasheet 255 n tel Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 55 ESD Element Self Description B D F Type 0 6 0 MMR Address Offset 144 147h Default Value 030001001 Access RO RWO Size 32 bits This register provides information about the root complex element containing this Link Declaration Capability Default xs Bit Access Value Description Port Number PN This field specifies the port number associated with this 4 element with respect to the component that contains this element This port 31 24 RO 03h dm number value is used by the egress port of the component to provide arbitration to this Root Complex Element 23 16 RWO 00h Component I D CI D This field indicates the physical component that contains this Root Complex Element Number of Link Entries NLE This field indicates the number of link entries 15 8 RO Olh following the Element Self Description This field reports 1 to Egress port only as we don t report any peer to peer capabilities in our topology 7 4 RO Oh Reserved 3 0 RO Oh Element Type ET This field indicates Configuration Space Element 256 Datasheet m e Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 56 LE1D Link Entry 1 Description B D F Type Address Offset Default Value Access Size
223. ase address register DRAM control including thermal throttling control and configuration for the DMI and other MCH specific registers Device 1 Primary Host PCl Express Bridge Logically this appears as a virtual PCI to PCI bridge residing on PCI bus 0 and is compliant with PCI Express Specification Rev 1 0 Device 1 contains the standard PCI to PCI bridge registers and the standard PCI Express PCI configuration registers including the PCI Express memory address mapping It also contains Isochronous and Virtual Channel controls in the PCI Express extended configuration space Device 3 Manageability Engine Device Logically this appears as a PCI device residing on PCI bus O Physically device 3 e Device 6 Secondary Host PCI Express Bridge Intel 3210 only Logically this appears as a virtual PCI to PCI bridge residing on PCI bus 0 and is compliant with PCI Express Specification Rev 1 0 Device 6 contains the standard PCI to PCI bridge registers and the standard PCI 5 configuration registers including the PCI Express memory address mapping It also contains Isochronous and Virtual Channel controls in the PCI Express extended configuration space Configuration Mechanisms The processor is the originator of configuration cycles so the FSB is the only interface in the platform where these mechanisms are used The MCH translates transactions received through both configuration mechanisms to the same form
224. at Standard PCI Configuration Mechanism The following is the mechanism for translating processor 1 bus cycles to configuration cycles The PCI specification defines a slot based configuration space that allows each device to contain up to 8 functions with each function containing up to 256 8 bit configuration registers The PCI specification defines two bus cycles to access the PCI configuration space Configuration Read and Configuration Write Memory and 1 spaces are supported directly by the processor Configuration space is supported by a mapping mechanism implemented within the MCH The configuration access mechanism makes use of the CONFIG ADDRESS Register at I O address OCF8h though OCFBh and CONFIG DATA Register at 1 0 address OCFCh though OCFFh To reference a configuration register a DW 1 0 write cycle is used to place a value into CONFIG ADDRESS that specifies the PCI bus the device on that bus the function within the device and a specific configuration register of the device function being accessed CONFIG ADDRESS 31 must be 1 to enable a configuration cycle CONFIG DATA then becomes a window into the four bytes of configuration space specified by the contents of CONFIG ADDRESS Any read or write to CONFIG DATA will result in the MCH translating the CONFIG ADDRESS into the appropriate configuration cycle Datasheet m e MCH Register Description n tel 4 3 2 Datasheet is responsible for tran
225. at this device does not support the 14 13 RO 00b power management data register Data Select DSEL This field indicates that this device does not support the 12 9 RO Oh power management data register PME Enable PMEE This bit indicates that this device does not generate PMEB assertion from any D state 0 PMEB generation not possible from any D State 8 RWP 0b 1 PMEB generation enabled from any D State The setting of this bit has no effect on hardware See PM_CAP 15 11 7 2 RO 00006 Reserved Power State PS This field indicates the current power state of this device and can be used to set the device into a new power state If software attempts to write an unsupported state to this field write operation must complete normally on the bus but the data is discarded and no state change occurs 00 DO 11 D3 Support of D3cold does not require any special action While in the D3hot state this device can only act as the target of PCI 1 0 RW 00b configuration transactions for power management control This device also cannot generate interrupts or respond to MMR cycles in the D3 state The device must return to the DO state in order to be fully functional When the Power State is other than DO the bridge will Master Abort i e not claim any downstream cycles with exception of type 0 configuration cycles Consequently these unclaimed cycles will go down DMI and come back up as Unsupported Requests which the MCH logs as Master Abor
226. atasheet m e DRAM Controller Registers DO FO n tel 5 2 31 EPCODRBO EP Channel 0 DRAM Rank Boundary Address 0 B D F Type 0 0 0 MCHBAR Address Offset 00 01 Default Value 0000h Access RW RO Size 16 bits Bit Access Derault Description Value 15 10 RO 000000b Reserved 9 0 RW 000h Channel 0 Dram Rank Boundary Address 0 CODRBAO 5 2 32 EPCODRB1 EP Channel 0 DRAM Rank Boundary Address 1 B D F Type 0 0 0 MCHBAR Address Offset A02 A03h Default Value 0000h Access RW RO Size 16 bits See CODRBO register Default Bit Access Value Description 15 10 RO 000000b Reserved 9 0 RW 000h Channel 0 Dram Rank Boundary Address 1 CODRBA1 5 2 33 EPCODRB2 EP Channel 0 DRAM Rank Boundary Address 2 B D F Type 0 0 0 MCHBAR Address Offset 04 05 Default Value 0000h Access RW RO Size 16 bits See CODRBO register Default Me Bit Access Value Description 15 10 RO 000000b Reserved 9 0 RW 000h Channel 0 DRAM Rank Boundary Address 2 CODRBA2 Datasheet 123 intel DRAM Controller Registers DO FO 5 2 34 EPCODRB3 EP Channel 0 DRAM Rank Boundary Address 3 B D F Type 0 0 0 MCHBAR Address Offset A06 A07h Default Value 0000h Access RW RO Size 16 bits See CODRBO register s Default Bit Access dine Description 15 10 RO 000000b Rese
227. ate the clocks necessary for the support of Primary PCI Express and DMI Differential Secondary PCI Express Clock In These pins EXP2 CLKINP receive a differential 100 MHZ Serial Reference clock from the EXP2 CLKINN external clock synthesizer This clock is used to generate the CMOS clocks necessary for the support of Secondary PCI Express 3210 MCH only Note For the 3200 MCH this signal pair is not used since only one 8 lane x8 PCI Express port is supported Reset In When asserted this signal will asynchronously reset the MCH logic This signal is connected to the PCIRST output of the ICH All PCI Express output signals and DMI output signals will also tri state compliant to Express Rev 1 1 RSTINB SSTL specification This input should have a Schmitt trigger to avoid spurious resets This signal is required to be 3 3 V tolerant 32 Datasheet Signal Description intel Signal Name Type Description 1 0 CL Power OK When asserted CL_PWROK is an indication to CL_PWROK the MCH that core power VCC_CL has been stable for at least SSTL 10 us PCI 5 Static Lane Reversal Form Factor Selection MCH s Express lane numbers are reversed to EXP SLR differentiate BTX and ATX form factors CMOS 0 PCI Express lane numbers are reversed BTX 1 Normal operation ATX Bus Speed Select At the de assertion of PWROK the value BSEL 2
228. ation Accesses Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs Transaction Layer Packets Bus Number 7 0 is Header Byte 8 7 0 Device Number 4 0 is Header Byte 9 7 3 Function Number 2 0 is Header Byte 9 2 0 And special fields for this type of TLP Extended Register Number 3 0 is Header Byte 10 3 0 Register Number 5 0 is Header Byte 11 7 2 See the PCI Express specification for more information on both the PCI 2 3 compatible and PCI Express Enhanced Configuration Mechanism and transaction rules PCI Express Configuration Accesses When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express Enhanced Configuration access matches the Device 1 Secondary Bus Number a PCI Express Type 0 Configuration is generated on the PCI Express link targeting the device directly on the opposite side of the link This should be Device 0 on the bus number assigned to the PCI Express link likely Bus 1 The device on other side of link must be Device 0 The MCH will Master Abort any Type 0 Configuration access to a non zero Device number If there is to be more than one device on that side of the link there must be a bridge implemented in the downstream device When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express Enhanced Configuration access is within the claimed range between the upper bound of the bridge device s Subordinate Bus Number regi
229. ation Select This field configures the VC resource to provide a particular Port Arbitration service This field is valid for RCRBs Root Ports that 00b support peer to peer traffic and Switch Ports but not for PCI Express Endpoint 19 17 RW 000 devices or Root Ports that do not support peer to peer traffic The permissible value of this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource 16 8 RO 00h Reserved TC VCO Map TCVCOM This field indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 7 is set in this field TC7 is mapped to this VC 7 1 RW 7Fh resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource To remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link 0 RO 1b TCO VCO Map TCOVCOM Traffic Class 0 is always routed to VCO 254 Datasheet m Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 53 VCORSTS VCO Resource Status B D F Type 0 6 0 MMR Address Offset 11A 11Bh Default Value 0002 Access RO Size 16 bits This register reports the Virtual Channel specific status Default c iu Bit
230. b Reserved RW L 1b EP Function 3 D3F3EN 0 Bus 0 Device 3 Function 3 is disabled and hidden 1 Bus 0 Device 3 Function 3 is enabled and visible If Device 3 Function 0 is disabled and hidden then Device 3 Function 3 is also disabled and hidden independent of the state of this bit If this does not have ME capability CAPIDO 57 1 or CAPIDO 56 1 then Device 3 Function 3 is disabled and hidden independent of the state of this bit RW L 1b EP Function 2 D3F2EN 0 Bus 0 Device 3 Function 2 is disabled and hidden 1 Bus 0 Device 3 Function 2 is enabled and visible If Device 3 Function 0 is disabled and hidden then Device 3 Function 2 is also disabled and hidden independent of the state of this bit If this does not have ME capability CAPI D0 57 1 or CAPIDO 56 1 then Device 3 Function 2 is disabled and hidden independent of the state of this bit RW L 1b EP Function 1 D3F1EN 0 Bus 0 Device 3 Function 1 is disabled and hidden 1 Bus 0 Device 3 Function 1 is enabled and visible If Device 3 Function 0 is disabled and hidden then Device 3 Function 1 is also disabled and hidden independent of the state of this bit If this MCH does not have ME capability CAPIDO 57 1 then Device 3 Function 1 is disabled and hidden independent of the state of this bit 74 RW L 1b EP Function 0 D3FOEN 0 Bus 0 Device 3 Function 0 is
231. be driven before PWROK asserts BSELO must be a 1 BSEL 2 1 need to be defined values but logic value in any order will do XORTEST must be driven to O Not all of the pins will be used in all implementations Due to the need to minimize test points and unnecessary routing the XOR Chain 14 is dynamic depending on the values of EXP SLR and RSVD Ball 118 See Figure 30 for what parts of XOR Chain 14 become valid XOR inputs depending on the use of EXP SLR and RSVD Ball L18 XOR Chain Definition The MCH has 15 XOR chains The XOR chain outputs are driven out on the following output pins During fullwidth testing XOR chain outputs will be visible on both pins XOR Chain 14 Functionality RSVD Ball L18 EXP SLR XOR Chain 14 EXP RXP 15 0 EXP RXN 15 0 EXP TXP 15 0 EXP TXN 15 0 EXP RXP 15 0 EXP RXN 15 0 EXP TXP 15 0 EXP TXN 15 0 EXP RXP 15 8 EXP RXN 15 8 EXP TXP 15 8 EXP TXN 15 8 EXP RXP 7 0 EXP RXN 7 0 EXP TXP 7 0 EXP TXN 7 0 EXP RXP 15 0 EXP RXN 15 0 EXP TXP 15 0 EXP TXN 15 0 EXP RXP 15 0 EXP RXN 15 0 EXP TXP 15 0 EXP TXN 15 0 Datasheet Testability Table 31 13 3 Datasheet XOR Chain Outputs intel XOR Chain Output Pins Coordinate Location xor outO ALLZTEST M21 xor outl XORTEST L22 xor out2 ICH SYNCB P16 xor out3 RSVD N18 xor out4 RSVD AN12 xor out5 RSVD AM14 xor_ou
232. becomes Read Only when the D LCK bit in the SMRAM register is set 19 0 RO 00000h Reserved 5 1 32 TSEGMB TSEG Memory Base B D F Type 0 0 0 PCI Address Offset AC AFh Default Value 00000000h Access RO RW L Size 32 bits This register contains the base address of TSEG DRAM memory BIOS determines the base of TSEG memory by subtracting the TSEG size PCI Device O offset 9E bits 2 1 from stolen base PCI Device 0 offset A4 bits 31 20 Once D LCK has been set these bits becomes read only Default Bit Access Value Description TESG Memory base TSEGMB This register contains bits 31 20 of the base address of TSEG DRAM memory BIOS determines the base of TSEG memory by 31 20 RW L 000h subtracting the TSEG size PCI Device 0 offset 9E bits 2 1 from stolen base PCI Device 0 offset 8 bits 31 20 Once D_LCK has been set these bits becomes read only 19 0 RO 00000h Reserved Datasheet 89 m n tel DRAM Controller Registers DO FO 5 1 33 TOLUD Top of Low Usable DRAM B D F Type 0 0 0 PCI Address Offset Default Value 0010h Access RW L RO Size 16 bits This 16 bit register defines the Top of Low Usable DRAM TSEG and Stolen Memory are within the DRAM space defined From the top MCH optionally claims 1 2 MB of DRAM for Stolen Memory and 1 2 or 8 MB of DRAM for TSEG if enabled Programming Example C1DRB3 is set to 4 GB TSEG is enabled and T
233. bit is forced to 1 by the MCH RO 1b L1 Cache Enable for SMRAM SM_L1 This bit is forced to 1 by the MCH RO 1b L2 Cache Enable for SMRAM SM_L2 This bit is forced to 1 by the MCH TSEG Size TSEG_ SZ Selects the size of the TSEG memory block if enabled Memory from the top of DRAM space is partitioned away so that it may only be accessed by the processor interface and only then when the SMM bit is set in the request packet Non SMM accesses to this memory region are sent to DMI when the TSEG memory block is enabled 00 1 MB TSEG TOLUD Stolen Memory Size 1M to TOLUD Stolen 2 1 RW L 00b Memon size 01 2 MB TSEG TOLUD Stolen Memory Size 2M to TOLUD Stolen Memory Size 10 8 MB TSEG TOLUD Stolen Memory Size 8M to TOLUD Stolen Memory Size 11 Reserved Once D_LCK has been set these bits become read only TSEG Enable T_EN This bit is for enabling of SMRAM memory for Extended 0 RW L Ob SMRAM space only When G_SMRAME 1 and TSEG_EN 1 the TSEG is enabled to appear in the appropriate physical address space Note that once D LCK is set this bit becomes read only Datasheet 87 n tel DRAM Controller Registers DO FO TOM Top of Memory B D F Type 0 0 0 PCI Address Offset AO A1h Default Value 0001h Access RO RW L Size 16 bits This Register contains the size of physical memory BIOS determines the memory size reported to the OS using this Register Bit Defa
234. ble for ensuring that 8 EN Ob FW does not cause the PME S bit to transition to 1 while the PMEE bit is O indicating that host SW had disabled PME This bit is reset to 0 by MRST 7 4 RO 0000b Reserved 200 Datasheet Intel Manageability Engine Subsystem PCI D3 FO F3 n tel Bit Access Default Description Value No_Soft_Reset NSR This bit indicates that when the HECI host controller is 3 RO 1b transitioning from D3hot to DO due to power state command it does not perform an internal reset 2 RO Ob Reserved Power State PS This field is used both to determine the current power state of the HECI host controller and to set a new power state The values are 00 DO state 1 0 RW 00b 11 D3HOT state The D1 and D2 states are not supported for this HECI host controller When in the D3HOT state the HBA s configuration space is available but the register memory spaces are not Additionally interrupts are blocked 7 1 19 MI D Message Signaled Interrupt Identifiers B D F Type 0 3 0 PCI Address Offset 8C 8Dh Default Value 0005 Access RO Size 16 bits Bit Access Derault Description Value Next Pointer NEXT Indicates the next item in the list This can be other 15 8 RO 00h capability pointers such as PCI X or PCI Express or it can be the last item in the list 7 0 RO 05h Capability ID CI D Capabilities ID indicates MSI 7
235. cal DRAM behind the HSEG transaction address is not remapped and is not accessible All cacheline writes with WB attribute or Implicit write backs to the HSEG range are completed to DRAM like an SMM cycle FSB Interrupt Memory Space FEEO 0000 FEEF FFFF The FSB Interrupt space is the address used to deliver interrupts to the FSB Any device on PCI Express or DMI may issue a Memory Write to OFEEx xxxxh The MCH will forward this Memory Write along with the data to the FSB as an Interrupt Message Transaction The MCH terminates the FSB transaction by providing the response and asserting HTRDYB This Memory Write cycle does not go to DRAM High BI OS Area The top 2 MB FFEO 0000h FFFF FFFFh of the PCI Memory Address Range is reserved for System BIOS High BIOS extended BIOS for PCI devices and the A20 alias of the system BIOS The processor begins execution from the High BIOS after reset This region is mapped to DMI Interface so that the upper subset of this region aliases to 16 MB 256 KB range The actual address space required for the BIOS is less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that full 2 MB must be considered 45 m n tel System Address Map 46 Main Memory Address Space 4 GB to TOUUD The MCH supports 36 bit addressing The maximum main memory size supported is 8 GB total DRAM memory A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger As a re
236. characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order 12 is two wire communications bus protocol developed by Philips SMBus is a subset of the I C bus protocol and was developed by Intel Implementations of the 12 bus protocol may require licenses from various entities including Philips Electronics and North American Philips Corporation No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT is a security technology under development by Intel and requires for operation a computer system with Intel Virtualization Technology a Intel Trusted Execution Technology enabled Intel processor chipset BIOS Authenticated Code Modules and an Intel or other Intel Trusted Execution Technology compatible measured virtual machine monitor In addition Intel Trusted Execution Technology requires the system to contain a TPMv1 2 as defined by the Trusted Computing Group and specific software for some uses Intel Pentium Xeon and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2007 Intel Corporation 2 Datasheet Contents 1 Introduction exe A ae rete
237. claiming An incoming address referred to as a logical address is checked to see if it falls in the memory re map window The bottom of the re map window is defined by the value in the RECLAI MBASE register The top of the re map window is defined by the value in the RECLAI MIT register An address that falls within this window is reclaimed to the physical memory starting at the address defined by the TOLUD register The TOLUD register must be 64M aligned when RECLAIM is enabled but can be 1M aligned when reclaim is disabled PCI Express Configuration Address Space There is a device 0 register PCIEXBAR which defines the base address for the configuration space associated with all devices and functions that are potentially a part of the PCI Express root complex hierarchy The size of this range will be programmable for the MCH BIOS must assign this address range such that it will not conflict with any other address ranges See the configuration portion of this document for more details 47 m n tel System Address Map 48 PCI Express Address Space The MCH can be programmed to direct memory accesses to the PCI Express interface when addresses are within either of two ranges specified via registers in MCH s Device 1 configuration space The first range is controlled via the Memory Base Register MBASE and Memory Limit Register MLIMIT registers The second range is controlled via the Pre fetchable Memory Base
238. coded 00 256 MB buses 0 255 Bits 31 28 are decoded in the PCI Express Base Address Field 01 128 MB Buses 0 127 Bits 31 27 are decoded in the PCI Express Base Address Field 10 64 MB Buses 0 63 Bits 31 26 are decoded in the PCI Express Base Address Field 11 Reserved This register is locked by Intel TXT RW L 00 PCI EXBAR Enable PCI EXBAREN 0 The PCIEXBAR register is disabled Memory read and write transactions proceed as if there were no PCIEXBAR register PCIEXBAR bits 35 26 are R W with no functionality behind them 1 The PCIEXBAR register is enabled Memory read and write transactions whose address bits 35 26 match PCIEXBAR will be translated to configuration reads and writes within the MCH These Translated cycles are routed as shown in the table above This register is locked by Intel TXT 76 Datasheet DRAM Controller Registers DO FO intel 5 1 16 DMI BAR Root Complex Register Range Base Address B D F Type 0 0 0 PCI Address Offset 68 6Fh Default Value 0000000000000000h Access RO RW L Size 64 bits This is the base address for the Root Complex configuration space This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the MCH There is no physical memory within this 4 KB window that can be addressed The 4 KB reserved by this register does not alias to any PCI 2 3 compliant memory
239. correct unreliable Link operation by reducing Link width Devices that do not implement the ability autonomously to change Link width are permitted to hardwire this bit to Ob The MCH does not support autonomous width change So this bit is RO RO Ob Enable Clock Power Management ECPM Applicable only for form factors that support a Clock Request CLKREQ mechanism this enable functions as follows 0 Clock power management is disabled and device must hold CLKREQ signal low 1 The device is permitted to use CLKREQ signal to power manage link clock according to protocol defined in appropriate form factor specification Default value of this field is Ob Components that do not support Clock Power Management as indicated by a Ob value in the Clock Power Management bit of the Link Capabilities Register must hardwire this bit to Ob 242 RW Ob Extended Synch ES 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and when in the Recovery state This mode provides external devices e g logic analyzers monitoring the Link time to achieve bit and symbol lock before the link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n
240. d Link Address LA Memory mapped base address of the RCRB that is the RWO 9909 target element Egress Port for this link entry 11 0 RO 000h Reserved 6 58 PESSTS PCI Express Sequence Status B D F Type 0 1 0 MMR Address Offset 218 21Fh Default Value 0000000000000FFFh Access RO Size 64 bits PCI Express status reporting that is required by the PCI Express specification Bit Access Description Value 63 60 RO Oh Reserved Next Transmit Sequence Number NTSN Value of the NXT_TRANS_SEQ 59 48 RO 000h counter This counter represents the transmit Sequence number to be applied to the next Transaction Layer Packet to be transmitted onto the Link for the first time 47 44 RO Oh Reserved Next Packet Sequence Number NPSN Packet sequence number to be 43 32 RO 000h applied to the next Transaction Layer Packet to be transmitted or re transmitted onto the Link 31 28 RO Oh Reserved Next Receive Sequence Number NRSN This is the sequence number 27 16 RO 000h associated with the Transaction Layer Packet that is expected to be received next 15 12 RO Oh Reserved 11 0 RO FFFh Last Acknowledged Sequence Number LASN This is the sequence number associated with the last acknowledged Transaction Layer Packet Datasheet 191 n tel Host Primary PCI Express Bridge Registers D1 FO 88 192 Datasheet Intel Manageability Engine Subsystem PCI D3 FO F3 7 7 1 Note Table 13
241. d Request 14 8 RO 0000h Reserved Port Arbitration Capability Indicates types of Port Arbitration supported by the VC resource This field is valid for all Switch Ports Root Ports that support peer to peer traffic and RCRBs but not for PCI Express Endpoint devices or Root Ports that do not support peer to peer traffic Each bit location within this field corresponds to a Port Arbitration Capability defined below When more than one bit in this field is Set it indicates that the VC resource can be configured to provide different arbitration services Software selects among these capabilities by writing to the Port Arbitration Select field see below 7 0 RO 01h Defined bit positions are l Bit 0 Default 016 Non configurable hardware fixed arbitration scheme e g Round Robin RR Bit 1 Weighted Round Robin WRR arbitration with 32 phases Bit 2 WRR arbitration with 64 phases Bit 3 WRR arbitration with 128 phases Bit 4 Time based WRR with 128 phases Bit 5 WRR arbitration with 256 phases Bits 6 7 Reserved MCH default indicates Non configurable hardware fixed arbitration scheme Datasheet 187 Host Primary PCI Express Bridge Registers D1 FO 6 52 VCORCTL VCO Resource Control B D F Type 0 1 0 MMR Address Offset 114 117h Default Value 800000FFh Access RO RW Size 32 bits This register controls the resources associated with PCI Express Virtual Channel 0
242. d by the Length field in this register above TOLUD and still within 64 bit addressable memory space The address bits decoded depend on the length of the region defined by this register This register is locked by Intel TXT The address used to access the PCI Express configuration space for a specific device can be determined as follows PCI Express Base Address Bus Number 1MB Device Number 32KB Function Number 4KB The address used to access the PCI Express configuration space for Device 1 in this component would be PCI Express Base Address 0 1MB 1 32KB 0 4KB PCI Express Base Address 32KB Remember that this address is the beginning of the 4KB space that contains both the PCI compatible configuration space and the PCI Express extended configuration space All the Bits in this register are locked in Intel TXT mode 27 RW L 00 128 Base Address Mask 128ADMSK This bit is either part of the PCI Express Base Address R W or part of the Address Mask RO read Ob depending on the value of bits 2 1 in this register 26 RW L Ob 64MB Base Address Mask 64ADMSK This bit is either part of the PCI Express Base Address R W or part of the Address Mask RO read Ob depending on the value of bits 2 1 in this register 25 3 RO 000000h Reserved 2 1 RW L K 00b Length LENGTH This Field describes the length of this region Enhanced Configuration Space Region Buses De
243. d cr preall act This field indicates the minimum allowed spacing in DRAM clocks between the PRE ALL and ACT commands to the same rank This field corresponds to tgp in the DDR Specification ALLPRE to ACT Delay COsdO cr preall act From the launch of a 12 9 RW Oh prechargeall command wait for these many of memory clocks before launching a activate command This field corresponds to the DDR Specification 7 0000000 REF to ACT Delayed COsd cr rfsh act This field indicates the minimum 8 0 RW 00b allowed spacing in DRAM clocks between REF and ACT commands to the same rank This field corresponds to in the DDR Specification 106 Datasheet DRAM Controller Registers DO FO n tel 5 2 10 COCYCTRKWR Channel O CYCTRK WR B D F Type 0 0 0 MCHBAR Address Offset 256 257h Default Value 0000h Access RW Size 16 bits Channel 0 CYCTRK WR registers Default T Bit Access Value Description ACT To Write Delay COsd cr act wr This field indicates the minimum 15 12 RW Oh allowed spacing in DRAM clocks between the ACT and WRITE commands to the same rank bank This field corresponds to wr in the DDR Specificaiton Same Rank Write To Write Delayed COsd_cr_wrsr_wr This field 11 8 RW Oh indicates the minimum allowed spacing in DRAM clocks between two WRITE commands to the same rank Different Rank Write to Write Delay COsd_cr_wrdr_wr This field
244. d device which controls the root port for PCI Express The link address specifies the configuration address segment bus device function of the target root port Link Valid LV 0 RWO Ob 0 Link Entry is not valid and will be ignored 1 Link Entry specifies a valid link 144 Datasheet m e DRAM Controller Registers DO FO n tel 5 3 7 EPLE3A EP Link Entry 3 Address B D F Type 0 0 0 PXPEPBAR Address Offset 78 7Fh Default Value 0000000000008000h Access RO Size 64 bits This register provides the second part of a Link Entry which declares an internal link to another Root Complex Element Default 4 22 Bit Access Value Description 0000000 63 28 RO 00h Reserved 27 20 RO 00h Bus Number BUSN 19 15 RO 00001b Device Number DEVN Target for this link is PCI Express port Device6 14 12 RO 000b Function Number FUNN 11 0 RO 000h Reserved Datasheet 88 145 n tel DRAM Controller Registers DO FO 146 Datasheet m e Host Primary PCI Express Bridge Registers D1 FO tel 6 Warning Note Table 12 Datasheet Host Primary Express Bridge Registers D1 FO Device 1 contains the controls associated with the PCI Express root port that is the intended attach point for external devices In addition it also functions as the virtual PCI to PCI bridge The table below provides an address map of the D1 FO registers listed by address offset
245. d fatal errors detected by the device to the Root Complex Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the 8 RW Ob Device Control Register 0 The SERR message is generated by the MCH for Device 6 only under conditions enabled individually through the Device Control Register 1 The MCH is enabled to generate SERR messages which will be sent to the ICH for specific Device 6 error conditions generated detected on the primary side of the virtual PCI to PCI bridge not those received by the secondary side The status of SERRs generated is reported in the PCISTS1 register 7 RO Ob Reserved Parity Error Response Enable PERRE Controls whether or not the Master 6 RW Ob Data Parity Error bit in the PCI Status register can bet set 0 Master Data Parity Error bit in PCI Status register can NOT be set 1 Master Data Parity Error bit in PCI Status register CAN be set 5 3 RO Ob Reserved Bus Master Enable BME Controls the ability of the PCI Express port to forward Memory and 1 0 Read Write Requests in the upstream direction 0 This device is prevented from making memory or IO requests to its primary bus Note that according to PCI Specification as MSI interrupt messages are in band memory writes disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them from its secondary bus to its primary bus Upstream memory writes reads
246. d to DMI 01 Rea nly All reads are servi DRAM All writes are forwarded to 1 0 RW L 00b i d y eads are serviced by writes are forw 10 Write Only All writes are sent to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet 81 n tel DRAM Controller Registers DO FO 5 1 21 PAM4 Programmable Attribute Map 4 B D F Type 0 0 0 PCI Address Offset 94h Default Value 00h Access RO RW L Size 8 bits This register controls the read write and shadowing attributes of the BIOS areas from 0D8000h ODFFFFh Default sats Bit Access Value Description 7 6 RO 00b Reserved ODCOOOh ODFFFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from ODCOO0h to ODFFFFh 00 DRAM Disabled Accesses are directed to DMI 5 4 RW L 00b 01 Read Only All reads are serviced by DRAM All writes are forwarded to DMI 10 Write Only All writes are sent to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 3 2 RO 00b Reserved 0D8000h ODBFFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D8000h to ODBFFFh 00 DRAM Disabled Accesses are directed to DMI 1 0 RW L 00b 01 Read Only All reads are ser
247. d with this Root Port or by the Root Port itself Datasheet 183 Host Primary PCI Express Bridge Registers D1 FO 6 45 RSTS Root Status B D F Type 0 1 0 PCI Address Offset CO C3h Default Value 000000008 Access RO RWC Size 32 bits This register provides information about PCI Express Root Complex specific parameters Bit Access Default Description Value 31 18 RO 0000h Reserved PME Pending PMEP Indicates that another PME is pending when the PME Status bit is set When the PME Status bit is cleared by software the PME is 17 RO Ob delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately The PME pending bit is cleared by hardware if no more PMEs are pending PME Status PMES Indicates that PME was asserted by the requestor ID 16 RWC Ob indicated in the PME Requestor ID field Subsequent PMEs are kept pending until the status register is cleared by writing a 1 to this field 15 0 RO 0000h PME Requestor I D PMERI D Indicates the PCI requestor ID of the last PME requestor 6 46 PELC PCI Express Legacy Control B D F Type 0 1 0 PCI Address Offset EC EFh Default Value 000000008 Access RO RW Size 32 bits This register controls functionality that is needed by Legacy Express aware OSs during run time Bit Access Default Description Value 31 3 RO 0009009 Reserved Oh PME GPE Enable PMEGPE
248. dary Default Bit Access Value Description 15 4 RW FFFh Prefetchable Memory Base Address MBASE Corresponds to A 31 20 of the lower limit of the memory range that will be passed to PCI Express 64 bit Address Support Indicates that the upper 32 bits of the prefetchable 3 0 RO 1h memory region base address are contained in the Prefetchable Memory base Upper Address register at 28h 226 Datasheet m Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 18 PMLI MI T1 Prefetchable Memory Limit Address B D F Type 0 6 0 PCI Address Offset 26 27h Default Value 0001h Access RO RW Size 16 bits This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express prefetchable memory access routing based on the following formula PREFETCHABLE MEMORY BASE lt address PREFETCHABLE MEMORY LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note that prefetchable memo
249. dary Side for 13 RWC Ob Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Unsupported Request Completion Status Received Target Abort RTA This bit is set when the Secondary Side for 12 RWC Ob Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Completer Abort Completion Status Signaled Target Abort STA Not Applicable or Implemented Hardwired to 0 11 RO Ob The MCH does not generate Target Aborts the MCH will never complete a request using the Completer Abort Completion status 10 9 RO 00b DEVSELB Timing DEVT Not Applicable or Implemented Hardwired to 0 Master Data Parity Error SMDPE When set indicates that the MCH received 8 RWC Ob across the link upstream a Read Data Completion Poisoned Transaction Layer Packet EP 1 This bit can only be set when the Parity Error Enable bit in the Bridge Control register is set RO Ob Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 6 RO Ob Reserved 5 RO Ob 66 60 MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 4 0 RO 00h Reserved Datasheet 157 intel Host Primary PCI Express Bridge Registers D1 FO 6 15 MBASE1 Memory Base Address B D F Type 0 1 0 PCI Address Offset 20 21h Default Value FFFOh Access RW RO Size 16 bits This register controls the p
250. depends on the state of the DLAB bit KTLCR 7 It must be 0 to access the KTTHR THR When host wants to transmit data in the non FIFO mode it writes to this register In FIFO mode writes by host to this address cause the data byte to be written by hardware to ME memory THR FIFO Note Reset Host System Reset or D3 gt D0 transition Bit Access Description Value Transmit Holding Register THR Implements the Transmit Data register of 7 0 WO 00h the Serial Interface If Host does a write it writes to the Transmit Holding Register 7 2 3 KTDLLR KT Divisor Latch LSB B D F Type 0 3 3 KT MM IO Address Offset Oh Default Value 00 Access RW V Size 8 bits This register implements the KT DLL register Host can Read Write to this register only when the DLAB bit KTLCR 7 is 1 When this bit is 0 Host accesses the KTTHR or the KTRBR depending on Read or Write This is the standard Serial Port Divisor Latch register This register is only for software compatibility and does not affect performance of the hardware Note Reset Host System Reset or D3 gt D0 transition Default Bit Access Value Description 7 0 RW V 00h Divisor Latch LSB DLL Implements the DLL register of the Serial Interface Datasheet 205 m n tel Intel Manageability Engine Subsystem PCI D3 FO F3 7 2 4 KTI ER KT Interrupt Enable B D F Type 0 3 3 KT MM IO Address Offset 1h
251. device supports MSI it can generate an interrupt request to the processor by writing a predefined data item a message to a predefined memory address Bit Access Description Value 15 8 RO Pointer to Next Capability This contains a pointer to the next item in the capabilities list which is the PCI Express capability Capability ID CI D Value of 05h identifies this linked list item capability 7 0 RO 05h structure as being for MSI registers 8 30 MC Message Control B D F Type 0 6 0 PCI Address Offset 92 93h Default Value 0000 Access RW RO Size 16 bits System software can modify bits in this register but the device is prohibited from doing SO If the device writes the same message multiple times only one of those messages is guaranteed to be serviced If all of them must be serviced the device must not generate the same message again until the driver services the earlier one Default Bit Access Value Description 15 8 RO 00h Reserved 64 bit Address Capable 64AC Hardwired to 0 to indicate that the function 7 RO Ob does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64 bit memory address Multiple Message Enable MME System software programs this field to indicate the actual number of messages allocated to this device This number 6 4 BW 000b will be equal to or less than the number actually requested The encoding is the same as for t
252. does not use this value rather it is used by device drivers and operating systems to determine priority and vector information Bit Access Default Description Value Interrupt Connection I NTCON Used to communicate interrupt line routing 7 0 RW 00h information 8 23 I NTRPI N1 I nterrupt Pin B D F Type 0 6 0 PCI Address Offset 3Dh Default Value 01h Access RO Size 8 bits This register specifies which interrupt pin this device uses Bit Access Default Description Value 7 0 RO Olh Interrupt Pin I NTPI N As a single function device the PCI Express device specifies as its interrupt O1h INTA 230 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 24 BCTRL1 Bridge Control B D F Type 0 6 0 PCI Address Offset 3E 3Fh Default Value 0000h Access RO RW Size 16 bits This register provides extensions to the PCI CMD1 register that are specific to PCI PCI bridges The BCTRL provides additional control for the secondary interface as well as some bits that affect the overall behavior of the virtual Host PCI Express bridge embedded within MCH Bit Access pelaut Description Value 15 12 RO Oh Reserved Discard Timer SERR Enable DTSERRE Not Applicable or Implemented 11 RO Ob Hardwired to 0 Discard Timer Status DTSTS Not Applicable or Implemented Hardwired to 1
253. dress Channel and rank map cho 0 200h cho rank1 202h cho rank2 204h cho rank3 206h ch1 0 600h ch1 1 602h ch1 rank2 604h ch1 rank3 606h Programming guide Non stacked mode If Channel 0 is empty all of the CODRBs are programmed with OOh CODRBO Total memory in 0 rankO in 64MB increments CODRB1 Total memory 0 0 rank1 in 64MB increments and so on If Channel 1 is empty all of the CIDRBs are programmed with OOh C1DRBO Total memory in ch1 rankO in 64MB increments C1DRB1 Total memory in ch1 rankO ch1 rank1 in 64MB increments and so on Stacked mode CODRBs Similar to Non stacked mode C1DRBO C1DRB1 and CIDRB2 They are also programmed similar to non stacked mode Only exception is the DRBs corresponding to the topmost populated rank and the unpopulated higher ranks in Channel 1 must be programmed with the value of the total Channel 1 population plus the value of total Channel 0 population CODRB3 Example If only ranks 0 and 1 are populated in Ch1 in stacked mode then C1DRBO Total memory in ch1 rankO in 64MB increments 101 intel C1DRB1 CODRB3 Total memory ch1 rankO ch1 rank1 64MB increments rank 1 is the topmost populated rank DRAM Controller Registers DO FO C1DRB2 C1DRB1 C1DRB3 C1DRB1 C1DRB3 C1DRB3 CODRB3 Total memory in Channel 1 Bit Access pe
254. du Ru 249 8 45 RSTS RoOO0t Status E a CR d Ra Fl C re EXE or H EE 250 8 46 PELC PCI Express Legacy 1 250 8 47 VCECH Virtual Channel Enhanced Capability 0 0 0 2 251 8 48 PVCCAP1 Port VC Capability Register 1 0 0 cece cence eterna e 251 8 49 PVCCAP2 Port VC Capability Register 2 252 8 50 PVCCTL Port VC Control err ty asides eat a eee eee 252 8 51 VCORCAP VCO Resource Capability renee Hs 253 8 Datasheet 10 11 12 8 52 VCORCTL VCO Resource Control sss eene 254 8 53 VCORSTS VCO Resource nnne e nn nn nnn 255 8 54 RCLDECH Root Complex Link Declaration 255 8 55 ESD Element Self 1 2 2 1 11 111 256 8 56 LE1D Link Entry 1 Description 257 8 57 LELA Link Entry 1 teense ee teens 257 Direct Media I nterface DMI 259 9 1 DMIVCECH DMI Virtual Channel Enhanced
255. e 31 16 RWO 0000h Subsystem ID SSID Identifies the particular subsystem and is assigned by the vendor Subsystem Vendor I D SSVI D Identifies the manufacturer of the subsystem 15 0 RWO 8086h and is the same as the vendor ID which is assigned by the PCI Special Interest Group 168 Datasheet Host Primary PCI Express Bridge Registers D1 FO tel 6 29 MSI D Message Signaled Interrupts Capability I D B D F Type 0 1 0 PCI Address Offset 90 91h Default Value 005 Access RO Size 16 bits When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item a message to a predefined memory address Bit Access Description Value 15 8 RO Pointer to Next Capability This contains a pointer to the next item in the capabilities list which is the PCI Express capability Capability ID CI D Value of 05h identifies this linked list item capability 7 0 RO 05h structure as being for MSI registers 6 30 MC Message Control B D F Type 0 1 0 PCI Address Offset 92 93h Default Value 0000h Access RW RO Size 16 bits System software can modify bits in this register but the device is prohibited from doing so If the device writes the same message multiple times only one of those messages is ensured to be serviced If all of them must be serviced the device must not generate the same message
256. e For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Memory range covered by MBASE and MLIMIT registers are used to map non prefetchable PCI Express address ranges typically where control status memory mapped 1 0 data structures of the controller will reside and PMBASE and PMLIMIT are used to map prefetchable address ranges typically device local memory This segregation allows application of USWC space attribute to be performed in a true plug and play manner to the prefetchable address range for improved processor PCI Express memory access performance Configuration software is responsible for programming all address range registers prefetchable non prefetchable with the values that provide exclusive address ranges i e prevent overlap with each other and or with the ranges covered with the main memory There is no provision in the MCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured Bit Access Default Value Description 15 4 RW 000h Memory Address Limit MLI MI T This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express 3 0 RO Oh Reserved Datasheet 159 m n tel Host Primary PCI Express Bridge Registers D1 FO 6 17 PMBASE1 Prefetchab
257. e LTSSM is not already in Recovery or Configuration the resulting Link training must use the modified values If the LTSSM is already in Recovery or Configuration the modified values are not required to affect the Link training that s already in progress RW Ob Link Disable LD 0 Normal operation 1 Link is disabled Forces the LTSSM to transition to the Disabled state via Recovery from LO LOs or L1 states Link retraining happens automatically on 0 to 1 transition just like when coming out of reset Writes to this bit are immediately reflected in the value read from the bit regardless of actual Link state RO Ob Read Completion Boundary RCB Hardwired to 0 to indicate 64 byte RO Ob Reserved 1 0 RW 00b Active State PM ASPM Controls the level of active state power management supported on the given link 00 Disabled 01 105 Entry Supported 10 Reserved 11 LOs and L1 Entry Supported Datasheet 177 Host Primary PCI Express Bridge Registers D1 FO LSTS Link Status B D F Type Address Offset Default Value Access Size 0 1 0 PCI B2 B3h 1000h RWC RO 16 bits This register indicates PCI Express link status Bit Access Default Value Description 15 RWC Ob Link Autonomous Bandwidth Status LABWS This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or
258. e MCH responses to various system errors Since the MCH does not have an SERRB signal SERR messages are passed from the MCH to the ICH over DMI When a bit in this register is set a SERR message will be generated on DMI whenever the corresponding flag is set in the ERRSTS register The actual generation of the SERR message is globally enabled for Device 0 via the PCI Command register Bit Access Default Description Value 15 12 RO Oh Reserved SERR on MCH Thermal Sensor Event TSESERR 1 The MCH generates a DMI SERR special cycle when bit 11 of the ERRSTS is 11 RW Ob set The SERR must not be enabled at the same time as the SMI for the same thermal sensor event 0 Reporting of this condition via SERR messaging is disabled 10 RO Ob Reserved SERR on LOCK to non DRAM Memory LCKERR 9 RW Ob 1 The MCH will generate a DMI SERR special cycle whenever a processor lock cycle is detected that does not hit DRAM 0 Reporting of this condition via SERR messaging is disabled 8 2 RO Os Reserved SERR Multiple Bit DRAM ECC Error DMERR 1 The MCH generates an SERR message over DMI when it detects a multiple 1 RW Ob bit error reported by the DRAM controller 0 Reporting of this condition via SERR messaging is disabled For systems not supporting ECC this bit must be disabled SERR on Single bit ECC Error DSERR 1 The MCH generates an SERR special cycle over DMI when the DRAM 0 RW Ob controller detects a single bit error 0 Reporting of thi
259. e corresponding bit in the ERRSTS register Correctable Error Status CERRSTS This bit is set when a correctable single bit error occurs on a memory read data transfer When this bit is set the address that caused the error and the error syndrome are also logged and they 0 RO P Ob are locked to further single bit errors until this bit is cleared But a multiple bit error that occurs after this bit is set will over write the address error syndrome info This bit is cleared when it receives an indication that the processor has cleared the corresponding bit in the ERRSTS register 5 2 30 C1ODTCTRL Channel 1 ODT Control B D F Type 0 0 0 MCHBAR Address Offset 69C 69Fh Default Value 000000008 Access RO RW Size 32 bits This register provides ODT controls Bit Access Default Description Value 31 12 RO 00000h Reserved DRAM ODT for Read Commands sd1_cr_odt_duration_rd Specifies the 11 8 RW Oh duration in MDCLKs to assert DRAM ODT for Read Commands The Async value should be used when the Dynamic Powerdown bit is set Else use the Sync value DRAM ODT for Write Commands sd1_cr_odt_duration_wr Specifies the 7 4 RW Oh duration in MDCLKs to assert DRAM ODT for Write Commands The Async value should be used when the Dynamic Powerdown bit is set Else use the Sync value 3 0 RW Oh ODT for Read Commands 541 cr mchodt duration Specifies the duration 5 to assert ODT for Read Commands 122 D
260. e regions Enabling Disabling these ranges are described in the MCH Control Register Device 0 GCC Pre allocated Memory Example for 64 MB DRAM 1 MB stolen and 1 MB TSEG Memory Segments Attributes Comments 0000 0000h 03CF FFFFh R W Available System Memory 61 MB SMM Mode Only TSEG Address Range amp Pre allocated 03DO 0000h 03DF FFFFh processor Reads memory Datasheet m e System Address Map tel 3 3 PCI Memory Address Range TOLUD 4 GB This address range from the top of low usable DRAM TOLUD to 4 GB is normally mapped to the DMI Interface Device 0 exceptions are Addresses decoded to the egress port registers PXPEPBAR Addresses decoded to the memory mapped range for internal MCH registers MCHBAR Addresses decoded to the flat memory mapped address spaced to access device configuration registers PCI EXBAR Addresses decoded to the registers associated with the Direct Media Interface DMI register memory range DMIBAR With PCI Express port there are two exceptions to this rule Addresses decoded to the PCI Express Memory Window defined by the MBASE1 MLIMIT1 registers are mapped to PCI Express Addresses decoded to the PCI Express prefetchable Memory Window defined by the PMBASE1 PMLIMIT1 registers are mapped to PCI Express In an Intel ME configuration there are exceptions to this rule 1 Addresses decoded to the ME Keyboard and Text MMIO ra
261. e requests to its primary bus Completions for previously issued memory read requests on the primary bus will be issued when the data is available This bit does not affect forwarding of Completions from the primary interface to the secondary interface Memory Access Enable MAE 1 RW Ob 0 All of device 1 s memory space is disabled 1 Enable the Memory and Pre fetchable memory address ranges defined in the MBASE1 MLIMIT1 PMBASE1 and PMLIMIT1 registers Access Enable 1OAE 0 RW Ob 0 All of device 1 s I O space is disabled 1 Enable the I O address range defined the 5 1 and IOLIMIT1 registers Datasheet 151 Host Primary PCI Express Bridge Registers D1 FO 6 4 PCI STS1 PCI Status B D F Type 0 1 0 PCI Address Offset 6 7h Default Value 0010 Access RO RWC Size 16 bits This register reports the occurrence of error conditions associated with primary side of the virtual Host PCI Express bridge embedded within the MCH Bit Access Default Description Value Detected Parity Error DPE Not Applicable or Implemented Hardwired to 0 15 RO Ob Parity generating poisoned Transaction Layer Packets is not supported on the primary side of this device Signaled System Error SSE This bit is set when this Device sends an SERR 14 RWC Ob due to detecting an ERR FATAL or ERR NONFATAL condition and the SERR Enable bit in the Command register
262. e transferred at 2x rate Asserted by the requesting agent during both halves of Request Phase In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request In the second half the signals carry additional information to define the complete transaction type The transactions supported by the MCH Host Bridge are defined in the Host Interface section of this document Datasheet 27 28 Signal Description Signal Name Type Description FSB TRDYB Host Target Ready Indicates that the target of the processor GTL transaction is able to enter the data transfer phase Response Signals Indicates type of response according to the table at left Encoding Response Type 000 Idle state 001 Retry response FSB RSB 2 0 GTL 010 Deferred response 011 Reserved not driven by MCH 100 Hard Failure not driven by MCH 101 No data response 110 Implicit Writeback 111 Normal data response 1 0 Host RCOMP Used to calibrate the Host GTL 1 0 buffers FSB_RCOMP A This signal is powered by the Host Interface termination rail VTT Connects to XRCOMPIIN in the package 1 0 ion i FSB SCOMP Slew Rate Compensation Compensation for the Host A Interface for rising edges 1 0 ion i FSB SCOMPB Slew Rate Compensation Compensation for the Host A Interface for falling edges 1 0 Host Voltage Swing These signals provide reference voltage
263. e value read from this bit is undefined In previous versions of this specification this bit was used to indicate a Link Training Error System software must ignore the value read from this bit System software is permitted to write any value to this bit 244 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel Bit Access Default Description Value Negotiated Link Width NLW Indicates negotiated link width This field is valid only when the link is in the LO LOs or L1 states after link width negotiation is successfully completed 9 4 RO 00h 1 10h x16 All other encodings are reserved Current Link Speed CLS This field indicates the negotiated Link speed of the given PCI Express Link Defined encodings are 0 RO Oh 3 0001b 2 5 GT s PCI Express Link All other encodings are reserved The value in this field is undefined when the Link is not up 8 41 SLOTCAP Slot Capabilities B D F Type 0 6 0 PCI Address Offset B4 B7h Default Value 00040000 Access RWO RO Size 32 bits PCI Express Slot related registers Bit Access pocius Description Value 31 19 RWO 0000h Physical Slot Number PSN Indicates the physical slot number attached to this Port 18 RO 1b Reserved Electromechanical I nterlock Present El P When set to 1b this bit 17 RO Ob indicates that an Electromechanical Interlock is implem
264. ec vss vec vss vec vss vec vss vec vec CL vec vec vss vec vss vec vss vec vss vec vec vec vcc cL vec vss vec vss vec vss vec vss vec vss vec vec CL vec vec vss vec vss vec vss vec vss vec vec vec CL vec vss vec vss vec vss vec vss vec vss vec vec VCCAUX vec vec vec vec vec vec vec vec vec vec vec vec VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX RSVD vss RSVD vec vec HPL HPL_CLKINP vss vss vss vss vss RSVD RSVD P19 vss ICH SYNCB FSB DB 37 FSB DINVB vss FSB DSTBP pg 42 vss vss RSVD vss RSVD vss FSB DB 35 vss VIT FSB FS DSTEN vss vss BSELO ALLZTEST RSVD_M19 vss RSVD FSB_DB_36 FSB DB 41 VTT_FSB FSB DB 43 FSB DB 44 vss XORTEST vss RSVD RSVD VECS ALLI vss FSB_DB_40 VTT_FSB VTT_FSB FSB_DB_46 vss RSVD RSVD EXP_SLR vss RSVD_K16 FSB_DB_39 VIT FSB VIT FSB VIT FSB FSB DB 45 vss vss RSVD vss vss RSVD_H16 FSB_DB_38 VIT_FSB VIT FSB VIT FSB FSB DB 47 vss RSVD TCEN RSVD vss as E VIT FSB VIT FSB VIT FSB VIT FSB vss vss VSS F22 BSELI RSVD BSEL2 vss VIT FSB FSB DVREF VCC E25 vss vss PEG_TXN_O VIT FSB vss Fsp_scomp 5 HPL vccA HPL vss p24 vss Vss D22 vss_p21 VCCA EXP EXP_CLKIN vss PEG TXP 0 vss ESBS COM FSB_RCOMP VSS C24 vss_c23 vss vss VCC C18 VCCR EXP vss VCCA_MPL VCC_B25 VSS 821 RSVD VSS B17 FSB FSB SWING vss VSS_A24 VCC3 3 vss vss PEG RXP 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Datasheet BE BD BC BB BA AY AW AV
265. ectrical Charac teristics Table 27 DC Characteristics Symbol Parameter Min Nom Max Unit Notes DQ DQS DQSB DDR2 Input Cio Output Pin Capacitance 1 0 es pr 1 25V PCI Express Interface 2 0 Differential Peak to Peak VTX DIFF P P Output Voltage 0 800 le VTX_CM ACp Output Voltage a ZTX DIFF DC DC Differential TX Impedance 80 100 120 Differential Peak to Peak AC Peak Common Mode Input CM ACp Voltage 150 Input Clocks Vib Input Low Voltage 0 150 0 N A V Vin Input High Voltage 0 660 0 710 0 850 V VCROSS ABS Absolute Crossing Voltage 0 300 N A 0 550 V 6 7 8 VCROSS REL Range of Crossing Points N A N A 0 140 V CiN Input Capacitance 1 3 pF CL DATA CL CLK Input Low Voltage 0 277 V Viu Input High Voltage 0 427 V Input Leakage Current 20 uA Cin Input Capacitance 1 5 pF Output Low Current CMOS _ VoL HI lon Outputs B mA max Output High Current CMOS Outputs an min Output Low Voltage CMOS VoL Outputs 0 06 V Output High Voltage CMOS Outputs os T M PWROK CL PWROK RSTIN Vu Input Low Voltage 0 3 V Vin Input High Voltage 2 7 V Input Leakage Current 1 mA Cin Input Capacitance 0 pF CL RST Vu Input Low Volta
266. ed 8 50 PVCCTL Port VC Control B D F Type 0 6 0 MMR Address Offset 10C 10Dh Default Value 0000h Access RO RW Size 16 bits Bit Access eraut Description Value 15 4 RO 000h Reserved VC Arbitration Select VCAS This field will be programmed by software to 3 1 RW 000b the only possible value as indicated the VC Arbitration Capability field Since there is no other VC supported than the default this field is reserved 0 RO Ob Reserved 252 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 51 VCORCAP VCO Resource Capability B D F Type 0 6 0 MMR Address Offset 110 113h Default Value 00000001 Access RO Size 32 bits Bit Access Derault Description Value 31 16 RO 0000h Reserved Reject Snoop Transactions RSNPT 0 Transactions with or without the No Snoop bit set within the Transaction 15 RO Ob Layer Packet header are allowed on this VC 1 When Set any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will be rejected as an Unsupported Request 14 8 RO 0000h Reserved Port Arbitration Capability Indicates types of Port Arbitration supported by the VC resource This field is valid for all Switch Ports Root Ports that support peer to peer traffic and RCRBs but not for PCI Express Endpoint devices or Root Ports that do not support peer to peer traffic
267. ed by hardware 208 Datasheet Intel Manageability Engine Subsystem PCI D3 FO F3 tel 7 2 8 KTLCR KT Line Control B D F Type 0 3 3 KT MM IO Address Offset 3h Default Value 03h Access RW Size 8 bits The line control register specifies the format of the asynchronous data communications exchange and sets the DLAB bit Most bits in this register have no affect on hardware and are only used by the FW Note Reset Host System Reset or D3 gt D0 transition Bit Access Derault Description Value Divisor Latch Address Bit DLAB This bit is set when the Host wants to 7 RW Ob read write the Divisor Latch LSB and MSB Registers This bit is cleared when the Host wants to access the Receive Buffer Register or the Transmit Holding Register or the Interrupt Enable Register 6 RW Ob Break Control BC This bit has no affect on hardware 5 4 RW 00b Parity Bit Mode PBM This bit has no affect on hardware 3 RW Ob Parity Enable PE This bit has no affect on hardware RW Ob Stop Bit Select SBS This bit has no affect on hardware 1 0 RW 11b Word Select Byte WSB This bit has no affect on hardware Datasheet 209 n tel Intel Manageability Engine Subsystem PCI D3 F0 F3 7 2 9 KTMCR KT Modem Control B D F Type 0 3 3 KT MM IO Address Offset 4h Default Value 00h Access RO RW Size 8 bits The Modem Control Register controls the interface with the modem
268. ed requests on any used virtual channel have been completed 1 Indicates that the device has transaction s pending including completions for any outstanding non posted requests for all used Traffic Classes Ob Reserved 3 RWC Ob Unsupported Request Detected URD When set this bit indicates that the Device received an Unsupported Request Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register Additionally the Non Fatal Error Detected bit or the Fatal Error Detected bit is set according to the setting of the Unsupported Request Error Severity bit In production systems setting the Fatal Error Detected bit is not an option as support for AER will not be reported 2 RWC Ob Fatal Error Detected FED When set this bit indicates that fatal error s were detected Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the uncorrectable error mask register 1 RWC Ob Non Fatal Error Detected NFED When set this bit indicates that non fatal error s were detected Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless
269. egister is locked by Intel TXT 3 2 RO 00b Reserved 0 0000 OC3FFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0 0000 to OC3FFFh 00 DRAM Disabled Accesses are directed to DMI 01 i i 1 0 RW L 00b E Only All reads are serviced by DRAM All writes are forwarded to 10 Write Only All writes are sent to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet 79 DRAM Controller Registers DO FO 5 1 19 PAM2 Programmable Attribute Map 2 B D F Type 0 0 0 PCI Address Offset 92h Default Value 00 Access RO RW L Size 8 bits This register controls the read write and shadowing attributes of the BIOS areas from OC8000h OCFFFFh Default Bit Access Value Description 7 6 RO 00b Reserved OCCOOOh OCFFFFh Attribute HI ENABLE 00 DRAM Disabled Accesses are directed to DMI 01 Read Only All reads are serviced by DRAM All writes are forwarded to 5 4 RW L 00b DMI 10 Write Only All writes are sent to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 3 2 RO 00b Reserved 0C8000h OCBFFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0C8000h to OCBFFFh 00 DRAM Disabled Acce
270. en set this bit enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting RW Ob Non Fatal Error Reporting Enable NERE When set this bit enables signaling of ERR_NONFATAL to the Rool Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting RW Ob Correctable Error Reporting Enable CERE When set this bit enables signaling of ERR_CORR to the Root Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting 238 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 37 DSTS Device Status B D F Type Address Offset Default Value Access Size 0 6 0 PCI AA ABh 0000h RO RWC 16 bits This register reflects status corresponding to controls in the Device Control register The error reporting bits are in reference to errors detected by this device not errors messages received across the link Bit Access Default Value Description 15 6 RO 000h Reserved Ob Transactions Pending TP 0 All pending transactions including completions for any outstanding non post
271. ence clock s when the link is in the L1 and L2 3 Ready link states A value of Ob indicates the component does not have this capability and that reference clock s must not be removed in these link states This capability is applicable only in form factors that support clock request CLKREQ capability For a multi function device each function indicates its capability independently Power Management configuration software must only permit reference clock removal if all functions of the multifunction device indicate a 1b in this bit 17 15 RWO 010b L1 Exit Latency LIELAT Indicates the length of time this Port requires to complete the transition from L1 to LO The value 010 b indicates the range of 2 us to less than 4 us Both bytes of this register that contain a portion of this field must be written simultaneously in order to prevent an intermediate and undesired value from ever existing 174 Datasheet Host Primary PCI Express Bridge Registers D1 FO tel Bit Access Default Value Description 14 12 RO 100b LOs Exit Latency LOSELAT Indicates the length of time this Port requires to complete the transition from LOs to LO 000 Less than 64 ns 001 64 ns to less than 128 ns 010 128 ns to less than 256 ns 011 256 ns to less than 512 ns 100 512 ns to less than 1 us 101 1 us to less than 2 us 110 2 us 4 us 111 More than 4 us The actual v
272. endent rank refresh 26 RW Ob Reserved Refresh Counter Enable REFCNTEN This bit is used to enable the refresh counter to count during times that DRAM is not in self refresh but refreshes are not enabled Such a condition may occur due to need to reprogram DIMMs following DRAM controller switch This bit has no effect when Refresh is enabled i e there is no mode where 25 RW Ob Refresh is enabled but the counter does not run So in conjunction with bit 23 REFEN the modes are REFEN REFCNTEN Description 0 0 Normal refresh disable 0 1 Refresh disabled but counter is accumulating refreshes 1 X Normal refresh enable All Rank Refresh ALLRKREF This configuration bit enables by default 24 RW Ob that all the ranks are refreshed in a staggered atomic fashion If set the ranks are refreshed in an independent fashion Refresh Enable REFEN Refresh is enabled 23 RW Ob 0 Disabled 1 Enabled DDR Initialization Done INI TDONE Indicates that DDR initialization is 22 RW Ob complete 21 20 RW 00b Reserved DRAM Refresh Panic Watermark REFPANI CWM When the refresh count exceeds this level a refresh request is launched to the scheduler and the dref panic flag is set 19 18 RW 00b 00 5 01 6 10 7 11 8 110 Datasheet DRAM Controller Registers DO FO intel Bit Access Description Value DRAM Refresh High Watermark REFHI GHWM When the refresh count exceeds this level a refresh request is launched
273. ented on the chassis for this slot Slot Power Limit Scale SPLS Specifies the scale used for the Slot Power Limit Value 00 1 0x 16 15 RWO 00b 01 0 1 10 0 01 11 0 001 If this field is written the link sends a Set_Slot_Power_Limit message Slot Power Limit Value SPLV In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by slot Power limit in 14 7 RWO 00h Watts is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field If this field is written the link sends a Set Slot Power Limit message 6 5 RO 00b Reserved 4 RO Ob Power Indicator Present PI P When set to 1b this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot Datasheet 245 intel Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only Bit Access Derault Description Value 3 RO Ob Attention Indicator Present When set to 1b this bit indicates that an Attention Indicator is electrically controlled by the chassis MRL Sensor Present MSP When set to 1b this bit indicates that an MRL 2 RO Ob om Sensor is implemented on the chassis for this slot Power Controller Present PCP When set to 1b this bit indicates that a 1 RO Ob software programmable Power Controller is implemented for this slot adapter depending on form factor 0 RO Ob Attention Button Present
274. entification 8086h RO 2 3h DID1 Device Identification 29F9h RO 4 5h PCICMD1 Command 0000h RO RW 6 7h PCISTS1 PCI Status 0010h RO RWC 8h RID1 Revision Identification paene RO 9 Bh 1 Class Code 060400h RO Ch CL1 Cache Line Size 00h RW Eh HDR1 Header Type Olh RO 18h PBUSN1 Primary Bus Number 00h RO 19h SBUSN1 Secondary Bus Number 00h RW 213 intel Table 15 214 Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only Host Secondary PCI Express Bridge Register Address Map D6 FO Sheet 2 of 3 7 peser Register Name 4 55 1Ah SUBUSN1 Subordinate Bus Number 00h RW 1 5 1 Base Address FOh RO RW 1Dh IOLIMIT1 1 O Limit Address 00h RW RO 1E 1Fh SSTS1 Secondary Status 0000h RO RWC 20 21h MBASE1 Memory Base Address FFFOh RW RO 22 23h MLIMIT1 Memory Limit Address 0000h RW RO 24 25h PMBASE1 Prefetchable Memory Base Address FFF1h RW RO 26 27h PMLIMIT1 Prefetchable Memory Limit Address 0001h RO RW 28 2Bh PMBASEU1 Prefetchable Memory Base Address Upper 00000000h RW 2C 2Fh PMLIMITU1 Prefetchable Memory Limit Address Upper 00000000h RW 34h CAPPTR1 Capabilities Pointer 88h RO 3Ch INTRLINE1 Interrupt Line 00h RW 3Dh INTRPIN1 Interrupt Pin 01 RO 3E 3Fh BCTRL1 Bridge Control 0000h RO RW 80 83h PM_CAPID1 Power Management Capabilities C80
275. er exactly 3 or exactly 5 check bit and syndrome bit equations Every check bit appears en exactly 1 syndrome bit equation This leads to six cases 1 If the data comes back exactly as it was written then the calculated check byte will match the stored check byte and the syndrome will be all Os If exactly one check bit is flipped between the time it is written and the time it is read back then the syndrome will contain exactly one 1 Since the check byte is not returned to the requesting agent no action is necessary If exactly one data bit is flipped between the time it is written and the time it is read back then the syndrome will contain either exactly three 1s or exactly five 1s The syndrome can then be decoded as a pointer to the bit that flipped using the same check byte generation table in reverse If the syndrome contains 1s that match the locations of all three or all five Xs in a given row then that is the bit which should be flipped before the QWord is returned to the requesting agent If exactly two bits flipped there will be a nonzero even number of 1s in the syndrome It cannot be determined which bits flipped based on that syndrome but a multi bit error will be recorded along with the address at which the error occurred In addition bits 0 and 31 of each DWord are forced to 0 in the returned data in case this read was a TLB fetch This ensures that the table entry is invalid such that additional data corruption can
276. ermometer mode is disabled and TSC1 TSE enabled the analog sensor mode should be fully functional In the analog sensor mode the Catastrophic trip is functional and the Hot trip is functional at the offset below the catastrophic programmed into TSC2 CHO The other trip points are not functional in this mode When Thermometer mode is enabled all the trip points Catastrophic Hot Aux0 will all operate using the programmed trip points and Thermometer mode rate Note When disabling the Thermometer mode while thermometer running the Thermometer mode controller will finish the current cycle Note During boot all other thermometer mode registers except lock bits should be programmed appropriately before enabling the Thermometer Mode Clocks are memory clocks Note Since prior MCHs counted the thermometer rate in terms of host clocks rather than memory clocks the clock count for each setting listed below has been doubled from what is was on those MCHs This should make the actual thermometer rate approximately equivalent across products are Oh Lockable via TCO bit 7 0000 Thermometer mode disabled i e analog sensor mode 0001 enabled 512 clock mode 0010 enabled 1024 clock mode normal Thermometer mode operation provides 3 85 us settling time 266 MHz provides 3 08 us settling time 333 MHz provides 2 56 us settling time 400 MHz 0011 enabled 1536 clock mode 0100 enabled 2048 clock mode 0101 enabled 3072 cl
277. error detection and error correction Physical Layer The Physical Layer includes all circuitry for interface operation including driver and input buffers parallel to serial and serial to parallel conversion PLL s and impedance matching circuitry Datasheet Functional Description 10 4 Thermal Sensor intel There are several registers that need to be configured to support the MCH thermal sensor functionality and SMI generation Customers must enable the Catastrophic Trip Point as protection for the MCH If the Catastrophic Trip Point is crossed then the MCH will instantly turn off all clocks inside the device Customers may optionally enable the Hot Trip Point to generate SMI Customers will be required to then write their own SMI handler in BIOS that will speed up the MCH or system fan to cool the part 10 4 1 PCI Device O Function O The SMICMD register requires that a bit be set to generate an SMI when the Hot Trip point is crossed The ERRSTS register can be inspected for the SMI alert Register Register Register Default Register Name Symbol Start End Value Recess Error Status ERRSTS C8 C9 0000h RWC S RO SMI Command SMICMD cc CD 0000h RO RW 10 4 2 MCHBAR Thermal Sensor Registers The Digital Thermometer Configuration Registers reside in the MCHBAR configuration space Register Register Register Default
278. escribes the configuration of PCI Express Virtual Channels associated with this port Bit Access Derauit Description Value 31 7 RO 00000h Reserved Low Priority Extended VC Count LPEVCC This field indicates the number of extended Virtual Channels in addition to the default VC belonging to the low 6 4 RO 000b priority VC LPVC group that has the lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration 3 RO Ob Reserved 2 0 RO 000b Extended VC Count EVCC This field indicates the number of extended Virtual Channels in addition to the default VC supported by the device Datasheet 251 m e n tel Host Secondary PCI Express Bridge Registers D6 FO I ntel 3210 MCH only 8 49 PVCCAP2 Port VC Capability Register 2 B D F Type 0 6 0 MMR Address Offset 108 10Bh Default Value 00000000h Access RO Size 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port Default Bit Access Value Description VC Arbitration Table Offset VCATO This field indicates the location of the VC Arbitration Table This field contains the zero based offset of the table in 31 24 RO 00h DQWORDS 16 bytes from the base address of the Virtual Channel Capability Structure A value of 0 indicates that the table is not present due to fixed VC priority 23 0 RO 0000h _ Reserv
279. ess Through TLB Accesses through TLB address translation to enabled SMM DRAM space are not allowed Writes will be routed to Memory address 000C_0000h with byte enables de asserted and reads will be routed to Memory address 000C_0000h If a TLB translated address hits enabled SMM DRAM space an error is recorded PCI Express and DMI Interface originated accesses are never allowed to access SMM space directly or through the TLB address translation If a TLB translated address hits enabled SMM DRAM space an error is recorded PCI Express and DMI Interface write accesses through GMADR range will be snooped Assesses to GMADR linear range defined via fence registers are supported PCI Express and DMI Interface tileY and tileX writes to GMADR are not supported If when translated the resulting physical address is to enabled SMM DRAM space the request will be remapped to address 000C_0000h with de asserted byte enables 51 m n tel System Address Map 3 8 3 9 52 PCI Express and DMI Interface read accesses to the GMADR range are not supported therefore will have no address translation concerns PCI Express and DMI Interface reads to GMADR will be remapped to address 000C 0000h The read will complete with UR unsupported request completion status Fetches are always decoded at fetch time to ensure not in SMM actually anything above base of TSEG or 640 1 M Thus they will be invalid and go to address 000C 0000h but t
280. essage Signaled I nterrupt Message Data B D F Type 0 3 0 PCI Address Offset 98 99h Default Value 0000h Access RW Size 16 bits Default Bit Access Description Data Data This 16 bit field is programmed by system software if MSI is 15 0 RW 0000h enabled Its content is driven onto the FSB during the data phase of the MSI memory write transaction 202 Datasheet m e Intel Manageability Engine Subsystem PCI D3 FO F3 n tel 7 1 24 HI DM HECI Interrupt Delivery Mode B D F Type 0 3 0 PCI Address Offset AOh Default Value 00h Access RW Size 8 bits BIOS Optimal Default 00h This register is used to select interrupt delivery mechanism for HECI to Host processor interrupts Bit Access Derault Description Value 7 2 RO Oh Reserved HECI Interrupt Delivery Mode HI DM These bits control what type of interrupt the HECI will send when ME FW writes to set the M IG bit in AUX space They are interpreted as follows 1 0 RW 00b Generate Legacy or MSI interrupt 01 Generate SCI 10 Generate SMI Datasheet 203 intel Intel Manageability Engine Subsystem PCI D3 FO F3 7 2 KT IO Memory Mapped Device Specific Registers D3 F3 Table 14 KT 1O Memory Mapped Register Address Map Address Register Default Offset Symbol Register Name Value Access Oh KTRxBR KT Receive Buffer 00h R
281. etchable Memory Limit Address Upper B D F Type 0 1 0 PCI Address Offset 2C 2Fh Default Value 00000000h Access RW Size 32 bits The functionality associated with this register is present in the PCI Express design implementation This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express prefetchable memory access routing based on the following formula PREFETCHABLE MEMORY BASE lt address lt MEMORY LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1MB aligned memory block Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC i e prefetchable from the processor perspective Default Bit Access Value Description 0000000 Prefetchable Memory Address Limit MI TU This field corresponds to 31 0 RW Oh A 63 32 of the upper limit of the prefetchable Memory range that will be passed to PCI Expres
282. ex err ta ai SER vin RR AR KGaA a Re ede es 52 3 9 1 PCI Express I O Address 1 53 Register 0 0 001 55 4 1 Register Terminology senna KK teeta 56 4 2 Configuration Process and Registers 1 memes 57 4 2 1 Platform Configuration 6 57 4 3 Configuration Mechanisms 1 58 4 3 1 Standard PCI Configuration 58 4 3 2 PCI Express Enhanced Configuration Mechanism 59 4 4 Routing Configuration ACCESSES 0 0 0 cect n semen sese seems een 60 4 4 1 Internal Device Configuration Accesses ssssssssssseseeee mms 61 4 4 2 Bridge Related Configuration Accesses sssssssssseseene mene 62 4 4 2 1 PCI Express Configuration 62 4 4 2 2 DMI Configuration 5 etree nent te mme 62 4 5 O Mapped Registers cerent need RE emite Cete 63 4 5 1 CONFIG ADDRESS Configuration Address 63 4 5 2 CONFIG DATA Configuration Data Register 64 DRAM Controller Regis
283. f their test cards That is why it is being supported There is no inherent BIOS request for the 15 16 MB window Datasheet 41 m n tel System Address Map 3 2 3 Figure 6 42 TSEG TSEG is optionally 1 MB 2 MB or 8 MB in size TSEG is below stolen memory which is at the top of Low Usable physical memory TOLUD SMM mode processor accesses to enabled TSEG access the physical DRAM at the same address Non processor originated accesses are not allowed to SMM space PCI Express and DMI originated cycles to enabled SMM space are handled as invalid cycle type with reads and writes to location 0 and byte enables turned off for writes When the extended SMRAM space is enabled processor accesses to the TSEG range without SMM attribute or without WB attribute are also forwarded to memory as invalid accesses see table 8 Non SMM mode Write Back cycles that target TSEG space are completed to DRAM for cache coherency When SMM is enabled the maximum amount of memory available to the system is equal to the amount of physical DRAM minus the value in the TSEG register which is fixed at 1 MB 2 MB or 8 MB Pre allocated Memory Voids of physical addresses that are not accessible as general system memory and reside within system memory address range TOLUD are created for SMM mode and stolen memory It is the responsibility of BIOS to properly initialize these regions The following table details the location and attributes of th
284. ftware to assign an MSI address to 31 2 RW Oh the device The device handles an MSI by writing the padded contents of the MD register to this address 1 0 RO 00b Force DWord Align FDWA Hardwired to 0 so that addresses assigned by system software are always aligned on dword address boundary 6 32 MD Message Data B D F Type 0 1 0 PCI Address Offset 98 99h Default Value 0000h Access RW Size 16 bits 3 Default Bit Access Value Description Message Data MD Base message data pattern assigned by system software and used to handle an MSI from the device 15 0 RW 0000h When the device must generate an interrupt request it writes a 32 bit value to the memory address specified in the MA register The upper 16 bits are always set to 0 The lower 16 bits are supplied by this register 6 33 PE CAPL PCI Express Capability List B D F Type 0 1 0 PCI Address Offset 0 1 Default Value 0010h Access RO Size 16 bits This register enumerates the PCI Express capability structure Default c Bit Access Value Description Pointer to Next Capability PNC This value terminates the capabilities list 15 8 RO 00h The Virtual Channel capability and any other PCI Express specific capabilities that are reported via this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space 7 0 RO 10h Capability ID CID Identifies this linked list item capability structure as being f
285. gacy nrnna 184 6 47 Channel Enhanced Capability 185 6 48 PVCCAP1 Port VC Capability Register 1 sss 185 6 49 PVCCAP2 Port VC Capability Register 2 cence eee terete mm 186 6 50 PVCCTL Port VC 4 13 2 2 1 n e ems e nee e emn eene 186 6 51 VCORCAP VCO Resource Capability sss nmm menn 187 6 52 VCORCTL VCO Resource 1 e nens 188 6 53 VCORSTS VCO Resource nennen nnn nn nnn 189 6 54 RCLDECH Root Complex Link Declaration 189 6 55 ESD Element Self eee enemies 190 6 56 LE1D Link Entry 1 Description 2 1 ese emere 190 6 57 WEIA Link Entry 1 ooo er tee tbe km d xr a one x Rx wide Rea 191 6 58 PESSTS PCI Express Sequence Status 191 7 Intel Manageability Engine Subsystem PCI D3 F0 F3 193 7 1 Function in ME Subsystem 3 0 1 4 1 1 193 Tkl ID Fdentifier In 194
286. ganization with Intel Flex Memory Mode Disabled Sample System Memory Dual Channel Asymmetric Organization Mode with Intel Flex Memory Mode Disabled Channel 0 Cumulative top Channel 1 Cumulative top Rank opulatlon address in opulation address in pepe Channel 0 por Channel 1 Rank 3 0 MB 1280 MB 0 MB 2304 MB Rank 2 256 MB 1280 MB 0 MB 2304 MB Rank 1 512 MB 1024 MB 512 MB 2304 MB Rank 0 512 MB 512 MB 512 MB 1792 MB System Memory Technology Supported The MCH supports the following DDR2 Data Transfer Rates DIMM Modules and DRAM Device Technologies DDR2 Data Transfer Rates 667 PC2 5300 and 800 PC2 6400 DDR2 DIMM Modules Raw Card C Single Sided x16 un buffered non ECC Raw Card D Single Sided x8 un buffered non ECC Raw Card E Double Sided x8 un buffered non ECC Raw Card F Single Sided x8 un buffered ECC Raw Card G Double Sided x8 un buffered ECC DDR2 DRAM Device Technology 512 Mb and 1 Gb Datasheet Functional Description intel Table 21 Supported DIMM Module Configurations of of of Memory Raw DI MM DRAM DRAM 3 or Physical Bowr Banks Page Card Device 2 2 DRAM Col 2 Capacity Organization Device Inside Size Version Technology Devices Address Ranks DRAM Bits 256MB 512Mb 32M X 16 4 1 13 10 4 8K 512MB 1Gb 64M X 16 4 1 13 10 8 8K 512 512Mb 64M
287. ge mz 0 13 V Vin Input High Voltage 1 17 V Input Leakage Current x20 uA Cin Input Capacitance 5 0 pF ICH SYNCB Output Low Current CMOS A m VoL HI lon Outputs 2 9 MA max Datasheet 287 intel Electrical Characteristics Table 27 DC Characteristics Symbol Parameter Min Nom Max Unit Notes Output High Current CMOS _ _ _ Outputs 2 0 MA min T Output Low Voltage CMOS VoL Outputs 0 33 V Output High Voltage CMOS u u Vou Outputs 2 97 V EXP SLR EXP EN Input Low Voltage 0 10 0 55 m E V 0 63 Vin Input High Voltage VTT 0 1 VTT VTT 0 1 V lt Input Leakage Current 20 HA Vpad Vtt Cin Input Capacitance 2 2 5 pF NOTES 1 Determined with 2 Buffer Strength Settings into a 50 Q to 0 5xVCC_DDR test load 2 Specified at the measurement point into a timing and voltage compliance test load as 288 shown in Transmitter compliance eye diagram of PCI Express specification and measured over any 250 consecutive TX Uls 3 Specified at the measurement point over any 250 consecutive Uls The test load shown in Receiver compliance eye diagram of PCI Express spec should be used as the RX device when taking measurements 4 Applies to pin to VCC or VSS leakage current for the DDR_A_DQ_63 0 and DDR_B_DQ_63 0 signals 5 Applies to pin to pin leakage current between DDR_A_DQS_ 7 0 DDR A DQS
288. gent If this is the case and the is not the target i e the device number is gt 2 then DMI Type 0 Configuration Cycle is generated If the Bus Number is non zero and does not fall within the ranges enumerated by device 1 s Secondary Bus Number or Subordinate Bus Number Register then a DMI Type 1 Configuration Cycle is generated R W If the Bus Number is non zero and matches the value programmed into 23 16 the Secondary Bus Number Register of device 1 a Type 0 PCI 00h configuration cycle will be generated on PCI Express If the Bus Number is non zero greater than the value in the Secondary Bus Number register of device 1 and less than or equal to the value programmed into the Subordinate Bus Number Register of device 1 a Type 1 PCI configuration cycle will be generated on PCI Express This field is mapped to byte 8 7 0 of the request header format during PCI Express Configuration cycles and A 23 16 during the DMI Type 1 configuration cycles 63 MCH Register Description Access amp Bit Default Description Device Number This field selects one agent on the PCI bus selected by the Bus Number When the Bus Number field is 00 the MCH decodes the Device Number field The MCH is always Device Number 0 for the Host R W bridge entity Device Number 1 for the Host PCI Express entity 15 11 Therefore when the Bus Number 0 and the Device Number equals 0 1 00h or 2 the interna
289. gh 4095 of each device may only be accessed using memory mapped transactions in DWord 32 bit quantities Some of the MCH registers described in this section contain reserved bits These bits are labeled Reserved Software must deal correctly with fields that are reserved On reads software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value On writes software must ensure that the values of reserved bit positions are preserved That is the values of reserved bit positions must first be read merged with the new values for other bit positions and then written back Note the software does not need to perform read merge and write operation for the Configuration Address Register In addition to reserved bits within a register the MCH contains address locations in the configuration space of the Host Bridge entity that are marked either Reserved or ntel Reserved The MCH responds to accesses to Reserved address locations by completing the host cycle When a Reserved register location is read a zero value is returned Reserved registers can be 8 16 or 32 bits in size Writes to Reserved registers have no effect on the MCH Registers that are marked as Intel Reserved must not be modified by system software Writes to Intel Reserved registers may cause system failure Reads from Intel Reserved registers may return a non zero value Upon a Full Reset the MCH sets it
290. hat isn t specific to PCI Express or DMI it applies to processor Also since the GMADR snoop would not be directly to the SMM space there wouldn t be a writeback to SMM In fact the writeback would also be invalid because it uses the same translation and go to address 000C 0000h Memory Shadowing Any block of memory that can be designated as read only or write only can be shadowed into MCH DRAM memory Typically this is done to allow ROM code to execute more rapidly out of main DRAM ROM is used as a read only during the copy process while DRAM at the same time is designated write only After copying the DRAM is designated read only so that ROM is shadowed Processor bus transactions are routed accordingly 1 Address Space The does not support the existence of any other 1 0 devices beside itself on the processor bus The MCH generates either DMI Interface or PCI Express bus cycles for all processor 1 0 accesses that it does not claim Within the host bridge the contains two internal registers in the processor 1 space Configuration Address Register CONFIG ADDRESS and the Configuration Data Register CONFIG DATA These locations are used to implement configuration space access mechanism The processor allows 64 K 3 bytes to be addressed within the 1 space The propagates the processor 1 0 address without any translation on to the destination bus and therefore provides addressability for 64K 3 byte l
291. he MMC field below Multiple Message Capable MMC System software reads this field to determine the number of messages being requested by this device The value of 3 1 RO 0006 0000 equates to 1 message requested 000 1 message requested All other encodings are reserved MSI Enable MSI EN Controls the ability of this device to generate MSIs 0 RW Ob 0 MSI will not be generated 1 MSI will be generated when we receive PME messages INTA will not be generated and INTA Status PCISTS1 3 will not be set Datasheet 235 Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 31 MA Message Address B D F Type 0 6 0 PCI Address Offset 94 97h Default Value 00000000h Access RO RW Size 32 bits Default uen Bit Access Value Description 0000000 Message Address MA Used by system software to assign an MSI address to 31 2 RW Oh the device The device handles an MSI by writing the padded contents of the MD register to this address 1 0 RO 00b Force DWord Align FDWA Hardwired to 0 so that addresses assigned by system software are always aligned a DWord address boundary 8 32 MD Message Data B D F Type 0 6 0 PCI Address Offset 98 99h Default Value 0000h Access RW Size 16 bits Default Bit Access Value Description Message Data MD Base message data pattern assigned by system software and used to handle an MS
292. he TOUUD register helps identify the address range in between the 4 GB boundary and the top of physical memory This identifies memory that can be directly accessed including reclaim address calculation which is useful for memory access indication early path indication and trusted read indication When reclaim is enabled TOLUD must be 64 MB aligned but when reclaim is disabled TOLUD can be 1 MB aligned C1DRB3 cannot be used directly to determine the effective size of memory as the values programmed in the DRBs depend on the memory mode stacked interleaved The Reclaim Base Limit registers also can not be used because reclaim can be disabled The CODRB3 register is used for memory channel identification channel 0 vs channel 1 in the case of stacked memory Datasheet m e System Address Map n tel 3 4 1 3 4 2 3 5 Datasheet Memory Re claim Background The following are examples of Memory Mapped 10 devices are typically located below 4 GB High BIOS HSEG TSEG XAPIC Local APIC FSB Interrupts Mbase Mlimit Memory Mapped 10 space that supports only 32 B addressing The MCH provides the capability to re claim the physical memory overlapped by the Memory Mapped 1 0 logical address space re maps physical memory from the Top of Low Memory TOLUD boundary up to the 4 GB boundary to an equivalent sized logical address range located just below the Intel ME s stolen memory Memory Re
293. he voltage regulator output DC tolerance and the decoupling performance of the capacitor network to stay within the voltage tolerances listed in Table 26 O Buffer Supply Voltage Symbol Parameter Min Nom Max Unit Notes VCC DDR DDR2 1 0 Supply Voltage 1 7 1 8 1 9 V VCC CKDDR DDR2 Clock Supply Voltage 1 7 1 8 1 9 V 1 VCC EXP PCI Express Supply Voltage 1 188 1 25 1 313 V vcca_exp PCl Express Analog Supply 3 135 33 3465 V 1 Voltage 1 2 V System Bus Input Supply 1 14 12 1 26 V Voltage VIT FSB 2 1 1 V System Bus Input Supply 1 045 11 1 155 V Voltage MCH Core Supply Voltage 1 188 1 25 1 313 VCC_CL Controller Supply Voltage 1 188 1 25 1 313 VCC3 3 CMOS Supply Voltage 3 135 3 3 3 465 V VCCA HPLL VCCAPLL EXP 2 Analog Supply 1188 125 1 313 V 1 VCCA MPLL 9 NOTES 1 These rails are filtered from other voltage rails on the platform and should be measured at the input of the filter 2 supports both Vr 1 2 V nominal and Vr 1 1 V nominal depending on the identified processor 285 intel Electrical Characteristics 11 4 2 General DC Characteristics Platform Reference Voltages at the top of Table 27 are specified at DC only VREF measurements should be made with respect to the supply voltage Table 27 DC Characteristics Symbol Parameter Min Nom Max U
294. ified by the target component ID Target Component 10 TCI D Identifies the physical or logical component that is targeted by this link entry 23 16 RWO 00h BIOS Requirement Must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS 15 2 RO 0000h Reserved 1 RO Ob Link Type LTYP Indicates that the link points to memory mapped space for RCRB The link address specifies the 64 bit base address of the target RCRB Link Valid LV 0 RWO Ob 0 Link Entry is not valid and will be ignored 1 Link Entry specifies a valid link 5 3 3 EPLEIA EP Link Entry 1 Address B D F Type 0 0 0 PXPEPBAR Address Offset 58 5Fh Default Value 0000000000000000h Access RO RWO Size 64 bits This register provides the second part of a Link Entry which declares an internal link to another Root Complex Element Bit Access pelaut Description Value 63 36 RO 0000000h Reserved 35 12 RWO 000000h Link Address LA Memory mapped base address of the RCRB that is the target element DMI for this link entry 11 0 RO 000h Reserved 142 Datasheet DRAM Controller Registers DO FO n tel 5 3 4 EPLE2D EP Link Entry 2 Description B D F Type 0 0 0 PXPEPBAR Address Offset 60 63h Default Value 02000002h Access RO RWO Size 32 bits This register provides the first part of a Link Entry which declares a
295. iguration SCC 0 The device uses an independent clock irrespective of the presence of a reference on the connector 1 The device uses the same physical reference clock that the platform provides on the connector 11 RO Ob Link Training LTRN Indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun Hardware clears this bit when the LTSSM exits the Configuration Recovery state once Link training is complete 178 10 RO Ob Undefined The value read from this bit is undefined In previous versions of this specification this bit was used to indicate a Link Training Error System software must ignore the value read from this bit System software is permitted to write any value to this bit Datasheet Host Primary PCI Express Bridge Registers D1 FO n tel Bit Access Default Description Value Negotiated Link Width NLW Indicates negotiated link width This field is valid only when the link is in the LO LOs or L1 states after link width negotiation is successfully completed 9 4 RO 00h 1 10h x16 All other encodings are reserved Current Link Speed CLS This field indicates the negotiated Link speed of the given PCI Express Link 3 0 RO Oh 0001b 2 5 GT s PCI Express Link All other encodings are reserved The
296. in Element Self Description 31 24 23 22 21 RO RO 000b 1b Reserved Link Bandwidth Notification Capability A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms This capability is required for all Root Ports and Switch downstream ports supporting Links wider than x1 and or multiple Link speeds This field is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to Ob 20 RO Ob Data Link Layer Link Active Reporting Capable DLLLARC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob 19 RO Ob Surprise Down Error Reporting Capable SDERC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of detecting and reporting a Surprise Down error condition For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob 18 RO Ob Clock Power Management CPM A value of 1b in this bit indicates that the component tolerates the removal of any refer
297. in ascending order This chapter provides a detailed bit description of the registers When reading the PCI Express conceptual registers such as this you may not get a valid value unless the register value is stable The PCI Express Specification defines two types of reserved bits Reserved and Preserved Reserved for future RW implementations software must preserve value read for writes to bits Reserved and Zero Reserved for future R WC S implementations software must use 0 for writes to bits Unless explicitly documented as Reserved and Zero all bits marked as reserved are part of the Reserved and Preserved type which have historically been the typical definition for Reserved Most if not all control bits in this device cannot be modified unless the link is down Software is required to first disable the link then program the registers and then re enable the link which will cause a full retrain with the new settings Express Bridge Register Address D1 FO Sheet 1 of 3 2 Register 0 1h VID1 Vendor Identification 8086h RO 2 3h DID1 Device Identification 29F1h RO 4 5h PCICMD1 PCI Command 0000h RO RW 6 7h PCISTS1 PCI Status 0010h RO RWC 8h RID1 Revision Identification RO 9 Bh CC1 Class Code 060400h RO Ch CL1 Cache Line Size 00h RW Eh HDR1 Header Type Olh RO 18h PBUSN1 Primary Bus Number
298. indow ACT to ACT Delayed Cisd_cr_act_act This field indicates the minimum 20 17 RW 0000b allowed spacing in DRAM clocks between two ACT commands to the same rank Corresponds to in the DDR Specification PRE to ACT Delayed 15 cr pre act This field indicates the minimum allowed spacing in DRAM clocks between the PRE and ACT commands to the same rank bank 12 9R WOOOObPRE ALL to ACT Delayed 16 13 iud 00905 C1sd_cr_preall_act This field indicates the minimum allowed spacing in DRAM clocks between the PRE ALL and ACT commands to the same rank This field corresponds to in the DDR Specification ALLPRE to ACT Delay C1sd cr preall act From the launch of a 12 9 RW Oh prechargeall command wait for these many of mclks before launching a activate command This field corresponds to tpait_rp 0000000 REF to ACT Delayed C1sd cr rfsh act This field indicates the minimum 8 0 RW 00b allowed spacing in DRAM clocks between REF and ACT commands to the same rank This field corresponds to in the DDR Specification Datasheet 117 DRAM Controller Registers DO FO 5 2 25 C1CYCTRKWR Channel 1 CYCTRK WR B D F Type 0 0 0 MCHBAR Address Offset 656 657h Default Value 0000h Access RW Size 16 bits Channel 1 CYCTRK WR registers Bit Access Default Description Value To Write Delay C1sd_cr_act_wr This field indicates the minimum 15 12
299. information to MSI the receiving agent through the same path that normally carries read and write commands Out of Order Queueing PCI Express A high speed serial interface whose configuration is software compatible with the legacy PCI specifications The physical PCI bus that is driven directly by the Intel CH9 Primary PCI Communication between Primary PCI and the MCH occurs over DMI The Primary PCI bus is not PCI Bus 0 from a configuration standpoint A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four Rank x16 SDRAM devices in parallel ignoring ECC These devices are usually but not always mounted on a single side of a DIMM SCI System Control Interrupt Used in ACPI protocol System Error An indication that an unrecoverable error has occurred on an SERR 1 O bus System Management Interrupt Used to indicate any of several system SMI conditions such as thermal sensor events throttling activated access to System Management RAM chassis open or other system state related activity Intel TXT Intel Trusted Execution Technology TXT defines platform level enhancements that provide the building blocks for creating trusted platforms VCO Voltage Controlled Oscillator Datasheet Introduction Table 1 Datasheet Intel Specification intel Document Name Location Intel 3200 and 3210 Chipset Specification Update http www intel com desig
300. ing interface Default 5 Bit Access Value Description 23 16 RO 06h Base Class Code BCC Indicates the base class code for this device This code has the value 06h indicating a Bridge device 15 8 RO 04h Sub Class Code SUBCC Indicates the sub class code for this device The code is 04h indicating a to Bridge Programming Interface PI Indicates the programming interface of this 7 0 RO 00h device This value does not specify a particular register set layout and provides no practical use for this device Datasheet 153 intel Host Primary PCI Express Bridge Registers D1 FO 6 7 CL1 Cache Line Size B D F Type 0 1 0 PCI Address Offset Ch Default Value 00h Access RW Size 8 bits 4 Default Bit Access Value Description Cache Line Size Scratch pad Implemented by PCI Express devices as a 7 0 RW 00h read write field for legacy compatibility purposes but has no impact on any PCI Express device functionality 6 8 HDR1 Header Type B D F Type 0 1 0 PCI Address Offset Eh Default Value Olh Access RO Size 8 bits This register identifies the header layout of the configuration space No physical register exists at this location Default Bit Access Value Description 7 0 RO 01h Header Type Register HDR Returns 01 to indicate that this is a single function device with bridge header layout 6 9 PBUSN1 Primary Bu
301. ink Interface 5 1 32 2 5 Clocks Reset and 32 2 6 Direct Media 10111 see meses ens 33 2 7 Power and Grounds reete iets 34 3 System Address Map ode t teta Re Med ends non dia cage da 35 3 1 Legacy Address Range eive teres bebe bere Cen epi enero re EE Fai 38 3 1 1 DOS Range Oh 9 FFFEh M EAE 38 3 1 2 Expansion Area 0000 0 0122 39 3 1 3 Extended System BIOS Area 0000 39 3 1 4 System BIOS Area 0000 2 7 2 40 3 1 5 Memory Area 088 40 3 2 Main Memory Address Range 1MB 4 2 1 1 1 12 00 0 4 4 40 3 2 1 ISA Hole 15 MB 16 MB eere eret rer ne crt ene pe eer ad eo n eR 41 922 dcm M EPUM 42 3 2 3 Pre allocated Memory eias reme Eee eo Ede ess 42 3 3 PCI Memory Address Range TOLUD 4 GB 2 4 00 440 4424 4 43 3 3 1 APIC Configuration Space FECO 0000h FECF 45 3 3 2 HSEG FEDA 0000h FE
302. intel Intel 3200 and 3210 Chipset Datasheet For the Intel 3200 and 3210 Chipset Memory Controller Hub MCH November 2007 Document Number 318463 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTI CULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining critical control or safety systems or in nuclear facility applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel 3200 3210 Memory Controller Hub MCH may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current
303. irtual Channel are cleared in both Components on a Link 0 RO Ob Reserved 9 7 DMI VCIRCAP DMI VC1 Resource Capability B D F Type 0 0 0 DMI BAR Address Offset 1C 1Fh Default Value 00008001 Access RO Size 32 bits Bit Access Derauit Description Value 31 16 RO 00h Reserved Reject Snoop Transactions REJ SNPT 0 Transactions with or without the No Snoop bit set within the TLP header are 15 RO 1b allowed on this VC 1 When Set any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will be rejected as an Unsupported Request 14 8 RO 00h Reserved Port Arbitration Capability PAC Having only bit 0 set indicates that the 7 0 RO 01 only supported arbitration scheme for this VC is non configurable hardware fixed Datasheet 263 n tel Direct Media I nterface DMI RCRB 9 8 DMI VCIRCTL1 DMI VC1 Resource Control B D F Type 0 0 0 DMI BAR Address Offset 20 23h Default Value 01000000h Access RW RO Size 32 bits This register controls the resources associated with PCI Express Virtual Channel 1 2 Default E Bit Access Value Description Virtual Channel 1 Enable VCIE 31 RW Ob 0 Virtual Channel is disabled 1 Virtual Channel is enabled 30 27 RO Oh Reserved Virtual Channel 1 I D VC1ID This field assigns VC ID to the VC resource 26 24 RW 0010 Assigned value must be non zero This field can not be modified when the VC is already enabled
304. is locked and doesn t change as a result of a new error until the error flag is cleared by software Same is the case with error syndrome field but the following priority needs to be followed if more than one error occurs on one or more of the 4 QWs MERR on QWO MERR QW1 on QW2 MERR on QW1 on QW2 CERR Bit Access Default Description Value 63 48 RO P 0000h Error Column Address ERRCOL Row address of the address block of main memory of which an error single bit or multi bit error has occurred 47 32 RO P 0000h Error Row Address ERRROW Row address of the address block of main memory of which an error single bit or multi bit error has occurred Error Bank Address ERRBANK Rank address of the address block of main 31 29 RO P 000b yel memory of which an error single bit or multi bit error has occurred Error Rank Address ERRRANK Rank address of the address block of main memory of which an error single bit or multi bit error has occurred E ds 00 rank 0 DIMMO Br RO P E 01 rank 1 DIMMO 10 rank 2 DIMM1 11 rank 3 DIMM1 26 24 RO Oh Reserved 23 16 RO P 00h Error Syndrome ERRSYND Syndrome that describes the set of bits associated with the first failing quadword 15 2 RO Oh Reserved Multiple Bit Error Status MERRSTS This bit is set when an uncorrectable multiple bit error occurs on a memory read data transfer When this bit is set 1 RO
305. ite of Ob to this field has no effect A read to this register always returns a 0 10 RO Ob Power Controller Control PCC If a Power Controller is implemented this field when written sets the power state of the slot per the defined encodings Reads of this field must reflect the value from the latest write unless software issues a write without waiting for the previous command to complete in which case the read value is undefined Depending on the form factor the power is turned on off either to the slot or within the adapter Note that in some cases the power controller may autonomously remove slot power or not respond to a power up request based on a detected fault condition independent of the Power Controller Control setting The defined encodings are 0 Power On 1 Power Off If the Power Controller Implemented field in the Slot Capabilities register is set to Ob then writes to this field have no effect and the read value of this field is undefined 180 Datasheet Host Primary PCI Express Bridge Registers D1 FO tel Bit Access Default Description Value Power I ndicator Control PIC If a Power Indicator is implemented writes to this field set the Power Indicator to the written state Reads of this field must reflect the value from the latest write unless software issues a write without waiting for the previous command to complete in which case the
306. l nterrupt Status B D F Type 0 0 0 MCHBAR Address Offset CEA CEBh Default Value 0000h Access RO RWC Size 16 bits This register is used to report which specific error condition resulted the Device 0 Function 0 ERRSTS Thermal Sensor event for SMI SCI SERR or memory mapped IIR Thermal Event SW can examine the current state of the thermal zones by examining the TSS Software can distinguish internal or external Trip Event by examining EXTTSCS Software must write a 1 to clear the status bits in this register Following scenario is possible An interrupt is initiated on a rising temperature trip the appropriate DMI cycles are generated and eventually the software services the interrupt and sees a rising temperature trip as the cause in the status bits for the interrupts Assume that the software then goes and clears the local interrupt status bit in the TIS register for that trip event It is possible at this point that a falling temperature trip event occurs before the software has had the time to clear the global interrupts status bit But since software has already looked at the status register before this event happened software may not clear the local status flag for this event Therefore after the global interrupt is cleared by sw sw must look at the instantaneous status in the TSS register All bits in this register are reset to their defaults by PLTRST 137 intel DRAM Controller Registers DO FO
307. l 0000h RW RO 94 97h MA Message Address 00000000h RO RW 98 99h MD Message Data 0000h RW 0 1 CAPL PCI Express Capability List 0010h RO A2 A3h PE_CAP PCI Express Capabilities 0142h RO RWO A4 A7h DCAP Device Capabilities 00008000h RO A8 A9h DCTL Device Control 0000h RW RO AA ABh DSTS Device Status 0000h RO RWC AC AFh Link Capabilities 020214001 no RWO BO B1h LCTL Link Control 0000h pu o B2 B3h LSTS Link Status 1000h RWC RO B4 B7h SLOTCAP Slot Capabilities 00040000h RWO RO B8 B9h SLOTCTL Slot Control 0000h RO RW BA BBh SLOTSTS Slot Status 0000h RO RWC BC BDh RCTL Root Control 0000h RO RW C0O C3h RSTS Root Status 00000000h RO RWC EC EFh PELC PCI Express Legacy Control 00000000h RO RW 100 103h VCECH Virtual Channel Enhanced Capability 14010002h RO Header 104 107h PVCCAP1 Port VC Capability Register 1 00000000h RO Datasheet m e Host Primary PCI Express Bridge Registers D1 FO n tel Table 12 Host PCI Express Bridge Register Address D1 FO Sheet 3 of 3 Address Register Default Offset Symbol Register Name Value Access 108 10Bh PVCCAP2 Port VC Capability Register 2 00000000h RO PVCCTL Port VC Control 0000h RO RW 10Dh 110 113h VCORCAP VCO Resource Capability 00000001h RO 114 117h VCORCTL VCO Resource Control 800000FFh RO RW 11A 11Bh VCORSTS VCO Resource Status 0002h RO 140 143h RCLDECH Root Complex Link Declaration Enhanced
308. l Ballout Sorted By Ball Ballout Sorted By Ball Ball Signal Name Ball Signal Name Ball Signal Name AF45 DDR_A_DQ_53 AE14 EXP2_CLKINP AD4 PEG2 TXP 1 AF43 VSS AE13 PEG2 6 7 AD3 PEG2 TXN 2 7 AF42 DDR_A_DQ_52 AE12 VSS AD1 VSS AF29 VCC CL AE11 PEG2 RXN 70 AC45 DDR A DQ 51 AF28 VCC AE10 PEG2_RXP_7 4 AC43 VSS AF27 VSS AE8 VSS AC42 DDR_A_DQ_50 AF26 VCC AE7 2 87 40 DDR A DQ 60 AF25 VSS 6 PEG2 RXN 8 AC39 DDR A DQ 55 AF24 VCC AE5 PEG2 TXN AC38 VSS AF23 VSS AE4 VSS AC36 DDR B DQ 62 AF22 PEG2 TXP 2 7 AC35 VSS AF21 VSS AD45 VSS AC34 DDR_B_DQ_63 AF20 VCC AD43 DDR_A_DQS_6 AC33 DDR B DQS 7 AF19 VSS AD42 DDR A DQSB 6 AC32 VSS AF18 VCC AD40 DDR_A_DQ_54 AC31 VCC_CL AF17 VCC AD39 DDR_B_DQ_56 AC29 VCC_CL AF4 PEG2 3 AD38 VSS AC28 VCC AF3 VCCR_EXP AD36 DDR_B_DQ_57 AC27 VCC 2 4 97 AD35 DDR B DM 7 AC26 VSS AE44 DDR_A_DM_6 AD34 VSS AC25 VCC AE42 DDR A DQ 49 AD33 DDR B DQSB 7 AC24 VSS AE41 DDR A DQ 48 AD32 RSVD AC23 VCC AE40 DDR_B_DQ_54 AD31 VCC_CL AC22 VSS AE39 DDR_B_DQ_50 AD29 VCC_CL AC21 VCC AE38 DDR_B_DQ_51 AD28 VCC AC20 VSS AE36 VSS AD27 VSS AC19 VCC AE35 DDR B DQ 60 AD26 VCC AC18 VCC AE34 DDR_B_DQ 61 AD25 VSS AC17 VCC AE33 DDR_B_DQ_55 AD24 VCC 15 VCCR_EXP AE32 VSS AD23 VSS AC14 VSS AE31 VCC CL AD22 VCC PEG2 3 7 AE29 VCC CL AD21 VSS AC12 VSS AE28 VCC AD20 VCC 11 PEG2_RXP_4 27 VCC AD19 VSS AC10 PEG2 RXN 4
309. l MCH devices are selected This field is mapped to byte 6 7 3 of the request header format during PCI Express Configuration cycles and A 15 11 during the DMI configuration cycles Function Number This field allows the configuration registers of a particular function in a multi function device to be accessed The MCH R W ignores configuration cycles to its internal devices if the function number 10 8 000b is not equal to 0 or 1 This field is mapped to byte 6 2 0 of the request header format during PCI Express Configuration cycles and A 10 8 during the DMI configuration cycles Register Number This field selects one register within a particular Bus Device and Function as specified by the other fields in the Configuration 7 2 R W Address Register 00h This field is mapped to byte 7 7 2 of the request header format during PCI Express Configuration cycles and A 7 2 during the DMI Configuration cycles 1 0 Reserved 4 5 2 CONFIG_DATA Configuration Data Register Address OCFCh Default Value 00000000h Access R W Size 32 bits CONFIG DATA is a 32 bit read write window into configuration space The portion of configuration space that is referenced by CONFIG DATA is determined by the contents of CONFIG ADDRESS Bit Description Configuration Data Window CDW If bit 31 of CONFIG ADDRESS R W is 1 any I O access to the CONFIG DATA register will produce 31 0 configuration transaction using the con
310. l be accessible above 8 GB In the following sections it is assumed that all of the compatibility memory ranges reside on the DMI Interface The MCH does not remap APIC or any other memory spaces above TOLUD Top of Low Usable DRAM The TOLUD register is set to the appropriate value by BIOS The reclaim base reclaim limit registers remap logical accesses bound for addresses above 4 GB onto physical addresses that fall within DRAM The Address Map includes a number of programmable ranges Device 0 PXPEPBAR Egress port registers Necessary for setting up VC1 as isochronous channel using time based weighted round robin arbitration 4 KB window MCHBAR Memory mapped range for internal registers For example memory buffer register controls 16 KB window PCIEXBAR Flat memory mapped address spaced to access device configuration registers This mechanism can be used to access PCI configuration space 0 FFh and Extended configuration space 100h FFFh for PCI Express devices This enhanced configuration access mechanism is defined in the PCI Express specification 64 MB 128 MB or 256 MB window DMIBAR This window is used to access registers associated with the Direct Media Interface DMI register memory range 4 KB window Device 1 MBASE1 MLIMIT1 PCI Express port non prefetchable memory access window PMBASE1 PMLIMIT1 PCI Express port prefetchable memory access window PMUBA
311. ld corresponds twrp the DDR Specification Different Ranks Write To READ Delayed C1sd cr wrdr rd This field 11 8 RW 0000b indicates the minimum allowed spacing in DRAM clocks between the WRITE and READ commands to different ranks This field corresponds to in the DDR Specification 7 Same Rank Read Read Delayed C1sd_cr_rdsr_rd This field indicates 7 4 RW 00006 the minimum allowed spacing in DRAM clocks between two READ commands to the same rank Different Ranks Read To Read Delayed Cl1sd cr rd This field 3 0 RW 00006 indicates the minimum allowed spacing in DRAM clocks between two READ commands to different ranks This field corresponds to tap 118 Datasheet DRAM Controller Registers DO FO n tel 5 2 27 C1CKECTRL Channel 1 Control B D F Type 0 0 0 MCHBAR Address Offset 660 663h Default Value 000008008 Access RO RW L RW Size 32 bits Channel 1 CKE Control registers Default Bit Access Walle Description 31 28 RO Oh Reserved 27 RW Ob Start the Self Refresh Exit Sequence sd1 cr srcstart This bit indicates the request to start the self refresh exit sequence CKE Pulse Width Requirement in High Phase 541 cr cke pw hl safe 26 24 RW 000b This bit indicates pulse width requirement in high phase This field Corresponds to high the DDR Specification Rank 3 Population 541 cr rankpop3 1
312. ld indicates the 34 0 R ih supported Link speed s of the associated Port 0001b 2 5GT s Link speed supported All other encodings are reserved Datasheet 241 Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only LCTL Link Control B D F Type Address Offset Default Value Access Size 0 6 0 PCI BO B1h 0000h RO RW RW SC 16 bits This register allows control of PCI Express link Bit Access Default Value Description 15 12 RO 0000000b Reserved 11 RW Ob Link Autonomous Bandwidth Interrupt Enable When Set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to Ob 10 RW 00 Link Bandwidth Management Interrupt Enable When Set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches RO Ob Hardware Autonomous Width Disable When Set this bit disables hardware from changing the Link width for reasons other than attempting to
313. le Memory Base Address B D F Type 0 1 0 PCI Address Offset 24 25h Default Value FFF1h Access RW RO Size 16 bits This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1MB boundary Bit Access eraut Description Value Prefetchable Memory Base Address MBASE This field corresponds to 15 4 RW FFFh A 31 20 of the lower limit of the memory range that will be passed to PCI Express 64 bit Address Support This field indicates that the upper 32 bits of the 3 0 RO 1h prefetchable memory region base address are contained in the Prefetchable Memory base Upper Address register at 28h 160 Datasheet m e Host Primary PCI Express Bridge Registers D1 FO n tel 6 18 PMLI MI T1 Prefetchable Memory Limit Address B D F Type 0 1 0 PCI Address Offset 26 27h
314. lemented as an XOR chain An XOR tree is a chain of XOR gates each with one input pin connected to it which allows for pad to ball to trace connection testing The XOR testing methodology is to boot the part using straps to enter XOR mode A description of the boot process follows Once in XOR mode all of the pins of an XOR chain are driven to logic 1 This action will force the output of that XOR chain to either a 1 if the number of the pins making up the chain is even or a 0 if the number of the pins making up the chain is odd Once a valid output is detected on the XOR chain output a walking 0 pattern is moved from one end of the chain to the other Every time the walking 0 is applied to a pin on the chain the output will toggle If the output does not toggle there is a disconnect somewhere between die package and board and the system can be considered a failure XOR Test Mode Initialization XOR Test Mode Initialization Cycles CL PWROK PWROK CL_RST RSTIN STRAP PINS HCLKP GCLKP HCLKN GCLKN XOR inputs XOR output X 315 13 2 Table 30 316 ntel Testability The above figure shows the wave forms to be able to boot the part into XOR mode The straps that need to be controlled during this boot process are BSEL 2 0 RSVD Ball L18 EXP SLR and XORTEST On the 3200 and 3210 Chipset platforms all strap values must
315. llout Sorted By Name Signal Name Ball Signal Name Ball Signal Name Ball FSB DB 31 M31 FSB DSTBPB 1 H34 PEG RXN 15 N10 FSB DB 32 F31 FSB DSTBPB 2 N25 PEG RXP 0 A16 FSB DB 33 K31 FSB DSTBPB 3 C40 PEG RXP 1 B13 FSB DB 34 H31 FSB DVREF E27 PEG RXP 2 H13 FSB DB 35 M30 FSB HITB R42 PEG RXP 3 L13 FSB DB 36 L30 FSB HITMB V42 PEG RXP 4 N13 FSB DB 37 N30 FSB LOCKB T45 PEG_RXP_5 H12 FSB_DB_38 G30 FSB_RCOMP C26 PEG_RXP_6 Kil FSB_DB_39 H30 FSB_REQB_0 C44 PEG RXP 7 G10 FSB DB 40 K28 FSB REQB 1 G40 PEG RXP 8 E6 FSB DB 41 L28 FSB REQB 2 L39 PEG RXP 9 F7 FSB DB 42 N24 FSB REQB 3 K36 PEG RXP 10 D2 FSB DB 43 L25 FSB REQB 4 H39 PEG RXP 11 K7 FSB DB 44 L24 FSB RSB 0 R44 PEG RXP 12 M11 FSB DB 45 H24 FSB RSB 1 W41 PEG_RXP_13 M7 FSB_DB_46 K24 FSB_RSB_2 R41 PEG_RXP_14 K3 FSB_DB_47 G24 FSB_SCOMP D28 PEG_RXP_15 N8 FSB_DB_48 F35 FSB_SCOMPB C28 PEG TXN O E17 FSB DB 49 A38 FSB SWING A28 PEG TXN 1 D14 FSB DB 50 E41 FSB TRDYB W40 PEG_TXN_2 D12 FSB_DB_51 C42 HPL_CLKINN P30 PEG_TXN_3 12 FSB DB 52 D44 HPL CLKINP P28 PEG TXN 4 E11 FSB DB 53 D43 ICH SYNCB P16 PEG TXN 5 C10 FSB DB 54 D38 RSVD G19 PEG TXN 6 E9 FSB DB 55 B42 NC BE2 PEG_TXN_7 A8 FSB DB 56 B39 NC BD45 PEG TXN 8 C4 FSB DB 57 D39 NC BD1 PEG TXN 9 B4 FSB DB 58 C36 NC B45 PEG TXN 10 D3 FSB DB 59 D36 NC 1 11 E4 FSB_DB_60 C37 NC A44 PEG_TXN_12 G2 FSB_DB 61 E37 PEG_RXN_O B15 PEG_TXN_13 H4 FSB DB 62 B35 PEG RXN 1 14 14 K4 FSB DB 63 E35 PEG RXN 2 G13 PEG TXN 15 L2 FSB DBSYB T42 PEG R
316. lue Description 7 0 RW 00h Secondary Bus Number BUSN This field is programmed by configuration software with the bus number assigned to PCI Express 8 11 SUBUSN1 Subordinate Bus Number B D F Type 0 6 0 PCI Address Offset 1Ah Default Value 008 Access RW Size 8 bits This register identifies the subordinate bus if any that resides at the level below PCI Express This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express Default Value Description Subordinate Bus Number BUSN This register is programmed by configuration software with the number of the highest subordinate bus that lies 7 0 RW 00h behind the device 6 bridge When only a single PCI device resides on the PCI Express segment this register will contain the same value as the SBUSN1 register Datasheet 221 m tel Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 12 I OBASE1 1 O Base Address B D F Type 0 6 0 PCI Address Offset 1Ch Default Value Access RO RW Size 8 bits This register controls the processor to PCI Express 1 0 access routing based on the following formula IO BASE lt address lt LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are treated as 0 Thus the bottom of the defined 1
317. ly n tel 8 16 Note Note MLI MI T1 Memory Limit Address B D F Type 0 6 0 PCI Address Offset 22 23h Default Value 0000h Access RW RO Size 16 bits This register controls the processor to PCI Express non prefetchable memory access routing based on the following formula MEMORY BASE address MEMORY LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Memory range covered by MBASE and MLIMIT registers are used to map non prefetchable PCI Express address ranges typically where control status memory mapped 1 0 data structures of the controller will reside and PMBASE and PMLIMIT are used to map prefetchable address ranges typically device local memory This segregation allows application of USWC space attribute to be performed in a true plug and play manner to the prefetchable address range for improved processor PCI Express memory access performance Configuration software is responsible for programming all address range registers prefetchable non prefetchable with the values that provide exclusive address range
318. ly reflected in the value read from the bit regardless of actual Link state 3 RO Ob Read Completion Boundary RCB Hardwired to 0 to indicate 64 byte RW Ob Reserved Active State PM ASPM Controls the level of active state power management supported on the given link 00 Disabled 150 895 01 105 Entry Supported 10 Reserved 11 LOs and L1 Entry Supported Datasheet 243 Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only LSTS Link Status B D F Type Address Offset Default Value Access Size 0 6 0 PCI B2 B3h 1000h RWC RO 16 bits This register indicates PCI Express link status Bit Access Default Value Description 15 RWC Ob Link Autonomous Bandwidth Status LABWS This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width without the port transitioning through DL Down status for reasons other than to attempt to correct unreliable link operation This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change 14 RWC Ob Link Bandwidth Management Status LBWMS This bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status A link retraining initiated by a write of 1b to the Retrain Link bit has completed NOTE Thi
319. memory devices Supports up to 32 simultaneous open pages per channel assuming 4 ranks of 8 bank devices Supports opportunistic refresh scheme Supports Partial Writes to memory using Data Mask DM signals Supports a memory thermal management scheme to selectively manage reads and or writes Memory thermal management can be triggered either by on die thermal sensor or by preset limits Management limits are determined by weighted sum of various commands that are scheduled on the memory interface Direct Media I nterface DMI Direct Media Interface DMI is the chip to chip connection between the MCH and ICH9 This high speed interface integrates advanced priority based servicing allowing for concurrent traffic and true isochronous transfer capabilities Base functionality is completely software transparent permitting current and legacy software to operate normally To provide for true isochronous transfers and configurable Quality of Service QoS transactions the I CH9 supports two virtual channels on DMI VCO VC1 These two channels provide a fixed arbitration scheme where VC1 is always the highest priority VCO is the default conduit of traffic for DMI and is always enabled VC1 must be enabled and configured at both ends of the DMI link i e the ICH9 and MCH chip to chip connection interface to Intel 9 2 GB s point to point DMI to ICH9 1 GB s each direction 100 MHz reference clock shared with
320. mmand 13 10 y 0010b 1010 1111 Reserved 0010 1001 2 9clocks 0000 0001 Reserved 0000000 Self Refresh Exit Count sdO cr slfrfsh exit cnt This field indicates the 9 1 RW 00b Self refresh exit count Program to 255 This field corresponds to tysnp txsrap in the DDR Specification 0 RW Ob Indicates only 1 DI MM Populated sdO cr singledimmpop This field indicates the that only 1 DIMM is populated Datasheet 109 n tel DRAM Controller Registers DO FO 5 2 14 COREFRCTRL Channel 0 DRAM Refresh Control B D F Type 0 0 0 MCHBAR Address Offset 269 26Eh Default Value 021830000 30 Access RW RO Size 48 bits This register provides the settings to configure the DRAM refresh controller Bit Access Derault Description Value 47 42 RO 00h Reserved Direct Rcomp Quiet Window DI RQUI ET This configuration setting 41 37 RW 10000b indicates the amount of refresh tick events to wait before the service of rcomp request in non default mode of independent rank refresh Indirect Rcomp Quiet Window INDI RQUI ET This configuration setting 36 32 RW 110006 indicates the amount of refresh tick events to wait before the service of rcomp request in non default mode of independent rank refresh Rcomp Wait RCOMPWAIT This configuration setting indicates the amount 31 27 RW 001106 ofrefresh tick events to wait before the service of rcomp request in non default mode of indep
321. mpatible with PCI Express 1 1 Signaling Environment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant Differential voltage spec D D 2 1 2 Vmax Single ended maximum 1 25 V Single ended minimum 0 V CMOS CMOS buffers 1 5 V tolerant COD CMOS Open Drain buffers 3 3 V tolerant HVCMOS High Voltage CMOS buffers 3 3 V tolerant HVIN SSTL 1 8 High Voltage CMOS input only buffers 3 3 V tolerant Stub Series Termination Logic These are 1 8 V output capable buffers 1 8 V tolerant A Analog reference or output May be used as a threshold voltage or for buffer compensation GTL Gunning Transceiver Logic signaling technology Implements a voltage level as defined by Vmr of 1 2 V and or 1 1 V Datasheet 25 intel Signal Description 2 1 Host I nterface Signals Note Unless otherwise noted the voltage level for all signals in this interface is tied to the termination voltage of the Host Bus Vr Signal Name Type Description 1 0 Address Strobe The processor bus owner asserts FSB_ADSB FSB_ADSB GTL to indicate the first of two cycles of a request phase The MCH can assert this signal for snoop cycles and interrupt messages 1 0 Block Next Request Used to block the current request bus FSB_BNRB G owner from issuing new requests This signal is used to dynamically control the processor bus pipeli
322. mplified form Datasheet intel System Address Map System Address Ranges Figure 3 Jo peuble gi v9 0 1 gor ssouppy KOUN 59 gii N8 0 35 9 9351 0391 9351 paubre gN 9 1992 0 jsva uejis T aba N3IOIS ssalppy WNOO3H N Kiowan G IBISIANI lOd SO 90 lt NISIA SO b SseJppy Away INS pasem pouse gj 979 810 da anro Winds peubire ao 7 noL MIIA H3TIOH INOO INVHQ TVOISAHd ssolppy Kowa Ure wa 0 pepooep SSeJppy Away at amp vaiwa amp vexalod HVHN uoweyy poubie airo vepis 9 WANNA tva Dida BSVgW Bvalo3Hd3 seg g n Leonaq sva peubite giro xasyg NIV 103 NIV O38 Hsv8 annor SwopurM Anuepuedepu amp vexalod UVEHON ESVENWd seg seg Leomag amp vglo3Hd3 5
323. n chipsets specupdt 318464 htm Intel 3200 and 3210 Chipset Thermal and Mechanical Design Guide http www intel com design chipsets designex 318465 htm Dual Core Intel Xeon Processor 3000 series Thermal and Mechanical Design Guidelines http www intel com design intarch designgd 314917 htm Intel 1 O Controller Hub 9 ICH9 Family Thermal Mechanical Design Guide http www intel com design chipsets designex 316974 htm Intel 1 0 Controller Hub 9 ICH9 Family Datasheet Designing for Energy Efficiency White Paper http www intel com design chipsets datashts 316972 htm http www intel com design chipsets applnots 316970 htm Advanced Configuration and Power Interface Specification Version 2 0 http www acpi info Advanced Configuration and Power Interface Specification Version 1 0b http www acpi info The PCI Local Bus Specification Version 2 3 http www pcisig com specifications PCI Express Specification Version 1 1 http www pcisig com specifications 19 1 2 1 2 1 1 2 2 20 MCH Overview The role of a MCH in a system is to manage the flow of information between its four interfaces the processor interface the system memory interface the PCI Express interface and the I O Controller through DMI interface This includes arbitrating between the four interfaces when each initiates transactions It supports one or two channel
324. n internal link to another Root Complex Element Bit Access Derault Description Value Target Port Number TPN Specifies the port number associated with the 31 24 RO 02h element targeted by this link entry PCI Express The target port number is with respect to the component that contains this element as specified by the target component ID Target Component 10 TCI D Identifies the physical or logical component that is targeted by this link entry A value of 0 is reserved Component IDs start at 1 This value is a mirror of the value in the Component ID field of all elements 23 16 RWO 00h in this component BI OS Requirement Must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS 15 2 RO 0000h Reserved Link Type LTYP Indicates that the link points to configuration space of the 1 RO 1b integrated device which controls the root port for PCI Express The link address specifies the configuration address segment bus device function of the target root port Link Valid LV 0 RWO Ob 0 Link Entry is not valid and will be ignored 1 Link Entry specifies a valid link 5 3 5 EPLE2A EP Link Entry 2 Address B D F Type 0 0 0 PXPEPBAR Address Offset 68 6Fh Default Value 0000000000008000h Access RO Size 64 bits This register provides the second part of a Link Entry which declares an internal link to another Root Complex Element Default
325. nd must be enabled by writing a 1 to the enable field in this register This base address shall be assigned on a boundary consistent with the number of buses defined by the Length field in this register above TOLUD and still within 64 bit addressable memory space All other bits not decoded are read only O The PCI Express Base Address cannot be less than the maximum address written to the Top of physical memory register TOLUD Software must guarantee that these ranges do not overlap with known ranges located above TOLUD Software must ensure that the sum of Length of enhanced configuration region TOLUD other known ranges reserved above TOLUD is not greater than the 64 bit addressable limit of 64 GB In general system implementation and number of PCI PCI express PCI X buses supported in the hierarchy will dictate the length of the region All the Bits in this register are locked in Intel TXT mode 75 intel DRAM Controller Registers DO FO Bit Access Default Value Description 63 36 RO 0000000h Reserved 35 28 RW L OEh PCI Express Base Address PCIEXBAR This field corresponds to bits 35 28 of the base address for PCI Express enhanced configuration space BIOS will program this register resulting in a base address for a contiguous memory address space size is defined by bits 2 1 of this register This Base address shall be assigned on a boundary consistent with the number of buses define
326. ndary for rank2 of Channel 0 64 MB granularity R2 R1 RO h RO Total rankO memory size 64MB a0 903 R1 Total rank1 memory size 64MB R2 Total rank2 memory size 64MB R3 Total rank3 memory size 64MB This register is locked by ME stolen Memory lock 5 2 5 CODRB3 Channel 0 DRAM Rank Boundary Address 3 B D F Type 0 0 0 MCHBAR Address Offset 206 207h Default Value 0000 Access RO RW L Size 16 bits See CODRBO register Bit Access Default Description Value 15 10 RO 000000b Reserved Channel 0 DRAM Rank Boundary Address 3 CODRBA3 This register defines the DRAM rank boundary for rank3 of Channel 0 64 MB granularity R3 R2 R1 RO RO Total rankO memory size 64MB 29 ae R1 Total 1 memory size 64MB R2 Total rank2 memory size 64MB R3 Total rank3 memory size 64MB This register is locked by ME stolen Memory lock Datasheet 103 m n tel DRAM Controller Registers DO FO 5 2 6 CODRAO1 Channel 0 DRAM Rank 0 1 Attribute B D F Type 0 0 0 MCHBAR Address Offset 208 209h Default Value 0000h Access RW L Size 16 bits The DRAM Rank Attribute Registers define the page sizes number of banks to be used when accessing different ranks These registers should be left with their default value all zeros for any rank that is unpopulated as determined by the corresponding CxDRB registers Each byte of information in the CxD
327. ndition via SMI messaging Datasheet 139 n tel DRAM Controller Registers DO FO 5 2 52 PMSTS Power Management Status B D F Type 0 0 0 MCHBAR Address Offset F14 F17h Default Value 00000000h Access RWC S RO Size 32 bits This register is Reset by PWROK only Bit Access Default Description Value 31 9 RO 000000h Reserved Warm Reset Occurred WRO Set by the PMunit whenever a Warm Reset is received and cleared by PWROK 0 0 No Warm Reset occurred 8 RWC S Ob 1 Warm Reset occurred BIOS Requirement BIOS can check and clear this bit whenever executing POST code This way BIOS knows that if the bit is set then the PMSTS bits 1 0 must also be set and if not BIOS needs to power cycle the platform 7 2 RO 00h Reserved Channel 1 in Self Refresh CISR Set by power management hardware after Channel 1 is placed in self refresh as a result of a Power State or a Reset Warn sequence Cleared by Power management hardware before starting Channel 1 self refresh 1 RWC S Ob exit sequence initiated by a power management exit Cleared by the BIOS by writing a 1 in a warm reset Reset asserted while PWROK is asserted exit sequence 0 Channel 1 not guaranteed to be in Self Refresh 1 Channel 1 in Self Refresh Channel 0 in Self Refresh COSR Set by power management hardware after Channel 0 is placed in self refresh as a result of a Power State or a Reset Warn sequence Cleared by Power
328. ne depth Priority Agent Bus Request The MCH is the only Priority Agent on the processor bus It asserts this signal to obtain the ownership of the address bus This signal has priority over FSB_BPRIB GTL symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the FSB_LOCKB signal was asserted Bus Request 0 The MCH pulls the processor bus FSB_BREQOB signal low during FSB_CPURSTB The processors sample this signal the active to inactive transition of FSB_BREQOB G FSB_CPURSTB The minimum setup time for this signal is 4 HCLKs The minimum hold time is 2 HCLKs and the maximum hold time is 20 HCLKs FSB_BREQOB should be tristated after the hold time requirement has been satisfied CPU Reset The FSB_CPURSTB pin is an output from the MCH The asserts FSB_CPURSTB while RSTINB PCIRST from FSB_CPURSTB G the ICH is asserted and for approximately 1 ms after RSTINB Te is de asserted The FSB_CPURSTB allows the processors to begin execution in a known state 1 0 Data Bus Busy Used by the data bus owner to hold the data FSB_DBSYB m GTL bus for transfers requiring more than one cycle Defer Signals that the will terminate the transaction FSB_DEFERB G currently being snooped with either a deferred response or with TEE a retry response Dynamic Bus Inversion Driven along with the FSB DB 63 0 signals Indicates if the associated signals are inverted
329. ng in DRAM clocks between two commands to the same rank PRE to ACT Delayed COsd cr pre act This field indicates the minimum allowed spacing in DRAM clocks between the PRE and ACT commands to the same rank bank 12 9R WO0O000bPRE ALL to ACT Delayed 15 24 RW 00009 COsd_cr_preall_act This configuration register indicates the minimum allowed spacing in DRAM clocks between the PRE ALL and ACT commands to the same rank 12 9 RO Oh Reserved 0000000 REF to ACT Delayed COsd cr rfsh act This configuration register 8 0 RW 00b indicates the minimum allowed spacing in DRAM clocks between REF and ACT commands to the same rank 5 2 39 EPDCYCTRKWRTWR EPD CYCTRK WRT WR B D F Type 0 0 0 MCHBAR Address Offset A20 A21h Default Value 0000h Access RW RO Size 16 bits EPD CYCTRK WRT WR Status registers Bit Access Detault Description Value To Write Delay COsd cr act wr This field indicates the minimum 15 12 RW Oh allowed spacing in DRAM clocks between the ACT and WRITE commands to the same rank bank Same Rank Write To Write Delayed COsd cr wrsr wr This field 11 8 RW Oh indicates the minimum allowed spacing in DRAM clocks between two WRITE commands to the same rank 7 4 RO Oh Reserved Same Rank WRITE to READ Delay COsd cr rd wr This field indicates the 3 0 RW Oh minimum allowed spacing in DRAM clocks between the WRITE and READ commands to the same rank 126 Datasheet m e DRAM Controlle
330. ng interrupt to Host Reset Host system Reset or 03 gt 00 transition Datasheet 207 n tel Intel Manageability Engine Subsystem PCI D3 FO F3 7 2 7 KTFCR KT FIFO Control B D F Type 0 3 3 KT MM IO Address Offset 2h Default Value 008 Access WO Size 8 bits When Host writes to this address it writes to the KTFCR The FIFO control Register of the serial interface is used to enable the FIFO s set the receiver FIFO trigger level and clear FIFO s under the direction of the Host When Host reads from this address it reads the KTIIR Note Reset Host System Reset or D3 gt D0 transition 5 Default Pr Bit Access Value Description Receiver Trigger Level RTL Trigger level in bytes for the RCV FIFO Once the trigger level number of bytes is reached an interrupt is sent to the Host 6 Gab 00 01 IR di Ob 1 04 10 08 11 14 5 4 00b Reserved 3 WO Ob RDY Mode RDYM This bit has no affect on hardware performance 2 WO Ob XMT FI FO Clear XFI C When the Host writes one to this bit the hardware will clear the XMT FIFO This bit is self cleared by hardware 1 WO Ob RCV FI FO Clear RFI C When the Host writes one to this bit the hardware will clear the RCV FIFO This bit is self cleared by hardware FI FO Enable Fl E When set this bit indicates that the KT interface is working 0 WO Ob in FIFO node When this bit value is changed the RCV and XMT FIFO are clear
331. nge EPKTBAR 2 Addresses decoded to the ME HECI MMIO range EPHECIBAR 3 Addresses decoded to the ME HECI2 MMIO range EPHECI2BAR Some of the MMIO Bars may be mapped to this range or to the range above TOUUD There are sub ranges within the PCI Memory address range defined as APIC Configuration Space FSB Interrupt Space and High BIOS Address Range The exceptions listed above for the PCI Express ports MUST NOT overlap with these ranges Datasheet 43 Figure 7 44 PCI Memory Address Range System Address Map FFFF FFFFh FFEO 0000h FEFO 0000h FEEO 0000h FEDO 0000h FEC8 0000h FECO 0000h 000 0000h E000 0000h High BIOS 4GB 4 GB 2MB DMI Interface subtractive decode 4 GB 17 MB FSB Interrupts DMI Interface subtractive decode 4 GB 18 MB Local CPU APIC 4 GB 19 MB Optional HSEG FEDA 0000h to APIC FEDB_FFFFh 4 GB 20 MB DMI Interface subtractive decode PCI Express Configuration Space DMI Interface subtractive decode 4 GB 256 MB Possible address range size not ensured 4 GB 512 MB BARs and PCI Express Port could be here TOLUD Datasheet m e System Address Map n tel 3 3 1 3 3 2 3 3 3 3 3 4 Datasheet APIC Configuration Space FECO 0000h FECF_FFFFh This range is reserved for APIC configuration space The I O APIC s usually reside the ICH
332. nit Notes Reference Voltages Host Data Address and 0 666 x 0 666 x Ee ae OPE Common Clock Signal VTT_FSB 2 VTT_FSB V Reference Voltages 2 2 0 25 x Host Compensation 0 25 x VIT FSB 0 25 x FSB SWING Reference Voltage 2 VTT_FSB 2 Controller Link Reference 0 270 x 0 279 x 0 287 x CL VREF Voltage VCC CL VCC CL VCC CL 0 49 0 50 x 0 51 x DDR_VREF DDR2 Reference Voltage VCC DDR VCC DDR VCC DDR V Host I nterface 0 666 x H Host GTL Input Low Voltage 0 10 0 VTT_FSB V 0 1 Host GTL Input High 0 666 x Voltage VIT_FSB 0 1 VTT_FSB VTT_FSB 0 1 V 0 25 x ioe Host GTL Output Low u u VIT FSB V Voltage 0 1 Host GTL Output High u Voltage VTT_FSB 0 1 VTT_FSB V i Host GTL Output Low asa Current Me 47 5 Rttmin lt Input Leakage m 45 uA Vpad lt Vtt_FSB Cpap Host GTL Input Capacitance 2 0 2 5 pF Host GTL Input Capacitance Cece common clock 0 30 2 pr DDR2 System Memory I nterface DDR VREF DDR2 Input Low Voltage m 0 125 V DDR_VREF DDR2 Input High Voltage 0 125 V ViL AC DDR2 Input Low Voltage oro V 0 20 Visti DDR2 Input High Voltage a V V DDR2 Output Low Voltage _ 0 2 V 1 oL p4 9 VCC_DDR Vou DDR2 Output High Voltage 0 8 VCC_DDR V 1 l Leak Input Leakage Current 20 4 l Leak Input Leakage Current 550 5 286 Datasheet El
333. nnected by hardware to the value of MCR bit 1 Delta Data Carrier Detect DDCD This bit is set when bit 7 is changed This 3 RO CR Ob bit is cleared by hardware when the MSR register is being read by the HOST driver Trailing Edge of Read Detector TERI This bit is set when bit 6 is changed 2 RO CR Ob from 1 to 0 This bit is cleared by hardware when the MSR register is being read by the Host driver 1 RO CR Ob Delta Data Set Ready DDSR This bit is set when bit 5 is changed This bit is cleared by hardware when the MSR register is being read by the Host driver 0 RO CR Ob Delta Clear To Send DCTS This bit is set when bit 4 is changed This bit is cleared by hardware when the MSR register is being read by the Host driver 7 2 12 KTSCR KT Scratch B D F Type 0 3 3 KT MM IO Address Offset 7h Default Value 00h Access RW Size 8 bits This register has no affect on hardware This is for the programmer to hold data temporarily Note Reset Host system reset or D3 gt D0 transition Bit Access eraut Description Value 7 0 RW 00h Scratch Register Data SCRD 212 88 Datasheet m Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only tel 8 Note Warning Note Table 15 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only The Device 6 register descriptions provided in this chapter applies only to the 3210 MCH in dual x8 mode
334. not remapped It is simply made visible 2 0 RO 0100 if the conditions are right to access SMM space otherwise the access is forwarded to DMI Since the MCH supports only the SMM space between A0000 and BFFFF this field is hardwired to 010b 86 Datasheet m DRAM Controller Registers DO FO n tel 5 1 28 ESMRAMC Extended System Management RAM Control B D F Type 0 0 0 PCI Address Offset 9Eh Default Value 38h Access RW L RWC RO Size 8 bits The Extended SMRAM register controls the configuration of Extended SMRAM space The Extended SMRAM E_SMRAM memory provides a write back cacheable SMRAM memory space that is above 1 MB Bit Access Default Description Value Enable High SMRAM H_SMRAME This bit controls the SMM memory space location i e above 1 MB or below 1 MB When G_SMRAME is 1 and H_SMRAME 7 RW L Ob is set to 1 the high SMRAM memory space is enabled SMRAM accesses within the range OFEDAO000h to OFEDBFFFFh are remapped to DRAM addresses within the range 000A0000h to OOOBFFFFh Once D_LCK has been set this bit becomes read only Invalid SMRAM Access E SMERR This bit is set when processor has 6 RWC Ob accessed the defined memory ranges in Extended SMRAM High Memory and T segment while not in SMM space and with the D OPEN bit 0 It is software s responsibility to clear this bit The software must write a 1 to this bit to clear it RO 1b SMRAM Cacheable SM_CACHE This
335. nterface signals These signals are compatible with PCI Express 1 0 DMI Signaling Environment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant Differential voltage spec D D 2 1 2 Vmax Single ended maximum 1 25 V Single ended minimum 0 V GTL Open Drain GTL interface signal Refer to the GTL 1 0 Specification for complete details Host Clock Signal Level buffers Current mode differential pair Differential typical HCSL swing D D 2 1 4 V Single ended input tolerant from 0 35 V to 1 2 V Typical crossing voltage 0 35 V Stub Series Termination Logic These are 1 8 V output capable buffers 1 8 V SSTL 1 8 tolerant CMOS CMOS buffers Anais Analog reference or output May be used as a threshold voltage or for buffer 9 compensation Datasheet Electrical Characteristics Table 25 Datasheet Signal Groups Signal Type Signals Host I nterface Signal Groups Notes GTL Input Outputs FSB_ADSB FSB_BNRB FSB_DBSYB FSB_DINVB_3 0 FSB DRDYB FSB AB 35 3 FSB_ADSTBB_1 0 FSB DB 63 0 FSB DSTBPB 3 0 FSB DSTBNB 3 0 FSB HITB FSB HITMB FSB REQB 4 0 GTL Common Clock Outputs FSB BPRIB FSB BREQOB FSB CPURSTB FSB DEFERB FSB TRDYB FSB RSB 2 0 Analog Host I F Ref amp Comp Signals FSB RCOMP FSB SCOMP FSB SCOMPB FSB SWING FSB DVREF FSB ACCVREF GTL Input FSB LOCKB BSEL2 0 PCI Express Graphics I nterface Signal Groups
336. o chip connection between the MCH and ICH The chipset requires that Clink is connected in the platform Core The internal base logic in the MCH DBI Dynamic Bus Inversion DDR2 A second generation Double Data Rate SDRAM memory technology Introduction Term Description Direct Media Interface is a proprietary chip to chip connection between the DMI MCH and ICH This interface is based on the standard PCI Express specification A collection of physical logical or virtual resources that are allocated to work Domain together Domain is used as a generic term for virtual machines partitions etc EP PCI Express Egress Port FSB Front Side Bus Synonymous with Host or processor bus Full Reset Full reset is when PWROK is de asserted Warm reset is when both RSTIN and PWROK are asserted Memory Controller Hub component that contains the processor interface MCH DRAM controller and PCI Express port It communicates with the 1 0 controller hub Intel ICH9 over the DMI interconnect Host This term is used synonymously with processor An interrupt request signal where X stands for interrupts D Ninth generation 1 Controller Hub component that contains the primary PCI Intel 1CH9 interface LPC interface USB2 0 SATA and other 1 0 functions For this the term ICH refers to the 9 10Q In Order Queue Message Signaled Interrupt A transaction conveying interrupt
337. o the run behind This will likely result in a resulting in a contract violation due to the MCH egress port taking too long to 13 RWC S Ob service the isochronous request If this bit is already set then a interrupt message will not be sent on a new error event 12 RO Ob Reserved MCH Thermal Sensor Event for SMI SCI SERR GTSE This bit indicates that a MCH Thermal Sensor trip has occurred and an SMI SCI or SERR has been generated The status bit is set only if a message is sent based on Thermal event 11 RWC S Ob enables in Error command SMI command and SCI command registers A trip point can generate one of SMI SCI or SERR interrupts two or more per event is illegal Multiple trip points can generate the same interrupt if software chooses this mode subsequent trips may be lost If this bit is already set then an interrupt message will not be sent on a new thermal sensor event 10 RO Ob Reserved 9 RWC S Ob LOCK to non DRAM Memory Flag LCKF When this bit is set to 1 the MCH has detected a lock operation to memory space that did not map into DRAM 8 RO Ob Reserved DRAM Throttle Flag DTF 7 RWC S Ob 1 Indicates that a DRAM Throttling condition occurred 0 Software has cleared this flag since the most recent throttling event 6 2 RO 00h Reserved Datasheet 91 m n tel DRAM Controller Registers DO FO Bit Access perault Description Value Multiple bit DRAM ECC Error Flag DMERR If this bit is
338. ocations Note that the upper 3 locations can be accessed only during I O address wrap around when processor bus HAB 16 address signal is asserted HAB 16 is asserted on the processor bus whenever an 1 access is made to 4 bytes from address OFFFDh OFFFEh or OFFFFh HAB 16 is also asserted when 1 0 access is made to 2 bytes from address OFFFFh The 1 0 accesses other than ones used for configuration space access are forwarded normally to the DMI Interface bus unless they fall within the PCI Express 1 0 address range as defined by the mechanisms explained below I O writes are NOT posted Memory writes to or PCI Express are posted The PCICMD1 register can disable the routing of I O cycles to the PCI Express The responds 1 0 cycles initiated on PCI Express DMI with an UR status Upstream 1 cycles and configuration cycles should never occur If one does occur the request will route as a read to Memory address 000C 0000h so a completion is naturally generated whether the original request was a read or write The transaction will complete with an UR completion status reads that lie within 8 byte boundaries but cross 4 byte boundaries are issued from the processor as 1 transaction The MCH will break this into 2 separate transactions I O writes that lie within 8 byte boundaries but cross 4 byte boundaries are assumed to be split into 2 transactions by the processor Datasheet e System Address Map
339. ock mode 0110 enabled 4096 clock mode 0111 enabled 6144 clock mode provides 23 1 us settling time 266 MHz provides 18 5 us settling time 333 MHz provides 15 4 us settling time 400 MHz all other permutations reserved 1111 enabled 4 clock mode for testing digital logic Datasheet 133 n tel DRAM Controller Registers DO FO 5 2 46 TSS Thermal Sensor Status B D F Type 0 0 0 MCHBAR Address Offset CDAh Default Value 001 Access RO Size 8 bits This read only register provides trip point and other status of the thermal sensor All bits in this register are reset to their defaults by MPWROK Bit Access Default Description Value Catastrophic Trip Indicator CTI A 1 indicates that the internal thermal d RO Ob sensor temperature is above the catastrophic setting Hot Trip Indicator HTI A 1 indicates that the internal thermal sensor B RO 95 temperature is above the Hot setting AuxO Trip Indicator AOTI A 1 indicates that the internal thermal sensor temperature is above the 0 setting Thermometer Mode Output Valid TOV A 1 indicates the Thermometer mode is able to converge to a temperature and that the TR register is reporting a reasonable estimate of the thermal sensor temperature A 0 indicates the Thermometer mode is off or that temperature is out of range or that the TR register is being looked at before a temperature conversion has had time to complete 3
340. ocks At 200 266 333MHz bus clock the data signals run at 800 1066 1333MT s for a maximum bandwidth of 6 4 8 5 10 6GB s 10 1 1 FSB 109 Depth The Scalable Bus supports up to 12 simultaneous outstanding transactions 10 1 2 FSB OOQ Depth The MCH supports only one outstanding deferred transaction on the FSB 10 1 3 FSB GTL Termination The MCH integrates GTL termination resistors on die 10 1 4 FSB Dynamic Bus Inversion The MCH supports Dynamic Bus Inversion DBI when driving and when receiving data from the processor DBI limits the number of data signals that are driven to a low voltage on each quad pumped data phase This decreases the worst case power consumption of the HDINV 3 0 indicate if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase HDINV 3 0 Data Bits HDINVO HD 15 0 HDINV1 HD 31 16 HDINV2 HD 47 32 HDINV3 HD 63 48 When the processor or the MCH drives data each 16 bit segment is analyzed If more than 8 of the 16 signals would normally be driven low on the bus the corresponding HDINV signal will be asserted and the data will be inverted prior to being driven on the bus When the processor or the MCH receives data it monitors HDINV 3 0 to determine if the corresponding data segment should be inverted Datasheet 267 intel Table 17 10 1 5 268 Host Interface 4X 2X and 1X Signal Groups
341. of the settings of the uncorrectable error mask register 0 RWC Ob Correctable Error Detected CED When set this bit indicates that correctable error s were detected Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the correctable error mask register Datasheet 239 Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only LCAP Link Capabilities B D F Type Address Offset Default Value Access Size 0 6 0 PCI AC AFh 03214D01h RO RWO 32 bits This register indicates PCI Express device specific capabilities Bit Access Default Value Description 31 24 RO 03h Port Number PN This field indicates the PCI Express port number for the given PCI Express link Matches the value in Element Self Description 31 24 23 22 21 RO RO 000b 1b Reserved Link Bandwidth Notification Capability A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms This capability is required for all Root Ports and Switch downstream ports supporting Links wider than x1 and or multiple Link speeds This field is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches
342. or DPE Not Applicable or Implemented Hardwired to 0 15 RO Ob Parity generating poisoned Transaction Layer Packets is not supported on the primary side of this device Signaled System Error SSE This bit is set when this Device sends a SERR 14 RWC Ob due to detecting an ERR FATAL or ERR NONFATAL condition and the SERR Enable bit in the Command register is 1 Both received if enabled by BCTRL1 1 and internally detected error messages do not affect this field Received Master Abort Status RMAS Not Applicable or Implemented 13 RO Ob Hardwired to 0 The concept of a master abort does not exist on primary side of this device Received Target Abort Status RTAS Not Applicable or Implemented 12 RO Ob Hardwired to 0 The concept of a target abort does not exist on primary side of this device Signaled Target Abort Status STAS Not Applicable or Implemented 11 RO Ob Hardwired to 0 The concept of a target abort does not exist on primary side of this device DEVSELB Timing DEVT This device is not the subtractively decoded device 10 9 RO 00b on bus 0 This bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode Master Data Parity Error PMDPE Because the primary side of the PCI Express s virtual peer to peer bridge is integrated with the MCH functionality there is no scenario where this bit will get set Because hardware will never set this bit it is impossible for software to have an oppor
343. or PCI Express registers 170 Datasheet Host Primary PCI Express Bridge Registers D1 FO tel 6 34 CAP PCI Express Capabilities B D F Type 0 1 0 PCI Address Offset A2 A3h Default Value 0142 Access RO RWO Size 16 bits This register indicates PCI Express device capabilities Default Bit Access Value Description 15 14 RO 00b Reserved 13 9 RO 00h Interrupt Message Number IMN Not Applicable or Implemented Hardwired to 0 Slot Implemented SI 0 The PCI Express Link associated with this port is connected to an integrated 8 RWO 1b component or is disabled 1 The PCI Express Link associated with this port is connected to a slot Device Port Type DPT Hardwired to 4h to indicate root port of PCI Express 7 4 RO 4h Root Complex 3 0 RO 2h PCI Express Capability Version PCI ECV Hardwired to 2h to indicate compliance to the Express Capabilities Register Expansion 6 35 DCAP Device Capabilities B D F Type 0 1 0 PCI Address Offset A4 A7h Default Value 00008000h Access RO Size 32 bits This register indicates PCI Express device capabilities z Default Bit Access Value Description 31 16 RO 0000h Reserved Role Based Error Reporting RBER Role Based Error Reporting RBER 15 RO 1b Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the P
344. ose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1MB aligned memory block Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC i e prefetchable from the processor perspective Bit Default Value Description 0000000 Prefetchable Memory Address Limit MLI MI TU This field corresponds to RW Oh A 63 32 of the upper limit of the prefetchable Memory range that will be passed to PCI Express Datasheet 229 m n tel Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 21 CAPPTR1 Capabilities Pointer B D F Type 0 6 0 PCI Address Offset 34h Default Value 88h Access RO Size 8 bits The capabilities pointer provides the address offset to the location of the first entry in this device s linked list of capabilities Bit Access Default Description Value 7 0 RO 88h First Capability CAPPTR1 The first capability in the list is the Subsystem ID Subsystem Vendor ID Capability 8 22 I NTRLI NE1 I nterrupt Line B D F Type 0 6 0 PCI Address Offset 3Ch Default Value 008 Access RW Size 8 bits This register contains interrupt line routing information The device itself
345. ove both Stolen memory and TSEG BIOS determines the base of Stolen Memory by subtracting the Stolen Memory Size from TOLUD and further decrements by TSEG size to determine base of TSEG All the Bits in this register are locked in Intel TXT mode This register must be 64 MB aligned when reclaim is enabled 3 0 RO 0000b Reserved 90 Datasheet DRAM Controller Registers DO FO n tel 5 1 34 ERRSTS Error Status B D F Type 0 0 0 PCI Address Offset C8 C9h Default Value 0000 Access RWC S RO Size 16 bits This register is used to report various error conditions via the SERR DMI messaging mechanism An SERR DMI message is generated on a zero to one transition of any of these flags if enabled by the ERRCMD and PCICMD registers These bits are set regardless of whether or not the SERR is enabled and generated After the error processing is complete the error logging mechanism can be unlocked by clearing the appropriate status bit by software writing a 1 to it Bit Access Description Value 15 RO Ob Reserved Isochronous TBWRR Run Behind FIFO Full I TCV If set this bit indicates a VC1 TBWRR is running behind resulting in the slot timer to stop until the 14 RWC S Ob request is able to complete If this bit is already set then a interrupt message will not be sent on a new error event Isochronous TBWRR Run behind FIFO Put I TSTV If set this bit indicates a VC1 TBWRR request was put int
346. ow mapping of configuration cycles to PCI Express Default NN Bit Access Value Description Subordinate Bus Number BUSN This register is programmed by configuration software with the number of the highest subordinate bus that lies 7 0 RW 00h behind the device 1 bridge When only a single PCI device resides on the PCI Express segment this register will contain the same value as the SBUSN1 register Datasheet 155 m n tel Host Primary PCI Express Bridge Registers D1 FO 6 12 I OBASE1 1 O Base Address B D F Type 0 1 0 PCI Address Offset 1Ch Default Value FOh Access RO RW Size 8 bits This register controls the processor to PCI Express 1 0 access routing based on the following formula IO BASE address 40 LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are treated as 0 Thus the bottom of the defined 1 address range will be aligned to a 4 KB boundary Default oo ae Bit Access Value Description 1 Address Base I OBASE Corresponds to A 15 12 of the I O addresses 7 4 RW Fh passed by bridge 1 to PCI Express 3 0 RO Oh Reserved 6 13 I OLI MIT1 I Limit Address B D F Type 0 1 0 PCI Address Offset 1Dh Default Value 00h Access RW RO Size 8 bits This register controls the processor to PCI Express 1 0 access routing based on the following formula IO BASE address lt LIMIT
347. porting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the uncorrectable error mask register RWC Ob Non Fatal Error Detected NFED When set this bit indicates that non fatal error s were detected Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the uncorrectable error mask register RWC Ob Correctable Error Detected CED When set this bit indicates that correctable error s were detected Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the correctable error mask register Datasheet 173 Host Primary PCI Express Bridge Registers D1 FO LCAP Link Capabilities B D F Type Address Offset Default Value Access Size 0 1 0 PCI AC AFh 02214D01h RO RWO 32 bits This register indicates PCI Express device specific capabilities Bit Access Default Value Description 31 24 RO 02h Port Number PN This field indicates the PCI Express port number for the given PCI Express link Matches the value
348. portion of the chipset IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be populated in the system Since it is difficult to relocate an interrupt controller using plug and play software fixed address decode regions have been allocated for them Processor accesses to the default IOAPIC region FECO 0000h to FEC7 FFFFh are always forwarded to DMI The optionally supports additional 1 APICs behind the PCI Express port When enabled via the PCI Express Configuration register Device 1 Offset 200h the PCI Express port will positively decode a subset of the APIC configuration space specifically FEC8 0000h thru FFFFh Memory request to this range would then be forwarded to the PCI Express port When disabled any access within entire APIC Configuration space FECO 0000h to FECF FFFFh is forwarded to DMI HSEG FEDA 0000h FEDB FFFFh This optional segment from FEDA 0000h to FEDB FFFFh provides a remapping window to SMM Memory It is sometimes called the High SMM memory space SMM mode processor accesses to the optionally enabled HSEG are remapped to 000A 0000h 000 FFFFh Non SMM mode processor accesses to enabled HSEG are considered invalid and are terminated immediately on the FSB The exceptions to this rule are Non SMM mode Write Back cycles which are remapped to SMM space to maintain cache coherency PCI Express and DMI originated cycles to enabled SMM space are not allowed Physi
349. ppr2 1 8 V Supply Current VCC_DDR 2 06 2 57 A DDR2 System Memory Clock Interface 5 lvcc cKDDR2 1 8 V Supply Current VCC CKDDR 521 581 mA 2 Express DMI Supply VCC_EXP 5 12 6 65 A 2 lvcc cL 1 25 V Controller Supply Current VCC CL 2 20 2 80 A 2 _ 5 System Bus Supply Current VTT_FSB 387 580 mA 1 3 3 V PCI Express and DMI Analog 1 _ Supply Current VCCA_EXP 167 175 mA IVCC3 3 3 3 V CMOS Supply Current VCC3 3 0 5 16 mA 1 25 V PCI Express and DMI PLL I VCCAPLL EXP Anal g Supply Current VCCAPLL_EXP 48 53 mA lVCCA_HPLL 1 25 V Host PLL Supply Current VCCA_HPLL 18 26 mA 1 25 V System Memory PLL Analog Ivoca MPLL Supply Current VCCA_MPLL 97 146 mA NOTES 1 Measurements are for current coming through chipset s supply pins 2 Rail includes DLLs and FSB sense amps on VCC 3 Sustained Measurements are combined because one voltage regulator on the platform supplies both rails on the MCH Datasheet 281 282 Electrical Characteristics Signal Groups The signal description includes the type of buffer used for the particular signal Type Description PCI Express interface signals These signals are compatible with PCI Express 2 0 PCI Signaling Environment AC Specifications and are AC coupled The buffers are not Express 3 3 V tolerant Differential voltage spec D D 2 1 2Vmax Single ended maximum 1 25 V Single ended minimum 0 V Direct Media I
350. program this value to be cumulative of ChO DRB3 This register is locked by ME stolen Memory lock 5 2 19 CIDRB2 Channel 1 DRAM Rank Boundary Address 2 B D F Type 0 0 0 MCHBAR Address Offset 604 605h Default Value 0000h Access RW L RO Size 16 bits The operation of this register is detailed in the description for CODRBO register Default Bit Access Value Description 15 10 RO 000000b Reserved Channel 1 DRAM Rank Boundary Address 2 CIDRBA2 See CODRB2 register 9 0 RW L 000h In stacked mode if this is the topmost populated rank in Channel 1 program this value to be cumulative of ChO DRB3 This register is locked by ME stolen Memory lock 114 Datasheet DRAM Controller Registers DO FO 5 2 20 B D F Type Address Offset 0000h Default Value Access Size intel C1DRB3 Channel 1 DRAM Rank Boundary Address 3 0 0 0 MCHBAR 606 607 RW L RO 16 bits The operation of this register is detailed in the description for CODRBO register Default Bit Value Access Description 15 10 RO 000000b Reserved 9 0 RW L 000h Channel 1 DRAM Rank Boundary Address 3 CIDRBA3 See CODRB3 register In stacked mode this will be cumulative of ChO DRB3 This register is locked by ME stolen Memory lock 5 2 21 B D F Type Address Offset Default Value Access Size The operation C1DRA01 Channel 1 DRAM Rank 0 1 Attributes 0
351. r Registers DO FO n tel 5 2 40 EPDCYCTRKWRTREF EPD CYCTRK WRT REF B D F Type 0 0 0 MCHBAR Address Offset A22 A23h Default Value 0000h Access RO RW Size 16 bits BIOS Optimal Default Oh EPD CYCTRK WRT ACT Status registers Default 4222 Bit Access Value Description 15 9 RO Os Reserved 0000000 Different Rank REF to REF Delayed COsd_cr_rfsh_rfsh This 8 0 RW 00b configuration register indicates the minimum allowed spacing in DRAM clocks between two REF commands to different ranks 5 2 41 EPDCYCTRKWRTRD EPD CYCTRK WRT READ B D F Type 0 0 0 MCHBAR Address Offset A24 A26h Default Value 000000h Access RW Size 24 bits BIOS Optimal Default 000h EPD CYCTRK WRT RD Status registers Default gu Bit Access Value Description 23 23 RO Oh Reserved 22 20 RW 000b EPDunit DQS Slave DLL Enable to Read Safe EPDSDLL2RD Configuration setting for Read command safe from the point of enabling the slave DLLs 19 18 RO Oh Reserved Min ACT To READ Delayed COsd_cr_act_rd This field indicates the 17 14 RW Oh minimum allowed spacing in DRAM clocks between the ACT and READ commands to the same rank bank Same Rank READ to WRITE Delayed COsd cr wrsr rd This field 13 9 RW 000000 indicates the minimum allowed spacing in DRAM clocks between the READ and WRITE commands 8 6 RO Oh Reserved Same Rank Read To Read Delayed COsd cr rdsr rd This field indicates 5 3 RW 000b
352. ram 211 eene 16 2 Intel 3200 Chipset System Diagram Exaimiple i rrr ter rto o ti o 17 3 System Address Ranges iocos tex ox me Ex EX ER RUE themed ceed TRI EXE REERUMERYR 37 4 DOS Legacy Address 38 5 Main Memory Address 1 1 1 41 6 Pre allocated Memory Example for 64 DRAM 1 MB stolen and 1 42 7 PCI Memory Address Range 01001111 44 8 Conceptual Platform PCI Configuration Diagram 57 9 Memory to PCI Express Device Configuration 60 10 Configuration Cycle Flow 1 61 11 System Clocking Diagram mess 277 12 Ballout Diagram Top View Left Columns 45 31 290 13 Ballout Diagram Top View Middle Columns 30 16 291 14 Ballout Diagram Top View Left Columns 15 1 2 292 15 Package Drawing wri iR wars 313 16 XOR Test Mode Initialization Cycles 10
353. range Seven Programmable Attribute Map PAM Registers are used to support these features Cacheability of these areas is controlled via the MTRR registers in the processor Two bits are used to specify memory attributes for each memory segment These bits apply to both host accesses and PCI initiator accesses to the PAM areas These attributes are RE Read Enable When RE 1 the processor read accesses to the corresponding memory segment are claimed by the MCH and directed to main memory Conversely when RE 0 the host read accesses are directed to PCI A WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the MCH and directed to main memory Conversely when WE 0 the host write accesses directed to PCI A The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only Each PAM Register controls two regions typically 16 KB in size Note that the MCH may hang if a PCI Express Link Attach or DMI originated access to Read Disabled or Write Disabled PAM segments occur due to a possible IWB to non DRAM For these reasons the following critical restriction is placed on the programming of the PAM regions At the time that a DMI or PCI Express Link Attach accesses to the PAM region may occur the targeted PAM segment must be programmed to be both readable
354. raut Description Value 15 10 RO 000000b Reserved Channel 0 Dram Rank Boundary Address 0 CODRBAO This register defines the DRAM rank boundary for rankO of Channel 0 64 MB granularity RO 9 h RO Total rankO memory size 64MB 5 009 R1 Total rank1 memory size 64MB R2 Total rank2 memory size 64MB R3 Total rank3 memory size 64MB This register is locked by ME stolen Memory lock 5 2 3 CODRB1 Channel 0 DRAM Rank Boundary Address 1 B D F Type 0 0 0 MCHBAR Address Offset 202 203h Default Value 0000h Access RW L RO Size 16 bits See CODRBO register Default n Sed Bit Access Value Description 15 10 RO 000000b Reserved Channel 0 Dram Rank Boundary Address 1 CODRBA1 This field defines the DRAM rank boundary for rank1 of Channel 0 64 MB granularity 1 RO i 60h RO Total rankO memory size 64MB 9 RE 009 R1 Total rank1 memory size 64MB R2 Total rank2 memory size 64MB R3 Total rank3 memory size 64MB This register is locked by ME stolen Memory lock 102 Datasheet m e DRAM Controller Registers DO FO n tel 5 2 4 CODRB2 Channel 0 DRAM Rank Boundary Address 2 B D F Type 0 0 0 MCHBAR Address Offset 204 205h Default Value 0000 Access RW L RO Size 16 bits See CODRBO register Bit Access Derault Description Value 15 10 RO 000000b Reserved Channel 0 DRAM Rank Boundary Address 2 CODRBA2 This register defines the DRAM rank bou
355. rded to 1 0 RW L 00b EM T e 10 Write Only All writes sent to DRAM Reads serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet 83 DRAM Controller Registers DO FO 5 1 23 PAM6 Programmable Attribute Map 6 B D F Type 0 0 0 PCI Address Offset 96h Default Value 00 Access RO RW L Size 8 bits This register controls the read write and shadowing attributes of the BIOS areas from OE8000h OEFFFFh Default Bit Access Value Description 7 6 RO 00b Reserved OECOOOh OEFFFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OE4000h to OE7FFFh 00 DRAM Disabled Accesses are directed to DMI 5 4 RW L 00b 01 Dur Only All reads are serviced by DRAM All writes are forwarded to 10 Write Only All writes are sent to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 3 2 RO 00b Reserved OE8000h OEBFFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0 0000 to OE3FFFh 00 DRAM Disabled Accesses are directed to DMI 1 0 RW L 00b 01 2 Only All reads serviced by DRAM All writes are forwarded to 10 Write Only All writes are sent to DRAM Reads are serviced by D
356. rne tereti rae Rx en up RR CURE RR RE 212 Datasheet 7 7 212 KTISCR KT Scratch 212 8 Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only tri ort cirea a rei d c bine nde ERN 213 81 VID1 Vendor Identification rennen ERE CERE KR RR No RR 215 8 2 DID1 Device m meses 216 8 3 PCICMDI PCI Command 2 eia ur x Rx RUF EE EN M 216 8 4 PCISTST PGI Status eet RR ERRARE NERA NR 218 8 5 RID1 Revision Identification 111 219 8 6 CCIl CGlass Code sii nee bee Ur LR Mode 219 8 7 CLl Cache Line SIZze HER RR RIARRRCYASRU E a i 220 8 8 rip eri xis kun io Aveda Fenda 220 8 9 PBUSN1 Primary Bus Number 41 2 4 6 6 6 ens enn 220 8 10 SBUSN1 Secondary Bus 1 3 een 221 8 11 SUBUSN1 Subordinate Bus 221 8 12 IOBASE1 1I O Address os ern treten Ex FORE RE REX EUREN KA KE EEERE 222 8 13 IOLIMI
357. rocessor to PCI Express non prefetchable memory access routing based on the following formula MEMORY BASE lt address MEMORY LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary Bit Access Para Description Value 15 4 RW FFFh Memory Address Base MBASE This field corresponds to A 31 20 of the lower limit of the memory range that will be passed to PCI Express 3 0 RO Oh Reserved 158 Datasheet m e Host Primary PCI Express Bridge Registers D1 FO n tel 6 16 Note Note MLI MI T1 Memory Limit Address B D F Type 0 1 0 PCI Address Offset 22 23h Default Value 0000h Access RW RO Size 16 bits This register controls the processor to PCI Express non prefetchable memory access routing based on the following formula MEMORY BASE address MEMORY LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration softwar
358. rrupts MSI capability at 90h Capability ID CID Value of O1h identifies this linked list item capability 7 0 RO Olh d structure as being for PCI Power Management registers 232 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 26 PM CS1 Power Management Control Status B D F Type Address Offset Default Value Access Size 0 6 0 PCI 84 87h 00000008h RO RW RW P 32 bits Bit Access Default Value Description 31 16 RO 0000h Reserved 15 RO Ob PME Status PMESTS Indicates that this device does not support PMEB generation from D3cold 14 13 12 9 RO RO 00b Oh Data Scale DSCALE Indicates that this device does not support the power management data register Data Select DSEL Indicates that this device does not support the power management data register RW P Ob PME Enable PMEE Indicates that this device does not generate PMEB assertion from any D state 0 PMEB generation not possible from any D State 1 PMEB generation enabled from any D State The setting of this bit has no effect on hardware See PM_CAP 15 11 7 2 RO 0000b Reserved 1 0 RW 00b Power State PS Indicates the current power state of this device and can be used to set the device into a new power state If software attempts to write an unsuppor
359. rved 9 0 RW 000h Channel 0 DRAM Rank Boundary Address CODRBA3 5 2 35 EPCODRAO1 EP Channel 0 DRAM Rank 0 1 Attribute B D F Type 0 0 0 MCHBAR Address Offset 08 09 Default Value 0000h Access RW Size 16 bits The DRAM Rank Attribute Registers define the page sizes number of banks to be used when accessing different ranks These registers should be left with their default value all zeros for any rank that is unpopulated as determined by the corresponding CxDRB registers Each byte of information in the CxDRA registers describes the page size of a pair of ranks Channel and rank map Ranko 1 108h 109h ChO Rank2 3 10Ah 10Bh Ch1 Ranko 1 188h 189h Ch1 Rank2 3 18Ah 18Bh Default Bit Access Description 15 Channel 0 DRAM Rank 1 Attributes CODRA1 This register defines DRAM 5 8 RW 00h pagesize number of banks for rank1 for given channel 7 0 RW 00h Channel 0 DRAM 0 Attributes CODRAO This register defines DRAM pagesize number of banks for rankO for given channel 124 Datasheet m e DRAM Controller Registers DO FO n tel 5 2 36 EPCODRA23 EP Channel 0 DRAM Rank 2 3 Attribute B D F Type 0 0 0 MCHBAR Address Offset AOA AOBh Default Value 0000h Access RW Size 16 bits See CODRAOI register Default T Bit Access Value Description Channel 0 DRAM Rank 3 Attributes CODRA3 This register defines DRAM 15 8 RW 00h
360. ry range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC i e prefetchable from the processor perspective Bit Access Default Value Description 15 4 RW 000h Prefetchable Memory Address Limit PMLI MI T Corresponds to A 31 20 of the upper limit of the address range passed to PCI Express 3 0 64 bit Address Support Indicates that the upper 32 bits of the prefetchable RO 1h memory region limit address are contained in the Prefetchable Memory Base Limit Address register at 2Ch Datasheet 227 n tel Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 19 PMBASEU1 Prefetchable Memory Base Address Upper B D F Type 0 6 0 PCI Address Offset 28 2Bh Default Value 00000000h Access RW Size 32 bits The functionality associated with this register is present in the PCI Express design implementation This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express prefetchable memory access routing based on the following formula PREFETCHABLE MEMORY BASE lt address xPREFETCHABLE MEMORY LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond
361. s 75 5 1 16 DMIBAR Root Complex Register Range Base 77 5 1 17 PAMO Programmable Attribute Map 0 78 5 1 18 PAM1 Programmable Attribute Map 1 79 5 1 19 PAM2 Programmable Attribute Map 2 80 5 1 20 PAM3 Programmable Attribute Map 3 81 5 1 21 PAM4 Programmable Attribute Map 4 82 5 1 22 PAM5 Programmable Attribute Map 5 mnes 83 5 1 23 PAM6 Programmable Attribute 6 84 5 1 24 LAC Legacy Access Control ssssssssseseses emen 84 5 1 25 REMAPBASE Remap Base Address 85 5 1 26 REMAPLIMI T Remap Limit Address Register 4 07 85 5 1 27 SMRAM System Management RAM 86 5 1 28 ESMRAMC Extended System Management RAM 87 5 1 29 TOM Top of MemloLFy iere AREA RI 88 5 1 30 TOUUD Top of Upper Usable 88
362. s 6 21 CAPPTR1 Capabilities Pointer B D F Type 0 1 0 PCI Address Offset 34h Default Value 88h Access RO Size 8 bits The capabilities pointer provides the address offset to the location of the first entry in this device s linked list of capabilities Default T Bit Access Value Description 7 0 RO 88h First Capability CAPPTR1 The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability Datasheet 163 intel Host Primary PCI Express Bridge Registers D1 FO 6 22 I NTRLI NE1 I nterrupt Line B D F Type 0 1 0 PCI Address Offset 3Ch Default Value 00h Access RW Size 8 bits This register contains interrupt line routing information The device itself does not use this value rather it is used by device drivers and operating systems to determine priority and vector information 2 Default Bit Access Value Description Interrupt Connection INTCON This field is used to communicate interrupt 7 0 RW 00h line routing information 6 23 INTRPIN1 I nterrupt Pin B D F Type 0 1 0 PCI Address Offset 3Dh Default Value Olh Access RO Size 8 bits This register specifies which interrupt pin this device uses Default ae Bit Access Value Description 7 0 RO 01h I nterrupt Pin I NTPI N As a single function device the PCI Express device specifies INTA as its interrupt O1h INTA 6 24 BCTRL1
363. s i e prevent overlap with each other and or with the ranges covered with the main memory There is no provision in the MCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured Bit Access Default Value Description 15 4 RW 000h Memory Address Limit MLI MI T Corresponds to A 31 20 of the upper limit of the address range passed to PCI Express 3 0 RO Oh Reserved Datasheet 225 m e n tel Host Secondary PCI Express Bridge Registers D6 FO I ntel 3210 MCH only 8 17 PMBASE1 Prefetchable Memory Base Address Upper B D F Type 0 6 0 PCI Address Offset 24 25h Default Value FFF1h Access RW RO Size 16 bits This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express prefetchable memory access routing based on the following formula PREFETCHABLE MEMORY BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boun
364. s FSB SWING used by the FSB RCOMP circuits FSB XSWING is used for the A signals handled by FSB_XRCOMP FSB DVREF 1 0 Host Reference Voltage Reference voltage input for the Data signals of the Host GTL interface 1 0 Host Reference Voltage Reference voltage input for the TSB ACCVREE A Address signals of the Host GTL interface Datasheet Signal Description intel 2 2 System Memory DDR2 Interface Signals 2 2 1 System Memory Channel A I nterface Signals Signal Name Type Description 6 SDRAM Differential Clocks SSTL 1 8 DDR2 Three per DIMM DDR A CKB O SDRAM Inverted Differential Clocks gt SSTL 1 8 DDR2 Three per DIMM 6 DDR A CSB 3 0 SSTL 1 8 DDR2 Device Rank 3 2 1 and 0 Chip Select DDR2 Clock Enable DDR_A_CKE_ 3 0 SSTL 1 8 1 per Device Rank DDR2 On Die Termination DDR A 18500 SSTL 1 8 1 per Device Rank DDR A MA 14 0 SSTL 1 8 DDR2 Address Signals 14 0 DDR A BS 2 0 o DDR2 Bank Select MP SSTL 1 8 O r DDR_A_RASB SSTL 1 8 DDR2 Row Address Select signal DDR A CASB SSTL 1 8 DDR2 Column Address Select signal DDR_A_WEB 2 DDR2 Write Enable signal SSTL 1 8 8 DDR_A_DQ 63 0 pe DDR2 Data Lines 2 07 SSTL 1 8 DDR A CB 7 0 1 0 ECC Check Byte SSTL 1 8 Y DDR A DM 7 0 9 DDR2 Data Mask d ee SSTL 1 8 DDR_A_DQS 8 0 ue DDR2 Data Strobes SSTL 1 8 DDR_A_DQSB 8 0 ue DDR2 Data Strobe
365. s RO RWC Size 16 bits PCI Express Slot related registers Bit Access perault Description Value 15 7 RO 0000000b Reserved Presence Detect State PDS This bit indicates the presence of an adapter in the slot reflected by the logical OR of the Physical Layer in band presence detect mechanism and if present any out of band presence detect mechanism defined for the slot s corresponding form factor Note that the in band presence detect mechanism requires that power be applied to an adapter 6 RG Ob for its presence to be detected 0 Slot Empty 1 Card Present in Slot This register must be implemented on all Downstream Ports that implement slots For Downstream Ports not connected to slots where the Slot Implemented bit of the PCI Express Capabilities Register is Ob this bit must return 1b 5 4 RO 00b Reserved 3 RWC Ob Detect Changed PDC This bit is set when the value reported in Presence Detect State is changed MRL Sensor Changed MSC If an MRL sensor is implemented this bit is set 2 RO Ob when a MRL Sensor state change is detected If an MRL sensor is not implemented this bit must not be set Power Fault Detected PFD If a Power Controller that supports power fault detection is implemented this bit is set when the Power Controller detects a power fault at this slot Note that depending on hardware capability it is possible that a power fault can be detected at any time independent of the Po
366. s The dref high flag is set when the dref high watermark level is exceeded and is cleared when the refresh count is less than the hysterisis level This bit should be set to a value less than the high 25 22 RW 0000b watermark level 0000 0 0001 1 1000 8 Datasheet 129 m n tel DRAM Controller Registers DO FO Bit Access Default Description Value DRAM Refresh High Watermark REFHIGHWM When the refresh count exceeds this level a refresh request is launched to the scheduler and the dref_high flag is set 21 18 RW 0000 0 0001 1 1000 8 DRAM Refresh Low Watermark REFLOWWM When the refresh count exceeds this level a refresh request is launched to the scheduler and the dref_low flag is set 17 14 RW 00006 0000 0 0001 21 1000 8 Refresh Counter Time Out Value REFTI MEOUT Program this field with a value that will provide 7 8 us at mclk frequency 00110000 At various mclk frequencies this results in the following values 1100000 400 Mhz gt C30 hex Default Value 533 Mhz gt 104B hex 666 Mhz gt 1450 hex 13 0 RW 130 Datasheet DRAM Controller Registers DO FO n tel 5 2 44 TSC1 Thermal Sensor Control 1 B D F Type Address Offset CD8h Default Value Access Size 0 0 0 MCHBAR 00h RW L RW RS WC 8 bits This register controls the operation of the thermal sensor Bits 7 1 of this register are re
367. s are powered down and the link does not attempt to train In addition Next Pointer 00h and IO cannot decode to the PCI Express interface From a Physical Layer perspective all 16 lanes are powered down and the link does not attempt to train 41 RO Ob Reserved ECC Disable ECCDIS 40 RO Ob 0 ECC capable 1 Not ECC capable Hardwires ECC enable field bit 7 of the CWB Control Registers MCHBAR Offset 243h and 643h to 0 39 RO Ob Reserved 38 RO Ob Reserved 37 35 RO 000b Reserved 34 RO Ob Reserved 33 32 RO 00b Reserved 96 Datasheet m DRAM Controller Registers DO FO n tel Default ici Bit Access Value Description DDR Frequency Capability DDRFC This field controls which values may be written to the Memory Frequency Select field 6 4 of the Clocking Configuration registers MCHBAR Offset COOh Any attempt to write an unsupported value will 31 30 RO 00b be ignored 10 MCH capable of up to DDR2 800 11 capable of up to DDR2 667 FSB Frequency Capability FSBFC This field controls which values are allowed in the FSB Frequency Select Field 2 0 of the Clocking Configuration Register These values are determined by the BSEL 2 0 frequency straps Any unsupported strap values will render the MCH System Memory Interface 29 28 RO 00b inoperable 00 MCH capable of All Memory Frequencies 01 MCH capable of up to FSB 1333 10 MCH capable of up to FSB 1067 11 MCH c
368. s Number B D F Type 0 1 0 PCI Address Offset 18h Default Value 00h Access RO Size 8 bits This register identifies that this virtual Host PCI Express bridge is connected to PCI bus 0 Default S Bit Access Value Description Primary Bus Number BUSN Configuration software typically programs this 7 0 RO 00h field with the number of the bus on the primary side of the bridge Since device 1 is an internal device and its primary bus is always 0 these bits are read only and are hardwired to 0 154 Datasheet m e Host Primary PCI Express Bridge Registers D1 FO n tel 6 10 SBUSN1 Secondary Bus Number B D F Type 0 1 0 PCI Address Offset 19h Default Value 00h Access RW Size 8 bits This register identifies the bus number assigned to the second bus side of the virtual bridge This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express Default ae Bit Access Value Description 7 0 RW 00h Secondary Bus Number BUSN This field is programmed by configuration software with the bus number assigned to PCI Express 6 11 SUBUSN1 Subordinate Bus Number B D F Type 0 1 0 PCI Address Offset 1Ah Default Value 00h Access RW Size 8 bits This register identifies the subordinate bus if any that resides at the level below PCI Express This number is programmed by the PCI configuration software to all
369. s bit has no effect when Refresh is enabled i e there is no mode where 25 RW Ob Refresh is enabled but the counter does not run So in conjunction with bit 23 REFEN the modes are Description 0 0 Normal refresh disable 0 1 Refresh disabled but counter is accumulating refreshes 1 X Normal refresh enable All Rank Refresh ALLRKREF This configuration bit enables by default that 24 RW Ob all the ranks are refreshed in a staggered atomic fashion If set the ranks are refreshed in an independent fashion Refresh Enable REFEN Refresh is enabled 23 RW Ob 0 Disabled 1 Enabled DDR Initialization Done INI TDONE Indicates that DDR initialization is 22 RW Ob complete 21 20 RO 00b Reserved DRAM Refresh Panic Watermark REFPANI CWM When the refresh count exceeds this level a refresh request is launched to the scheduler and the dref panic flag is set 19 18 RW 00b 00 5 01 6 10 7 11 8 120 Datasheet m DRAM Controller Registers DO FO n tel Bit Access Default Description Value DRAM Refresh High Watermark REFHI GHWM When the refresh count exceeds this level a refresh request is launched to the scheduler and the dref_high flag is set 17 16 RW 00b 00 3 01 24 10 5 11 6 DRAM Refresh Low Watermark REFLOWWM When the refresh count exceeds this level a refresh request is launched to the scheduler and the dref low flag is
370. s bit is Set following any write of 1b to the Retrain Link bit including when the Link is in the process of retraining for some other reason Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation either through an LTSSM timeout or a higher level process This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change 13 RO Ob Data Link Layer Link Active Optional DLLLA This bit indicates the status of the Data Link Control and Management State Machine It returns a 1b to indicate the DL_Active state Ob otherwise This bit must be implemented if the corresponding Data Link Layer Active Capability bit is implemented Otherwise this bit must be hardwired to Ob 12 RO 1b Slot Clock Configuration SCC 0 The device uses an independent clock irrespective of the presence of a reference on the connector 1 The device uses the same physical reference clock that the platform provides on the connector 11 RO Ob Link Training LTRN This bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun Hardware clears this bit when the LTSSM exits the Configuration Recovery state once Link training is complete 10 RO Ob Undefined Th
371. s condition via SERR messaging is disabled For systems that do not support ECC this bit must be disabled Datasheet 93 intel DRAM Controller Registers DO FO 5 1 36 SMI CMD SMI Command B D F Type 0 0 0 PCI Address Offset CC CDh Default Value 0000h Access RO RW Size 16 bits This register enables various errors to generate an SMI DMI special cycle When an error flag is set in the ERRSTS register it can generate an SERR SMI or SCI DMI special cycle when enabled in the ERRCMD SMI CMD or SCICMD registers respectively Note that one and only one message type can be enabled Bit Access perau t Description Value 15 12 RO Oh Reserved SMI Thermal Sensor Trip 5 5 1 A SMI DMI special cycle is generated by MCH when the thermal sensor trip 11 RW Ob requires an SMI A thermal sensor trip point cannot generate more than one special cycle 0 Reporting of this condition via SMI messaging is disabled 10 2 RO 000h Reserved SMI on Multiple Bit DRAM ECC Error DMESMI 1 The MCH generates an SMI DMI message when it detects a multiple bit error 1 RW Ob reported by the DRAM controller 0 Reporting of this condition via SMI messaging is disabled For systems not supporting ECC this bit must be disabled SMI on Single bit ECC Error DSESMI 1 The MCH generates an SMI DMI special cycle when the DRAM controller 0 RW Ob detects a single bit error 0
372. s entire set of internal configuration registers to predetermined default states Some register values at reset are determined by external strapping options The default state represents the minimum functionality feature set required to successfully bringing up the system Hence it does not represent the optimal system configuration It is the responsibility of the system initialization software usually BIOS to properly determine the DRAM configurations operating parameters and optional system features that are applicable and to program the MCH registers accordingly 55 intel 4 1 56 MCH Register Description Register Terminology The following table shows the register related terminology that is used Item Description RO Read Only bit s Writes to these bits have no effect RO S Read Only Sticky Writes to these bits have no effect These are status bits only Bits are not returned to their default values by warm reset but will be reset with a cold complete reset for PCI Express related bits a cold reset is Power Good Reset as defined in the PCI Express specification RS WC Read Set Write Clear bit s These bits are set to 1 when read and then will continue to remain set until written A write of 1 clears sets to 0 the corresponding bit s and a write of 0 has no effect R W Read Write bit s These bits can be read and written R WC Read
373. s generated on the FSB and the result is an IWB Since the PAM region is Read Disabled the default target for the Memory Read becomes DMI The IWB associated with this cycle will cause the MCH to hang Non snooped accesses from PCI Express or DMI to this region are always sent to DRAM Main Memory Address Range 1MB TOLUD This address range extends from 1 MB to the top of Low Usable physical memory that is permitted to be accessible by the MCH as programmed in the TOLUD register All accesses to addresses within this range will be forwarded by the MCH to the DRAM unless it falls into the optional TSEG or optional ISA Hole Datasheet m e System Address Map n te Figure 5 Main Memory Address Range 8 GB Main Memory FFFF_FFFFh 4 GB FLASH APIC ET PCI Memory Range TSEG 1MB 2MB 8MB optional Main Memory 0100 0000h ISA Hole optional 00 0 0000h Main Memory 0010 0000h DOS Compatibility Memory Oh 3 2 1 ISA Hole 15 MB 16 MB A hole can be created at 15 MB 16 MB as controlled by the fixed hole enable in Device 0 space Accesses within this hole are forwarded to the DMI Interface The range of physical DRAM memory disabled by opening the hole is not remapped to the top of the memory that physical DRAM space is not accessible This 15 16 MB hole is an optionally enabled ISA hole The ISA Hole is used by validation and customer SV teams for some o
374. s of DDR2 SDRAM It also supports the PCI Express based external device attach The Intel 3200 3210 Chipset platform supports the ninth generation I O Controller Hub Intel ICH9 to provide 1 0 related features Host I nterface The MCH supports a single LGA775 socket processor The MCH supports a FSB frequency of 800 1066 1333 MHz Host initiated 1 0 cycles are decoded to PCI Express DMI or the MCH configuration space Host initiated memory cycles are decoded to PCI Express DMI or system memory PCI Express device accesses to non cacheable system memory are not snooped on the host bus Memory accesses initiated from PCI Express using PCI semantics and from DMI to system SDRAM will be snooped on the host bus Processor Host Interface FSB Details Supports the Dual Core Intel Xeon Processor 3000 Series and Quad Core Intel Xeon Processor 3200 Series Supports Front Side Bus FSB at the following Frequency Ranges 800 1066 1333MT s Supports FSB Dynamic Bus Inversion DBI Supports 36 bit host bus addressing allowing the processor to access the entire 64 GB of the host address space Has a 12 deep In Order Queue to support up to twelve outstanding pipelined address requests on the host bus Has a 1 deep Defer Queue Uses GTL bus driver with integrated GTL termination resistors Supports a Cache Line Size of 64 bytes System Memory Interface The MCH integrates a system memory DDR2 controller with two 64 bit
375. s on the external PCI bus and this number is configurable The system s primary PCI expansion bus is physically attached to the ICH and from a configuration perspective appears to be a hierarchical PCI bus behind a PCI to PCI bridge therefore it has a programmable PCI Bus number The PCI Express interface appears to system software to be a real PCI bus behind a PCI to PCI bridge that is a device resident on PCI bus 0 Note A physical PCI bus 0 does not exist DMI and the internal devices in the MCH and ICH logically constitute PCI Bus 0 to configuration software see Figure 8 Figure 8 Conceptual Platform PCI Configuration Diagram CPU MCH PCI Configuration Window Space Primary Host PCl DRAM Controller Express Bridge Interface Device Bus 0 Device 1 Bus 0 LL LL Device 0 Manageability Engine Device A Bus 0 Secondary Host Device 3 PCI Express Bridg Bus 0 Device 6 Direct Media Interface 1 Datasheet 57 m n tel MCH Register Description 4 3 4 3 1 58 The MCH contains four PCI devices within a single physical component The configuration registers for the four devices are mapped as devices residing on PCI bus O Device 0 Host Bridge DRAM Controller Logically this appears as a PCI device residing on PCI bus 0 Device 0 contains the standard PCI header registers PCI Express b
376. s the 1 0 RW 00b minimum allowed spacing in DRAM clocks between two PRE commands to the same rank Datasheet 105 DRAM Controller Registers DO FO 5 2 9 COCYCTRKACT Channel 0 CYCTRK ACT B D F Type 0 0 0 MCHBAR Address Offset 252 255h Default Value 000000008 Access RW RO Size 32 bits Channel 0 CYCTRK Activate registers Bit Access Default Description Value 31 28 RO Oh Reserved ACT Window Count COsd cr act windowcnt This field indicates the window duration in DRAM clocks during which the controller counts the of activate commands which are launched to a particular rank If the number of 27 22 RW 000900 activate commands launched within this window is greater than 4 then a check is implemented to block launch of further activates to this rank for the rest of the duration of this window Max ACT Check Disable COsd cr maxact dischk This field enables the 21 RW Ob check which ensures that there are no more than four activates to a particular rank in a given window ACT to ACT Delayed COsd cr act act This field indicates the minimum 20 17 RW 0000b allowed spacing in DRAM clocks between two ACT commands to the same rank This field corresponds to tarp in the DDR Specification PRE to ACT Delayed COsd cr pre act This field indicates the minimum allowed spacing in DRAM clocks between the PRE and ACT commands to the 16 13 RW 0000b same rank bank 12 9R WO000bPRE ALL to ACT Delayed COs
377. s the minimum 10 6 RW 00000b allowed spacing in DRAM clocks between the WRITE and PRE commands to the same rank bank This field corresponds to tyg in the DDR Specification READ PRE Delayed 15 cr rd pchg This field indicates the minimum 5 2 RW 0000b allowed spacing in DRAM clocks between the READ and PRE commands to the same rank bank PRE To PRE Delayed Cl1sd cr pchg pchg This field indicates the 1 0 RW 00b minimum allowed spacing in DRAM clocks between two PRE commands to the same rank 116 Datasheet DRAM Controller Registers DO FO n tel 5 2 24 CICYCTRKACT Channel 1 CYCTRK ACT B D F Type 0 0 0 MCHBAR Address Offset 652 655h Default Value 00000000h Access RO RW Size 32 bits Channel 1 CYCTRK ACT registers Bit Access Default Description Value 31 28 RO Oh Reserved ACT Window Count Cl1sd_cr_act_windowcnt This field indicates the window duration in DRAM clocks during which the controller counts the of activate commands which are launched to a particular rank If the number of 27 22 RW 000990 activate commands launched within this window is greater than 4 then a check is implemented to block launch of further activates to this rank for the rest of the duration of this window Max ACT Check Disable C1sd_cr_maxact_dischk This field enables the 21 RW Ob check which ensures that there are no more than four activates to a particular rank in a given w
378. se noted Datasheet 15 intel Figure 1 16 Intel 3210 Chipset System Diagram Example Introduction Processor System Memory Intel 3210 supports two PCI Express x8 as shown or one PCI Express x16 2 PCI Express Intel 3210 PCI Express x8 cr s s t t t n MCH PCI Express PCI Express x8 C Link Still DMI connect on non AMT system USB2 0 Power 12 Ports Management Clock SATA 6 Ports SMBus2 0 Intel ICH9 SST PECI Fan Speed Control WU Flash WLAN LPC 6 PCle x1 au PCle Bus 4 PCI Masters SIO PCI Bus Datasheet Introduction Figure 2 1 1 Datasheet Intel 3200 Chipset System Diagram Example PCI Express USB2 0 12 Ports GPIO SATA 6 Ports SPI Flash Firmware PCI Express x8 Processor System Memory Intel 3200 MCH C Link Still connect on non AMT system Power Management Clock Generation SMBus2 0 Intel ICH 9 PC SST PECI Fan Speed Control SPI Gb LAN WLAN reel CEU 4 PCI Masters LPC PCle Bus SIO PCI Bus Terminology Term Description Used in this specification to refer to one or more hardware components that Chipset Root connect processor complexes to the 1 0 and memory subsystems The chipset Complex may include a variety of integrated devices CLink Controller Link is a proprietary chip t
379. set 40 47h Default Value 0000000000000000h Access RO RW L Size 64 bits This is the base address for the PCI Express Egress Port MMIO Configuration space There is no physical memory within this 4 KB window that can be addressed The 4 KB reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset the EGRESS port MMIO configuration space is disabled and must be enabled by writing a 1 to PXPEPBAREN Dev 0 offset 40h bit 0 All the bits in this register are locked in Intel TXT mode Bit Access Description Value 63 36 RO 0000000h Reserved PCI Express Egress Port MMI O Base Address PXPEPBAR This field corresponds to bits 35 to 12 of the base address PCI Express Egress Port MMIO configuration space BIOS will program this register resulting in a base address for a 4 KB block of contiguous memory address space This register 32 12 ETE ensures that a naturally aligned 4KB space is allocated within the first 64 GB of addressable memory space System Software uses this base address to program the MCH MMIO register set All the bits in this register are locked in Intel TXT mode 11 1 RO 000h Reserved PXPEPBAR Enable PXPEPBAREN 0 PXPEPBAR is disabled and does not claim any memory 0 RW L Ob 1 PXPEPBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT 72 Datasheet m e DRAM Controller Registers DO FO tel
380. set to their defaults by MPWROK Bit 0 is reset to it s default by PLTRST Bit Access Default Value Description 7 RW L Ob Thermal Sensor Enable TSE This bit enables power to the thermal sensor Lockable via TCO bit 7 0 Disabled 1 Enabled Ob Analog Hysteresis Control AHC This bit enables the analog hysteresis control to the thermal sensor When enabled about 1 degree of hysteresis is applied This bit should normally be off in thermometer mode since the thermometer mode of the thermal sensor defeats the usefulness of analog hysteresis 0 Hysteresis disabled 1 Analog hysteresis enabled 5 2 RW 0000b Digital Hysteresis Amount DHA This bit determines whether no offset 1 LSB 2 15 is used for hysteresis for the trip points 0000 Digital hysteresis disabled no offset added to trip temperature 0001 Offset is 1 LSB added to each trip temperature when tripped 0110 3 0 C Recommended setting 1110 Added to each trip temperature when tripped 1111 Added to each trip temperature when tripped 1 RW L Ob Thermal Sensor Comparator Select TSCS This bit multiplexes between the two analog comparator outputs Normally Catastrophic is used Lockable via TCO bit 7 0 Catastrophic 1 Hot Datasheet 131 intel DRAM Controller Registers DO FO Bit Access perat Description Value I n Use
381. should ensure that D OPEN 1 and D CLS 1 are not set at the same time SMM Space Closed D CLS When D CLS 1 SMM space DRAM is not accessible to data references even if SMM decode is active Code references 5 RW Ob may still access SMM space DRAM This will allow SMM software to reference through SMM space to update the display Software should ensure that D_OPEN 1 and D_CLS 1 are not set at the same time SMM Space Locked D_LCK When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK D_OPEN C_BASE_SEG H_SMRAM_EN TSEG_SZ and TSEG_EN become read only D_LCK can be set to 1 via a normal configuration space write 4 RW L K Ob but can only be cleared by a Full Reset The combination of D LCK and D OPEN provide convenience with security The BIOS can use the D OPEN function to initialize SMM space and then use D LCK to lock down SMM space in the future so that no application software or BIOS itself can violate the integrity of SMM space even if the program has knowledge of the D OPEN function Global SMRAM Enable G SMRAME If set to a 1 then Compatible SMRAM functions are enabled providing 128 KB of DRAM accessible at the A0000h 3 RW L Ob address while in SMM ADSB with SMM decode To enable Extended SMRAM function this bit has be set to 1 Refer to the section on SMM for more details Once D_LCK is set this bit becomes read only Compatible SMM Space Base Segment C_BASE_ SEG This field indicates the location of SMM space SMM DRAM is
382. slating and routing the processor s 1 0 accesses to the CONFIG ADDRESS and CONFIG DATA registers to internal MCH configuration registers DMI or PCI Express PCI Express Enhanced Configuration Mechanism PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by PCI Specification Revision 2 3 PCI Express configuration space is divided into a PCI 2 3 compatible region which consists of the first 256B of a logical device s configuration space and a PCI Express extended region which consists of the remaining configuration space The PCI compatible region can be accessed using either the Standard PCI Configuration Mechanism or using the PCI Express Enhanced Configuration Mechanism described in this section The extended configuration registers may only be accessed using the PCI Express Enhanced Configuration Mechanism To maintain compatibility with PCI configuration addressing mechanisms system software must access the extended configuration space using 32 bit operations 32 bit aligned only These 32 bit operations include byte enables allowing only appropriate bytes within the DWord to be accessed Locked transactions to the PCI Express memory mapped configuration address space are not supported All changes made using either access mechanism are equivalent The PCI Express Enhanced Configuration Mechanism utilizes a flat memory mapped address space to access device configuration registers
383. ss Code BCC This is an 8 bit value that indicates the base class code for the This code has the value 06h indicating a Bridge device 15 8 RO 00h Sub Class Code SUBCC This is an 8 bit value that indicates the category of Bridge into which the falls The code is indicating a Host Bridge Programming Interface PI This is an 8 bit value that indicates the 7 0 RO 00h programming interface of this device This value does not specify a particular register set layout and provides no practical use for this device 5 1 7 MLT Master Latency Timer B D F Type 0 0 0 PCI Address Offset Dh Default Value 00h Access RO Size 8 bits Device 0 in the MCH is not a PCI master Therefore this register is not implemented Default er Bit Access Value Description 7 0 RO 00h Reserved 70 Datasheet m e DRAM Controller Registers DO FO n tel 5 1 8 HDR Header Type B D F Type 0 0 0 PCI Address Offset Eh Default Value 00 Access RO Size 8 bits This register identifies the header layout of the configuration space No physical register exists at this location i Default 4 22 Bit Access Value Description PCI Header HDR This field always returns 0 to indicate that the MCH is a 7 0 RO 00h single function device with standard header layout Reads and writes to this location have no effect 5 1 9 SVI D Subsystem Vendor Identification
384. ss related clocks including the Direct Media that connect to the ICH This PLL uses the 100 MHz clock EXP_CLKNP EXP2_CLKNP as a reference CK505 is the clocking chip required for the platform Datasheet Functional Description Figure 11 Datasheet System Clocking Diagram 56 Pin SSOP C3 S7 R1 P1 5 56 55 53 eeeecece PCI Express Pair PCI Express DIff Pair PCI Express Pair PCI Express Pair PCI Express SATA REF 14 MH PCI 33 MHz PCI 33 MHz PCI 33 MHz PCI 33 MHz Processor Diff Pair CK505 Processor Diff Pair co ER Processor Diff Pair ecccccccece PCI Express DIff Pair 54 LAN Nineveh PCI Express Slot Diff Pair 2 DOT 96 MHz Diff Pair USB 48 MHz REF 14 MHz Processor Dual x8 PCI Express 1 PCI Express 279 PCI Express 51 2 SIO LPC PCI Down Device TPM LPC Memory Intel ICH9 0 32 768 kHz Signal Reference BCLK ITPCLK HCLK C1 C3 i NC SATACLK ICHCLK MCHCLK LANCLK 51 57
385. sses are directed to DMI 1 0 RW L 00b 01 porn Only All reads are serviced by DRAM All writes are forwarded to 10 Write Only All writes are sent to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 80 Datasheet DRAM Controller Registers DO FO n tel 5 1 20 PAM3 Programmable Attribute Map 3 B D F Type Address Offset Default Value Access Size 0 0 0 PCI 93h 00h RO RW L 8 bits This register controls the read write and shadowing attributes of the BIOS areas from 000000 0D7FFFh i Default 4 22 Bit Access Value Description 7 6 RO 00b Reserved 0D4000h 0D7FFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D4000h to OD7FFFh 00 DRAM Disabled Accesses are directed to DMI 1 Read Only All reads are service DRAM All writes are forwarded t 5 4 RW L 00b 0 Sg y eads are serviced by writes are forwa 10 Write Only All writes sent to DRAM Reads serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 3 2 RO 00b Reserved 000000 OD3FFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0000001 to OD3FFFh 00 DRAM Disabled Accesses are directe
386. ster and the lower bound of the bridge device s Secondary Bus Number register but does not match the Device 1 Secondary Bus Number a PCI Express Type 1 Configuration TLP is generated on the secondary side of the PCI Express link PCI Express Configuration Writes Internally the host interface unit will translate writes to PCI Express extended configuration space to configuration writes on the backbone Writes to extended space are posted on the FSB but non posted on the PCI Express or DMI i e translated to config writes DMI Configuration Accesses Accesses to disabled MCH internal devices bus numbers not claimed by the Host PCI Express bridge or PCI Bus 0 devices not part of the MCH will subtractively decode to the ICH and consequently be forwarded over the DMI via a PCI Express configuration TLP If the Bus Number is zero the MCH will generate a Type 0 Configuration Cycle TLP on DMI If the Bus Number is non zero and falls outside the range claimed by the Host PCI Express bridge the MCH will generate a Type 1 Configuration Cycle TLP on DMI The ICH routes configurations accesses in a manner similar to the MCH The ICH decodes the configuration TLP and generates a corresponding configuration access Accesses targeting a device on PCI Bus 0 may be claimed by an internal device The ICH compares the non zero Bus Number with the Secondary Bus Number and Datasheet m e MCH Register Description n tel 4 5 4 5 1
387. sult TOM and TOUUD registers and RECLAIMBASE RECLAIMLI MIT registers become relevant The new reclaim configuration registers exist to reclaim lost main memory space The greater than 32 bit reclaim handling will be handled similar to other MCHs Upstream read and write accesses above 36 bit addressing will be treated as invalid cycles by PCI Express and DMI Top of Memory The Top of Memory TOM register reflects the total amount of populated physical memory This is NOT necessarily the highest main memory address holes may exist in main memory address map due to addresses allocated for memory mapped 1 above TOM TOM is used to allocate the Intel Management Engine s stolen memory The Intel ME stolen size register reflects the total amount of physical memory stolen by the Intel ME The ME stolen memory is located at the top of physical memory The ME stolen memory base is calculated by subtracting the amount of memory stolen by the Intel ME from TOM The Top of Upper Usable Dram TOUUD register reflects the total amount of addressable DRAM If reclaim is disabled TOUUD will reflect TOM minus Intel ME stolen size If reclaim is enabled then it will reflect the reclaim limit Also the reclaim base will be the same as TOM minus ME stolen memory size to the nearest 64 MB alignment TOLUD register is restricted to 4 GB memory A 31 20 but the MCH can support up to 16 GB limited by DRAM pins For physical memory greater than 4 GB t
388. t occurred based on a lower 2 RWC Ob s to higher temperature transition thru the trip point 0 No trip for this event Software must write a 1 to clear this status bit 1 0 RO 00b Reserved 138 Datasheet m e DRAM Controller Registers DO FO n tel 5 2 51 TSMI CMD Thermal SMI Command B D F Type Address Offset Default Value Access Size 0 0 0 MCHBAR 00h RO RW 8 bits This register selects specific errors to generate a SMI DMI special cycle as enabled by the Device 0 SMI Error Command Register SMI on MCH Thermal Sensor Trip The SMI must not be enabled at the same time as the SERR SCI for the thermal sensor event All bits in this register are reset to their defaults by PLTRST Bit Access Derauit Description Value 7 3 RO 00h Reserved SMI on MCH Catastrophic Thermal Sensor Trip SMGCTST 1 Does not mask the generation of an SMI DMI special cycle on a catastrophic 2 RW Ob thermal sensor trip 0 Disable reporting of this condition via SMI messaging SMI on MCH Hot Thermal Sensor Trip SMGHTST 1 RW Ob 1 Does not mask the generation of an SMI DMI special cycle on a Hot thermal sensor trip 0 Disable reporting of this condition via SMI messaging SMI on MCH Aux Thermal Sensor Trip SMGATST 1 Does not mask the generation of an SMI DMI special cycle on an Auxiliary 0 RW Ob thermal sensor trip 0 Disable reporting of this co
389. t6 BSEL1 F21 xor_out7 BSEL2 F18 xor out8 RSVD AN13 xor out9 RSVD AP12 xor outl0 EXP SLR K19 xor outll RSVD L18 xor out12 BSELO M22 xor out13 RSVD H21 xor outl4 RSVD G22 XOR Chains This section provides the XOR chains 317 intel 13 4 318 XOR Chains Table 32 XOR Chain 0 M21 ALLZTEST 1 B39 FSB DB 56 2 D44 FSB DB 52 3 B42 FSB DB 55 4 D39 FSB DB 57 5 C42 FSB DB 51 6 C36 FSB DB 58 7 A38 FSB DB 49 8 B35 FSB DB 62 9 D38 FSB DB 54 10 E41 FSB DB 50 11 D43 FSB DB 53 12 D36 FSB DB 59 13 E35 FSB DB 63 14 E37 FSB DB 61 15 F35 FSB DB 48 16 C37 FSB DB 60 17 F33 FSB DB 26 18 B43 FSB DB 18 19 F39 FSB DB 17 20 F38 FSB DB 16 21 H33 FSB DB 25 22 G36 FSB DB 22 23 G38 FSB DB 20 24 G35 FSB DB 23 25 L36 FSB DB 19 26 L33 FSB DB 29 27 L34 FSB DB 27 28 N33 FSB DB 28 29 N31 FSB DB 30 30 K34 FSB DB 24 31 M31 FSB DB 31 32 K35 FSB DB 21 33 L24 FSB DB 44 Testability Table 32 XOR Chain O 34 H24 FSB DB 45 35 G24 FSB DB 47 36 K28 FSB DB 40 37 K24 FSB DB 46 38 F31 FSB DB 32 39 L30 FSB DB 36 40 G30 FSB DB 38 41 N24 FSB DB 42 42 H31 FSB DB 34 43 H30 FSB DB 39 44 L28 FSB DB 41 45 M30 FSB DB 35 46 N30 FSB DB 37 47 K31 FSB DB 33 48 L25 FSB DB 43 49 E42 FSB DB 15 50 41 FSB_DB_14 51 G42 FSB_D
390. ted state to this field write operation must complete normally on the bus but the data is discarded and no state change occurs 00 DO 01 D1 Not supported in this device 10 D2 Not supported in this device 11 D3 Support of D3cold does not require any special action While in the D3hot state this device can only act as the target of PCI configuration transactions for power management control This device also cannot generate interrupts or respond to MMR cycles in the D3 state The device must return to the DO state in order to be fully functional When the Power State is other than DO the bridge will Master Abort i e not claim any downstream cycles with exception of type 0 config cycles Consequently these unclaimed cycles will go down DMI and come back up as Unsupported Requests which the MCH logs as Master Aborts in Device 0 PCISTS 13 There is no additional hardware functionality required to support these Power States Datasheet 233 m n tel Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 27 SS CAPID Subsystem ID and Vendor ID Capabilities B D F Type 0 6 0 PCI Address Offset 88 8Bh Default Value 0000800Dh Access RO Size 32 bits This capability is used to uniquely identify the subsystem where the PCI device resides Because this device is an integrated part of the system and not an add in device it is
391. tents of CONFIG ADDRESS to 0000 0000 h determine the bus device function and offset of the register to be accessed 64 Datasheet DRAM Controller Registers DO FO 5 Warning Table 8 Datasheet DRAM Controller Registers DO FO The DRAM Controller registers are in Device 0 DO Function 0 FO ntel Address locations that are not listed are considered Intel Reserved registers locations Reads to Reserved registers may return non zero values Writes to reserved locations may cause system failures All registers that are defined in the PCI 2 3 specification but are not necessary or implemented in this component are simply not included in this document The reserved unimplemented space in the PCI configuration header space is not documented as such in this summary DRAM Controller Register Address Map Address Register Register Name Default Offset Symbol Value 0 1h VID Vendor Identification 8086h RO 2 3h DID Device Identification 29F0h RO 4 5h PCICMD PCI Command 0006h RO RW 6 7h PCISTS PCI Status 0090h RO RWC 8h RID Revision Identification 2 RO 9 Bh Class Code 060000h RO Dh MLT Master Latency Timer 00h RO Eh HDR Header Type 00h RO 2C 2Dh SVID Subsystem Vendor Identification 0000h RWO 2E 2Fh SID Subsystem Identification 0000h RWO 34h CAPPTR Capabilities Pointer EOh RO 40 47h PXPEPBAR PCI Express Egress
392. ters 0 65 5 1 Configuration Register Details sss nemen emm mene 67 5 11 VID Vendor Identification m nee 67 5 1 2 DlD Device Identification 67 5 1 3 68 5 L4 5 outer tee arson 69 5 1 5 RID Revision Identification 4 4 144 4 20 0 6 70 5 1 6 CC Class Code Rr anten 70 5 1 7 MLT Master Latency enemies 70 5 1 8 HDR Header 71 5 19 SVID Subsystem Vendor 2 22 1 71 5 1 10 SID Subsystem 71 5 1 11 CAPPTR Capabilities 0 72 5 1 12 PXPEPBAR PCI Express Egress Port Base Address 72 5 1 13 MCHBAR MCH Memory Mapped Register Range Base 73 5 1 14 DEVEN Device seems 74 5 1 15 PCIEXBAR PCI Express Register Range Base Addres
393. the Divisor Latch MSB register of the Serial I nterface 206 Datasheet Intel Manageability Engine Subsystem PCI D3 FO F3 tel 7 2 6 KTI I R KT Interrupt I dentification B D F Type 0 3 3 KT MM IO Address Offset 2h Default Value 1 Access RO Size 8 bits The KT IIR register prioritizes the interrupts from the function into 4 levels and records them in the IIR_STAT field of the register When Host accesses the IIR hardware freezes all interrupts and provides the priority to the Host Hardware continues to monitor the interrupts but does not change its current indication until the Host read is over Table in the Host Interrupt Generation section shows the contents Note Reset See specific Bit descriptions Default eo Bit Access Value Description FIFO Enable FI EN1 This bit is connected by hardware to bit 0 in the FCR 7 RO Ob register Reset Host System Reset or D3 gt D0 transition FI FO Enable FI ENO This bit is connected by hardware to bit 0 in the FCR 6 RO Ob register Reset Host System Reset or 3 gt 0 transition 5 4 RO 00b Reserved STATUS IIRSTS These bits are asserted by the hardware according to the source of the interrupt and the priority level Refer to the section on Host 3 1 RO 000b Interrupt Generation for a table of values Reset ME system Reset Interrupt Status INTSTS When 0 indicates pending interrupt to Host 0 RO 1b When 1 indicates no pendi
394. the PCI Command Register Bit Access perault Description Value 15 4 RO 000h Reserved PME Interrupt Enable PMEI E 0 No interrupts are generated as a result of receiving PME messages 3 RW Ob 1 Enables interrupt generation upon receipt of a PME message as reflected in the PME Status bit of the Root Status Register A PME interrupt is also generated if the PME Status bit of the Root Status Register is set when this bit is set from a cleared state System Error on Fatal Error Enable SEFEE Controls the Root Complex s response to fatal errors 2 RW Ob 0 No SERR generated on receipt of fatal error 1 Indicates that an SERR should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself System Error on Non Fatal Uncorrectable Error Enable SENFUEE Controls the Root Complex s response to non fatal errors 1 RW Ob 0 SERR generated on receipt of non fatal error 1 Indicates that an SERR should be generated if a non fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself System Error on Correctable Error Enable SECEE Controls the Root Complex s response to correctable errors 0 RW Ob 0 No SERR generated on receipt of correctable error 1 Indicates that an SERR should be generated if a correctable error is reported by any of the devices in the hierarchy associate
395. the minimum allowed spacing in DRAM clocks between two READ commands to the same rank 2 0 RO Oh Reserved Datasheet 127 DRAM Controller Registers DO FO 5 2 42 EPDCKECONFI GREG EPD Related Configuration B D F Type 0 0 0 MCHBAR Address Offset A28 A2Ch Default Value 00E0000000h Access RW Size 40 bits BIOS Optimal Default Oh CKE related configuration registers For EPD Default Bit Access Value Description EPDunit TXPDLL Count EPDTXPDLL Specifies the delay from precharge 39 35 RW 00000b power down exit to a command that requires the DRAM DLL to be operational The commands are read write EPDunit TXP Count EPDCKETXP Specifies the timing requirement for 34 32 RW 000b Active power down exit or fast exit pre charge power down exit to any command or slow exit pre charge power down to Non DLL rd wr odt command Mode Select 540 cr sms Mode Select register This configuration setting 31 29 RW 111b indicates the mode in which the controller is operating in 111 Indicates normal mode of operation else special mode of operation EPDunit EMRS Command Select EPDEMRSSEL EMRS mode to select BANK address 28 27 RW 00b 01 EMRS 10 EMRS2 11 EMRS3 26 24 RW 000b CKE Pulse Width Requirement in High Phase sdO cr cke pw hl safe This field indicates pulse width requirement high phase One Hot Active Rank Population ep scr actrank This field indicates the
396. three Root Complex Register Blocks RCRBs The DMI RCRB contains registers for control of the Intel ICH9 attach ports PCI Express Architecture The PCI Express architecture is specified in layers Compatibility with the PCI addressing model a load store architecture with a flat address space is maintained to ensure that all existing applications and drivers operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The initial speed of 1 25 GHz 250 MHz internally results in 2 5 Gb s each direction which provides a 250 MB s communications channel in each direction 500 MB s total that is close to twice the data rate of classic PCI per lane The initial speed of 2 5 GHz results in 5 Gb s each direction which provides a 500 MB s communications channel in each direction 1000 MB s total Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is the assembly and disassembly of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs Data Link Layer The middle layer in the PCI Express stack the Data Link Layer serves as an intermediate stage between the Transaction Layer and the Physical Layer Responsibilities of Data Link Layer include link management
397. tiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling 0 RO Ob Reserved 9 10 DMI LCAP DMI Link Capabilities B D F Type 0 0 0 DMIBAR Address Offset 84 87h Default Value 00012 41 Access RO RWO Size 32 bits This register indicates DMI specific capabilities Default Bit Access Value Description 31 18 RO 0000h Reserved L1 Exit Latency LISELAT This field indicates the length of time this Port requires to complete the transition from L1 to LO 12252 RWO 9185 010 2 us to less than 4 us All other encodings are reserved LOs Exit Latency LOSELAT This field indicates the length of time this Port requires to complete the transition from LOs to LO Torte RWO 010 128 ns to less than 256 ns All other encodings are reserved 11 10 RO 11b Active State Link PM Support ASLPMS 105 amp L1 entry supported Max Link Width MLW This field indicates the maximum number of lanes supported for this link 9 4 RO 04h 04h x4 All other encodings are reserved 3 0 RO 1h Max Link Speed MLS Hardwired to indicate 2 5 Gb s Datasheet 265 intel Direct Media I nterface DMI RCRB 9 11 DMILCTL DMI Link Control B D F Type 0 0 0 DMIBAR Address Offset 88 89h Default Value 0000h Access RW RO Size 16 bits This register allows control of DMI Bit Access Description Value 15 8 RO 0
398. tification number for the Device 0 Refer to the description Intel 3200 and 3210 Chipset Specification Update for the value of this 8 6 CC1 Class Code B D F Type 0 6 0 PCI Address Offset 9 Bh Default Value 060400 Access RO Size 24 bits This register identifies the basic function of the device a more specific sub class and a register specific programming interface Default 525 Bit Access Value Description 23 16 RO 06h Base Class Code BCC Indicates the base class code for this device This code has the value 06h indicating a Bridge device 15 8 RO 04h Sub Class Code SUBCC Indicates the sub class code for this device The code is 04h indicating a to Bridge Programming Interface PI Indicates the programming interface of this 7 0 RO 00h device This value does not specify a particular register set layout and provides no practical use for this device Datasheet 219 intel Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 7 CL1 Cache Line Size B D F Type 0 6 0 PCI Address Offset Ch Default Value 00h Access RW Size 8 bits 4 Default Bit Access Value Description Cache Line Size Scratch pad Implemented by PCI Express devices as a 7 0 RW 00h read write field for legacy compatibility purposes but has no impact on any PCI Express device functionalit
399. tion on a power fault event Default value of this field is Ob If Power Fault detection is not supported this bit is permitted to be read only with a value of 06 0 RO Ob Button Pressed Enable ABPE When set to 1b this bit enables software notification on an attention button pressed event Datasheet 181 n tel Host Primary PCI Express Bridge Registers D1 FO 6 43 SLOTSTS Slot Status B D F Type 0 1 0 PCI Address Offset BA BBh Default Value 0000h Access RO RWC Size 16 bits PCI Express Slot related registers Bit Access perault Description Value 15 7 RO 0000000b Reserved Presence Detect State PDS This bit indicates the presence of an adapter in the slot reflected by the logical OR of the Physical Layer in band presence detect mechanism and if present any out of band presence detect mechanism defined for the slot s corresponding form factor Note that the in band presence detect mechanism requires that power be applied to an adapter 6 RG Ob for its presence to be detected 0 Slot Empty 1 Card Present in Slot This register must be implemented on all Downstream Ports that implement slots For Downstream Ports not connected to slots where the Slot Implemented bit of the PCI Express Capabilities Register is Ob this bit must return 1b 5 4 RO 00b Reserved 3 RWC Ob Detect Changed PDC This bit is set when the value reported in Presence Detect State is changed
400. to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary Bit Access perault Description Value 0000000 Prefetchable Memory Base Address MBASEU Corresponds to A 63 32 of 31 0 RW Oh the lower limit of the prefetchable memory range that will be passed to PCI Express 228 Datasheet m Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 20 PMLI MI TU1 Prefetchable Memory Limit Address Upper B D F Type 0 6 0 PCI Address Offset 2C 2Fh Default Value 00000000h Access RW Size 32 bits The functionality associated with this register is present in the PCI Express design implementation This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express prefetchable memory access routing based on the following formula PREFETCHABLE MEMORY BASE address PREFETCHABLE MEMORY LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purp
401. ts in Device 0 PCISTS 13 There is no additional hardware functionality required to support these Power States Datasheet 167 m n tel Host Primary PCI Express Bridge Registers D1 FO 6 27 SS CAPID Subsystem ID and Vendor ID Capabilities B D F Type 0 1 0 PCI Address Offset 88 8Bh Default Value 0000800Dh Access RO Size 32 bits This capability is used to uniquely identify the subsystem where the PCI device resides Because this device is an integrated part of the system and not an add in device it is anticipated that this capability will never be used However it is necessary because Microsoft will test for its presence Default Bit Access Value Description 31 16 RO 0000h Reserved 15 8 RO 80h Pointer to Next Capability PNC This field contains a pointer to the next item in the capabilities list which is the PCI Power Management capability 7 0 RO ODh Capability ID CID Value of ODh identifies this linked list item capability structure as being for SSID SSVID registers in PCI to PCI Bridge 6 28 SS Subsystem ID and Subsystem Vendor ID B D F Type 0 1 0 PCI Address Offset 8C 8Fh Default Value 000080861 Access RWO Size 32 bits System BIOS can be used as the mechanism for loading the SSID SVID values These values must be preserved through power management transitions and a hardware reset Bit Access Description Valu
402. tunity to clear this bit or 8 RO Ob otherwise test that it is implemented The PCI specification defines it as a R WC but for our implementation an RO definition behaves the same way and will meet all Microsoft testing requirements This bit can only be set when the Parity Error Enable bit in the PCI Command register is set RO Ob Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 6 RO Ob Reserved 5 RO Ob 66 60MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 4 RO 1b Capabilities List CAPL Indicates that a capabilities list is present Hardwired to 1 INTA Status INTAS Indicates that an interrupt message is pending 3 RO Ob internally to the device Only PME sources feed into this status bit not PCI INTA INTD assert and deassert messages The INTA Assertion Disable bit PCI CMD1 10 has no effect on this bit 2 0 RO 000b Reserved 218 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only 8 5 RI D1 Revision Identification B D F Type 0 6 0 PCI Address Offset 8h Default Value see table below Access RO Size 8 bits This register contains the revision number of the MCH device 6 These bits are read only and writes to this register have no effect Bit Access Derault Description Value 7 0 RO register Revision Identification Number RI D1 This is an 8 bit value that see indicates the revision iden
403. ue 31 18 RO 0000h Reserved PME Pending PMEP Indicates that another PME is pending when the PME Status bit is set When the PME Status bit is cleared by software the PME is 17 RO Ob delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately The PME pending bit is cleared by hardware if no more PMEs are pending PME Status PMES Indicates that PME was asserted by the requestor ID 16 RWC Ob indicated in the PME Requestor ID field Subsequent PMEs are kept pending until the status register is cleared by writing a 1 to this field 15 0 RO 0000h PME Requestor I D PMERI D Indicates the PCI requestor ID of the last PME requestor 8 46 PELC PCI Express Legacy Control B D F Type 0 6 0 PCI Address Offset EC EFh Default Value 000000008 Access RO RW Size 32 bits This register controls functionality that is needed by Legacy Express aware OSs during run time Bit Access Default Description Value 31 3 RO 0009009 Reserved Oh PME GPE Enable PMEGPE 0 Do not generate GPE PME message when PME is received 2 RW Ob 1 Generate a GPE PME message when PME is received Assert_PMEGPE and Deassert_PMEGPE messages on DMI This enables the MCH to support PMEs on the PCI Express port under legacy OSs 1 RO Ob Reserved General Message GPE Enable GENGPE 0 Do not forward received GPE assert deassert messages 0 RW 0b 1 Forward received GPE assert deassert messages These general GP
404. ult Access Description Value 15 10 9 0 RO 00h Reserved Top of Memory TOM This register reflects the total amount of populated physical memory This is NOT necessarily the highest main memory address RW L 001h holes may exist in main memory address map due to addresses allocated for memory mapped 10 These bits correspond to address bits 35 26 64MB granularity Bits 25 0 are assumed to be O All the bits in this register are locked in Intel TXT mode 5 1 30 TOUUD Top of Upper Usable Dram B D F Type 0 0 0 PCI Address Offset A2 A3h Default Value 0000h Access RW L Size 16 bits This 16 bit register defines the Top of Upper Usable DRAM Configuration software must set this value to TOM minus all EP stolen memory if reclaim is disabled If reclaim is enabled this value must be set to reclaim limit 1byte 64 MB aligned since reclaim limit is 64 MB aligned Address bits 19 0 are assumed to be 000 0000h for the purposes of address comparison The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than or equal to 4 GB These bits are Intel TXT lockable Bit Access Description Default Value 15 0 RW L 0000h reclaim limit 64 MB aligned since reclaim limit 1byte is 64 MB aligned Address TOUUD TOUUD This register contains bits 35 20 of an address one byte above the maximum
405. unction device indicate a 1b in this bit 17 15 RWO 010b L1 Exit Latency LIELAT Indicates the length of time this Port requires to complete the transition from L1 to LO The value 010 b indicates the range of 2 us to less than 4 us Both bytes of this register that contain a portion of this field must be written simultaneously in order to prevent an intermediate and undesired value from ever existing 240 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel Bit Access Default Description Value LOs Exit Latency LOSELAT Indicates the length of time this Port requires to complete the transition from LOs to LO 000 Less than 64 ns 001 64ns to less than 128ns 010 128ns to less than 256 ns 1912 RO 1085 011 256ns to less than 512ns 100 512ns to less than lus 101 1 us to less than 2 us 110 2 us 4 us 111 More than 4 us 11 10 RWO llb State Link Support ASLPMS The supports ASPM 105 and Max Link Width MLW Indicates the maximum number of lanes supported for this link 08h x8 9 4 RO jg 190 x16 For the 3210 MCH with dual 8 lane x8 configuration the value of 10h is reserved The supported maximum lane size is 8 lanes x8 for this link For the 3200 MCH the value of 10h is reserved The supported maximum lane size is 8 lanes x8 for this link Max Link Speed MLS Supported Link Speed This fie
406. uration B D F Type 0 0 0 MCHBAR Address Offset A30 A33h Default Value 0000C30h Access RW RO Size 32 bits This register provides the settings to configure the EPD refresh controller Default pike Bit Access Value Description 31 RO Ob Reserved EPDunit refresh count addition for self refresh exit EPDREF4SR Configuration indicating the number of additional refreshes that needs to be added to the refresh request count after exiting self refresh Typical value is to add 2 refreshes 30 29 RW 106 00 Add 0 Refreshes 01 Add 1 Refreshes 10 Add 2 Refreshes 11 Add 3 Refreshes Refresh Counter Enable REFCNTEN This bit is used to enable the refresh counter to count during times that DRAM is not in self refresh but refreshes are not enabled Such a condition may occur due to need to reprogram DIMMs following DRAM controller switch This bit has no effect when Refresh is enabled i e there is no mode where 28 RW Ob Refresh is enabled but the counter does not run So in conjunction with bit 23 REFEN the modes are REFEN REFCNTEN Description 0 0 Normal refresh disable 0 1 Refresh disabled but counter is accumulating refreshes 1 X Normal refresh enable Refresh Enable REFEN Refresh is enabled 27 RW Ob 0 Disabled 1 Enabled DDR Initialization Done INI TDONE Indicates that DDR initialization is 26 RW Ob complete DRAM Refresh Hysterisis REFHYSTERI SI S Hysterisis level Useful for dref high watermark case
407. uration wr Specifies the 7 4 RW Oh duration in MDCLKs to assert DRAM ODT for Write Commands The Async value should be used when the Dynamic Powerdown bit is set Else use the Sync value 3 0 RW Oh MCH ODT for Read Commands sdO cr mchodt duration Specifies the duration in MDCLKs to assert MCH ODT for Read Commands 5 2 17 C1DRBO Channel 1 DRAM Rank Boundary Address 0 B D F Type 0 0 0 MCHBAR Address Offset 600 601h Default Value 0000h Access RW L RO Size 16 bits The operation of this register is detailed in the description for the CODRBO register Default Bit Access Value Description 15 10 RO 000000b Reserved Channel 1 DRAM Rank Boundary Address 0 CIDRBAO See CODRBO register 9 0 RW L 000h In stacked mode if this is the topmost populated rank in Channel 1 program this value to be cumulative of ChO DRB3 This register is locked by ME stolen Memory lock Datasheet 113 intel DRAM Controller Registers DO FO 5 2 18 CIDRBI1 Channel 1 DRAM Rank Boundary Address 1 B D F Type 0 0 0 MCHBAR Address Offset 602 603h Default Value 0000 Access RO RW L Size 16 bits The operation of this register is detailed in the description for the CODRBO register 3 Default Bit Access Value Description 15 10 RO 000000b Reserved Channel 1 DRAM Rank Boundary Address 1 CIDRBA1 See CODRB1 register 9 0 RW L 000h In stacked mode if this is the topmost populated rank in Channel 1
408. value in this field is undefined when the Link is not up 6 41 SLOTCAP Slot Capabilities B D F Type 0 1 0 PCI Address Offset B4 B7h Default Value 000400001 Access RWO RO Size 32 bits PCI Express Slot related registers Bit Access Detault Description Value 31 19 RWO 0000h Physical Slot Number PSN Indicates the physical slot number attached to this Port 18 RO 1b Reserved Electromechanical I nterlock Present El P When set to 1b this bit 17 RO Ob indicates that an Electromechanical Interlock is implemented on the chassis for this slot Slot Power Limit Scale SPLS Specifies the scale used for the Slot Power Limit Value 00 1 0x 16 15 RWO 00b 01 0 1 10 0 01 11 0 001 If this field is written the link sends a Set_Slot_Power_Limit message Slot Power Limit Value SPLV In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by slot Power limit in 14 7 RWO 00h Watts is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field If this field is written the link sends a Set Slot Power Limit message 6 5 RO 00b Reserved 4 RO Ob Power Indicator Present PI P When set to 1b this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot 3 RO Ob Attention Indicator Present AIP When set to 1b this bit indicates that an Attention Indicator is electrically controlled by the chassis
409. viced by DRAM All writes are forwarded to DMI 10 Write Only All writes are sent to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet DRAM Controller Registers DO FO n tel 5 1 22 PAM5 Programmable Attribute Map 5 B D F Type Address Offset Default Value Access Size 0 0 0 PCI 95h 00h RO RW L 8 bits This register controls the read write and shadowing attributes of the BIOS areas from 0 0000 OE7FFFh i Default 4 22 Bit Access Value Description 7 6 RO 00b Reserved OE4000h OE7FFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from 0E4000 to OE7FFF 00 DRAM Disabled Accesses are directed to DMI 1 Read Only All reads are service DRAM All writes are forwarded t 5 4 RW L 00b 0 ied y eads are serviced by writes are forwa 10 Write Only All writes sent to DRAM Reads serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT 3 2 RO 00b Reserved 0 0000 OE3FFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0 0000 to OE3FFF 00 DRAM Disabled Accesses are directed to DMI 01 Read Only All reads are serviced by DRAM All writes are forwa
410. vide 16 bit decoding of VGA 1 0 address precluding the decoding of alias addresses every 1 KB This bit only has meaning if bit 3 VGA Enable of this register is also set to 1 enabling VGA 1 0 decoding and forwarding by the bridge 0 Execute 10 bit address decodes on VGA 1 0 accesses 1 Execute 16 bit address decodes VGA 1 0 accesses RW Ob VGA Enable VGAEN Controls the routing of processor initiated transactions targeting VGA compatible 1 0 and memory address ranges See the VGAEN MDAP table in device 0 offset 97h 0 RW Ob ISA Enable I SAEN Needed to exclude legacy resource decode to route ISA resources to legacy decode path Modifies the response by the to an 1 0 access issued by the processor that target ISA 1 0 addresses This applies only to I O addresses that are enabled by the IOBASE and IOLIMIT registers 0 All addresses defined by the IOBASE and IOLIMIT for processor I O transactions will be mapped to PCI Express 1 will not forward to PCI Express any 1 0 transactions addressing the last 768 bytes in each 1KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers RW Ob SERR Enable SERREN 0 No forwarding of error messages from secondary side to primary side that could result in an SERR 1 ERR_COR ERR_NONFATAL and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register
411. wer Controller Control setting or the occupancy of the slot If power fault detection is not supported this bit must not be set Attention Button Pressed ABP If an Attention Button is implemented 0 RO Ob this bit is set when the attention button is pressed If an Attention Button is not supported this bit must not be set 248 Datasheet Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only n tel 8 44 RCTL Root Control B D F Type Address Offset Default Value Access Size 0 6 0 PCI BC BDh 0000h RO RW 16 bits This register allows control of PCI Express Root Complex specific parameters The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error reported in this device s Device Status register or when an error message is received across the link Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register Bit Access perault Description Value 15 4 RO 000h Reserved PME Interrupt Enable PMEIE 0 No interrupts are generated as a result of receiving PME messages 3 RW Ob 1 Enables interrupt generation upon receipt of a PME message as reflected in the PME Status bit of the Root Status Register A PME interrupt is also generated if the PME Status bit of the Root Status Register is set when this bit is set from a cleared state
412. wer states in which this device may indicate PME wake via PCI Express messaging DO D3hot amp D3cold This 31 27 RO 19h device is not required to do anything to support D3hot and D3cold it simply must report that those states supported Refer to the PCI Power Management 1 1 specification for encoding explanation and other power management details D2 Power State Support D2PSS Hardwired to 0 to indicate that the D2 26 RO Ob power management state is NOT supported D1 Power State Support D1PSS Hardwired to 0 to indicate that the D1 25 RO Ob power management state is NOT supported 24 22 RO 000b Auxiliary Current AUXC Hardwired to 0 to indicate that there are no 3 3Vaux auxiliary current requirements Device Specific Initialization DSI Hardwired to 0 to indicate that special 21 RO Ob initialization of this device is NOT required before generic class device driver is to use it 20 RO Ob Auxiliary Power Source APS Hardwired to 0 PME Clock PMECLK Hardwired to 0 to indicate this device does NOT support 19 RO Ob PMEB generation 18 16 RO 011b PCI PM CAP Version PCI PMCV A value of 011b indicates that this function complies with revision 1 2 of the Power Management Interface Specification Pointer to Next Capability PNC This contains a pointer to the next item in 15 8 RO 90h the capabilities list If MSICH 7Fh is 0 then the next item in the capabilities list is the Message Signaled Inte
413. wide interfaces The buffers support SSTL 1 8 Stub Series Terminated Logic for 1 8 V signal interfaces The memory controller interface is fully configurable through a set of control registers System Memory Interface Details Directly supports one or two channels of DDR2 memory with a maximum of two DIMMs per channel Supports single and dual channel memory organization modes Supports a data burst length of eight for all memory organization modes Supports memory data transfer rates of 667 and 800 MHz for DDR2 O Voltage of 1 8 V for DDR2 Supports both un buffered ECC and non ECC DDR2 DIMMs The MCH does not support memory configurations that mix ECC and non ECC un buffered DIMMs Datasheet Introduction 1 2 3 Datasheet Supports maximum memory bandwidth of 6 4 GB s in single channel mode or 12 8 GB s in dual channel mode assuming DDR2 800 MHz Supports 512 Mb and 1 Gb DDR2 DRAM technologies for x8 and x16 devices Using 512 Mb device technologies the smallest memory capacity possible is 256 MB assuming Single Channel Mode with a single x16 single sided un buffered non ECC DIMM memory configuration Using 1 Gb device technologies the largest memory capacity possible is 8 GB assuming Dual Channel Mode with four x8 double sided un buffered non ECC or ECC DIMM memory configurations Note The ability to support greater than the largest memory capacity is subject to availability of higher density
414. width without the port transitioning through DL_Down status for reasons other than to attempt to correct unreliable link operation This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change 14 RWC Ob Link Bandwidth Management Status LBWMS This bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through DL Down status A link retraining initiated by a write of 1b to the Retrain Link bit has completed NOTE This bit is Set following any write of 1b to the Retrain Link bit including when the Link is in the process of retraining for some other reason Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation either through an LTSSM timeout or a higher level process This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change 13 RO Ob Data Link Layer Link Active Optional DLLLA This bit indicates the status of the Data Link Control and Management State Machine It returns a 1b to indicate the DL_Active state Ob otherwise This bit must be implemented if the corresponding Data Link Layer Active Capability bit is implemented Otherwise this bit must be hardwired to Ob 12 RO 1b Slot Clock Conf
415. witches Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to Ob Link Bandwidth Management I nterrupt Enable When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management 10 RW Ob Status bit has been set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Hardware Autonomous Width Disable When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width 2 ind 95 Devices that do not implement the ability autonomously to change Link width are permitted to hardwire this bit to Ob The MCH does not support autonomous width change So this bit is RO Enable Clock Power Management ECPM Applicable only for form factors that support a Clock Request CLKREQ mechanism this enable functions as follows 0 Clock power management is disabled and device must hold CLKREQ signal low 1 When this bit is set to 1 the device is permitted to use CLKREQ signal to 8 RO Ob power manage link clock according to protocol defined in appropriate form factor specification Default value of this field is Ob Components that do not support Clock Power Management as indicated by a Ob value in the Clock Power Management bit of the Link Capabilities Register must hardwire this bit to Ob Extended Synch E
416. xiliary current requirements Device Specific nitialization DSI Hardwired to 0 to indicate that special 21 RO Ob initialization of this device is NOT required before generic class device driver is to use it 20 RO Ob Auxiliary Power Source APS Hardwired to 0 PME Clock PMECLK Hardwired to 0 to indicate this device does NOT support 19 RO Ob generation 18 16 RO 011b PCI PM CAP Version PCI PMCV A value of 0116 indicates that this function complies with revision 1 2 of the PCI Power Management Interface Specification Pointer to Next Capability PNC This contains a pointer to the next item in 15 8 RO 90h the capabilities list If MSICH 7Fh is 0 then the next item in the capabilities list is the Message Signaled Interrupts MSI capability at 90h Capability ID CI D Value of O1h identifies this linked list item capability structure as being for PCI Power Management registers 7 0 RO 01 166 Datasheet Host Primary PCI Express Bridge Registers D1 FO tel 6 26 PM_CS1 Power Management Control Status B D F Type 0 1 0 PCI Address Offset 84 87h Default Value 00000008 Access RO RW RW P Size 32 bits Bit Access Default Description Value 31 16 RO 0000h Reserved PME Status PMESTS This bit indicates that this device does not support 15 RO Ob 6 PMEB generation from D3cold Data Scale DSCALE This field indicates th
417. xpress port 6 3 PCI CMD1 PCI Command B D F Type 0 1 0 PCI Address Offset 4 5h Default Value 0000h Access RO RW Size 16 bits Default Bit Access Value Description 15 11 RO 00h Reserved INTA Assertion Disable INTAAD 0 This device is permitted to generate INTA interrupt messages 1 This device is prevented from generating interrupt messages Any INTA 10 RW Ob interrupts already asserted must be de asserted when this bit is Only affects interrupts generated by the device PCI INTA from a PME event controlled by this command register It does not affect upstream MSIs upstream PCI INTA INTD assert and de assert messages Fast Back to Back Enable FB2B Not Applicable or Implemented Hardwired 9 RO Ob to 0 150 Datasheet Host Primary PCI Express Bridge Registers D1 FO tel Bit Access Default Description Value SERR Message Enable SERRE1 Controls Device 1 SERR messaging The MCH communicates the SERR condition by sending an SERR message to the ICH This bit when set enables reporting of non fatal and fatal errors detected by the device to the Root Complex Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control Register 8 RW Ob ape 0 The SERR message is generated by the for Device 1 only under conditions enabled individually through the Device Control Register
418. y 8 8 HDR1 Header Type B D F Type 0 6 0 PCI Address Offset Eh Default Value 018 Access RO Size 8 bits This register identifies the header layout of the configuration space No physical register exists at this location Default Bit Access Value Description 7 0 RO 01h Header Type Register HDR Returns 01 to indicate that this is a single function device with bridge header layout 8 9 PBUSN1 Primary Bus Number B D F Type 0 6 0 PCI Address Offset 18h Default Value 00 Access RO Size 8 bits This register identifies that this virtual Host PCI Express bridge is connected to PCI bus 0 Default S Bit Access Value Description Primary Bus Number BUSN Configuration software typically programs this 7 0 RO 00h field with the number of the bus on the primary side of the bridge Since device 6 is an internal device its primary bus is always 0 these bits read only and are hardwired to 0 220 Datasheet m Host Secondary PCI Express Bridge Registers D6 FO Intel 3210 MCH only tel 8 10 SBUSN1 Secondary Bus Number B D F Type 0 6 0 PCI Address Offset 19h Default Value 00h Access RW Size 8 bits This register identifies the bus number assigned to the second bus side of the virtual bridge This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express Default Bit Access Va
419. y read write or disabled Typically these blocks are mapped through MCH and are subtractive decoded to ISA space Memory that is disabled is not remapped Non snooped accesses from PCI Express or DMI to this region are always sent to DRAM Table 2 Expansion Area Memory Segments Memory Segments Attributes Comments 0 0000 OC3FFFh WE RE Add on BIOS 0C4000h OC7FFFh WE RE Add on BIOS 0C8000h OCBFFFh WE RE Add on BIOS 0CCOO00h OCFFFFh WE RE Add on BIOS 000000 OD3FFFh WE RE Add on BIOS 0D4000h 0D7FFFh WE RE Add on BIOS 0D8000h ODBFFFh WE RE Add on BIOS ODCOOO0h ODFFFFh WE RE Add on BIOS 3 1 3 Extended System BI OS Area E 0000h E FFFFh This 64 KB area 000 0000h OOOE_FFFFh is divided into four 16 KB segments Each segment can be assigned independent read and write attributes so it can be mapped either to main DRAM or to DMI Interface Typically this area is used for RAM or ROM Memory segments that are disabled are not remapped elsewhere Non snooped accesses from PCI Express or DMI to this region are always sent to DRAM Table 3 Extended System BIOS Area Memory Segments Memory Segments Attributes Comments 0 0000 OE3FFFh WE RE BIOS Extension 0 4000 OE7FFFh WE RE BIOS Extension OE8000h OEBFFFh WE RE BIOS Extension OECOOOh OEFFFFh WE RE BIOS Extension Datasheet 39 m n tel System Address Map Table 4 3 1 5 3 2
420. y Pull down RCOMP 1 0 DDR_RCOMPYPU A System Memory Pull up RCOMP DDR_VREF A System Memory Reference Voltage DDR_RCOMPVOH A System Memory Pull up Reference Signal DDR_RCOMPVOL System Memory Pull down Reference Signal PCI Express Interface Signals Signal Name Type Description Primary PCI Express Receive Differential Pair For the 3200 MCH a maximum width of x8 is supported The PEG RXN 15 0 1 0 upper 8 lanes are used for static lane reversal This also applies to PEG_RXP_ 15 0 PCIE the 3210 dual x8 mode For the 3210 MCH in single x16 mode the MCH supports a maximum width of x16 where all lanes are used Primary PCI Express Transmit Differential Pair For the 3200 MCH a maximum width of x8 is supported The PEG_TXN_ 15 0 upper 8 lanes used for static lane reversal This also applies to PEG_TXP_ 15 0 PCIE the 3210 in dual x8 mode For the 3210 MCH in single x16 mode the MCH supports a maximum width of x16 where all lanes are used Secondary PCI Express Receive Differential Pair PEG2_RXN_ 15 0 o Note When using the 3210 in dual x8 mode the PEG2 RXP 15 0 PCIE supports a maximum width of x8 The upper 8 lanes are used for 3210 MCH only static lane reversal For the 3200 MCH these signals are No Connects Secondary PCI Express Transmit Differential Pair PEG2 TXN 15 0 Note When using the 3210 in dual 8 mode the PEG2

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