Elixir RAM DDR2 2GB, 800Mhz, 128Mx8, CL5
Contents
1. FRONT 67 60 a gt 63 60 e gt oO Oo LLII A gt a a TTT NK oO 2 S 8 S So N 2X O Y PaO O i tt aa 199 l x y N I 2 15 11 40 N _J 2 g Tia gt q gt Detail A N Detail B 4 20 p 47 40 p P 2 70 2 45 gt lt BACK SIDE 3 80 MAX U gt O O 1 00 0 10 gt Detail A Detail B x lt lt 0 45 4 00 0 10 a fen N oO A o ha 1 00 0 1 A 080 8 Note All dimensions are typical with tolerances of 0 15 unless otherwise stated Units Millimeters Inches Note Device position and scale are only for reference REV 1 1 18 07 2008 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F MZ2N2G64TU8HD6B es 1GB 128M x 64 2GB 256M x 64 Celixir Unbuffered DDR2 SO DIMM Revision Log Rev Date Modifi2. oO S a x D GooS D N E z S s S o S N Sy 2X ok L wa Zs 1 80 1 39 7 N 41 Fa S 199 N 7 v 2 15 1140 iA Mw ji gt a gt Detail A Detail B 4 20 b 47 40 x e 2 70 p lo 2 45 IDE BACK S 1 00 0 10 ain ttt O O C 3 80 MAX gt a Detail A Detail B x lt g 0 45 4 00 0 10 D gt _ rm A oO A p 1 00 0 1 t in 0 60 8 N Note All dimensions are typical with tolerances of 0 15 unless otherwise stated Units Millimeters Inches Note Device position and scale are only for reference REV 1 1 17 07 2008 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B ie 1GB 128M x 64 2GB 256M x 64 Celixir Unbuffered DDR2 SO DIMM Package Dimensions 2GB 2 Ranks 128M x8 DDR2 SDRAMs
3. 2431 2523 mA IDD6 Self Refresh Current CKE lt 0 2V 194 194 mA Operating Current four bank four bank interleaving with BL 4 address IDD7 and control inputs randomly changing 50 of data changing at every 2593 2991 mA transfer tac trc min lour OMA Note Module IDD was calculated from component IDD It may differ from the actual measurement REV 1 1 14 07 2008 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SO DIMM iming Specifications for 2 evices Used on Module Tcase 0 C 85 C Vona 1 8V 0 1V Voo 1 8V 0 1V See AC Characteristics Part 1 of 2 Symbol Parameter Ae Unit Notes Min Max Min Max tac DQ output access time from CK CK 0 48 0 52 0 40 0 40 ns tpascx DQS output access time from CK CK 0 4 0 4 0 35 0 35 ns tcH CK high level width 0 48 0 52 0 48 0 52 tck teL CK low level width 0 48 0 52 0 48 0 52 tok ve anaa m te tet tet tck Clock Cycle Time 3 8 2 5 8 ns tDH DQ and DM input hold time 175 a 125 ps tps DQ and DM input setup time 100 50 ps tipw Input pulse width 0 6 0 6 tck tpipw DQ and DM input pulse width each input 0 35
4. 2 5 2 5 2 5 2 5 tok taor ODT turn off tacinin A liin t ng 2 5tcK 2 5tcK taorpp ODT turn off Power down mode ba bens eet ie ns 1 1 tanpp ODT to power down entry latency 3 3 tck taxpp ODT power down exit latency 8 8 E tex Speed Grade Definition Symbol Parameter al Min Max Min Max tras Row Active Time 45 70000 45 70000 ns trop RAS to CAS delay 15 12 5 ns tro Row Cycle Time 60 57 5 ns trp Row Precharge Time 15 12 5 ns REV 1 1 16 07 2008 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B n 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR2 SO DIMM Package Dimensions 1GB 2 Ranks 64Mx16 DDR2 SDRAMs FRONT 67 60 l 63 60 l lt gt
5. 2GB 256M x 64 Unbuffered DDR2 SO DIMM Serial Presence Detect 1GB 2 Ranks 64Mx16 DDR2 SDRAMs Part 1 of 2 SPD Entry Value Serial PD Data Entry Hex Note Byte Description 3C AC 3C AC 0 Number of Serial PD Bytes Written during Production 128 80 80 1 Total Number of Bytes in Serial PD device 256 08 08 2 Fundamental Memory Type DDR2 SDRAM 08 08 3 Number of Row Addresses on Assembly 13 oD oD 4 Number of Column Addresses on Assembly 10 0A 0A 5 Number of DIMM Ranks Package and Height Module Height 30 0mm 2 ranks 61 61 6 Data Width of Assembly X64 40 40 7 Reserved Undefined 00 00 8 Voltage Interface Level of this Assembly SSTL 1 8V 05 05 9 DDR2 SDRAM Device Cycle Time at CL 5 3ns 2 5ns 30 25 10 ae ee Device Access Time tac from Clock 0 45ns 0 4ns 45 40 Non Address Command Parity 11 DIMM Configuration Type Non Data ECC 00 00 Non Data Parity 12 Refresh Rate Type 7 8 us 82 82 13 Primary DDR2 SDRAM Width X16 10 10 14 Error Checking DDR2 SDRAM Device Width Undefined 00 00 15 Reserved Undefined 00 00 16 eee Device Attributes Burst Length 48 oc oC 17 eee SDRAM Device Attributes Number of Device 8 08 08 18 ries ie aa Device Attributes CAS Latencies 3 4 5 38 38 19 DIMM Mechanical Characteristics x lt 3 80 mm 01 01 20 DDR2 SDRAM DIMM Type Information SO DIMM 67 6mm 04 04 Analysi
6. DQ7 65 Vss 66 Vss 115 CS1 116 A13 NC 165 Vss 166 CK1 17 DQ2 18 Vss 67 DM3 68 DQS3 117 Voo 118 Voo 167 DQS6 168 Vss 19 DQ3 20 DQ12 69 NC 70 DQS3 119 ODT1 120 NC 169 DQS6 170 DM6 21 Vss 22 DQ13 71 Vss 72 Vss 121 Vss 122 Vss 171 Vss 172 Vss 23 DQ8 24 Vss 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 Vss 28 Vss 77 Vss 78 Vss 127 Vss 128 Vss 177 Vss 178 Vss 29 DQS1 30 CKO 79 CKEO 80 CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60 31 DQS1 32 CKO 81 Vop 82 Vop 131 DQS4 132 Vss 181 DQ57 182 DQ61 33 Vss 34 Vss 83 NC 84 NC 133 Vss 134 DQ38 183 Vss 184 Vss 35 DQ10 36 DQ14 85 BA2 86 NC 135 DQ34 136 DQ39 185 DM7 186 DQS7 37 DQ11 38 DQ15 87 Vop 88 Vop 137 DQ35 138 Vss 187 Vss 188 DQS7 39 Vss 40 Vss 89 A12 90 A11 139 Vss 140 DQ44 189 DQ58 190 Vss 41 Vss 42 Vss 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQi6 44 DQ20 93 A8 94 A6 143 DQ41 144 Vss 193 Vss 194 DQ63 45 DQ17 46 DQ21 95 Voo 96 Vop 145 Vss 146 DQS5 195 SDA 196 Vss 47 Vss 48 Vss 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SAO 49 DQS2 50 NC 99 A3 100 A2 149 Vss 150 Vss 199 Vboseo 200 SA1 Note 1 All pin assignments are consistent for all 8 byte unbuffered versions 2 A13 is for 2GB modules only REV 1 1 3 07 2008 NANYA TECHNOLOGY CORPORATION NANYA reserves the right t
7. DQS CSi CKE1 ODT1 Dasi j Das DQS DM1 DM DM Da8 N Oo 10 0 DQ9 N 01 1O 1 DQ10 M O 2 D1 VO 2 D9 DQ11 M 103 10 3 DQ12 NV 104 VO 4 DQ13 M 05 VO5 pa14a _ 06 V0 6 DQ1I5S 107 VO 7 Das2 jy DQS CS0 CKEO ODTO DQS CS1 CKE1 ODT1 DQS2 M DQS DQS DM2 M DM DM DQ16 M 100 10 0 DQ17 M 101 VO 1 DQ18 NMN 102 D10 VO 2 D2 DQ1I9 MN 103 V0 3 DQ20 M O 4 VO 4 DQ21 M 105 VO5 DQ22 M 1 06 1 0 6 DQ23 M O7 O7 Dpas3 _ DQS CSO CKEO ODTO DQS CS1 CKE1 ODT1 DQS3 M DQS DQS DM3 M DM DM DQ24 M roo vO 0 DQ25 M O 1 1O 1 DQ26 M 02 D11 VO 2 D3 DQ27 M 03 VO 3 DQ28 M VO 4 VO 4 DQ29 M o5 VO5 DQ30 M o6 1 0 6 DQ31 M O7 O7 10 Ohms 5 poe i f BAO BA2 1 gt SDRAMS D0 D15 AO A1 sv SDRAMS DO D15 Vooso e gt 7 Ez RAS M gt SDRAMS D0 D15 D Sas i VREF er gt CAS gt SDRAMS DO D15 Veg _____ gt WE HM gt SDRAMS D0 D15 j ae i Notes Unless otherwise noted resistor values are 22 Ohms 5 DQ wiring may differ from that described in this drawing However DQ DM DQS DQS relationships are maintained as shown REV 1 1 07 2008 Das4 j __ DAS CSO CKEO ODTO DQS CSi CKE1 ODT1 pas4 DQ
8. M 02 V02 o3 O3 pass O3 03 N 104 VO 4 DQ36 N 1 04 VO 4 M 05 05 DQ37 M O5 VO5 NH o6 vO6 Dass v_ __ 06 1 06 M O7 VO7 Da39 M VO7 VO7 UDOS Do UDQS D4 Dass5 UDQS D2 UDOQS D6 M UDQS UDQS DQAS5 M UDQS UDQS NM UDM UDM DM5 M UDM UDM rosg O8 DQ40 MN O8 08 WN o9 vO9 Da4i v _ 09 09 M ro10 VO 10 DQ42 N O10 VO 10 M VO 11 VO 11 DQ43 M VO 11 O 11 NH vo 12 VO 12 DQ44 N 0 12 VO 12 WN 0 13 VO 13 DQ45 N VO 13 VO 13 NH O14 VO 14 DQ46 N VO 14 VO 14 NH 015 VO 15 DQ47 N VO 15 VO 15 bas cs C O pas CS C O Das _ bas CS C O pas CS C O M LDQS A 2 LDQS K 2 pase M LDQS i p LDQS K 2 NV LDM LDM DM6 LDM LDM M 00 00 DQ48 M 00 00 n O1 DQ49 N 101 O1 o2 O2 DQa50 M O2 V02 N 103 03 DQ51 M 103 03 Ww o4 O4 DQ52 M 104 VO 4 Vos VO5 DQ53 M 05 VO5 N4 106 06 DQ54 M O6 06 o7 VO7 DQa55 M O7 VO7 UDS Di UDQS D5 pas7 _ UDAS D3 UDQS D7 M UDQS UDQS DQS7 M UDQS UDQS M UDM UDM DM7 M UDM UDM M 08 08 pase M 08 08 V4 o9 09 DQ57 M o9 09 M VO 10 VO 10 DQ58 M VO 10 VO 10 M O11 VO 11 DQ59 N VO 11 VO 11 Ww VO 12 VO 12 Daso vW _ VO 12 VO 12 V4 VO 13 VO 13 DQ61 MN 0 13 VO 13 NH VO 14 VO 14 DQ62 NM 1O14 VO 14 o15 VO 15 DQ63 M VO 15 VO 15 BA N gt SDRAMS D0 D7 A12 N gt SDRAMS D0 D7 cko gt Jiba RAS N gt SDRAMS D0 D7 V psp gt SPD oads ad Voo 2 __ D0 D7 VDD and VDDQ o
9. 0 35 tox thz Data out high impedance time from CK CK tacmax tacmax NS t_z pq Data out low impedance time from CK CK 2tacmin tac max 2taC min tacmax NS tLz Das DQS low impedance time from CK CK taCmin tacmax tacmin tacmax NS toasa DQS DQ skew DQS amp associated DQ signals i 0 24 0 20 ns taHs Data hold Skew Factor 0 34 z 0 30 ns ton Data output hold time from DQS a ce ns tooss Write command to 1 DQS latching transition 0 25 0 25 0 25 0 25 tok tpasH DQS input high pulse width 0 35 0 35 tox toas DQS input low pulse width 0 35 0 35 tok toss a aa S to CK setup time 0 2 i 0 2 i tok ER E hold time from CK 0 2 i 0 2 i tok MRD Mode register set command cycle time 2 s 2 tex twest Write postamble 0 40 0 60 0 40 0 60 tck twere Write preamble 0 35 0 35 tck tiH Address and control input hold time 0 275 0 250 ns tis Address and control input setup time 0 2 0 175 ns trpre Read preamble 0 9 1 1 0 9 1 1 tck trpsr Read postamble 0 4 0 6 0 4 0 6 tck tbeiay Minimum time clocks remains ON after CKE ts tek _ ts tok n asynchronously drops Low tH tH tRFC Refresh to active Refresh command time 105 105 ns e as Interval 3 9 39 us REFI Average Periodic Refresh Interval 78 78 us 0 C lt Tcase lt 85 C REV 1 1 07 2008 15 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH
10. 2N1G64TUH8D6F M2N2G64TU8HD6B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SO DIMM erial Presence Detect 2GB 2 Ranks 128Mx8 DDR2 SDRAMs Part 1 of 2 _ SPD Entry Value Serial PD Data Entry Hex Note Byte Description 3C AC 3C AC 0 Number of Serial PD Bytes Written during Production 128 80 80 1 Total Number of Bytes in Serial PD device 256 08 08 2 Fundamental Memory Type DDR2 SDRAM 08 08 3 Number of Row Addresses on Assembly 14 0E 0E 4 Number of Column Addresses on Assembly 10 0A 0A 5 Number of DIMM Ranks Package and Height Module Height 30 0mm 2 ranks 61 61 6 Data Width of Assembly X64 40 40 7 Reserved Undefined 00 00 8 Voltage Interface Level of this Assembly SSTL 1 8V 05 05 9 DDR2 SDRAM Device Cycle Time at CL 5 3ns 2 5ns 30 25 10 oak eer Device Access Time tac from Clock 0 45ns 0 4ns 45 40 Non Address Command Parity 11 DIMM Configuration Type Non Data ECC 00 00 Non Data Parity 12 Refresh Rate Type 7 8 us 82 82 13 Primary DDR2 SDRAM Width X8 08 08 14 Error Checking DDR2 SDRAM Device Width Undefined 00 00 15 Reserved Undefined 00 00 16 apes ra Device Attributes Burst Length 48 oc 0c 17 pees SDRAM Device Attributes Number of Device 8 08 08 18 ae ee Device Attributes CAS Latencies 3 4 5 38 38 19 DIMM Mechanical Characteristics x lt 3 80 mm 01 01 20 DDR2 SDRAM DIMM Typ
11. 3 1447 mA once per clock cycle Precharge Power Down Standby Current all banks idle power down IDD2P 176 176 mA mode CKE lt Vit max tck tox Min IDD2Q Precharge quiet standby current 771 840 mA DDAN Idle Standby Current CS gt Vin min all banks idle CKE gt Vin minj tex tck 1115 1252 mA min address and control inputs changing once per clock cycle Active P D Standby C t bank active d IDD3PF ctive Power Down Standby Current one bank active power down 524 553 A mode CKE lt Vit wax tex tex MIN MRS 1 2 0 Active P D Standby t bank active d IDDSPS ctive Power Down Standby Current one bank active power down 231 234 RAN mode CKE lt Vi max tex tck MIN MRS 12 1 Active Standby Current one bank active precharge CS gt Vin mmn CKE gt Vin MIN trc tras MAX tex tck MIN DQ DM and DQS inputs changing POIN twice per clock cycle address and control inputs changing once per clock iji 1069 mA cycle Operating Current one bank Burst 4 reads continuous burst address IDD4R and control inputs changing once per clock cycle DQ and DQS outputs 1572 1740 mA changing twice per clock cycle CL 4 tck tck min lour OMA Operating Current one bank Burst 4 writes continuous burst address IDD4W and control inputs changing once per clock cycle DQ and DQS inputs 1417 1556 mA changing twice per clock cycle CL 4 tek tek min IDD5B Burst Refresh Current tac trrc min
12. 8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TUSHD6B a 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR2 SO DIMM iming Specifications for 2 evices Used on NModauie Tcase 0 C 85 C Vona 1 8V 0 1V Voo 1 8V 0 1V See AC Characteristics Part 2 of 2 Symbol Parameter Unit Notes Min Max Min Max RRD Active bank A to Active bank B command 7 5 7 5 ns tccp CAS to CAS 2 2 tck twR Write recovery time 15 5 15 E ns WR Write recovery time with Auto Precharge twr tck twar tcx ns DAL Auto precharge write recovery precharge time ak tox twTrR Internal write to read command delay 7 5 7 5 ns tRTP Internal read to precharge command delay 7 5 7 5 ns txsup Exit self refresh to a Non read command T 0 a ns txsrop Exit self refresh to a Read command 200 i 200 tox typ Exit precharge power down to any Non read 2 2 i tox command txaron Exit active power down to read command 2 2 tox txanps Exit active power down to read command 7 AL E 8 AL s tck tCKE CKE minimum pulse width 3 E 3 tck toT OCD drive mode output delay 0 12 0 12 ns ODT taonp ODT turn on delay 2 2 2 2 tck taon ODT turn on tacmin taoma tacmin tacna ons tac min tok tac min tok taonpp ODT turn on Power down mode 42 Bete 42 te ns taorp ODT turn off delay
13. Current CKE lt 0 2V Operating Current four bank four bank interleaving with BL 4 address and control inputs randomly changing 50 of data changing at every transfer tac trc min lour OMA PC2 5300 3C 693 796 88 379 549 250 106 510 928 804 1223 97 1751 Note Module IDD was calculated from component IDD It may differ from the actual measurement REV 1 1 13 07 2008 PC2 6400 AC 782 900 88 412 620 265 106 561 1032 886 1270 97 1952 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TUSHD6B tee 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR2 SO DIMM Operating Standby and Refresh Currents Tcase 0 C 85 C Vipa Von 1 8V 0 1V 2GB 2 Ranks 128M x 8 DDR2 SDRAMs PC2 5300 PC2 6400 Symbol Parameter Condition Unit 3C AC Operating Current one bank active precharge tac tre min tek tek Min IDDO DQ DM and DQS inputs changing twice per clock cycle address and 1379 1556 mA control inputs changing once per clock cycle Operating Current one bank active read precharge Burst 4 tre trac IDD1 minj CL 4 tok tex min lour OMA address and control inputs changing 129
14. M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SO DIMM elixir Based on DDR2 667 800 64Mx16 1GB 128Mx8 2GB SDRAM D Die Features Performance PC2 5300 PC2 6400 Apea aon 3C AC Unit DIMM CAS Latency 5 5 fck Clock Freqency 333 400 MHz tck Clock Cycle 3 2 5 ns Data Transfer Speed 667 800 Mbps e 200 Pin Small Outline Dual In Line Memory Module SO DIMM e 1GB 128Mx64 Unbuffered DDR2 SO DIMM based on 64Mx16 DDR2 SDRAM D Die devices e 2GB 256Mx64 Unbuffered DDR2 SO DIMM based on 128Mx8 DDR2 SDRAM D Die devices Intended for 333MHz and 400MHz applications e Inputs and outputs are SSTL 18 compatible e Voo Vong 1 8V 0 1V SDRAMs have 8 internal banks for concurrent operation e Differential clock inputs e Data is read or written on both clock edges e DRAM DLL aligns DQ and DQS transitions with clock transitions e Address and control signals are fully synchronous to positive clock edge e Auto Refresh CBR and Self Refresh Modes Description e Automatic and controlled precharge commands e Programmable Operation DIMM CAS Latency 3 4 5 Burst Type Sequential or Interleave Burst Length 4 8 Operation Burst Read and Write 13 10 2 Addressing 1GB e 14 10 2 Addressing 2GB e 7 8 us Max Average Periodic Refresh Interval e Serial Presence Detect e Gold contacts 1GB module s SDRAMs ar
15. M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B a 1GB 128M x 64 2GB 256M x 64 elixir Unbuffered DDR2 SO DIMM Environmental Requirements Symbol Parameter Rating Units Topr Operating Temperature ambient 0 to 65 C Hopr Operating Humidity relative 10 to 90 Tstg Storage Temperature 50 to 100 ce Hstg Storage Humidity without condensation 5 to 95 Barometric pressure operating amp storage up to 9850ft 105 to 69 kPa Note Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability Absolute Maximum DC Ratings Symbol Parameter Rating Units VDD Voltage on VDD pins relative to Vss 1 0 to 2 3 V VDDQ Voltage on VDDQ pins relative to Vss 0 5 to 2 3 V VDDL Voltage on VDDL pins relative to Vss 0 5 to 2 3 V Vins Vout Voltage on I O pins relative to Vss 0 5 to 2 3 V TsTG Storage Temperature Plastic 55 to 100 C Note Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may a
16. cation 1 0 03 2008 Official Release 1 1 07 2008 Revision update Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd Kueishan Taoyuan 333 Taiwan R O C Tel 886 3 328 1688 Please visit our home page for more information www nanya com Printed in Taiwan 2008 REV 1 1 19 07 2008 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
17. ds are ignored but previous operations continue When sampled at the positive rising edge of the clock RAS CAS WE define the operation to be executed by the SDRAM Reference voltage for SSTL 18 inputs On Die Termination control signals Selects which SDRAM bank is to be active During a Bank Activate command cycle AO A12 A13 define the row address RAO RA12 RA13 when sampled at the rising clock edge A13 applies on 2GB SODIMM only During a Read or Write command cycle A0 A9 defines the column address CAO CA9 when sampled at the rising clock edge In addition to the column address AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle If AP is high autoprecharge is selected and BAO BA1 BA2 define the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BA1 BA2 to control which bank s to precharge If AP is high all 8 banks will be precharged regardless of the state of BAO BA1 BA2 If AP is low then BAO BA1 BA2 are used to define which bank to pre charge Data and Check Bit Input Output pins Power and ground for the DDR2 SDRAM input buffers and core logic Data strobe for input and output data The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no eff
18. e 84 ball BGA Package 2GB module s SDRAMs are 60 ball BGA Package RoHS compliance M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F and M2N2G64TU8HDEB are unbuffered 200 Pin Double Data Rate 2 DDR2 Synchronous DRAM Small Outline Dual In Line Memory Module SO DIMM organized as two ranks of 128Mx64 1GB 256Mx64 2GB high speed memory array M Z2N1G64TUH8D4F M2N1G64TUH8D5F and 2N1G64TUH8D6F use eight 64Mx16 84 ball BGA packaged devices and M2N2G64TU8HD4B M2N2G64TU8HD5B and M2N2G64TU8HDE6B use sixteen 128Mx8 60 ball BGA packaged devices These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR2 SODIMMs provide a high performance flexible 8 byte interface in a space saving footprint The DIMM is intended for use in applications operating of 333MHz 400MHz clock speeds and achieves high speed data transfer speed of 667Mbps 800Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs A0 A12 1GB AO A13 2GB and I O inputs BAO BA1 and BA2 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial EEPROM using a standard IIC protocol The first 128 bytes of SPD data are programmed and locked during module assembly The remaining 128 bytes are available f
19. e Information SO DIMM 67 6mm 04 04 Analysis probe installed No 21 DDR2 SDRAM Module Attributes re e 00 00 Number of Active Registers 1 Supports Weak Driver 22 DDR2 SDRAM Device Attributes General Supports 50 ohm ODT 07 07 Supports PASR 23 Minimum Clock Cycle at CL 4 3 75ns 3D 3D 24 Maximum Data Access Time from Clock at CL 4 0 5ns 50 50 25 Minimum Clock Cycle Time at CL 3 5ns 50 50 26 Maximum Data Access Time from Clock at CL 3 0 6ns 60 60 27 Minimum Row Precharge Time trp 15ns 12 5ns 3C 32 28 Minimum Row Active to Row Active delay trrp 7 5ns 1E 1E 29 Minimum RAS to CAS delay taco 15ns 12 5ns 3C 32 30 Minimum Active to Precharge Time tras 45ns 2D 2D 31 Module Rank Density 1GB 01 01 32 i and Command Setup Time Before Clock 0 2ns 0 17ns 20 17 33 Address and Command Hold Time After Clock ti 0 27ns 0 25ns 27 25 34 Data Input Setup Time Before Clock tps 0 1ns 0 05ns 10 05 35 Data Input Hold Time After Clock tDH 0 17ns 0 12ns 17 12 36 Write Recovery Time twa 15ns 3C 3C REV 1 1 9 07 2008 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SO DIMM Serial Presence Detect 2GB 2 Ranks 128 M x 8 DDR2 SDRAMs Part 2 of 2 Byte 37 38 39 40 41 42 43 44 45 46 61 62 63 64 71 72 73 91 92 255 N
20. ect DM8 is associated with check bits CBO CB7 and is not used on x64 modules Address inputs Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address This bi directional pin is used to transfer data into or out of the SPD EEPROM A resistor must be connected from the SDA bus line to V DD to act as a pull up This signal is used to clock data into and out of the SPD EEPROM A resistor may be connected from the SCL bus time to V DD to act as a pull up Serial EEPROM positive power supply NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SO DIMM Functional Block Diagram 1GB 2 Ranks 64Mx16 DDR2 SDRAMs ODT1 ODTO CKE1 CKEO BAO AO Notes 3 Ohms 5 WW pas tS C O DaS CSC O Das m DaS CS C O IDAS CS C O ENYE ocs K p LDQS r p pas4 _ _ LD s x p LDQS K p N LDM LDM DM4 N LDM LDM roo 00 DQ32 M 00 00 NH oi O1 DQ33 _ 101 vO1 N 02 vO2 DQ34
21. eter Condition Rtt effective impedance value for EMRS A6 A2 0 1 750hm Rtt effective impedance value for EMRS A6 A2 1 0 1500hm Rtt effective impedance value for EMRS A6 A2 1 1 500hm Deviation of Vm with respect to VDDQ 2 Note1 Test condition for Rtt measurements Input AC DC logic level Symbol Parameter VIH AC Input High Logic1 Voltage VIL AC Input Low Logic0 Voltage VIH DC Input High Logic1 Voltage VIL DC Input Low LogicO Voltage REV 1 1 07 2008 Symbol Min Nom Rtt1 eff 60 75 Rtt2 eff 120 150 Rtt3 eff 40 50 Delta VM 6 PC2 5300 PC2 6400 Min Max Min Max VREF VREF i 0 200 0 200 7 VREF i VREF 0 200 0 200 VREF VREF 0 125 VDDQ 0 3 0 125 VDDQ 0 3 VREF VREF 0 3 0 125 a3 0 125 12 Max Units Note 90 ohm 1 180 ohm 1 60 ohm 1 6 1 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUHS8D6F M2N2G64TUSHD6B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SO DIMM Operating Standby and Refresh Currents Tcase 0 C 85 C Vona Voo 1 8V 0 1V 1GB 2 Ranks 64Mx16 DDR2 SDRAMs Symbol IDDO IDD1 IDD2P IDD2Q IDD2N IDD3PF IDD3PS IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 Parameter Condition Operating Current one bank active precharge tac trc min tek tek Min DQ DM and DQS inpu
22. f gt CAS _ gt SDRAMS D0 D7 Ba pi VREF gt DO D7 iy WEN SDRAMS D0 D7 ne aa DO D7 SPD 4 loads Vopip 9 CKI gt Serial PD sc sAo gt 1 DQ wiring may differ from thai ribed in this drawing SA1 _ gt 2 DODOS DME S SS a ented ae chow wP gt gt AO Al A2 P gt SDA 3 DQ DQS DM DQS resistors are 22 5 Ohms T T FA 4 Voom strap connections for memory device Vop Vona SAO SA1 STRAP OUT OPEN Voo Vova STRAP IN Vss Vopis not equal to Vona REV 1 1 07 2008 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SO DIMM Functional Block Diagram 2GB 2 Ranks 128M x8 DDR2 SDRAMs 3 Ohms 5 ODT1 M ODTO0 M CKE1 CKEO csi cso Daso j w DQS CSO CKEO ODTO DQS CS1 CKE1 ODT1 DQS0 M DQS DQS DMO N H DM DM Dao N O0 V0 0 pai M 1O 1 1O 1 DQ2 M 102 DO VO 2 D8 Da3 WW _ 103 V0 3 DQ4 N 04 VO 4 pas Vw 105 VO5 pas VW _ 06 V0 6 DQ7 M 107 107 DQSI1 M Das CSO CKEO ODTO
23. ffect reliability Storage temperature is the case surface temperature on the center top side of the DRAM Operating temperature Conditions Symbol Parameter Rating Units Note TCASE Operating Temperature Ambient 0 to 95 C 1 Note 1 Case temperature is measured at top and center side of any DRAMs 2 tcase gt 85 C gt tper 3 9 us DC Electrical Characteristics and Operating Conditions Symbol Parameter Min Max Units Notes VDD Supply Voltage 1 7 1 9 V 1 VDDL DLL Supply Voltage 1 7 1 9 V 1 VDDQ Output Supply Voltage 1 7 1 9 V 1 Vss VSSQ_ Supply Voltage I O Supply Voltage 0 0 V VREF Input Reference Voltage 0 49VDDQ 0 51VDDQ V 1 2 VTT Termination Voltage VREF 0 04 VREF 0 04 V 3 Note 1 There is no specific device VDD supply voltage requirement for SSTL_18 compliance However VDDQ must be less than or equal to VDD under all conditions 2 VREF is expected to be equal to 0 5 V DDQ of the transmitting device and to track variations in the DC level of the same Peak to peak noise on VREF may not exceed 2 of the DC value 3 VTT of transmitting device must track VREF of receiving device REV 1 1 11 07 2008 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SO DIMM ODT DC Electrical Characteristics Param
24. ite to Read Command delay twrn Internal Read to Precharge delay trate Reserved Extension of Byte 41 trc and Byte 42 tarc Minimum Core Cycle Time tac Min Auto Refresh Command Cycle Time tarc Maximum Clock Cycle Time tcx Max DQS DQ Skew Factor tQHS Read Data Hold Skew Factor tQHS Reserved SPD Reversion Checksum for Byte 0 62 Manufacturer s JEDEC ID Code Module Manufacturing Location Module Part number Reserved Module part number M2N1G64TUH8D4F 3C 4D324E31473634545548384434462D33432020 M2N1G64TUH8D4F AC 4D324E31473634545548384434462D41 432020 M2N1G64TUH8D5F 3C 4D324E31473634545548384435462D33432020 M2N1G64TUH8D5F AC4D324E31473634545548384435462D41 432020 M2N1G64TUH8D6F 3C 4D324E31473634545548384436462D33432020 M2N1G64TUH8D6F AC4D324E31473634545548384436462D41 432020 REV 1 1 07 2008 SPD Entry Value elixir Serial PD Data Entry Hex 3C AC 3C AC 7 5ns 1E 1E 7 5ns 1E 1E Undefined 00 00 The number below a decimal point of tRC and tRFC are 0 tRFC is less than 06 36 256ns 60ns 57 5ns 3C 39 127 5ns 7F 7F 8ns 80 80 0 24ns 0 2ns 18 14 0 34ns 0 3ns 22 1E Undefined 00 00 1 3 13 13 Checksum Data AA 90 Nanya 7F7F7FOB00000000 Manufacturing code Module Part Number in ASCII Undefined Note NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B elixir M
25. o change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SO DIMM Input Output Functional Description Symbol CKO CK1 CK1 a CKEO CKE1 VREF ODTO ODT1 BAO BA1 BA2 A0 A9 A10 AP A11 A12 A13 DQO DQ63 Vopn Vss DQS0 DQS7 DQS0 DQS7 DMO DM7 SAO SA1 SDA SCL Vopspp REV 1 1 07 2008 Type SSTL SSTL SSTL SSTL SSTL Supply Input SSTL SSTL SSTL Supply SSTL Input Supply Polarity Positive Edge Negative Edge Active High Active Low Active Low Active High Active High Negative and Positive Edge Active High Function The positive line of the differential pair of system clock inputs which drives the input to the on DIMM PLL All the DDR2 SDRAM address and control inputs are sampled on the rising edge of their associated clocks The negative line of the differential pair of system clock inputs which drives the input to the on DIMM PLL Activates the SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new comman
26. or use by the customer REV 1 1 1 07 2008 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SO DIMM Ordering Information Part Number M2N2G64TU8HD4B AC DDR2 800 PC2 6400 M2N2G64TU8HD4B 3C DDR2 667 PC2 5300 M2N2G64TU8HD5B AC DDR2 800 PC2 6400 M2N2G64TU8HD5B 3C DDR2 667 PC2 5300 M2N2G64TU8HD6B AC DDR2 800 PC2 6400 M2N2G64TU8HD6B 3C DDR2 667 PC2 5300 M2N1G64TUH8D4F AC DDR2 800 PC2 6400 M2N1G64TUH8D4F 3C DDR2 667 PC2 5300 M2N1G64TUH8D5F AC DDR2 800 PC2 6400 M2N1G64TUH8D5F 3C DDR2 667 PC2 5300 M2N1G64TUH8D6F AC DDR2 800 PC2 6400 Speed 400MHz 2 50ns CL 5 333MHz 3 00ns CL 5 400MHz 2 50ns CL 5 333MHz 3 00ns CL 5 400MHz 2 50ns CL 5 400MHz 2 50ns CL 5 333MHz 3 00ns CL 5 400MHz 2 50ns CL 5 333MHz 3 00ns CL 5 400MHz 2 50ns CL 5 Organization M2N1G64TUH8D6F 3C Pin Description DDR2 667 PC2 5300 333MHz 3 00ns CL 5 333MHz 3 00ns CL 5 CKO CK1 CKO CK1 Differential Clock Inputs DQO0 DQ63 CKEO CKE1 Clock Enable DQS0 DQS7 RAS Row Address Strobe DQs0 DQS7 CAS Column Address Strobe DM0 DM7 WE Write Enable Voo CSO CS1 Chip Selects VREF A0 A9 A11 A13 Row Address Inputs VbpsPo A0 A9 Column Address Inputs V
27. ote 1 Description Internal Write to Read Command delay twrn Internal Read to Precharge delay trate Reserved Extension of Byte 41 trc and Byte 42 tarc Minimum Core Cycle Time tac Min Auto Refresh Command Cycle Time tarc Maximum Clock Cycle Time tcx Max DQS DQ Skew Factor tQHS Read Data Hold Skew Factor tQHS Reserved SPD Reversion Checksum for Byte 0 62 Manufacturer s JEDEC ID Code Module Manufacturing Location Module Part number Reserved Module part number M2N2G64TU8HD4B 3C gt 4D324E32473634545538484434422D33432020 M2N2G64TU8HD4B AC 4D324E32473634545538484434422D41 432020 M2N2G64TU8HD5B 3C 4D324E32473634545538484435422D33432020 M2N2G64TU8HD5B AC 4D324E32473634545538484435422D41 432020 M2N2G64TU8HD6B 3C 4D324E32473634545538484436422D33432020 M2N2G64TU8HD6B AC4D324E32473634545538484436422D41 432020 REV 1 1 07 2008 SPD Entry Value elixir Serial PD Data Entry Hex 3C AC 3C AC 7 5ns 1E 1E 7 5ns 1E 1E Undefined 00 00 The number below a decimal point of tRC and tRFC are 0 tRFC is less than 06 36 256ns 60ns 57 5ns 3C 39 127 5ns 7F 7F 8ns 80 80 0 24ns 0 2ns 18 14 0 34ns 0 3ns 22 1E Undefined 00 00 1 3 13 13 Checksum Data 1A 00 Nanya 7F7F7FOB00000000 Manufacturing code Module Part Number in ASCII 10 Undefined Note NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B
28. s DQs pM4 DM DM Da32 _ 00 0 0 DQ33 M vO 1 vo 1 Dpas4 _ 0 2 D4 10 2 D12 DQ35 M 103 10 3 DQ36 M 104 I O 4 DQ37 M 105 105 pass 106 1 0 6 DQ39 M 107 107 Das5 mM DQS CSO CKEO ODTO DQS CSi CKE1 ODT1 Dass _ DQS DQs DM5 W DM DM Da4o _ oo 1 0 0 DQ4 N 101 vO 1 DQ42 M VO 2 DS 10 2 D13 Da43a _ 03 V0 3 DQ44 N 104 VO 4 DQ45 M O 5 105 pase 06 1 0 6 DQ47 N 107 107 pase M DQS CSO CKEO ODTO DQS CSi CKE1 ODT1 passe _ DQS DQs DM6 _ DM DM Doss _ 00 1 0 0 DQ49 N 101 vO 1 DQ50 M 102 D14 vO 2 D6 DQ51 M 103 10 3 DQ52 NM 104 I O 4 DQ53 M O5 105 pas4 _ 06 1 0 6 DQ55 M 107 107 DAS7 M DQS CSO CKEO ODTO DQS CS1 CKE1 ODT1 bpas7 Das Das DM7 W DM DM pass 00 1 0 0 DQ57 M VO 1 vo 1 pass W _ 0 2 D15 VO 2 D7 DQ59 M 103 103 DQ60 M VO 4 VO 4 Desi o5 105 DQ62 O6 1 0 6 DQ63 M O7 107 CcKo _ _ 5 6pF 8 loads Serial PD CKO _ _ SDRAMS DO0 D15 VDD and VDDQ CK1 _ gt SDRAMS D0 D15 _ 7 56pF 8loads SDRAMS D0 D15 and SPD CK 1 _ gt Serial PD scL yp I SCL sao AO SA1 gt A 4 gt SDA g WP NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B elixir M2N1G64TUH8D6F M2N2G64TU8HD6B 1GB 128M x 64
29. s probe installed No 21 DDR2 SDRAM Module Attributes cs ech sel rac 00 00 Number of Active Registers 1 Supports Weak Driver 22 DDR2 SDRAM Device Attributes General Supports 50 ohm ODT 07 07 Supports PASR 23 Minimum Clock Cycle at CL 4 3 75ns 3D 3D 24 Maximum Data Access Time from Clock at CL 4 0 5ns 50 50 25 Minimum Clock Cycle Time at CL 3 5ns 50 50 26 Maximum Data Access Time from Clock at CL 3 0 6ns 60 60 27 Minimum Row Precharge Time trp 15ns 12 5ns 3C 32 28 Minimum Row Active to Row Active delay trrp 10ns 28 28 29 Minimum RAS to CAS delay taco 15ns 12 5ns 3C 32 30 Minimum Active to Precharge Time tras 45ns 2D 2D 31 Module Rank Density 512MB 80 80 32 oo and Command Setup Time Before Clock 0 2ns 0 17ns 20 17 33 Address and Command Hold Time After Clock ti 0 27ns 0 25ns 27 25 34 Data Input Setup Time Before Clock tps 0 1ns 0 05ns 10 05 35 Data Input Hold Time After Clock tDH 0 17ns 0 12ns 17 12 36 Write Recovery Time twa 15ns 3C 3C REV 1 1 7 07 2008 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR2 SO DIMM Serial Presence Detect 1GB 2 Ranks 64Mx16 DDR2 SDRAMs Part 2 of 2 Byte 37 38 39 40 41 42 43 44 45 46 61 62 63 64 71 72 73 91 92 255 Note 1 Description Internal Wr
30. ss A10 AP Column Address Input Auto precharge SCL BAO BA1 BA2 SDRAM Bank Address Inputs SDA ODTO ODT1 Active termination control lines SAO SA1 NC No Connect Note A13 is only support in 2GB module type REV 1 1 07 2008 Power Leads Note 256Mx64 1 8V Gold 128Mx64 Data input output Bidirectional data strobes Differential data strobes Input Data Masks Power 1 8V Ref Voltage for SSTL_18 inputs Serial EEPROM positive power supply Ground Serial Presence Detect Clock Input Serial Presence Detect Data input output Serial Presence Detect Address Inputs NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8D4F M2N2G64TU8HD4B M2N1G64TUH8D5F M2N2G64TU8HD5B M2N1G64TUH8D6F M2N2G64TU8HD6B ee 1GB 128M x 64 2GB 256M x 64 Celixir Unbuffered DDR2 SO DIMM 1GB 2GB DDR2 SDRAM SODIMM Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 2 Vss 51 DQS2 52 DM2 101 A1 102 AO 151 DQ42 152 DQ46 Vss 4 DQ4 53 Vss 54 Vss 103 Vop 104 Voo 153 DQ43 154 DQ47 DQO 6 DQ5 55 DQ18 56 DQ22 105 A10 AP 106 BA1 155 Vss 156 Vss Dat 8 Vss 57 DQ19 58 DQ23 107 BAO 108 RAS 157 DQ48 158 DQ52 on oO wo Vss 10 DMO 59 Vss 60 Vss 109 WE 110 CSO 159 DQ49 160 DQ53 11 DQSO 12 Vss 61 DQ24 62 DQ28 111 Vop 112 Voo 161 Vss 162 Vss 13 DQSO 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODTO 163 NC 164 CK1 15 Vss 16
31. ts changing twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank active read precharge Burst 4 tre trc minj CL 4 tok tex min lour OMA address and control inputs changing once per clock cycle Precharge Power Down Standby Current all banks idle power down mode CKE lt Vit max tck tck min Precharge quiet standby current Idle Standby Current CS gt Vin min all banks idle CKE gt Vin minj tex tck min address and control inputs changing once per clock cycle Active Power Down Standby Current one bank active power down mode CKE lt Vit max tek tex mn MRS 12 0 Active Power Down Standby Current one bank active power down mode CKE lt Vit max tek tex mnj MRS 12 1 Active Standby Current one bank active precharge CS gt Vin mmn CKE gt Vin min tac tras max tek tck mn DQ DM and DQS inputs changing twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank Burst 4 reads continuous burst address and control inputs changing once per clock cycle DQ and DQS outputs changing twice per clock cycle CL 4 tek tck min lour OMA Operating Current one bank Burst 4 writes continuous burst address and control inputs changing once per clock cycle DQ and DQS inputs changing twice per clock cycle CL 4 tek tek min Burst Refresh Current tac trrc min Self Refresh
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