Transcend JetRam 1GB DIMM DDR400 CL3
Contents
1. 9 2430 ePi N mnn o gt to PUUT Transcend Information Inc JM388D643A 5L 184PIN DDR400 Unbuffered DIMM 1024MB With 64Mx8 CL3 Pin Identification Symbol Function A0 A12 BAO BA1 Address input Dimensions Side Millimeters Inches A 133 35 0 20 5 250 0 008 B 72 39 2 850 C 6 35 0 250 D 2 20 0 087 E 29 46 0 20 1 160 0 008 F 19 80 0 779 G 4 00 0 157 H 12 00 0 472 l 1 27 0 10 0 050 0 004 Refer Placement DQ0 DQ63 Data Input Output DQS0 DQS7 Data strobe input output CKO CKO CK1 CK1 Clock Input CK2 CK2 CKEO CKE1 Clock Enable Input CSO CS1 Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe WE Write Enable DM0 DM7 Data in Mask VDD 2 5 Voltage power supply VDDQ 2 5 Voltage Power Supply for DQS VREF Power Supply for Reference VDDSPD 2 5 Voltage Serial EEPROM Power Supply SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground NC No Connection Transcend Information Inc JM388D643A 5L 184PIN DDR400 Unbuffered DIMM 1024MB With 64Mx8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 VREF 47 DQS8 93 VSS 139 VSS 02 DQO 48 AO 94 DQ4 140 DM8 03 VSS 49 CB2 95 DQ5 141 A10 04 DQ1 50 VS2. JM388D643A 5L 184PIN DDR400 Unbuffered DIMM 1024MB With 64Mx8 CL3 Description The JM388D643A 5L is a 128Mx64bits Double Data Rate SDRAM high density Module for DDR400 The JM388D643A 5L consists of 16pcs CMOS 64Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages and a 2048 bits serial EEPROM on a 184 pin printed circuit board The JM388D643A 5L is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e RoHS compliant products e Power supply VDD 2 6V 0 1V VDDQ 2 6V 0 1V e Max clock Freq 200MHZ e Double data rate architecture two data transfers per clock cycle e Differential clock inputs CK and Ck e Burst Mode Operation e Auto and Self Refresh e Data I O transactions on both edge of data strobe e Edge aligned data output center aligned data input e Serial Presence Detect SPD with serial EEPROM e SSTL 2 compatible inputs and outputs e MRS cycle with address key programs CAS Latency Access from column address 3 Burst Length 2 4 8 Data Sequence Sequential amp Interleave CII COTTE CCC y COCO PCB 0
3. S 96 VDDQ 142 CB6 05 DQSO 51 CB3 97 DMO 143 VDDQ 06 DQ2 52 BA1 98 DQ6 144 CB7 07 VDD 53 DQ32 99 DQ7 145 VSS 08 DQ3 54 VDDQ 100 VSS 146 DQ36 09 NC 55 DQ33 101 NC 147 DQ37 10 NC 56 DQS4 102 NC 148 VDD 11 VSS 57 DQ34 103 NC 149 DM4 12 DQ8 58 VSS 104 VDDQ 150 DQ38 13 DQ9 59 BAO 105 DQ12 151 DQ39 14 DQS1 60 DQ35 106 DQ13 152 VSS 15 VDDQ 61 DQ40 107 DM1 153 DQ44 16 CK1 62 VDDQ 108 VDD 154 RAS 17 CK1 63 IWE 109 DQ14 155 DQ45 18 VSS 64 DQ41 110 DQ15 156 VDDQ 19 DQ10 65 CAS 111 CKE1 157 CSO 20 DQ11 66 VSS 112 VDDQ 158 CS1 21 CKEO 67 DQS5 113 NC 159 DM5 22 VDDQ 68 DQ42 114 DQ20 160 VSS 23 DQ16 69 DQ43 115 A12 161 DQ46 24 DQ17 70 VDD 116 VSS 162 DQ47 25 DQS2 71 NC 117 DQ21 163 NC 26 VSS 72 DQ48 118 Ali 164 VDDQ 27 A9 73 DQ49 119 DM2 165 DQ52 28 DQ18 74 VSS 120 VDD 166 DQ53 29 A7 75 CK2 121 DQ22 167 NC 30 VDDQ 76 CK2 122 A8 168 VDD 31 DQ19 77 VDDQ 123 DQ23 169 DM6 32 A5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 A6 171 DQ55 34 VSS 80 DQ51 126 DQ28 172 VDDQ 35 DQ25 81 VSS 127 DQ29 173 NC 36 DQS3 82 NC 128 VDDQ 174 DQ60 37 A4 83 DQ56 129 DM3 175 DQ61 38 VDD 84 DQ57 130 A3 176 VSS 39 DQ26 85 VDD 131 DQ30 177 DM7 40 DQ27 86 DQS7 132 VSS 178 DQ62 41 A2 87 DQ58 133 DQ31 179 DQ63 42 VSS 88 DQ59 134 CB4 180 VDDQ 43 Al 89 VSS 135 CB5 181 SAO 44 CBO 90 NC 136 VDDQ 182 SAI 45 CB1 91 SDA 137 CKO 183 SA2 46 VDD 92 SCL 138 CKO 184 VDDSPD Transcend Information Inc
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