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Lenovo Xeon 1.6GHz

1. Pin Name Pin No SA oce Direction Pin Name Pin No EE Direction BPM4 E8 Input Output D22 AE23 Source Sync Input Output D23 AC23 Source Sync Input Output 5 4 Input Output D24 AA18 Source Sync Input Output mom Dos Common 2297 20 Source Sync Input Output 6 AC21 Source Sync Input Output BRO D20 ae Input Output D27 AE22 Source Sync Input Output voeem D28 AE20 Source Sync Input Output BR1 Clk Input D29 AD21 Source Sync Input Output BRo 11 Input D30 AD19 Source Sync Input Output D31 AB17 Source Sync Input Output BR3 D10 M Input D32 AB16 Source Sync Input Output BSELO Power Other Output D33 AA16 Source Sync Input Output BSEL12 AB3 Power Other Output D34 AC17 Source Sync Input Output COMPO AD16 Power Other Input D35 AE13 Source Sync Input Output COMP1 E16 Power Other Input D36 AD18 Source Sync Input Output 00 Y26 Source Sync Input Output D37 AB15 Source Sync Input Output 01 AA27 Source Sync Input Output 038 AD13 Source Sync Input Output D2 Y24 Source Sync Input Output D39 AD14 Source Sync Input Output D3 AA25 Source Sync Input Output D40 AD11 Source Sync Input Output D4 AD27 Source Sync Input Output D41 AC12 Source Sync
2. z Signal p Signal Buffer Type Direction Pin Name Pin No Buffer Type Direction D59 AC6 Source Sync Input Output IGNNE C26 Async GTL Input D60 AC5 Source Sync Input Output INIT D6 Async GTL Input D61 AA8 Source Sync Input Output LINTO B24 Async GTL Input D62 Y9 Source Sync Input Output LINT1 G23 Async GTL Input D63 AB6 Source Sync Input Output LOCK M7 Ed Input Output Common DBSY F18 Input Output Clk MCERR D7 Input Output Common DEFER c23 Cik Input Mechanical AE30 Key DBIO AC27 Source Sync Input Output ODTEN B5 Power Other Input DBH 4 AD22 Source Sync Input Output PROCHOT B25 Async GTL Input Output DBI2 AE12 Source Sync Input Output PWRGOOD AB7 Async GTL Input DBI3 AB9 Source Sync Input Output REQO B19 Source Sync Input Output DPO AC18 Input Output Clk REQ14 B21 Source Sync Input Output DP1 AE19 E Input Output REQ2 C21 Source Sync Input Output REQ3 C20 Source Sync Input Output DP2 AC15 n Input Output REQ4 B22 Source Sync Input Output Reserved A1 Reserved Reserved DP3 AE17 ee Input Output Reserved A4 Reserved Reserved DRDY E18 ER Input Output Reserved A15 Reserved Reserved Reserved A16 Reserved Reserved DSTBNO Y
3. Pin No Pin Name Direction Pin No Pin Name utter Typ o Direction T6 VCC Power Other V8 VCC Power Other T7 VSS Power Other V9 VSS Power Other T8 VCC Power Other V23 VSS Power Other T9 VSS Power Other V24 VCC Power Other T23 VSS Power Other V25 VSS Power Other T24 VCC Power Other V26 VCC Power Other T25 VSS Power Other V27 VSS Power Other T26 VCC Power Other V28 VCC Power Other T27 VSS Power Other V29 VSS Power Other T28 VCC Power Other V30 VCC Power Other T29 VSS Power Other V31 VSS Power Other T30 VCC Power Other W1 VCC Power Other T31 VSS Power Other W2 VSS Power Other U1 VCC Power Other W3 Reserved Reserved Reserved U2 VSS Power Other WA VSS Power Other U3 VCC Power Other W5 BCLK1 Sys Bus Clk Input U4 VSS Power Other W6 TESTHIO Power Other Input U5 VCC Power Other W7 TESTHI1 Power Other Input U6 VSS Power Other W8 TESTHI2 Power Other Input U7 Power Other wg GTLREF Power Other Input U8 VSS Power Other W23 GTLREF Power Other Input 09 VCC Power Other W24 VSS Power Other U23 VCC Power Other W25 VCC Power Other U24 VSS Power Other W26 VSS Power Other U25 VCC Power Other W27 VCC Power Other U26 VSS Power Other W28 VSS Power Other U27 VCC Power Other W29 VCC Power Other U28 VSS Power Other W30 VSS Power Other U29 VCC Power Other W31 VCC Power Other U30 VSS Power Other Y1 VSS Power Other U31 VCC Power Other Y2 VCC Power Other V1 VSS Power Other Y3 R
4. 97 8 0 Debug Tools Specifications 99 8 1 Logic Analyzer Interface LAT ret eH eit EEEE 99 8 1 1 Mechanical Consideration S pessoas nennen 99 8 1 2 Electrical Considerations ics ort rper ened apddedevsatteaneess uncnsesaedeedessaenis 99 9 0 Append A 101 9 1 Processor Core Frequency Determination 101 Figures 1 Typical VCCIOPLL VCCA and VSSA Power 16 2 Phase Lock Loop PLL Filter Requirements asns aa a 16 3 Low Voltage Intel Xeon Processor Voltage and Current Projections a Dual Processor Configuration eee 24 4 Electrical Test eorr ecce tet 32 E Leg ele Su Fen 32 6 Differential Clock nennen nennen nennen 33 7 Differential Clock Crosspoint na 33 9 System Bus Source Synchronous 2X Address Timing 34 8 System Bus Common Clock Valid Delay Timing Waveform seen 34 10 System Bus Source Synchronous 4X Data Timing Waveform
5. 35 11 System Bus Reset and Configuration Timing Waveform sseneenen 36 12 Power On Reset and Configuration Timing Waveform ssseeeeneeen 36 13 TAP Valid Delay Timing Waveform 37 4 Datasheet Contents ntel Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz 20 21 22 23 24 25 26 27 28 Test Reset TRST Async GTL Input and PROCHOT Timing Waveform 37 THERMTRIP to Timing nensi nennen 37 Example 3 3 VDO VID Sequencing eese nnne 38 BCLK 1 0 Signal Integrity Waveform sess eene nnne nnns 40 Low to High System Bus Receiver Ringback Tolerance for AGTL and Asynchronous GTL 41 High to Low System Bus Receiver Ringback Tolerance for AGTL and Asynchronous GTL 41 Low to High System Bus Receiver Ringback Tolerance for PWRGOOD TAP 42 High to Low System Bus Receiver Ringback Tolerance for PWRGOOD and 43 Maximum Acceptable Overshoot Undershoot 50 Low Voltage Intel Xeon Processor
6. 24 ee08086 0 8IH eceecoecoeceort eecocoeece089 Mu e e eo o 6 e 6 O0 S N eeesesceaes ap eeeceocoeocofe8j n veeecoecooo00j eeeocoocos J 22 20 14 16 18 DATA 12 10 eeoooeoococeooeooeoeo e eo cleeoeeo ooeooeooeoco Deeooeooeocgoeooeoooe Heeeeeeeeoee Jeeeeeccce Keeeeecoeccoe Leeeeoecococe Meeeeeeeee Neeeeeecee Reeeeeeeee Tleeeeeeceocce Aae e oeo ADe SSA 99A Figure 32 Processor Pin Out Diagram Top View 59 Mechanical Key e Reserved Signal Power Ground o e e CLOCKS Datasheet Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Figure 33 Processor Pin Out Diagram Bottom View Async COMMON COMMON JTAG CLOCK ADDRESS CLOCK 31 29 27 25 23 21 18 17 15 13 11 9 7 5 3 6000 o e o e o e e o e o e oj6 o e o e Vcc Vss 5 05 Z2 camovzErxc rommcoomu e o e o e 0o e o e 0 o 06 o e 00 0 eo o 6 SID o e o e o O0 o O o o e e o e o e o 6 o e o Vcc Vss oOoeooeooeooeooeooe eooeooeooeoeooeooeoo ejo edle eooeooeooeoooeooeooeooi eojle OOoeooeooeooeooeooeooeooeee O ooeooeooeoeooeooeooesiooee 0 e oj6 0 e 0 e o0 o0 e o0 e o eo e o c a
7. Processor die FC uPGA2 package Land side Capacitors amp N Package Pin 51 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz lal amp 4 1 Mechanical Specifications Figure 24 Low Voltage Intel Xeon Processor in the FC uPGA2 Package Top View Component Placement Detail Pin A1 7 52 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Processor the FC uPGA2 Package Figure 25 Low Voltage Intel Xeon Drawing mig ALI M3IA 3015 dl TR Vn 3NVTd 9 110735 MIIA 401 Q11 SH T aa m MILA 101108 f T 3 Ly 9992000000600c0 o002 0020000099 GOcocOOGOSOPOOOOPODODSDODEGDODOS 6889009800000080808090000808000 06860688968068608088089696886686656 9600000000005000000000000069000 gt GoacocoSG eeeaaccena SH amp 9090008000 N eeeccoces 660060006 gt eecesecos l 960060009 80059000 96606665690 660808906 608608080 900800008 OWN 660090000 L Peeeseces 60660000 bitte ttt td
8. 1 31 1 3 1 29 1 28 Vccmax 1 27 1 26 1 25 Maximum Processor Voltage VDC 1 24 0 5 10 15 20 25 30 35 40 Processor Current System Bus Differential BCLK Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Unit Figure M Input Low VL Voltage 150 0 0 N A V 6 Input High Vu Voltage 0 660 0 710 0 850 V 6 Absolute VcROSS abs Crossing 0 250 N A 0 550 V 6 8 2 8 Point Vorossirel Crossing _ N A M V 6 7 2 8 Point 0 5 VHavg 0 710 0 5 VHavg 0 710 Range of AVcross Crossing N A N A 0 140 V 6 8 2 10 Points Voy Overshoot N A N A VH 0 3 V 6 4 Vus Undershoot 0 300 N A N A 6 5 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 8 System Bus Differential BCLK Specifications Sheet 2 of 2 Ringback Margin aa 2d i E Vcross 9 100 N A Vcross 0 100 V j NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLKO equals the falling edge of BCLK1 VHaw is the statistical average of the VH measured by the oscilloscope Overshoot is defined as the absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage
9. Direction Pin No Pin Name Direction E11 BR2 ps Input F12 BR1 a Input E12 VCC Power Other F13 VSS Power Other E13 A28 Source Sync Input Output F14 ADSTB1 Source Sync Input Output E14 A24 Source Sync Input Output F15 A19 Source Sync Input Output E15 VSS Power Other F16 VCC Power Other E16 COMP1 Power Other Input F17 ADSTBO Source Sync Input Output E17 VSS Power Other F18 DBSY Ed Input Output EIS DRDY Input Output F19 VSS Power Other E19 TRDY ba Input F20 BNR Input Output E20 VCC Power Other F21 RS2 Input EN RS0 uu Input F22 VCC Power Other E22 HIT Input Output F23 GTLREF Power Other Input F24 TRST TAP Input E23 VSS Power Other F25 vss Powertihsr Ep4 TUR Input F26 THERMTRIP Async GTL Output ER TEM TAP Output F27 A20M Async GTL Input E26 VCC Power Other F28 vss PowerOther E27 FERR Async GTL Output F29 Power Other E28 VCC Power Other F30 vss Power Other E29 VSS Power Other 1 VCG Power Other E30 VCC Power Other Gi vss Power Other E31 VSS Power Other G2 Pawer Other F1 VCC Power Other G3 vss PowarDthar F2 VSS Power Other G4 Power Other F3 VIDO Power Other Output G5 vss Pawer Other F4 VCC Power Other G6 Power Other F5 Input Output G7 vss Power Other F6 BPMO Input Output G9 VSS Power Other F7 VSS Power Other G23 LINT1 Async GTL Input F8 BPM1 d Input Output G24 VCC Power Other F9 GTLREF Pow
10. 1 4 112 3 4 T1 BCLK BCLK BOLK BCLK1 euo A XX ADSTB driver A driver ADSTB receiver A receiver T23 Source Sync Address Output Valid Before Address Strobe T24 Source Sync Address Output Valid After Address Strobe T27 Source Sync Input Setup to BCLK T26 Source Sync Input Hold Time T25 Source Sync Input Setup Time T 128 First Address Strobe to Second Address Strobe Tg T20 Source Sync Output Valid Delay T31 Address Strobe Output Valid Delay T T Ty 34 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz In lel Figure 10 System Bus Source Synchronous 4X Data Timing Waveform TO 1 4 12 3 4 T2 BCLK BCLK BOLK BCLK1 BCLKO VENE DSTBp driver DSTBn driver D driver DSTBp receiver DSTBn receiver D receiver T21 Source Sync Data Output Valid Delay Before Data Strobe T22 Source Sync Data Output Valid Delay After Data Strobe T27 Source Sync Setup Time to BCLK T30 Source Sync Data Strobe N DSTBN Output Valid Delay T25 Source Sync Input Setup Time gt oy g o og og y d T26 Source Sync Input Hold Time T29 First Data Strobe to Subsequent Strobes T20 Source Sync Data Output Valid Delay CDD AD Datasheet 35 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz
11. pins must be supplied the voltage determined by the processor VID Voltage ID pins Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values when bulk decoupling is not adequate Larger bulk storage Cay such as electrolytic capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 7 Failure to do so may result in timing violations or reduced lifetime of the component For further information and guidelines refer to the appropriate platform design guidelines 13 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz lal amp 2 3 1 2 3 2 2 4 Table 2 Vcc Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and the baseboard designer must ensure a low interconnect resistance from the regulator or VRM pins to the 604 pin socket Bulk decoupling may be provided on the voltage regulation module VRM to meet help
12. All AC timings for the Asynchronous GTL signals are referenced to the BCLKO rising edge at Crossing Voltage Vcnoss All Asynchronous GTL signal timings are referenced at GTLREF 2 These signals may be driven asynchronously 3 4 Refer to the PWRGOOD signal definition in Section 5 2 for more detail information on behavior of the Refer to Section 7 2 for additional timing requirements for entering and leaving low power states signal Length of assertion for PROCHOT does not equal TCC activation time Time is required after the assertion and before the deassertion of PROCHOT for the processor to enable or disable the TCC This specification applies to PROCHOT when asserted by the processor A minimum pulse width of 500 us is recommended when PROCHOT is asserted by the system Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 17 System Bus AC Specifications Reset Conditions T Parameter Min Max Unit Figure Notes T45 Reset Configuration Signals A 31 3 BRO INIT SMI Setup Time BCLKS 1 T46 Reset Configuration Signals A 31 3 SMI Hold Time 2 20 BCLKs 11 2 T47 Reset Configuration Signal BRO Hold Time 2 2 BCLKs 1d 2 NOTES 1 Before the de assertion of RESET 2 After the clock that de asserts RESET Table 18 TAP Signal Group AC Specifications T Parameter Min Ma
13. This signal does not have on die termination and must be terminated at the end agent See the appropriate Platform Design Guideline for additional information RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor system bus agents RSP RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all processor system bus agents A correct parity signal is high when an even number of covered signals are low and low when an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity SKTOCC SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present SLP SLP Sleep when asserted in Stop Grant state causes processors to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal deassertion of SLP
14. yo AP 1 0 Address Parity are driven by the request initiator along with ADS A 35 3 and the transaction type on the REQ 4 0 pins A correct parity signal is high when an even number of covered signals are low and low when an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all system bus agents The following table defines the coverage model of these signals Request Signals Subphase 1 Subphase 2 35 24 APO 1 23 3 1 APO 4 0 1 APO BCLK 1 0 The differential pair BCLK Bus Clock determines the bus frequency All processor system bus agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing the falling edge of BCLK1 Datasheet 79 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz 80 Intel Table 36 Signal Definitions Sheet 2 of 9 Name Type Description BINIT BINIT Bus Initialization may be observed and driven by all processor system bus agents and when used must connect the appropriate pins of all such agents When the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future inform
15. 1 0011 1 0021 1 0030 2 3 4 Rr 3 64 W 2 3 5 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Characterized at 75 C 3 Not 100 tested Specified by design characterization 4 The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation Igwls e Where ls saturation current q electronic charge Vp voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin 5 The series resistance Ry is provided to allow for a more accurate measurement of the diode junction temperature as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor may be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term Another application is that a temperature offset may be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation Terror Pr N 3 ewm N Where Terror sensor temperature error N sensor current ration Boltzmann Constant electronic charge aVb nkT 4 Table 40 Thermal Diode Interface Datasheet Pin Name Pin Number Pin Description THERMDA Y27 diode anode THERMDC Y28 diode cathode 97 Low
16. Input Output D54 Y23 Source Sync Input Output D42 AE10 Source Sync Input Output 06 AA24 Source Sync Input Output D43 AC11 Source Sync Input Output D7 AB26 Source Sync Input Output D44 AE9 Source Sync Input Output 08 AB25 Source Sync Input Output D45 AD10 Source Sync Input Output 09 AB23 Source Sync Input Output D46ft AD8 Source Sync Input Output D10 AA22 Source Sync Input Output 047 9 Source Sync Input Output 011 21 Source Sync Input Output D48 1 Source Sync Input Output 012 20 Source Sync Input Output D49 14 Source Sync Input Output D13 AB22 Source Sync Input Output 050 14 Source Sync Input Output 014 AB19 Source Sync Input Output 051 12 Source Sync Input Output D15 AA19 Source Sync Input Output 052 AB13 Source Sync Input Output D16 AE26 Source Sync Input Output 053 11 Source Sync Input Output D17 AC26 Source Sync Input Output 054 10 Source Sync Input Output 018 AD25 Source Sync Input Output 055 AB10 Source Sync Input Output D19 AE25 Source Sync Input Output 056 8 Source Sync Input Output D20 AC24 Source Sync Input Output 057 AD7 Source Sync Input Output D21 AD24 Source Sync Input Output 058 AE7 Source Sync Input Output 62 Datasheet In Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 34 Pin Listing by Pin Name Table 34 Pin Listing by Pin Name
17. eicit eene Enn erat E 61 5 1 2 Pin Listing by Pin nme nennen nennen 70 52 Signal Definitloris i tree terae ede en xen re X eS 79 60 Thermal Specifications iced redet enlaces beu ua vega teen dte ev p 89 6 1 Thermal SpecifiCaliOnis t ee door insect SE PIXEE 89 6 2 Measurements for Thermal Specifications sseseeeenne enne 90 6 2 1 Processor Case Temperature 90 TO F 93 7 1 Power On Configuration en nennt entre 93 7 2 Clock Control Low Power EENEN 93 7 21 Normal State State EER AA 93 7 2 2 AutoHALT Powerdown State State 2 sse 93 7 2 3 Stop Grant State State 94 7 2 4 HALT Grant Snoop State State 4 essere 95 TAS Sleep State 5Stale 5 uere eed e Lote 95 7 2 6 Bus Response During Low Power 96 fo Thermal ceca eire adea te 96 7 31 Diodo nosso ate 96 re
18. Care should be taken to read all notes associated with a particular timing parameter Table 13 System Bus Differential Clock Specifications T Parameter Min Nom Max Unit Figure Notes Front Side Bus Clock Frequency 400 MHz 100 0 MHz 1 Front Side Bus Clock Frequency 533 MHz 130 07 133 33 MHz 1 T1 BCLK 1 0 Period 400 MHz 10 00 10 20 ns 6 2 T1 BCLK 1 0 Period 533 MHz 7 5 7 65 ns 6 2 T2 BCLK 1 0 Period Stability N A 150 ps 3 4 T3 TPH BCLK 1 0 Pulse High Time 400 MHz 3 94 5 6 12 ns 6 T3 TPH BCLK 1 0 Pulse High Time 533 MHz 2 955 3 75 4 59 ns 6 T4 TPL BCLK 1 0 Pulse Low Time 400 MHz 3 94 5 6 12 ns 6 T4 TPL BCLK 1 0 Pulse Low Time 533 MHz 2 955 3 75 4 59 ns 6 T5 BCLK 1 0 Rise Time 175 700 ps 6 5 T6 BCLK 1 0 Fall Time 175 700 ps 6 5 NOTES 1 The processor core clock frequency is derived from BCLK 2 The period specified here is the average period A given period may vary from this specification as governed by the period stability specification T2 3 For the clock jitter specification refer to the CK00 Clock Synthesizer Driver Design Guidelines 4 In this context period stability is defined as the worst case timing difference between successive crossover voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability 5 Slew rate is measured between the 35 and 65 points of the
19. max min 0 5 Vcc Threshold Region to switch receiver to a logic 1 Vss Vt max ARR a Allowable Ringback Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Figure 21 High to Low System Bus Receiver Ringback Tolerance 3 3 3 3 1 Datasheet for PWRGOOD and TAP Buffer Vcc Allowable Ringback Vt min 0 5 Vcc Vt max Vt min Threshold Region to switch receiver to a logic O Vss System Bus Signal Quality Specifications and Measurement Guidelines Overshoot Undershoot Guidelines Overshoot or undershoot is the absolute value of the maximum voltage above or below Vss The overshoot undershoot specifications limit transitions beyond or due to the fast signal edge rates The processor may be damaged by single and or repeated overshoot or undershoot events on any input output or I O buffer when the charge is large enough 1 when the over undershoot is great enough Determining the impact of an overshoot undershoot condition requires knowledge of the magnitude the pulse direction and the activity factor AF Permanent damage to the processor is the likely result of excessive overshoot undershoot When performing simulations to determine impact of overshoot and undershoot ESD diodes must be properly characterized ESD protection diodes do not act as voltag
20. 12 illustrates the relationship of PWRGOOD to the RESET signal PWRGOOD may be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 14 and be followed by a 1 mS RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 y o REQ 4 0 Request Command must connect the appropriate pins of all processor System bus agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Refer to the AP 1 0 signal description for details on parity checking of these signals RESET Asserting the RESET signal resets all processors to known states and invalidates their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after Vcc and BCLK have reached their proper specifications On observing active RESET all system bus agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10ms A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section l
21. 25 Materials Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz The processor is assembled from several components The basic material properties are described in Table 33 Table 33 Processor Material Properties Datasheet Component Material Integrated Heat Spreader Nickel plated copper FC uPGA2 BT Resin Package pins Cu Alloy 194 57 In Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz 4 6 Markings The following section details the processor top side laser markings It is provided to aid in the identification of the processor Figure 30 Processor Top Side Markings INTEL CONFIDENTIAL i 00 NOTES 1 Character size for laser markings is height 0 050 1 27mm width 0 032 0 81mm 2 All characters are in upper case Figure 31 Processor Bottom Side Markings 4 7 Processor Pin Out Diagram This section provides two view of the processor pin grid Figure 32 and Figure 33 detail the coordinates of the processor pins 58 Datasheet 31 Async JTAG 27 29 eooeeeee A ooeoeeeep O e O O e e eej eooeeeeej p OO e o e ee ej 23 25 COMMON CLOCK 21 18 15 17 19 11 Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz ADDRESS CLOCK 3 1 COMMON Vcc Vss lt gt 2 gt lt e AB O O O O e BlaD 0o s AE oOoee 26
22. B26 VCC Power Other B27 VCCSENSE Power Other Output B28 VSS Power Other B29 VCC Power Other B30 VSS Power Other B31 VCC Power Other C1 VSS Power Other C2 VCC Power Other C3 VID3 Power Other Output C4 VCC Power Other C5 Reserved Reserved Reserved C6 RSP Input Datasheet In Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 35 Pin Listing by Pin Number Table 35 Pin Listing by Pin Number Signal i Signal Pin No Pin Name Buffer Type Direction Pin No Pin Name Buffer Type Direction C7 VSS Power Other D10 BR3 Common Input Clk C8 5 Source Sync Input Output D11 VSS Power Other C9 A34 Source Sync Input Output idi VCC 012 A29 Source Sync Input Output D1 A25 S S Input Output C11 A30 Source Sync Input Output 3 ege D14 VCC Power Other C12 A23 Source Sync Input Output D1 Al S Input Output C13 VSS Power Other o Source Syne Ifput Qutpu D16 A17 S S Input Output C14 A16 Source Sync Input Output eee D17 9 Source Sync Input Output C15 A15 Source Sync Input Output y D18 VCC Power Other C16 VCC Power Other Common C17 8 Source Sync Input Output D19 ADS Clk Input Output C18 A6 Source
23. GHz 3 2 Figure 17 BCLK 1 0 Signal Integrity Waveform Overshoot BCLK1 VH Rising Edge E M NEED Ringback p PUO Y I Crossing Crossing Ringback Falling Edge Threshold Voltage Voltage Margin Region UU d EEUU RUE WO a Ringback BCLKO VL Undershoot System Bus Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of AGTL layout guidelines which are available in the appropriate platform design guidelines Table 20 provides the signal quality specifications for all processor signals for use in simulating signal quality at the processor pads Maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in Table 22 through Table 25 Figure 18 shows the system bus ringback tolerance for low to high transitions and Figure 19 shows ringback tolerance for high to low transitions Table 20 Ringback Specifications for AGTL and Asynchronous GTL Buffers 40 Signal Group Transition ie tee Unit Figure Notes AGTL Asynch GTL GTLREF 0 100 GTLREF V 18 1 2 3 4 5 8 AGTL Asynch GTL HoL GTLREF 0 100 GTLREF V 19 1 2 3 4 5 6 NOTES All signal integrity specifications are measured at the processor core pads Specifications are for the edge rate of 0 3 4 0 V ns atthe receiver All values specified by design characterization Pl
24. GHz and 2 4 GHz Figure 27 Low Voltage Intel Xeon Processor in the FC uPGA2 Package Cross Section View Pin Side Component Keep In FC uPGA2P j 1 5 mm Package Component Component Keepin B2488 01 Figure 28 Low Voltage Intel Xeon Processor in the FC uPGA2 Package Pin Detail t 0 65 MAX 0 065 R0 0254 MIN 20 65 MAX 20 37 MAX 1 032 MAX Bos 0 3 MAX F 2 03 0 08 Figure 29 details the flatness and tilt specifications for the IHS of the Low Voltage Intel Xeon processor respectively Tilt is measured with the reference datum set to the bottom of the processor interposer Datasheet 55 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Figure 29 Low Voltage Intel Xeon Processor FC uPGA2 Package 4 2 56 Table 31 IHS Flatness and Tilt Drawing THS SEALANT HS 0 203 Yu DU PACKAGE SUBSTRATE Processor Package Load Specifications Table 31 provides dynamic and static load specifications for the processor IHS These mechanical load limits should not be exceeded during heat sink assembly mechanical stress testing or standard drop and shipping conditions The heat sink attach solutions must not induce continuous stress onto the processor wit
25. Normal execution Snoops and interrupts allowed A k Se STPCLK STPCLK As Asserted De asserted S Ry Snoop Snoop Event Event Occurs Serviced 2v A Y 4 HALT Grant Snoop State Snoop Event Occurs 3 Stop Grant State BCLK running BCLK running Service snoops to caches Snoop Event Serviced gt Snoops and interrupts allowed SLP SLP Asserted De asserted 5 Sleep State BCLK running No snoops or interrupts allowed Stop Grant State State 3 When the STPCLK pin is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Once the STPCLK pin has been asserted it may only be deasserted once the processor is in the Stop Grant state Both logical processors of the Low Voltage Intel Xeon processor must be in the Stop Grant state before the deassertion of STPCLK Since the signal pins receive power from the system bus these pins should not be driven allowing the level to return to Vcc for minimum power drawn by the termination resistors in this state In addition all other input pins on the system bus should be driven to the inactive state Datasheet 7 2 4 7 2 5 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz BINIT may be recognized while the processor is in Stop Grant state When STPCLKT is still asserted at the completion of
26. Paragon PC Dads PC Parents PDCharm Pentium Pentium II Xeon Pentium Xeon Performance at Your Command RemoteExpress Shiva SmartDie Solutions960 Sound Mark StorageExpress The Computer Inside The Journey Inside TokenExpress Trillium VoiceBrick Vtune and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright Intel Corporation 2003 2 Datasheet Contents ntel Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Contents 1 0 Introduction 9 EE 10 1 1 1 Processor Packaging Terminology 10 1 2 State OF 1 11 PNE CChu e 11 2 0 Electrical Specifications ooo ed eet Li a edu d o e emp 13 2 1 System Bus and GTLREF nennen nnns nnn nensi nnn nnne 13 2 2 Power and Ground ee ere Gad EPA HU Ee cxx UE teens Ye suis EE 13 2 3 Decoupling eene nnne eintreten trennen nenas 13 2 31 VOC Decoupling iue ier eere pP cotta 14 2 3 2 System Bus AGTL Decoupling sesseeneneennen n 14 2 4 System Bus Clock BCLK 1 0 and Processo
27. Reserved Reserved Y22 VCC Power Other AA29 Reserved Reserved Reserved Y23 D5 Source Sync Input Output AA30 VSS Power Other Y24 D2 Source Sync Input Output AA31 VCC Power Other Y25 VSS Power Other AB1 VSS Power Other Y26 DO Source Sync Input Output AB2 VCC Power Other Y27 THERMDA Anode Pin Output AB3 BSEL1 Power Other Output Y28 THERMDC Cathode Pin Output AB4 VCCA Power Other Input Y29 Reserved Reserved Reserved AB5 VSS Power Other Y30 VCC Power Other AB6 D63 Source Sync Y31 VSS Power Other AB7 PWRGOOD Power Other Input AA1 VCC Power Other AB8 VCC Power Other AA2 VSS Power Other AB9 DBI3 Source Sync Input Output AA3 BSELO Power Other Output AB10 D55 Source Sync Input Output AA4 VCC Power Other AB11 VSS Power Other AA5 VSSA Power Other Input AB12 D51 Source Sync Input Output AA6 VCC Power Other AB13 D52 Source Sync Input Output AA7 TESTHI4 Power Other Input AB14 VCC Power Other AA8 D61 Source Sync Input Output AB15 D37 Source Sync Input Output AA9 VSS Power Other AB16 D32 Source Sync Input Output AA10 D54 Source Sync Input Output AB17 D31 Source Sync Input Output AA11 D53 Source Sync Input Output AB18 VCC Power Other AA12 VCC Power Other AB19 D14 Source Sync Input Output AA13 D48 Source Sync Input Output AB20 D12 Source Sync Input Output AA14 D49 Source Sync Input Output AB21 VSS Power Other AA15 VSS Power Other AB22 D13 Source Sync Input Output 76 Datasheet In Low Voltage Inte Xeon Pr
28. Signal Group Type Signals BPRI BR 3 1 4 DEFER RESET AGTL Common Clock Input Synchronous to BCLK 1 0 5 2 0 RSP TRDY ADS AP 1 0 BINITZ BNR BPM 5 0 Common Clock I O Synchronous to BCLK 1 0 BRO DBSY DP 3 0 DRDY HIT HITM LOCK MCERR Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 AGTL Source Synchronous Synchronous to assoc strobe 0 15 0 DBIO DSTBPO DSTBNO 0 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2st DSTBP2 DSTBN2 D 63 48 DBIS DSTBP3 DSTBN3 AGTL Strobes Synchronous to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 A20M IGNNE INIT LINTO INTR Asynchronous GTL Input Asynchronous LINTT NMP SMHS SLP STPCLK Asynchronous GTL Output Asynchronous FERR IERR THERMTRIP Asynchronous GTL Input Output Asynchronous PROCHOT System Bus Clock Clock BCLK1 BCLKO TAP Input Synchronous to TCK TCK TDI TMS TRST TAP Output Synchronous to TCK TDO BSEL 1 0 COMP 1 0 GTLREF ODTEN Reserved SKTOCC TESTHI 6 0 VID 4 0 Power Other Power Other Voc Veca Vas VCCSENSE VssseNse PWRGOOD THERMDA THERMDC VID Voc NOTES 1 Refer to Section 5 2 for signal descriptions 2 These AGTL signal groups are not terminated by the processor Refer the TP700 Debug Port
29. a lt muzzrmm gt o9000090 0 0e o e o e o o e o e o e o e o e 28 26 24 22 20 18 16 14 12 10 8 6 4 2 DATA CLOCKS Ground D GTLREF eserved MISC Power D VID Vec Signal C Mechanical Key B2487 01 60 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Intel 5 0 Pin Listing and Signal Definitions 5 1 Processor Pin Assignments Section 2 8 contains the system bus signal groups in Table 5 for the Low Voltage Intel Xeon processor This section provides a sorted pin list in Table 34 and Table 35 Table 34 is a listing of all processor pins ordered alphabetically by pin name Table 35 is a listing of all processor pins ordered by pin number 5 1 1 Pin Listing by Pin Name Table 34 Pin Listing by Pin Name Table 34 Pin Listing by Pin Name i 2 Signal Pin Pin No bue ise Direction Pin Name Pin No Direction A3 A22 Source Sync Input Output A29 D12 Source Sync Input Output 4 20 Source Sync Input Output A30 C11 Source Sync Input Output A5 B18 Source Sync Input Output A31 B7 Source Sync Input Output 18 Source Sync Input Output A32 A6 Source Sync Input Output 7 19 Source Sync Input Output A33 A7 Sour
30. and removal of the BCLK input while in Sleep state When SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units Datasheet 85 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz In Table 36 Signal Definitions Sheet 8 of 9 Name Type Description SMI SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler When is asserted during the deassertion of RESET the processor will tri state its outputs STPCLK STPCLK Stop Clock when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the system bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK TCK Test Clock provides the clock input for the processor Test Bus al
31. assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor system bus agents When INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST Datasheet 83 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 36 Signal Definitions Sheet 6 of 9 Intel Name Type Description configuration LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all system bus agents When the APIC functionality is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names LINT 1 0 on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default LOCK 1 0 LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor system bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the proc
32. clock swing Vj and Vj Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 14 System Bus Common Clock AC Specifications T Parameter Min Max Unit Figure Notes 2 T10 Common Clock Output Valid Delay 0 12 1 27 ns 8 3 T11 Common Clock Input Setup Time 0 65 N A ns 8 4 T12 Common Clock Input Hold Time 0 40 N A ns 8 4 T13 RESET Pulse Width 1 00 10 00 ms 11 5 5 7 NOTES 1 Not 100 tested Specified by design characterization 2 NO OC All common clock AC timings for AGTL signals are referenced to the Crossing Voltage Vcnoss of the BCLK 1 0 at rising edge of BCLKO All common clock AGTL signal timings are referenced at GTLREF at the processor core Valid delay timings for these signals are specified into the test circuit described in Figure 4 and with GTLREF at 0 63 Voc 2 Specification is for a minimum swing defined between AGTL Vi max to This assumes an edge rate of 0 3 V ns to 4 0 V ns RESET may be asserted active asynchronously but must be deasserted synchronously This should be measured after Vcc and BCLK 1 0 become stable Maximum specification applies only while PWRGOOD is asserted Table 15 System Bus Source Synchronous AC Specifications Sheet 1 of 2 Datasheet T Parameter Min Max Unit Figure Notes T20 Source Sync Output Valid Delay first dat
33. guidelines 15 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz In lal Figure 1 Typical VccA and Vssa Power Distribution Trace lt 0 02 Q WES TT Processor interposer pin a __ R Socket f WA Baseboard via that connects T f R Socket filter to VCC plane Socket pin Processor C R Trace R Socket L1 L2 Figure 2 Phase Lock Loop PLL Filter Requirements idd T C lt passband high frequency band ES 1 Diagram not to scale 2 No specifications for frequencies beyond fore core frequency if existent should be less than 0 05 MHz Datasheet intel 2 5 1 2 6 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Mixing Processors Intel only supports those processor combinations operating with the same system bus frequency core frequency VID settings and cache sizes Not all operating systems may support multiple processors with mixed frequencies Intel does not support or validate operation of processors with different cache sizes Mixing processors of different steppings but the same model as per CPUID instruction is supported and is outlined in the Intel Xeon Processor Specification Update Additional details are provided in AP 485 the Intel Processor Identification and the CPUID Instruction application note Unlike previous Intel Xeon proces
34. in the FC uPGA2 Package Assembly Drawing 51 Low Voltage Intel Xeon Processor in the FC uPGA2 Package Top View Component Placement ene 52 Low Voltage Intel Xeon Processor in the FC uPGA2 Package I E 53 Low Voltage Intel Xeon Processor the FC uPGA2 Package Top View Component Height enne 54 Low Voltage Intel Xeon Processor in the FC uPGA2 Package Cross Section View Pin Side Component Keep In55 Low Voltage Intel Xeon Processor in the FC uPGA2 Package Pin Detail55 29 Low Voltage Intel Xeon Processor FC uPGA2 Package IHS Flatness and Tilt Drawing nnn nnns 56 30 Processor Top Side Markings tees deed aee sva vocas eda se 58 31 Processor Bottom Side Markings n nennen 58 32 Processor Pin Out Diagram Top 59 33 Processor Pin Out Diagram Bottom 60 34 Processor with Thermal and Mechanical Components Exploded View 89 35 Thermal Measurement Point for Processor 91 36 Stop Clock State Machi
35. meet the large current swing requirements The remaining decoupling is provided on the baseboard The power delivery path must be capable of delivering enough current while maintaining the required tolerances defined in Table 7 For further information regarding power delivery decoupling and layout guidelines refer to the appropriate platform design guidelines System Bus AGTL Decoupling The Intel Xeon processor integrates signal termination on the die as well as part of the required high frequency decoupling capacitance on the processor package However additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the system bus Bulk decoupling must also be provided by the baseboard for proper AGTL bus operation Decoupling guidelines are described in the appropriate platform design guidelines System Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the system bus interface speed as well as the core frequency of the processor As in previous generation processors the processor core frequency is a multiple of the BCLK 1 0 frequency The maximum processor bus ratio multiplier may be set during manufacturing The default setting may equal the maximum speed for the processor The BCLK 1 0 inputs directly control the operating speed of the system bus interface The processor core frequency is configured during reset by using values stored internally during ma
36. of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to volume 3 of the Intel Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note This signal does not have on die termination and must be terminated at the end agent See the appropriate Platform Design Guideline for additional information GTLREF GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 0 63 Vcc GTLREF is used by the AGTL receivers to determine when a signal is a logical 0 or a logical 1 HIT HITM y o yo HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any system bus agent may assert both HIT and HITM together to indicate that it requires a snoop stall which may be continued by reasserting HIT and HITM together Since multiple agents may deliver snoop results at the same time HIT and HITM are wire OR signals which must connect the appropriate pins of all processor System bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers HIT and HITM are activated on specific clock edges and sampled on specific clock edges IERR IERR Internal Error is assert
37. the BINIT bus initialization the processor may remain in Stop Grant mode When STPCLK is not asserted at the completion of the BINIT bus initialization the processor may return to Normal state RESET may cause the processor to immediately initialize itself but the processor may stay in Stop Grant state A transition back to the Normal state may occur with the deassertion of the STPCLK signal When re entering the Stop Grant state from the sleep state STPCLK should only be deasserted one or more bus clocks after the deassertion of SLP A transition to the HALT Grant Snoop state may occur when the processor detects a snoop on the system bus see Section 7 2 4 A transition to the Sleep state see Section 7 2 5 may occur with the assertion of the SLP signal While in the Stop Grant state SMI INIT BINIT and LINT 1 0 may be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event may be recognized upon return to the Normal state HALT Grant Snoop State State 4 The processor may respond to snoop transactions on the system bus while in Stop Grant state or in AutoHALT Power Down state During a snoop transaction the processor enters the HALT Grant Snoop state The processor may stay in this state until the snoop on the system bus has been serviced whether by the processor or another agent on the system bus After the snoop is serviced the processor may return to
38. the Stop Grant state or AutoHALT Power Down state as appropriate Sleep State State 5 The Sleep state is a very low power state in which each processor maintains its context maintains the phase locked loop PLL and has stopped most of internal clocks The Sleep state may only be entered from Stop Grant state Once in the Stop Grant state the SLP pin may be asserted causing the processor to enter the Sleep state The SLP pin is not recognized in the Normal or AutoHALT states Snoop events that occur while in Sleep state or during a transition into or out of Sleep state may cause unpredictable behavior In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP or RESET are allowed on the system bus while the processor is in Sleep state Any transition on an input signal before the processor has returned to Stop Grant state may result in unpredictable behavior When RESET is driven active while the processor is in the Sleep state and held active specified in the RESET pin specification the processor may reset itself ignoring the transition through Stop Grant state When RESET is driven active while the processor is in the Sleep state the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the reset sequence Once in the Sleep stat
39. used to determine when the overshoot undershoot pulse is within specifications Overshoot Undershoot Pulse Duration Pulse duration describes the total time an overshoot undershoot event exceeds the overshoot undershoot reference voltage The total time could encompass several oscillations above the reference voltage Multiple overshoot undershoot pulses within a single overshoot undershoot event may need to be measured to determine the total pulse duration Oscillations below the reference voltage cannot be subtracted from the total overshoot undershoot pulse duration Activity Factor Activity Factor AF describes the frequency of overshoot or undershoot occurrence relative to a clock Since the highest frequency of assertion of any common clock signal is every other clock an AF 1 indicates that the specific overshoot or undershoot waveform occurs every other clock cycle Thus an AF 0 01 indicates that the specific overshoot or undershoot waveform occurs one time in every 200 clock cycles For source synchronous signals address data and associated strobes the activity factor is in reference to the strobe edge The highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe So an AF 1 indicates that the specific overshoot or undershoot waveform occurs every strobe cycle The specifications provided in Table 22 through Table 25 show the maximum pulse duration al
40. 0 DP 3 0 Data Parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving 0 63 0 and must connect the appropriate pins of all processor system bus agents DRDY DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor system bus agents DSTBN 3 0 1 0 Data strobe used to latch in D 63 0 DSTBP 3 0 Data strobe used to latch D 63 0 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 36 Signal Definitions Sheet 5 of 9 Name Type Description FERR PBE FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion
41. 0 0 0 0 1 850 Mixing Processors of Different Voltages Mixing processors operating with different VID settings voltages is not supported and may not be validated by Intel Datasheet 2 8 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Reserved Or Unused Pins All Reserved pins must remain unconnected on the system baseboard Connection of these pins to V ss or to any other signal including one another may result in component malfunction or incompatibility with future processors See Chapter 5 0 for a pin listing of the processor and for the location of all Reserved pins For reliable operation unused inputs or bidirectional signals should always be connected to an appropriate signal level In a system level design on die termination has been included on the processor to allow signal termination to be accomplished by the processor silicon Most unused AGTL inputs should be left as no connects as termination is provided on the processor silicon However see Table 5 for details on AGTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground Vss Unused outputs may be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing resistor must be used when tying bidirectional signals to power or ground When tying any signal
42. 21 Source Sync Input Output Reserved A26 Reserved Reserved DSTBN1 Y18 Source Sync Input Output Reserved B1 Reserved Reserved DSTBN2 Y15 Source Sync Input Output Reserved C5 Reserved Reserved DSTBN3 Y12 Source Sync Input Output Reserved D25 Reserved Reserved DSTBPO Y20 Source Sync Input Output Reserved W3 Reserved Reserved DSTBP1 Y17 Source Sync Input Output Reserved Reserved Reserved DSTBP2 Y14 Source Sync Input Output Reserved Y29 Reserved Reserved DSTBP3 Y11 Source Sync Input Output Reserved AA28 Reserved Reserved FERR E27 Async GTL Output Reserved AA29 Reserved Reserved GTLREF W23 Power Other Input Reserved AB28 Reserved Reserved GTLREF W9 Power Other Input Reserved AB29 Reserved Reserved GTLREF F23 Power Other Input Reserved AC1 Reserved Reserved GTLREF F9 Power Other Input rumen Reserved AC28 Reserved Reserved HIT mE Clk Input Output Reserved AC29 Reserved Reserved HITM amp A23 en Input Output Reserved AD1 Reserved Reserved Reserved AD28 Reserved Reserved IERR E5 Async GTL Output Datasheet 63 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz In lel Table 34 Pin Listing by Pin Name Table 34 Pin Listing by Pin Name Pin Name Pin No Signal Direction Pin Name Pin No Signal Direction Buffer Type Buffer Type Reserved
43. 5 00 15 00 15 00 NOTES 1 These specifications are measured at the processor pad 2 BCLK period is 10 ns 3 WIRED OR processor signals may tolerate up to 1 V of overshoot undershoot 4 AF is referenced to BCLK 1 0 Undershoot Tolerance Maximum Marium Pulse Duration Pulse Duration Pulse Duration Overshoot V Undershoot V gt TRR 1 700 0 400 3 78 37 62 45 00 1 650 0 350 11 25 45 00 45 00 1 600 0 300 32 94 45 00 45 00 1 550 0 250 45 00 45 00 45 00 1 500 0 200 45 00 45 00 45 00 1 450 0 150 45 00 45 00 45 00 1 400 0 100 45 00 45 00 45 00 1 350 0 050 45 00 45 00 45 00 NOTES 1 These specifications are measured at the processor pad 2 These signals are assumed in a 33 MHz time domain Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Figure 22 Maximum Acceptable Overshoot Undershoot Waveform Maximum Absolute Time dependent Overshoot Overshoot Vmax Voc GTLREF Vo Vss Mn RR RN ODER Time dependent Maximum Undershoot Absolute Undershoot 000588 50 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Mechanical Specifications The Low Voltage Intel Xeon processor uses the Flip Chip Micro Pin Grid Array FC uPGA2 package technology This includes an integrated heat spreader IHS mounted to a pinned substrate Mechanical specific
44. 5 Power Other VSS M24 Power Other VSS T27 Power Other VSS M26 Power Other VSS T29 Power Other VSS M28 Power Other VSS T31 Power Other VSS M30 Power Other VSS U2 Power Other VSS N2 Power Other VSS U4 Power Other VSS N4 Power Other VSS U6 Power Other VSS N6 Power Other VSS U8 Power Other VSS N8 Power Other VSS U24 Power Other VSS N24 Power Other VSS U26 Power Other VSS N26 Power Other VSS U28 Power Other VSS N28 Power Other VSS U30 Power Other 68 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Intel Table 34 Pin Listing by Pin Name Table 34 Pin Listing by Pin Name Pin Name Pin No ae Direction Pin Name Pin No ae Direction Buffer Type Buffer Type VSS V1 Power Other VSS AC13 Power Other VSS V3 Power Other VSS AC19 Power Other VSS V5 Power Other VSS AC25 Power Other VSS V7 Power Other VSS AC30 Power Other VSS v9 Power Other VSS AD3 Power Other VSS V23 Power Other VSS AD9 Power Other VSS V25 Power Other VSS AD15 Power Other VSS V27 Power Other VSS AD17 Power Other VSS V29 Power Other VSS AD23 Power Other VSS V31 Power Other VSS AD31 Power Other VSS W2 Power Other VSS AE2 Power Other VSS W4 Power Other VSS AE4 Power Other VSS W24 Power Other VSS AE11 Power Other VSS W26 Power Other VSS AE21 Power Other VSS W28
45. 6 Power Other VCC N25 Power Other VCC J28 Power Other VCC N27 Power Other VCC J30 Power Other VCC N29 Power Other VCC K1 Power Other VCC N31 Power Other VCC K3 Power Other VCC P2 Power Other VCC K5 Power Other VCC P4 Power Other VCC K7 Power Other VCC P6 Power Other VCC K9 Power Other VCC P8 Power Other VCC K23 Power Other VCC P24 Power Other VCC K25 Power Other VCC P26 Power Other VCC K27 Power Other VCC P28 Power Other VCC K29 Power Other VCC P30 Power Other VCC K31 Power Other VCC R1 Power Other VCC L2 Power Other VCC R3 Power Other Datasheet 65 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz In lel Table 34 Pin Listing by Pin Name Table 34 Pin Listing by Pin Name Pin Name Pin No Signal Direction Pin Name Pin No Signal Direction Buffer Type Buffer Type VCC R5 Power Other VCC W29 Power Other VCC R7 Power Other VCC W31 Power Other VCC R9 Power Other VCC Y10 Power Other VCC R23 Power Other VCC Y16 Power Other VCC R25 Power Other VCC Y2 Power Other VCC R27 Power Other VCC Y22 Power Other VCC R29 Power Other VCC Y30 Power Other VCC R31 Power Other VCC AA1 Power Other VCC T2 Power Other VCC AA4 Power Other VCC T4 Power Other VCC AA6 Power Other VCC T6 Power Other VCC AA12 Power Other VCC T8 Power Other VCC AA20 Power Other VCC T24 Power Other VCC AA26 Power Other VCC T26 Power Other VCC AA31 Po
46. 9 PoweilOther VCC A24 Power Other VEC 1 Power Other 64 Datasheet In Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 34 Pin Listing by Pin Name Table 34 Pin Listing by Pin Name Pin Name Pin No MIC D Direction Pin Name Pin No S NS Direction VCC G2 Power Other VCC L4 Power Other VCC G4 Power Other VCC L6 Power Other VCC G6 Power Other VCC L8 Power Other VCC G8 Power Other VCC L24 Power Other VCC G24 Power Other VCC L26 Power Other VCC G26 Power Other VCC L28 Power Other VCC G28 Power Other VCC L30 Power Other VCC G30 Power Other VCC M1 Power Other VCC H1 Power Other VCC M3 Power Other VCC H3 Power Other VCC M5 Power Other VCC H5 Power Other VCC M7 Power Other VCC H7 Power Other VCC Mg Power Other VCC H9 Power Other VCC M23 Power Other VCC H23 Power Other VCC M25 Power Other VCC H25 Power Other VCC M27 Power Other VCC H27 Power Other VCC M29 Power Other VCC H29 Power Other VCC M31 Power Other VCC H31 Power Other VCC N1 Power Other VCC J2 Power Other VCC N3 Power Other VCC J4 Power Other VCC N5 Power Other VCC J6 Power Other VCC N7 Power Other VCC J8 Power Other VCC N9 Power Other VCC J24 Power Other VCC N23 Power Other VCC J2
47. AD29 Reserved Reserved VCC A28 Power Other Reserved AE15 Reserved Reserved VCC A30 Power Other Reserved AE16 Reserved Reserved VCC B4 Power Other RESET yg a Input VCC B6 Power Other VCC B12 Power Other RSO E21 ag Input VCC B20 Power Other ET Common cut VCC B26 Power Other VCC B29 Power Other RS2 F21 ae Input VCC B31 Power Other VCC C2 Power Other RSP xu non Input VCC C4 Power Other SKTOCC A3 Power Other Output VCC C10 Power Other SLP AE6 Async GTL Input VCC C16 Power Other SMI C27 Async GTL Input VCC C22 Power Other STPCLK D4 Async GTL Input VCC C28 Power Other TCK E24 TAP Input VCC C30 Power Other TDI C24 TAP Input VCC D1 Power Other TDO E25 TAP Output VCC D8 Power Other TESTHIO W6 Power Other Input VCC D14 Power Other TESTHI1 W7 Power Other Input VCC D18 Power Other TESTHI2 W8 Power Other Input VCC D24 Power Other TESTHI3 Y6 Power Other Input VCC D29 Power Other TESTHI4 AA7 Power Other Input VCC D31 Power Other TESTHI5 AD5 Power Other Input VCC E2 Power Other TESTHI6 AE5 Power Other Input VCC E6 Power Other THERMDA Y27 Anode Pin Output VCC E12 Power Other THERMDC Y28 Cathode Pin Output VCC E20 Power Other THERMTRIP F26 Async GTL Output VCC E26 Power Other TMS A25 TAP Input VCC E28 Power Other TRDY E19 ae Input VCC E30 Power Other VCC F1 Power Other TRST B VCC F4 Power Other ee Fowerorer VCC F10 Power Other vog a VCC F16 Power Other VCC A14 Power Other VEC F22 Power Other VCC A18 Power Other VCC F2
48. AF 0 01 Overshoot V Undershoot V j 1 45 0 15 10 00 10 00 10 00 1 40 0 10 10 00 10 00 10 00 1 35 0 05 10 00 10 00 10 00 NOTES 1 These specifications are measured at the processor pad 2 Assumes a BCLK period of 10 ns 3 AF is referenced to associated source synchronous strobes Table 24 Common Clock 400 MHz AGTL Signal Group Overshoot Undershoot Tolerance rain t pesti Pulse ee ns ped eh pq ns Overshoot V Undershoot V ics pe 1 70 0 40 1 68 16 72 20 00 1 65 0 35 5 00 20 00 20 00 1 60 0 30 14 64 20 00 20 00 1 55 0 25 20 00 20 00 20 00 1 50 0 20 20 00 20 00 20 00 1 45 0 15 20 00 20 00 20 00 1 40 0 10 20 00 20 00 20 00 1 35 0 05 20 00 20 00 20 00 NOTES 1 These specifications are measured at the processor pad 2 BCLK period is 10 ns 3 WIRED OR processor signals may tolerate up to 1 V of overshoot undershoot 4 AF is referenced to BCLK 1 0 Table 25 400 MHz Asynchronous GTL PWRGOOD and TAP Signal Groups Overshoot Undershoot Tolerance Sheet 1 of 2 Absolute Pulse Duration ns Pulse Duration Pulse Duration ns AF 1 ns AF 0 1 AF 0 01 Overshoot V Undershoot V xig 1 70 0 40 5 04 50 16 60 00 1 65 0 35 14 99 60 00 60 00 1 60 0 30 43 92 60 00 60 00 1 55 0 25 60 00 60 00 60 00 1 50 0 20 60 00 60 00 60 00 NOTES 1 These spe
49. Buffer Type Direction VCCA AB4 Power Other Input VSS E1 Power Other VCCIOPLL AD4 Power Other Input VSS E9 Power Other VCCSENSE B27 Power Other Output VSS E15 Power Other VIDO F3 Power Other Output VSS E17 Power Other VID1 E3 Power Other Output VSS E23 Power Other VID2 D3 Power Other Output VSS E29 Power Other VID3 C3 Power Other Output VSS E31 Power Other VID4 B3 Power Other Output VSS F2 Power Other VID Voc AE28 Power Other VSS F7 Power Other VID Voc AE29 Power Other VSS F13 Power Other VSS A5 Power Other VSS F19 Power Other VSS A11 Power Other VSS F25 Power Other VSS A21 Power Other VSS F28 Power Other VSS A27 Power Other VSS F30 Power Other VSS A29 Power Other VSS G1 Power Other VSS A31 Power Other VSS G3 Power Other VSS B2 Power Other VSS G5 Power Other VSS B9 Power Other VSS G7 Power Other VSS B15 Power Other VSS G9 Power Other VSS B17 Power Other VSS G25 Power Other VSS B23 Power Other VSS G27 Power Other VSS B28 Power Other VSS G29 Power Other VSS B30 Power Other VSS G31 Power Other VSS C1 Power Other VSS H2 Power Other VSS C7 Power Other VSS H4 Power Other VSS C13 Power Other VSS H6 Power Other VSS C19 Power Other VSS H8 Power Other VSS C25 Power Other VSS H24 Power Other VSS C29 Power Other VSS H26 Power Other VSS C31 Power Other VSS H28 Power Other VSS D2 Power Other VSS H30 Power Other VSS D5 Power Other VSS J1 Power Other VSS D11 Power Other VSS J3 Power Other VSS D21 Power Other VSS J5 Power Other VSS D27 Power Other VSS J7 Powe
50. CC PWR OK OUTEN VID OUT L T 4 10mS VRM PWRGD gt 10ms Processor PWRGOOD gt T 100ms Processor RESET i ol ie ims T4 10ms VID 4 0 PWRGD oY VRM PWRGOOD OUTEN Processor VID VCC PWR OK Power Supply 3 3 VDC 95 3 3 volt level E 3 3 VDC VID_VCC Power Down X PWROK EE OUTEN mwi Power Down Warning gt 1ms 38 Datasheet 3 0 tel Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz System Bus Signal Quality Specifications 3 1 This section documents signal quality metrics used to derive topology and routing guidelines through simulation All specifications are made at the processor core pad measurements Source synchronous data transfer requires the clean reception of data signals and their associated strobes Ringing below receiver thresholds non monotonic signal edges and excessive voltage swing may adversely affect system timings Ringback and signal non monotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines Excessive signal swings overshoot and undershoot are detrimental to silicon gate oxide integrity and may cause device failure when absolute voltage limits are exceeded Additionally overshoot and undershoot may degrade timing due to th
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52. Design Guide and corresponding Design Guide for termination requirements and further details 3 The Low Voltage Intel Xeon processor utilizes only BRO and BR1 BR2 and BR3 are not driven by the processor but must be terminated to Vcc For additional details regarding the BR 3 0 signals see Section 5 2 and Section 7 1 and the appropriate Platform Design Guidelines 4 These signal groups are not terminated by the processor Refer to the appropriate platform design guidelines and the 17 700 Debug Port Design Guide for termination recommendations 5 The volume on these pins during active to inactive edge of RESET determines the multiplier that the Phase Lock Loop PLL will use for internal core clock 6 The value of these pins during the active to inactive edge of RESET to determine processor configuration options See Section 7 1 for details 7 These signals may be driven simultaneously by multiple agents wired OR 8 VID Voc is required for correct operation of the Low Voltage Intel Xeon Processor Refer to Figure 16 for details 9 It is an output only on the 1 60 GHz Low Voltage Intel Xeon processor with CPUID of 0F27h Datasheet intel 2 9 2 10 Table 6 Datasheet Low Voltage Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Asynchronous GTL Signals The Low Voltage Intel Xeon processor does not utilize CMOS voltage levels on any signals that connect to the processor silicon As a result le
53. Dynamic Execution enhanced Floating Point and Multimedia unit and Streaming SIMD Extensions 2 SSE2 The Hyper Pipelined Technology doubles the pipeline depth in the processor allowing the processor to reach much higher core frequencies The Rapid Execution Engine allows the two integer ALUS in the processor to run at twice the core frequency which allows many integer instructions to execute in one half of the internal core clock period The Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The floating point and multi media units have been improved by making the registers 128 bits wide and adding a separate register for data movement Finally SSE2 adds 144 new instructions for double precision floating point SIMD integer and memory management for improvements in video multimedia processing secure transactions and visual internet applications Also part of the Intel NetBurst micro architecture the system bus and caches on the Low Voltage Intel Xeon processor provide tremendous throughput for embedded applications The 400 533 MHz system bus provides a high bandwidth pipeline to the system memory and I O It is a quad pumped bus running off a 100 133 MHz system bus clock making 3 2 4 3 Gigabytes per second 3 200 4 300 Megabytes per second data transfer rates possible The Execution Trace Cache is a level 1 cache that stores approximately twelve thousand decoded micro operations which remov
54. GocacoccGOSCODOODpODODODODOODODOn 600000000005006009008080009066 amp 6 D EER amp amp j OV 27 i HW 0 53 Datasheet Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz lal amp Table 30 Dimensions for the Low Voltage Intel Xeon Processor in the FC uPGA2 Package Syrrbol Mlimeters Notes Min Nominal Max A 42 40 42 50 42 60 B 30 90 31 00 31 10 E 3 42 3 60 3 78 F 1 95 2 03 2 11 G 18 80 19 05 19 30 H 37 85 38 10 38 35 J 6 35 Noninal Component Keepin K 12 70 Nominal Component Keepin L 14 99 15 24 15 49 M 30 23 30 48 30 73 N 6 35 Nominal Component Keepin R 1 27 Norrinal T 12 70 oP 0 26 0 31 0 36 Pin Diameter Pin Tp 0 25 Figure 26 details the keep in zone for components mounted to the top side of the processor interposer Figure 26 Low Voltage Intel Xeon Processor in the FC uPGA2 Package Top View Component Height Keep In 1 61 pt x COMPONENT KEEPOUT CROSS HATCHED AREA 2 2 27 mm ALLOWABLE COMPONENT HEIGHT 155 J 1 61 15 5 54 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0
55. In lal Figure 11 System Bus Reset and Configuration Timing Waveform BCLK Reset Configuration A 31 3 SM INIT Configuration BRO Notes Tv 13 RESET Pulse Width Tw 45 Reset Configuration Signals Setup Time Tx T46 Reset Configuration Signals A 31 3 SM and INIT Hold Time Ty T47 Reset Configuration BRO Hold Time B2276 01 Figure 12 Power On Reset and Configuration Timing Waveform TB B LM NX XX XXX XXX PWRGOOD T37 PWRGOOD Inactive Pluse Width Tb T36 PWRGOOD to RESET de assertion time 36 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz tel e Signal Tx T63 Valid Time Ts T61 Setup Time Th T62 Hold Time V 0 5 Vcc Figure 14 Test Reset TRST Async GTL Input and PROCHOT Timing Waveform T 164 TRST Pulse Width V 0 5 Vcc 38 Pulse Width V GTLREF Figure 15 THERMTRIP to Timing THERMTRIP Power Down Sequence T39 THERMTRIP Vcc T39 lt 0 5 seconds Note THERMTRIP is undefined when RESET is active Datasheet 37 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz lal amp Figure 16 Example 3 3 VDC VID Vcc Sequencing 95 3 3 volt level Power Up 3 3 VDC VID V
56. Low Voltage Intel Xeon Processor Datasheet are also suitable for the Intel Xeon processor However Intel recommends new designs or designs undergoing design updates follow the trace impedance matching termination guidelines outlined in this section System Bus Signal Groups In order to simplify the following discussion the system bus signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF as a reference level In this document the term AGTL Input refers to the AGTL input group as well as AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the I O group when driving With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as 19 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz 20 Table 5 intel rising edge of BCLKO Asynchronous signals are still present A20M IGNNE etc and may become active at any time during the clock cycle Table 5 identifies which signals are common clock source synchronous and asynchronous System Bus Signal Groups
57. Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Product Features W Available at 1 60 GHz 2 0 GHz and 2 4 GHz Dual Uni processing support W Binary compatible with applications running on previous members of Intel s IA32 microprocessor line m Intel NetBurst micro architecture W Hyper Threading Technology Hardware support for multithreaded applications 400 MHz System bus 1 6 Ghz and 2 0 Ghz Bandwidth up to 3 2 GBytes second 533 MHz System bus 2 4 Ghz Bandwidth up to 4 3 GBytes second W Rapid Execution Engine Arithmetic Logic Units ALUs run at twice the processor core frequency W Hyper Pipelined Technology W Advance Dynamic Execution Very deep out of order execution Enhanced branch prediction Level 1 Execution Trace Cache stores 12 micro ops and removes decoder latency from main execution loops m Level 1 of 8 Kbytes data cache Datasheet 512 KB Advanced Transfer L2 Cache on die full speed Level 2 cache with 8 way associativity and Error Correcting Code ECC Enables system support of up to 64 Gbytes of physical memory Streaming SIMD Extensions 2 SSE2 144 new instructions for double precision floating point operations media video streaming and secure transactions Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D performance Power Management capabilities System Management mode M
58. N Output Valid Delay 400 MHz 8 80 10 20 ns 10 1 2 9 4 12 T30 Data Strobe n DSTBN Output Valid Delay 533 MHz 6 47 8 00 ns 10 1 2 5 4 12 T31 Address Strobe Output Valid Delay 400 MHz 2 27 4 23 ns 9 T31 Address Strobe Output Valid Delay 533 MHz 1 655 3 50 ns 9 1 2 8 NOTES 1 2 9 Not 100 tested Specified by design characterization All source synchronous AC timings are referenced to their associated strobe at GTLREF Source synchronous data signals are referenced to the falling edge of their associated data strobe Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe All source synchronous AGTL signal timings are referenced at GTLREF at the processor core Unless otherwise noted these specifications apply to both data and address timings Valid delay timings for these signals are specified into the test circuit described in Figure 4 and with GTLREF at 0 63 Voc 2 Specification is for a minimum swing defined between AGTL Vi max to This assumes an edge rate of 0 3 V ns to 4 0 V ns All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe This specification represents the minimum time the data or address may be valid before its strobe Refer to the appropriate platform design guidelines for more information on the definitions and use of t
59. Power Other VSS AE27 Power Other VSS W30 Power Other VSSA AA5 Power Other Input VSS Y1 Power Other VSSSENSE D26 Power Other Output Lis Poweroiher 1 In systems utilizing the Low Voltage Xeon processor the VSS Y7 Power Other system designer must pull up these signals to the processor Voc VSS Y13 Power Other 2 Baseboard treating AA3 and AB3 as Reserved may iss 3 is an output only on 1 6 GHz Low Voltage Intel Xeon VSS Y25 Power Other processor with CPUID of OF 27h VSS 1 Power Other VSS AA2 Power Other VSS AA9 Power Other VSS AA15 Power Other VSS AA17 Power Other VSS AA23 Power Other VSS AA30 Power Other VSS AB1 Power Other VSS AB5 Power Other VSS AB11 Power Other VSS AB21 Power Other VSS AB27 Power Other VSS AB31 Power Other VSS AC2 Power Other VSS AC7 Power Other Datasheet 69 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz 5 1 2 Pin Listing by Pin Number Table 35 Pin Listing by Pin Number Intel Table 35 Pin Listing by Pin Number Signal Pin No Pin Name Buffer Type Direction A1 Reserved Reserved Reserved A2 VCC Power Other A3 SKTOCC Power Other Output A4 Reserved Reserved Reserved A5 VSS Power Other A6 A32 Source Sync In
60. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches It includes input threshold hysteresis 8 The crossing point must meet the absolute and relative crossing point specifications simultaneously 9 VHavg can be measured directly using Vtop on Agilent scopes and High on Tektronix scopes 10 Vcross is defined as the total variation of all crossing voltages as defined in note 2 N Table 9 AGTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vin Input High Voltage 1 10 GTLREF Voc V 2 4 6 Vit Input Low Voltage 0 0 0 90 GTLREF V 3 6 Vou Output High Voltage N A Voc V 4 6 Vcc lot Output Low Current N A 0 50 Rrr min RoN mA 6 50 lui Pin Leakage High N A 100 9 lLo Pin Leakage Low N A 500 8 Ron Buffer On Resistance 7 11 Q 5 7 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes 2 Viu is defined as the minimum voltage level at a receiving agent that may be interpreted as a logical high value 3 Vy is defined as the maximum voltage level at a receiving agent that may be interpreted as a logical low value A and Voy may experi
61. Signal Integrity Models Inte Xeon Processor with 512 KB L2 Cache Mechanical Models in ProE Format http developer intel com Inte Xeon Processor with 512 KB L2 Cache Mechanical Models in IGES Format http developer intel com Inte Xeon Processor with 512 KB L2 Cache Core Boundary Scan Descriptor Language BSDL Model http developer intel com NOTES 1 Contact your Intel representative for the latest revision of documents without order numbers 2 The signal integrity models are in IBIS format Datasheet intel 2 0 Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Electrical Specifications 2 1 2 2 2 3 Datasheet System Bus and GTLREF Most Low Voltage Intel Xeon processor system bus signals use Assisted Gunning Transceiver Logic signaling technology This signaling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates The processor termination voltage level is the operating voltage of the processor core The use of a termination voltage that is determined by the processor core allows better voltage scaling on the processor system bus Because of the speed improvements to data and address busses signal integrity and platform design methods become more critical than with previous processor families The AGTL inputs require a reference voltage GILREF that is used by th
62. Sync Input Output D20 BRO ca Input Output C19 VSS Power Other D21 VSS Power Other C20 REQ3 ae Input Output Common D22 RS1 Clk Input Common C21 REQ2 Input Output Clk Common D23 BPRI Clk Input C22 VCC Power Other D24 VCC Power Other C23 DEFER ae Input D25 Reserved Reserved Reserved C24 TDI TAP Input D26 VSSSENSE Power Other Output C25 VSS Power Other Input D27 vss Power Other C26 IGNNE Async GTL Input D28 vss Power Other C27 SMI Async GTL Input D29 VCC Power Other Ges 030 VSS Power Other C29 VSS Power Other D31 VCC Power Other C30 VCC Power Other E1 VSS Power Other C31 VSS Power Other VCC Power Other D1 VCC Power Other E3 VID1 Power Other Output D2 VSS Power Other E4 BPM5 Input Output D3 VID2 Power Other Output D4 STPCLK Async GTL Input 5 IERR en Output D5 VSS Power Other E6 VCC Power Other D6 INIT Async GTL Input E7 BPM2 Input Output D7 MCERR ER Input Output Clk Common D8 VCC Power Other E8 BPM4 Clk Input Output D9 1 Mia Input Output E9 VSS Power Other E10 APO Co ae Input Output Datasheet 7i Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 35 Pin Listing by Pin Number intel Table 35 Pin Listing by Pin Number Pin No Pin Name
63. VCC Power Other M25 VCC Power Other P27 VSS Power Other M26 VSS Power Other P28 VCC Power Other M27 VCC Power Other P29 VSS Power Other M28 VSS Power Other P30 VCC Power Other M29 VCC Power Other P31 VSS Power Other M30 VSS Power Other R1 VCC Power Other M31 VCC Power Other R2 VSS Power Other N1 VCC Power Other R3 VCC Power Other N2 VSS Power Other R4 VSS Power Other N3 VCC Power Other R5 VCC Power Other N4 VSS Power Other R6 VSS Power Other N5 VCC Power Other R7 VCC Power Other N6 VSS Power Other R8 VSS Power Other N7 VCC Power Other R9 VCC Power Other N8 VSS Power Other R23 VCC Power Other N9 VCC Power Other R24 VSS Power Other N23 VCC Power Other R25 VCC Power Other N24 VSS Power Other R26 VSS Power Other N25 VCC Power Other R27 VCC Power Other N26 VSS Power Other R28 VSS Power Other N27 VCC Power Other R29 VCC Power Other N28 VSS Power Other R30 VSS Power Other N29 VCC Power Other R31 VCC Power Other N30 VSS Power Other T1 VSS Power Other N31 VCC Power Other T2 VCC Power Other P1 VSS Power Other T3 VSS Power Other P2 VCC Power Other T4 VCC Power Other P3 VSS Power Other T5 VSS Power Other 74 Datasheet In Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 35 Pin Listing by Pin Number Table 35 Pin Listing by Pin Number
64. Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz This page intentionally left blank 98 Datasheet intel 8 0 Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Debug Tools Specifications 8 1 8 1 1 Datasheet The Debug Port design information has been moved This includes all information necessary to develop a Debug Port on this platform including electrical specifications mechanical requirements and all In Target Probe ITP signal layout guidelines Please reference the 7P700 Debug Port Design Guide for the design of your platform Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging systems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of systems the LAI is critical in providing the ability to probe and capture system bus signals There are two sets of considerations to keep in mind when designing a system that may make use of an LAI mechanical and electrical Mechanical Considerations The LAT is installed between the processor socket and the processor The LAI pins plug into the socket while the processor pins plug into a socket on the LAI Cabling that is part of the LAI egresse
65. a 0 20 13 Hs 9 10 1 2 3 4 address only T21 Tven Source Sync Data Output Valid Before Data Strobe 400 MHz ns T21 Source Sync Data Output Valid Before Data Strobe 533 MHz gt ns hs T22 Tvap Source Sync Data Output Valid After Data Strobe 400 MHz 0 85 ns 10 1 2 3 4 7 T22 Tvap Source Sync Data Output Valid After Data Strobe 533 MHz 0 535 ns 10 1 2 98 4 7 T23 TvBA Source Sync Address Output Valid Before Address Strobe 400 MHz 188 us 23 TvBA Source Sync Address Output Valid Before Address Strobe 533 MHz 7980 ns 1 2 8 4 T T24 TvAA Source Sync Address Output Valid After Address Strobe 400 MHz 968 us 1 8 94 5 T24 TvAA Source Sync Address Output Valid After Address Strobe 533 MHz ieee ns 1 2 9 4 8 T25 Tsuss Source Sync Input Setup Time 0 21 ns 9 10 12 8 26 THSs Source Sync Input Hold Time 0 21 ns 9 10 1 233 2 T27 Tsucc Source Sync Input Setup Time to BCLK 0 65 ns 9 10 1 2 3 4 6 T28 Trass First Address Strobe to Second Address 1 2 BCLKs 9 1 2 3 4 9 Strobe 13 1 2 3 4 T29 Trpss First Data Strobe to Subsequent Strobes n 4 BCLKs 10 10 11 13 29 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz 30 Intel Table 15 System Bus Source Synchronous AC Specifications Sheet 2 of 2 T Parameter Min Max Unit Figure Notes T30 Data Strobe n DSTB
66. al configuration options that are determined by the state of specific processor pins at the active to inactive transition of the processor RESET signal These configuration options cannot be changed except by another reset Both power on and software induced resets reconfigure the processor s Power On Configuration Option Pins Configuration Option Pin Notes Output tri state Execute BIST Built In Self Test INIT In Order Queue de pipelining set IOQ depth to 1 A7 Disable MCERR observation AQ Disable BINIT observation A10 APIC cluster ID 0 3 12 11 2 Disable bus parking A15 Disable Hyper Threading Technology A31 Symmetric agent arbitration ID BR 3 0 3 NOTES 1 Asserting this signal during active to inactive edge of RESET may select the corresponding option 2 The Low Voltage Intel Xeon processor does not support this feature therefore platforms utilizing this processor should not use these configuration pins 3 The Low Voltage Intel Xeon processor utilizes only BRO and BR1 signals Two way platforms must not utilize BR2 and BR3 signals Clock Control and Low Power States The processor allows the use of AutoHALT Stop Grant and Sleep states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 36 for a visual representation of the processor low power states Due to the inability
67. ase Lock Loop PLL which requires a constant frequency BCLK inputs For Spread Spectrum Clocking please refer to the CKO00 Clock Synthesizer Driver Design Guidelines and the CK408 Clock Synthesizer Driver Design Guidelines The system bus frequency ratio cannot be changed dynamically during normal processor operation nor can it be changed during any low power modes The system bus frequency ratio can be changed when RESET is active assuming that all Reset specifications are met However the reprogrammed values will not take effect until after the processor has undergone a warm RESET 101 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz This page intentionally left blank 102 Datasheet
68. ation When BINIT observation is enabled during power on configuration see Section 7 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT assertion Once the BINIT assertion has been observed the bus agents will re arbitrate for the system bus and attempt completion of their bus queue and IOQ entries When BINIT observation is disabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wire OR signal which must connect the appropriate pins of all processor system bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges 5 0 VO 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for mo
69. ations for the processor are given in this section See Section 1 1 for terminology definitions Figure 23 provides a basic assembly drawing and includes the components which make up the entire processor Package dimensions are provided in Table 30 The Low Voltage Intel Xeon processor utilizes a surface mount 604 pin zero insertion force ZIF socket for installation into the baseboard See the 604 Pin Socket Design Guidelines for further details on the processor socket For Figure 25 through Figure 29 the following notes apply 1 Unless otherwise specified the following drawings are dimensioned in millimeters 2 All dimensions are not tested but are ensured by design characterization 3 Figures and drawings labelled as Reference Dimensions are provided for informational purposes only Reference Dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied Reference Dimensions are NOT checked as part of the processor manufacturing process Unless noted as such dimensions in parentheses without tolerances are Reference Dimensions 4 Drawings are not to scale Figure 23 Low Voltage Intel Xeon Processor in the FC uPGA2 Package Note Datasheet Assembly Drawing 1 2 This drawing is not to scale and is for reference only The assembly applies to the Low Voltage Intel Xeon processor in the FC uPGA2 package 1 Integrated Heat Spreader IHS
70. be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 3 The processor should not be subjected to any static Vcc level that exceeds the max associated with any particular current Moreover Vcc should never exceed Voc vip Failure to adhere to this specification may shorten the processor lifetime 4 Maximum current is defined at max 5 The current specified is also for AutoHALT State 6 The maximum instantaneous current the processor may draw while the thermal control circuit is active as indicated by the assertion of PROCHOT 7 This specification applies to the PLL power pins VCCA and VCCIOPLL See Section 2 5 for details This parameter is based on design characterization and is not tested 8 This specification applies to each GTLREF pin 9 The loadlines specify voltage limits at the die measured at Voc sense and Vss sense pins Voltage regulation feedback for voltage regulator circuits must be taken from processor and Vgs pins 10 Adherence to this loadline specification is required to ensure reliable processor operation 11 VID Voc is required for correct operation of the Low Voltage Intel Xeon Processor VID and BSEL logic Refer to Figure 16 for details Datasheet 23 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Figure 3 Low Voltage Intel Xeon Processor Voltage and Current Projections in a Dual Processor Configuration Table 8 24
71. ce Sync Input Output 8 C17 Source Sync Input Output A34 C9 Source Sync Input Output 9 017 Source Sync Input Output 5 C8 Source Sync Input Output A10 A13 Source Sync Input Output A20M F27 Async GTL Input 11 B16 Source Syne Input Output ADS D19 d Input Output 12 14 Source Sync Input Output ADSTBO F17 Source Sync Input Output A13 B13 Source Sync Input Output ADSTB1 F14 Source Sync Input Output A144 A12 Source Sync Input Output C ommon A15 C15 Source Sync Input Output APO E10 Clk Input Output A16 C14 Source Sync Input Output 1 D9 Input Output A17 D16 Source Sync Input Output A18 D15 Source Sync Input Output BOLKO 34 SyS Input A19 F15 Source Sync Input Output BOLM Nm Sys Bus Input A20 A10 Source Sync Input Output BINIT F11 Input Output 21 B10 Source Sync Input Output BNR F20 Common Input Output A22 B11 Source Sync Input Output Clk A23 C12 Source Sync Input Output F6 g Input Output A24 E14 Source Sync Input Output C ommon A25 D13 Source Sync Input Output 1 F8 Clk Input Output A26 AQ Source Sync Input Output BPM2 E7 Input Output A27 B8 Source Sync Input Output Common A28 E13 Source Sync Input Output BPM3 F5 Clk Input Output Datasheet 61 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 34 Pin Listing by Pin Name intel Table 34 Pin Listing by Pin Name
72. cifications are measured at the processor pad 2 These signals are assumed in a 33 MHz time domain Datasheet 47 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Intel Table 25 400 MHz Asynchronous GTL PWRGOOD and TAP Signal Groups Overshoot Undershoot Tolerance Sheet 2 of 2 Absolute Absolute Pulse Duration ns Pulse Duration Pulse Duration ns Maximum Maximum AF 1 ns AF 0 1 AF 0 01 Overshoot V Undershoot V 1 45 0 15 60 00 60 00 60 00 1 40 0 10 60 00 60 00 60 00 1 35 0 05 60 00 60 00 60 00 1 These specifications are measured at the processor pad 2 These signals are assumed in a 33 MHz time domain Table 26 Source Synchronous 533 MHz AGTL Signal Group Overshoot Undershoot Tolerance sies esum Pesce Rasen Overshoot V Undershoot V E i 1 700 0 400 0 32 3 14 3 75 1 650 0 350 0 94 3 75 3 75 1 600 0 300 2 74 3 75 3 75 1 550 0 250 3 75 3 75 3 75 1 500 0 200 3 75 3 75 3 75 1 450 0 150 3 75 3 75 3 75 1 400 0 100 3 75 3 75 3 75 1 350 0 050 3 75 3 75 3 75 NOTES 1 These specifications are measured at the processor pad 2 Assumes a BCLK period of 10 ns 3 AF is referenced to associated source synchronous strobes Table 27 Source Synchronous 533 MHz AGTL Signal Group Overshoot Undershoot Tolerance Sheet 1 of 2 48 ita an
73. ct of all overshoot events are considered the system may fail A guideline to ensure a system passes the overshoot and undershoot specifications is presented as follows Ensure that no signal ever exceeds or 0 25 V OR When only one overshoot undershoot event magnitude occurs ensure it meets the overshoot undershoot specifications in the following tables OR When multiple overshoots and or multiple undershoots occur measure the worst case pulse duration for each magnitude and compare the results against the AF 1 specifications When all of these worst case overshoot or undershoot events meet the specifications measured time lt specifications in the table where AF 1 the system passes 45 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz 46 The following notes apply to Table 22 through Table 25 Intel Absolute Maximum Overshoot magnitude of 1 8 V must never be exceeded e Absolute Maximum Overshoot is measured referenced to V ss Pulse Duration of overshoot is measured relative to Vcc Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to Ringback below cannot be subtracted from overshoots undershoots Lesser undershoot does not allocate longer or larger overshoot System designers are strongly encouraged to follow Intel s layout guidelines All values specified by design characterization Overshoot Undershoot Tolerance Tabl
74. e Pulse Duration Pulse Duration Pulse Duration Overshoot V Undershoot V a pea merenti 1 700 0 400 0 63 6 27 7 50 1 650 0 350 1 87 7 50 7 50 1 600 0 300 5 49 7 50 7 50 1 550 0 250 7 50 7 50 7 50 1 500 0 200 7 50 7 50 7 50 1 450 0 150 7 50 7 50 7 50 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Intel Table 27 Source Synchronous 533 MHz AGTL Signal Group Overshoot Undershoot Table 28 Common Clock 533 MHz AGTL Signal Group Overshoot Undershoot Tolerance Table 29 533 MHz Asynchronous GTL PWRGOOD and TAP Signal Groups Overshoot Datasheet Tolerance Continued Sheet 2 of 2 Absolute Absolute Pulse Duration Pulse Duration Pulse Duration Maximum Maximum ns AF 1 ns AF 0 1 ns AF 0 01 Overshoot V Undershoot V 1 400 0 100 7 50 7 50 7 50 1 350 0 050 7 50 7 50 7 50 NOTES 1 These specifications are measured at the processor pad 2 Assumes a BCLK period of 10 ns 3 AF is referenced to associated source synchronous strobes Maximum Maximum Pulse Duration Pulse Duration Pulse Duration Overshoot V Undershoot V D 1 700 0 400 1 26 12 54 15 00 1 650 0 350 3 75 15 00 15 00 1 600 0 300 10 98 15 00 15 00 1 550 0 250 15 00 15 00 15 00 1 500 0 200 15 00 15 00 15 00 1 450 0 150 15 00 15 00 15 00 1 400 0 100 15 00 15 00 15 00 1 350 0 050 1
75. e the SLP pin may be deasserted when another asynchronous system bus event occurs The SLP pin should only be asserted when the processor and all logical processors within the physical processor is in the Stop Grant state SLP assertions while the processors are not in the Stop Grant state is out of specification and may result in illegal operation 95 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz lal amp 7 2 6 7 3 7 3 1 96 Bus Response During Low Power States While in AutoHALT Power Down and Stop Grant states the processor may process a system bus snoop When the processor is in Sleep state the processor may not process interrupts or snoop transactions Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the Thermal Control Circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption by modulating starting and stopping the internal processor core clocks The Thermal Monitor feature must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor feature is e
76. e 16 for details The processor uses five voltage identification pins VID 4 0 to support automatic selection of processor voltages Table 4 specifies the voltage level corresponding to the state of VID 4 0 In this table a 1 refers to a high voltage and a 0 refers to low voltage level When the processor socket is empty VID 4 0 2 11111 or the VRD or VRM cannot supply the voltage that is requested it must disable its voltage output For further details see the Dual Intel Xeon Processor Voltage Regulator Down VRD Design Guidelines or VRM 9 0 DC DC Converter Design Guidelines or the VRM 9 1 DC DC Converter Design Guidelines 17 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 4 Voltage Identification Definition 2 6 1 18 Processor Pins VIDA VID3 VID2 VID1 VIDO Vcc vip V 1 1 1 1 1 VRM output off 1 1 1 1 0 1 100 1 1 1 0 1 1 125 1 1 1 0 0 1 150 1 1 0 1 1 1 175 1 1 0 1 0 1 200 1 1 0 0 1 1 225 1 1 0 0 0 1 250 1 0 1 1 1 1 275 1 0 1 1 0 1 300 1 0 1 0 1 1 325 1 0 1 0 0 1 350 1 0 0 1 1 1 375 1 0 0 1 0 1 400 1 0 0 0 1 1 425 1 0 0 0 0 1 450 0 1 1 1 1 1 475 0 1 1 1 0 1 500 0 1 1 0 1 1 525 0 1 1 0 0 1 550 0 1 0 1 1 1 575 0 1 0 1 0 1 600 0 1 0 0 1 1 625 0 1 0 0 0 1 650 0 0 1 1 1 1 675 0 0 1 1 0 1 700 0 0 1 0 1 1 725 0 0 1 0 0 1 750 0 0 0 1 1 1 775 0 0 0 1 0 1 800 0 0 0 0 1 1 825 0
77. e 22 Source Synchronous 400 MHz AGTL Signal Group ren d pier diui eec ns in Overshoot V Undershoot V E 1 70 0 40 0 42 4 18 5 00 1 65 0 35 1 25 5 00 5 00 1 60 0 30 3 66 5 00 5 00 1 55 0 25 5 00 5 00 5 00 1 50 0 20 5 00 5 00 5 00 1 45 0 15 5 00 5 00 5 00 1 40 0 10 5 00 5 00 5 00 1 35 0 05 5 00 5 00 5 00 NOTES 1 These specifications are measured at the processor pad 2 Assumes a BCLK period of 10 ns 3 AF is referenced to associated source synchronous strobes Overshoot Undershoot Tolerance Table 23 Source Synchronous 400 MHz AGTL Signal Group Absolute Absolute Pulse Duration Pulse Duration ns Pulse Duration ns Maximum Maximum ns AF 1 AF 0 1 AF 0 01 Overshoot V Undershoot V E hs 1 70 0 40 0 84 8 36 10 00 1 65 0 35 2 50 10 00 10 00 1 60 0 30 7 32 10 00 10 00 1 55 0 25 10 00 10 00 10 00 1 50 0 20 10 00 10 00 10 00 NOTES 1 These specifications are measured at the processor pad 2 Assumes a BCLK period of 10 ns 3 AF is referenced to associated source synchronous strobes Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Intel Table 23 Source Synchronous 400 MHz AGTL Signal Group Overshoot Undershoot Tolerance Absolute Absolute Pulse Duration Pulse Duration ns Pulse Duration ns Maximum Maximum ns AF 1 AF 0 1
78. e Cathode THERMTRIP Activation of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135 C To properly protect the processor power must be removed upon THERMTRIP becoming active See Figure 15 THERMTRIP to VCC Timing on page 37 for the appropriate power down sequence and timing requirement In parallel the processor will attempt to reduce its temperature by shutting off internal clocks and stopping all program execution Once activated THERMTRIP remains latched and the processor will be stopped until RESET is asserted A RESET pulse will reset the processor and execution will begin at the boot vector When the temperature has not dropped below the trip level the processor will assert THERMTRIP and return to the shutdown state The processor releases THERMTRIP when RESET is activated even when the processor is still too hot This signal do not have on die termination and must be terminated at the end agent See the appropriate platform design guidelines for additional information 86 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 36 Signal Definitions Sheet 9 of 9 Name Type Description TMS Test Mode Select is a JTAG specification su
79. e Sync Input Output AC10 VCC Power Other AD15 VSS Power Other AC11 D43 Source Sync Input Output AD16 COMPO Power Other Input AC12 D41 Source Sync Input Output AD17 VSS Power Other AC13 VSS Power Other AD18 D36 Source Sync Input Output AC14 D50 Source Sync Input Output AD19 D30 Source Sync Input Output AC15 DP2 a Input Output AD20 VCC Power Other AD21 D29 Source Sync Input Output AGIS we Poner omer AD22 DBI1 Source Sync Input Output AC17 D34 Source Sync Input Output AD23 vss Power Other AC18 DPO a Input Output AD24 D21 Source Sync Input Output AC19 VSS Power Other AD25 D18 Source Sync Input Output AC20 025 Source Sync Input Output AD26 voc Power Other AC21 026 Source Sync Input Output AD27 D4 Source Sync Input Output AC22 VCC Power Other AD28 Reserved Reserved Reserved AC23 D23 Source Sync Input Output AD29 Reserved Reserved Reserved AC24 D20 Source Sync Input Output AD30 voc Power Other AC25 VSS Power Other nos MES Powerother AC26 D17 Source Sync Input Output AE2 VSS Power Other AC27 DBIO Source Sync Input Output AES VCC Power Other AE4 VSS Power Other Datasheet 77 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 35 Pin Listing by Pin Number Signal Pin No Pin Name Buffer Type Direction AE5 TESTHI6 Power Other Input AE6 SLP Async GTL Input AE7 D58 Source Sync Input Ou
80. e build up of inter symbol interference ISI effects For these reasons it is crucial that the designer assure acceptable signal quality across all systematic variations encountered in volume manufacturing Specifications for signal quality are for measurements at the processor core only and are only observable through simulation The same is true for all system bus AC timing specifications in Section 2 13 Therefore proper simulation of the processor system bus is the only means to verify proper timing and signal quality metrics System Bus Clock BCLK Signal Quality Specifications and Measurement Guidelines Table 19 describes the signal quality specifications at the processor pads for the processor system bus clock BCLK signals Figure 17 describes the signal quality waveform for the system bus clock at the processor pads Table 19 BCLK Signal Quality Specifications Data sheet Parameter Min Max Unit Figure Notes BCLK 1 0 Overshoot N A 0 30 V 17 BCLK 1 0 Undershoot N A 0 30 V 17 BCLK 1 0 Ringback Margin 0 20 N A V nri BCLK 1 0 Threshold Region N A 0 10 V t T The rising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the BCLK signal may dip back to after passing the V rising or falling voltage limits This specification is an absolute value 39 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4
81. e clamps and may not provide overshoot or undershoot protection ESD diodes modelled within Intel s signal integrity models do not clamp undershoot or overshoot and may yield correct simulation results When other signal integrity models are being used to characterize the processor system bus care must be taken to 43 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz In lal 3 3 2 3 3 3 3 3 4 44 Note ensure that ESD models do not clamp extreme voltage levels Intel s signal integrity models also contain I O capacitance characterization Therefore removing the ESD diodes from a signal integrity model may impact results and may yield excessive overshoot undershoot Overshoot Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level Vgg It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently Overshoot undershoot magnitude levels must observe the absolute maximum specifications listed in Table 22 through Table 25 These specifications must not be violated at any time regardless of bus activity or system state Within these specifications are threshold levels that define different allowed pulse duration Provided that the magnitude of the overshoot undershoot is within the absolute maximum specifications the pulse magnitude duration and activity factor must all be
82. e receivers to determine if a signal is a logical 0 or a logical 1 GTLREF must be generated on the baseboard See Table 12 for GTLREF specifications Termination resistors are provided on the processor silicon and are terminated to its core voltage The on die termination resistors are selectable feature and may be enabled or disabled through the ODTEN pin For end bus agents on die termination may be enabled to control reflections on the transmission line For middle bus agents on die termination must be disabled Intel chipsets may also provide on die termination thus eliminating the need to terminate the bus on the baseboard for most AGTL signals Refer to Section 2 12 for details on ODTEN resistor termination requirements Some signals do not include on die termination and must be terminated on the baseboard See Table 5 for details regarding these signals The signals depend on incident wave switching Therefore timing calculations for AGTL signals are based on flight time as opposed to capacitive deratings Analog signal simulation of the system bus including trace lengths is highly recommended when designing a system Power and Ground Pins For clean on chip power distribution the Low Voltage Intel Xeon processor has 190 power and 189 Vss ground inputs All pins must be connected to the system power plane while all Vss pins must be connected to the system ground plane The processor
83. ease see Section 3 0 for maximum allowable overshoot Ringback between GTLREF 100 mV and GTLREF 100 mV is not supported Intel recommends simulations not exceed a ringback value of GTLREF 200 mV to allow margin for other Sources of system noise Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz In lel Table 21 Ringback Specifications for TAP Buffers Signal Maximum Ringback Pil Transition with Input Diodes Threshold Unit Figure Notes Present TAP and PWRGOOD TO VT max V 20 1 2 8 4 TAP and PWRGOOD HL Vz min TO VT min VT min V 21 1 2 3 4 NOTES 1 All signal integrity specifications are measured at the processor core pads 2 Specifications are for the edge rate of 0 3 4 0 V ns 3 All values specified by design characterization 4 Please see Section 3 3 for maximum allowable overshoot Figure 18 Low to High System Bus Receiver Ringback Tolerance for AGTL and Asynchronous GTL Buffers Noise Margin Figure 19 High to Low System Bus Receiver Ringback Tolerance for AGTL and Asynchronous GTL Buffers 10 Vcc GTLREF 10 Vcc Noise Margin Vss Datasheet 41 42 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Figure 20 Low to High System Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers Vcc Vt
84. ecifications and Measurement 43 3 3 1 Overshoot Undershoot 43 3 3 2 Overshoot Undershoot 44 3 3 3 Overshoot Undershoot Pulse Duration sese 44 334 Activity 2 a nsu euis 44 3 3 5 Reading Overshoot Undershoot Specification Tables 45 3 3 6 Determining When a System Meets the Overshoot Undershoot sleep 45 4 0 Mechanical nennen enne 51 4 1 Mechanical 5 scriniis a aE ATE AEE TS 52 4 2 Processor Package Load Specifications 56 4 3 lnsertion Specifications rrisnin ceder vere ade er YR 57 44 Mass SpecifiCatiOlis soo dich ele ele ie eae aie Aint eee 57 Datasheet 3 Contents n Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz tel LEM Materials ercsi E A E 57 4 6 MIKIS eene E A OEE E OE O 58 4 7 Processor Pin Out 58 5 0 Pin Listing and Signal Definitions 61 5 1 Processor Pin AENEAN NANENANE NENADNE 61 5 1 1 Pin Listing by Pin Name
85. ed by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor system bus This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET BINIT or INIT This signal does not have on die termination and must be terminated at the end agent See the appropriate Platform Design Guideline for additional information IGNNE IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions When IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction when a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an write instruction it must be valid along with the TRDY assertion of the corresponding write bus transaction INIT INIT Initialization when asserted resets integer registers inside all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT
86. enable on die termination for end bus agents For middle bus agents pull this signal down via a resistor to ground to disable on die termination Whenever ODTEN is high on die termination will be active regardless of other states of the bus PROCHOT 1 0 with CPUID of 0F27h PROCHOT As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled The TCC will remain active until the system deasserts PROCHOT See Section 7 3 for more details The PROCHOT is an output only on 1 6 GHz Low Voltage Intel Xeon processor 84 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 36 Signal Definitions Sheet 7 of 9 Name Type Description PWRGOOD PWRGOOD Power Good is an input The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state Figure
87. ence excursions above However input signal drivers must comply with the signal quality specifications in Chapter 3 0 Refer to the Low Voltage Inte Xeon Processor Signal Integrity Models for I V characteristics The referred to in these specifications refers to instantaneous max Of 0 450 V is ensured when driving into a test load as indicated in Figure 4 with enabled Leakage to with pin held at 300 mV Leakage Vgg with pin held at Vcc Datasheet 25 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 10 TAP and PWRGOOD Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vuys TAP Input Hysteresis 200 300 Fi TAP input low to high x VT ehed 0 5 Vuvs 0 5 Voc Vuvs 4 TAP input high to low VT 0 5 Vuvs 0 5 Vcc Vuvs 4 Vou Output High Voltage N A Vec V 2 4 lo Output Low Current 40 mA 5 6 lui Pin Leakage High N A 100 9 lio Pin Leakage Low N A 500 8 Ron Buffer On Resistance 8 75 13 75 Q 3 NOTES 1 All outputs are open drain 2 TAP signal group must meet the system signal quality specification in Chapter 3 0 3 Refer to the Low Voltage Inte Xeon Processor Signal Integrity Models for I V characteristics 4 The Vcg referred to in these specifications ref
88. equency and input voltages Care should be taken to read all notes associated with each parameter Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 7 Voltage and Current Specifications Symbol Parameter I VID Unit Notes Voc for Low Voltage Intel Xeon processor 1 60 GHz 1 187 RS 1 274 Vec core ina 2 0 GHz 1 179 Figure 3 1 270 1 8 V 1 2 3 8 10 dual processor 2 4GHz 1 170 1 265 configuration VID Voc VID supply voltage All freq 3 135 3 3 3 465 V 11 for Low Voltage Intel Xeon processor 1 60 GHz 30 4 loc core ina 2 0 GHz 35 7 3 4 dual processor 2 4GHz 40 9 configuration loc for VID power loc_VID supply All freq 100 0 122 5 mA 11 Icc for PLL power loc_PLL in All freq 60 mA 7 Ioc_GTLREF loc for GTLREF pins All freq 15 uA 8 IsGnt lsLP loc Stop Grant Sleep All freq 10 1 A 5 TCC active All freq 10 1 A 6 NOTES 1 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 6 and Table 4 for more information 2 The voltage specification requirements are measured across vias on the platform for the Vcc sense and Vss sense Pins close to the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 milliohm minimum impedance The maximum length of ground wire on the probe should
89. er Other Input d m Fio VEG PowerlOther G26 Power Other G27 VSS Power Other i BIN Input Output 628 VCC Power Other 72 Datasheet In Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 35 Pin Listing by Pin Number Table 35 Pin Listing by Pin Number Pin No Pin Name Iv Direction Pin No Pin Name utter Typ o Direction G29 VSS Power Other J31 VSS Power Other G30 Power Other K1 VCC Power Other G31 VSS Power Other K2 VSS Power Other H1 VCC Power Other K3 VCC Power Other H2 VSS Power Other K4 VSS Power Other H3 VCC Power Other K5 VCC Power Other H4 VSS Power Other K6 VSS Power Other H5 VCC Power Other K7 VCC Power Other H6 VSS Power Other K8 VSS Power Other H7 VCC Power Other K9 VCC Power Other H8 VSS Power Other K23 VCC Power Other H9 VCC Power Other K24 VSS Power Other H23 VCC Power Other K25 VCC Power Other H24 VSS Power Other K26 VSS Power Other H25 VCC Power Other K27 VCC Power Other H26 VSS Power Other K28 VSS Power Other H27 VCC Power Other K29 VCC Power Other H28 VSS Power Other K30 VSS Power Other H29 VCC Power Other K31 VCC Power Other H30 VSS Power Other L1 VSS Power Other H31 VCC Power Other L2 VCC P
90. ermal Design Power TDP value listed per frequency in Table 37 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the appropriate processor thermal design guidelines The case temperature is defined at the geometric top center of the processor IHS Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained periods of time Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 37 instead of the maximum processor power consumption The Thermal Monitor feature is intended to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time For more details on the usage of this feature refer to Section 7 3 Thermal Monitor on page 96 In all cases the Thermal Monitor feature must be enabled for the processor to remain within specification Processor Thermal Design Power Core Frequency Thermal Design Powert W Minimum Tease C Maximum Tease 1 60 GHz 30 5 81 2 0 GHz 35 5 83 2 4 GHz 40 5 81 T Intel recommends that thermal solutions be designed utilizing the Thermal Design Power values Refer to the Low Voltage Intel Xeon Processor Thermal Design Guide
91. ers to instantaneous Vcc 5 The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load VoL max Of 0 300V is ensured when driving a test load Vuvs represents the amount of hysteresis nominally centered about 0 5 V cc for all TAP inputs Leakage to with Pin held at 300 mV Leakage to Vss with pin held at Voc Table 11 Asynchronous GTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vin Input High Voltage 1 10 GTLREF Voc V 2 4 6 Vi Input Low Voltage 0 0 0 90 GTLREF V 3 5 Vou Output High Voltage N A Vcc V 1 4 6 lot Output Low Current 50 mA 7 8 lui Pin Leakage High N A 100 10 lio Pin Leakage Low N A 500 9 Ron Buffer On Resistance 7 11 Q 5 NOTES 1 All outputs are open drain 2 Viu is defined as the minimum voltage level at a receiving agent that may be interpreted as a logical high value 3 is defined as the maximum voltage level at a receiving agent that may be interpreted as a logical low value 4 and Voy may experience excursions above However input signal drivers must comply with the signal quality specifications in Chapter 3 0 5 Refer to the Low Voltage Inte Xeon Processor Signal Integrity Models for V characteristics 6 The Vcc referred to in these specifications refers to instantaneous Vcc 7 The maximum out
92. es All system bus agents must operate at the same frequency Individual processors will only operate at their specified front side bus FSB frequency On baseboards which support operation only at 100 MHz bus clocks these signals may be ignored On baseboards employing the use of these signals a 1 KQ pull up resistor be used See Table 3 System Bus Clock Frequency Select Truth Table for BSEL 1 0 on page 15 for output values COMP 1 0 COMPT 1 0 must be terminated to Vas on the baseboard using precision resistors These inputs configure the AGTL drivers of the processor Refer to the appropriate platform design guidelines and Table 12 for implementation details Datasheet 81 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz 82 Intel Table 36 Signal Definitions Sheet 4 of 9 Name Type Description D 63 0 1 0 D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor system bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to str
93. es the decoder latency from the main execution path and increases performance The Advanced Transfer Cache is a 512 KB on die level 2 cache running at the speed of the processor core providing increased bandwidth over previous micro architectures In addition to the Intel NetBurst micro architecture the Low Voltage Intel Xeon processor includes a ground breaking new technology called Hyper Threading technology which enables multi threaded software to execute tasks in parallel within the processor resulting in a more efficient simultaneous use of processor resources Embedded applications may realize increased performance from Hyper Threading technology today through software and processor evolution The combination of Intel NetBurst micro architecture and Hyper Threading technology delivers outstanding performance throughput and headroom for peak software workloads resulting in faster response times and improved scalability The Low Voltage Intel Xeon processor is intended for high performance embedded systems with up to two processors on a single bus The processor supports both uni and dual processor designs and includes manageability features The Low Voltage Intel Xeon processor is packaged in a 604 pin Flip Chip Micro Pin Grid Array 2 package and utilizes a surface mount ZIF socket with 604 pins Mechanical components used for attaching thermal solutions to the baseboard should have a high degree of commonality with the ther
94. eserved Reserved Reserved V2 VCC Power Other Y4 BCLKO Sys Bus Clk Input V3 VSS Power Other Y5 VSS Power Other V4 VCC Power Other Y6 TESTHIS Power Other Input V5 VSS Power Other Y7 VSS Power Other V6 VCC Power Other y8 RESET some Input V7 VSS Power Other Datasheet 75 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 35 Pin Listing by Pin Number intel Table 35 Pin Listing by Pin Number Pin No Pin Name wel Direction Pin No Pin Name reas Direction Y9 D62 Source Sync Input Output AA16 D33 Source Sync Input Output Y10 VCC Power Other AA17 VSS Power Other Y11 DSTBP3 Source Sync Input Output AA18 D24 Source Sync Input Output Y12 DSTBN3 Source Sync Input Output AA19 D15 Source Sync Input Output Y13 VSS Power Other AA20 VCC Power Other Y14 DSTBP2 Source Sync Input Output AA21 D11 Source Sync Input Output Y15 DSTBN2 Source Sync Input Output AA22 D10 Source Sync Input Output Y16 VCC Power Other AA23 VSS Power Other Y17 DSTBP1 Source Sync Input Output AA24 D6 Source Sync Input Output Y18 DSTBN1 Source Sync Input Output AA25 D3 Source Sync Input Output Y19 VSS Power Other AA26 VCC Power Other Y20 DSTBPO Source Sync Input Output AA27 01 Source Sync Input Output Y21 DSTBNO Source Sync Input Output AA28 Reserved
95. essor system bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock agents are defined by the following options Enabled or disabled MCERR VO observes an error sampled on specific clock edges MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor system bus MCERR assertion conditions are configurable at a system level Assertion options Asserted when configured for internal errors along with IERR Asserted when configured by the request initiator of a bus transaction after it Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the A 32 Software Developer s Manual Volume 3 System Programming Guide Since multiple agents may drive this signal at the same time MCERR is a wire OR signal which must connect the appropriate pins of all processor system bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers is activated on specific clock edges and Mechanical Key Inert The mechanical key is to prevent compatibility with 603 pin socket ODTEN ODTEN On die termination enable should be connected to Vcc to
96. gacy input signals such as 20 IGNNE INIT LINTO INTR LINT1 NMI SMI SLP and STPCLK utilize input buffers Legacy output FERR PBE and other non AGTL signals IERR and THERMTRIP utilize output buffers PROCHOT uses GTL input output buffer All of these asynchronous GTL signals follow the same DC requirements as AGTL signals however the outputs are not driven high during the logical 0 to 1 transition by the processor the major difference between GTL AGTL Asynchronous signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the asynchronous GTL signals are required to be asserted for at least two BCLKs in order for the processor to recognize them See Table 11 and Table 16 for the DC and AC specifications for the asynchronous signal groups Maximum Ratings Table 6 lists the processor s maximum environmental stress ratings Functional operation at the absolute maximum and minimum is neither implied nor ensured The processor should not receive a clock while subjected to these conditions Functional operating parameters are listed in the AC and DC tables Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circuitry to resist damage from static electric discharge one should always take precautions to avoid high static voltages or electric fields Processor Absolute Maxi
97. h the exception of a uniform load to maintain the heat sink to processor thermal interface It is not recommended to use any portion of the processor interposer as a mechanical reference or load bearing surface for thermal solutions Package Dynamic and Static Load Specifications Parameter Max Unit Unit Static 50 Ibf 12 3 Dynamic 50 1 Ib 50G input 1 8 AF 140 Ibf 1 2 4 5 NOTES 1 This specification applies to a uniform compressed load 2 This is the maximum static force that may be applied by the heatsink and clip to maintain the heatsink and processor interface 3 These parameters are based on design characterization and not tested 4 Dynamic loading specifications are defined assuming a maximum duration of 11 ms 5 The heatsink weight is assumed to be one pound Shock input to the system during shock testing is assumed to be 50 G s AF is the amplification factor Datasheet intel 4 3 4 4 Table 32 4 5 Insertion Specifications The processor may be inserted and removed 15 times from a 604 pin socket meeting the 604 Pin Socket Design Guidelines document Note that this specification is based on design characterization and is not tested Mass Specifications Table 32 specifies the processors mass This includes all components which make up the entire processor product Processor Mass Processor Mass grams The Low Voltage Intel Xeon processor
98. hese specifications This specification represents the minimum time the data or address may be valid after its strobe Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications The rising edge of ADSTB must come approximately 1 2 BCLK period 5 ns after the falling edge of ADSTB 10 For this timing parameter n 1 2 and 3 for the second third and last data strobes respectively 11 The second data strobe the falling edge of DSTBn must come approximately 1 4 BCLK period 2 5 ns after the first falling edge of DSTBp The third data strobe the falling edge of DSTBp must come approximately 2 4 BCLK period 5 ns after the first falling edge of DSTBp The last data strobe the falling edge of DSTBn must come approximately 3 4 BCLK period 7 5 ns after the first falling edge of DSTBp 12 This specification applies only to DSTBN 3 0 and is measured to the second falling edge of the strobe 13 This specification reflects a typical value not a minimum or maximum Table 16 Miscellaneous Signals AC Specifications T Parameter Min Max Unit Figure Notes T35 Async GTL input pulse width 2 N A BCLKs 1 2 3 T36 PWRGOOD to RESET de assertion time 1 10 ms 12 1 2 3 T37 PWRGOOD inactive pulse width 10 N A BCLKs 12 1 2 3 4 T38 PROCHOT pulse width 500 us 14 1 2 3 4 5 T39 THERMTRIP to Vcc Removal 0 5 S 15 NOTES 1
99. latform design guide refer to Section 1 3 Features Comparison for Low Voltage Intel Xeon Processors of L2 Front Side Intel Hyper Frequency supported Advanced Bus Threading Package Socket Systematic Transfer F eau ne T c nol Agent Cache gy 1 60 GHz 1 2 512 KB 400MHz Yes Pris 604 pin 2 0 GHz 1 2 512 400MHz Yes Prim 604 pin FC uPGA2 2 4 GHz 1 2 512 KB 533 MHz Yes 604 pins 604 pin Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the asserted state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 refers to a hex A and D 3 0 also refers to a hex A H High logic level L Low logic level System bus refers to the interface between the processor system core logic the chipset components and other bus agents The system bus is a multiprocessing interface to processors _ memory and I O For this document system bus is used as the generic term for the Intel Xeon processor scalable system bus Processor Packaging Terminology Commonly
100. lines for more information Measurements for Thermal Specifications Processor Case Temperature Measurement The maximum and minimum case temperature Tc Asp for the Intel Xeon processor is specified in Table 37 This temperature specification is meant to help ensure proper operation of the processor Figure 35 on page 91 illustrates where Intel recommends TCASE thermal measurements should be made Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Figure 35 Thermal Measurement Point for Processor 21 25 mm 837 inches Measure at this point geometric enter of IHS 21 25 mm 837 inches Thermal grease should cover entire area of IHS Low Voltage Intel Xeon Processor in FC uPGA2P package 31 mm x 31 mm IHS 42 5 mm x 42 5 substrate Notes Measure from edge of processor substrate Figure is not to scale and is for reference only B2486 01 NOTES 1 Measure from edge of processor substrate 2 Figure is not to scale and is for reference only Datasheet 91 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz This page intentionally left blank 92 Datasheet intel 7 0 Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Features 7 1 Table 38 7 2 7 2 1 7 2 2 Datasheet Power On Configuration Options The Low Voltage Intel Xeon processor has sever
101. lowed for a given overshoot undershoot magnitude at a specific activity factor Each table entry is independent of all others meaning that the pulse duration reflects the existence of overshoot undershoot events of that magnitude ONLY A platform with an overshoot undershoot that just meets the pulse duration for a specific magnitude where the AF 1 means that there may be no other overshoot undershoot events even of lesser magnitude note that when AF 1 the event occurs at all times and no other events may occur Datasheet 3 3 5 3 3 6 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz The following three notes apply to the activity factor 1 Activity factor for common clock signals is referenced to BCLK 1 0 frequency 2 Activity factor for source synchronous 2x signals is referenced to ADSTB 1 0 3 Activity factor for source synchronous 4x signals is referenced to DSTBP 3 0 and DSTBN 3 0 Reading Overshoot Undershoot Specification Tables The processor overshoot undershoot specification is not a simple single value Instead many factors are needed to determine what the overshoot undershoot specification is In addition to the magnitude of the overshoot the following parameters must also be known the width of the overshoot and the activity factor AF To determine the allowed overshoot for a particular overshoot event the following must be done 1 Determine the signal gr
102. mal solution components enabled for the Low Voltage Intel Xeon processor Heatsinks and retention mechanisms have been designed with manufacturability as a high priority Hence mechanical assembly may be completed from the top of the baseboard The Low Voltage Intel Xeon processor uses a scalable system bus protocol referred to as the system bus in this document The processor system bus utilizes a split transaction deferred reply protocol similar to that introduced by the Intel Pentium Pro processor system bus but is not Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 1 1 1 1 1 1 10 intel compatible with the Pentium Pro processor system bus The system bus uses Source Synchronous Transfer SST of address and data to improve performance and transfers data four times per bus clock 4X data transfer rate Along with the 4X data bus the address bus may deliver addresses two times per bus clock and is referred to as a double clocked or 2X address bus In addition the Request Phase completes in one clock cycle Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3 2 4 3 Gigabytes per second Finally the system bus also introduces transactions that are used to deliver interrupts For a list of features for each processor see Table 1 below Signals on the system bus use Assisted AGTL level voltages which are fully described in the appropriate p
103. mum Ratings Symbol Parameter Min Max Unit Notes TstoraGe Processor storage temperature 40 85 C 2 Any processor supply voltage with respect to Vss os 175 id L AGTL buffer DC input voltage with respect to Vss O 175 Async GTL buffer DC input voltage with respect to Vss TU VID pin current 5 mA NOTES 1 This rating applies to any pin of the processor 2 Contact Intel for storage requirements in excess of one year 21 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz lal amp 2 11 22 Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless noted otherwise See Section 5 1 for the processor pin listings and Section 5 2 for the signal definitions The voltage and current specifications for all versions of the processor are detailed in Table 7 For platform planning refer to Figure 3 Notice that the graphs include Thermal Design Power TDP associated with the maximum current levels The DC specifications for the AGTL signals are listed in Table 9 The system bus clock signal group is detailed in Table 7 The DC specifications for these signal group is listed in Table 10 Table 7 through Table 12 list the processor DC specifications and are valid only while meeting specifications for case temperature Tc agg as specified in Chapter 6 0 clock fr
104. nabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 to 50 percent Frequently clocks will not be off for more than 3 0 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be ca
105. nation resistor values For more details on platform design see the appropriate platform design guidelines Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF Table 12 lists the GTLREF specifications The AGTL reference voltage GTLREF should be generated on the baseboard using high precision voltage divider circuits It is important that the baseboard impedance is held to the specified tolerance and that the intrinsic trace capacitance for the AGTL signal group traces is known and well controlled For more details on platform design see the appropriate platform design guidelines AGTL Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes GTLREF Bus Reference Voltage 0 63 Voc 2 0 63 Voc 0 63 Voc 2 V 1 2 5 Termination Resistance 45 50 55 Q 3 7 COMP 1 0 COMP Resistance 49 55 50 50 45 Q 4 6 7 NOTES 1 The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of 2 is generated from Vcc on the baseboard by a voltage divider of 1 percent resistors Refer to the appropriate platform design guidelines for implementation details 3 Rrr is the on die termination resistance measured from Vcc 1 3 at the AGTL output driver Refer to the Low Voltage Inte Xeon Processor Cache Signal Integrit
106. nga iuran 94 Tables 1 Features Comparison for Low Voltage Intel Xeon 10 2 Front Side Bus to Core Frequency Ratio 14 3 System Bus Clock Frequency Select Truth Table for 1 0 15 4 Voltage Identification Definition srs nennen nnnm en nnns 18 5 System Bus Signal Groups iore ni ship 20 6 Processor Absolute Maximum Ratings seen nennen nnne nnns 21 7 Voltage and Current Specifications 23 8 System Bus Differential BCLK 24 9 AGTL Signal Group DC ener 25 10 and PWRGOOD Signal Group DC 26 11 Asynchronous GTL Signal Group DC Specifications essen 26 12 AGTL Bus Voltage Definitions eintreten eren nennen nnne 27 13 System Bus Differential Clock Specifications essseeeeneeennnnn 28 14 System Bus Common Clock AC 29 15 System Bus Source Synchronous AC Specifications s
107. nitoring processor performance BPM 5 0 should connect the appropriate pins of all system bus agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents These signals do not have on die termination and must be terminated at the end agent See the appropriate platform design guidelines for additional information BPRI BPRI Bus Priority Request is used to arbitrate for ownership of the processor system bus It must connect the appropriate pins of all processor system bus agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 36 Signal Definitions Sheet 3 of 9 Name Type Description BRO BR 1 3 yo BR 3 0 Bus Request drive the BREQ 3 0 signals in the system The BREQ S 0 signals are interconnected in a rotating manner to individual processor pins BR2 and BR3 must
108. not be utilized in a dual processor platform design The table below gives the rotating interconnect between the processor and bus signals for dual processor systems BR 1 0 Signals Rotating Interconnect dual processor system Bus Signal Agent 0 Pins Agent 1 Pins BREQO BRO BR1 BREQ1 BR1 BRO During power up configuration the central agent must assert the BRO bus signal All symmetric agents sample their BR 1 0 pins on active to inactive transition of RESET The pin on which the agent samples an active level determines its agent ID All agents then configure their pins to match the appropriate bus signal protoco as shown below BR 1 0 Signal Agent IDs BR 1 0 Signals Rotating Interconnect dual processor system BRO 0 BR1 1 Agent ID During power on configuration the central agent must assert the BRO bus signal All symmetric agents sample their BR 3 0 pins on the active to inactive transition of RESET The pin which the agent samples asserted determines it s agent ID These signals do not have on die termination and must be terminated at the end agent See the appropriate platform design guidelines for additional information BSEL 1 0 These output signals are used to select the system bus frequency A BSEL 1 0 00 will select a 100 MHz bus clock frequency The frequency is determined by the processor s chipset and frequency synthesizer capabiliti
109. nufacturing The stored value sets the highest bus fraction at which the particular processor may operate Clock multiplying within the processor is provided by the internal PLL which requires a constant frequency BCLK 1 0 input with exceptions for spread spectrum clocking Processor DC and AC specifications for the BCLK 1 0 inputs are provided in Table 7 and Table 12 respectively These specifications must be met while also meeting signal integrity requirements as outlined in Chapter 3 0 The processor utilizes a differential clock Details regarding BCLK 1 0 driver specifications are provided in the CK00 Clock Synthesizer Driver Design Guidelines Table 1 contains the supported bus fraction ratios and their corresponding core frequencies Front Side Bus to Core Frequency Ratio x nda EM Front Side Bus Frequency Core Frequency 1 16 100 MHz 1 60 GHz 1 18 133 MHz 2 40 GHz 1 20 100 MHz 2 0 GHz Datasheet intel 2 4 1 Table 3 2 5 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Bus Clock The system bus frequency is set to the maximum supported by the individual processor BSEL 1 0 are outputs used to select the system bus frequency Table 3 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processor s chipset and clock synthesizer All system bus agents must operate at the
110. obes and DSTBN DSTBP DBI Data Group 0 15 0 0 0 0131 16 1 1 D 47 32 2 2 0163 48 3 3 Furthermore the DBI pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 DBI 3 0 are source synchronous indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted The bus agent will invert the data bus signals when more than half the bits within a 16 bit group change logic level in the next cycle DBI 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DBIO D 15 0 DBI1 D 31 16 DBI2 D 47 32 DBI3 amp 0163 48 DBSY DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor system bus agents DEFER DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the appropriate pins of all processor system bus agents DP 3
111. ocessor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 35 Pin Listing by Pin Number Table 35 Pin Listing by Pin Number Pin No Pin Name Direction Pin No Pin Name utter Typ o Direction AB23 09 Source Sync Input Output AC28 Reserved Reserved Reserved AB24 VCC Power Other AC29 Reserved Reserved Reserved AB25 D8 Source Sync Input Output AC30 VSS Power Other AB26 D7 Source Sync Input Output AC31 VCC Power Other AB27 VSS Power Other AD1 Reserved Reserved Reserved AB28 Reserved Reserved Reserved AD2 VCC Power Other AB29 Reserved Reserved Reserved AD3 VSS Power Other AB30 VCC Power Other AD4 VCCIOPLL Power Other Input 1 VSS Power Other AD5 TESTHI5 Power Other Input AC1 Reserved Reserved Reserved AD6 VCC Power Other AC2 VSS Power Other AD7 D57 Source Sync Input Output AC3 VCC Power Other AD8 D46 Source Sync Input Output AC4 VCC Power Other AD9 VSS Power Other AC5 D60 Source Sync Input Output AD10 D45 Source Sync Input Output AC6 D59 Source Sync Input Output AD11 D40 Source Sync Input Output AC7 VSS Power Other AD12 VCC Power Other AC8 D56 Source Sync Input Output AD13 D38 Source Sync Input Output AC9 D47 Source Sync Input Output AD14 D39 Sourc
112. of processors to recognize bus transactions during the Sleep state multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the other processor in the Normal or Stop Grant state Normal State State 1 This is the normal operating state for the processor AutoHALT Powerdown State State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction The processor may transition to the Normal state upon the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or an interrupt delivered over the system bus RESET may cause the processor to immediately initialize itself 93 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz In lal The return from a System Management Interrupt SMI handler may be to either Normal Mode or the AutoHALT Power Down state See the Intel Architecture Software Developer s Manual Volume IIT System Programmer s Guide for more information The system may generate a STPCLK while the processor is in the AutoHALT Power Down state When the system deasserts the STPCLK interrupt the processor may return execution to the HALT state Figure 36 Stop Clock State Machine 7 2 3 94 HALT Instruction and HALT Bus Cycle Generated 2 Auto HALT Power Down State INIT BINIT INTR NMI 1 Normal State BCLK running 5 RESET gt
113. oup that particular signal falls into For AGTL signals operating in the 4X source synchronous domain Table 22 should be used For AGTL signals operating in the 2X source synchronous domain Table 23 should be used When the signal is an signal operating in the common clock domain Table 24 should be used Finally for all other signals residing in the 33 MHz domain asynchronous GTL TAP etc Table 25 should be used 2 Determine the magnitude of the overshoot or the undershoot relative to Vg Determine the activity factor how often does this overshoot occurs 4 Next from the appropriate specification table determine the maximum pulse duration in nanoseconds allowed 5 Compare the specified maximum pulse duration to the signal being measured When the pulse duration measured is less than the pulse duration shown in the table the signal meets the specifications Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive Determining When a System Meets the Overshoot Undershoot Specifications The overshoot undershoot specifications listed in the following tables specify the allowable overshoot undershoot for a single overshoot undershoot event However most systems may have multiple overshoot and or undershoot events that each have their own set of parameters duration AF and magnitude While each overshoot on its own may meet the overshoot specification when the total impa
114. ower Other J1 VSS Power Other L3 VSS Power Other J2 VCC Power Other L4 VCC Power Other J3 VSS Power Other L5 VSS Power Other J4 VCC Power Other L6 VCC Power Other J5 VSS Power Other L7 VSS Power Other J6 VCC Power Other L8 VCC Power Other J7 VSS Power Other L9 VSS Power Other J8 VCC Power Other L23 VSS Power Other J9 VSS Power Other L24 VCC Power Other J23 VSS Power Other L25 VSS Power Other J24 VCC Power Other L26 VCC Power Other J25 VSS Power Other L27 VSS Power Other J26 VCC Power Other L28 VCC Power Other J27 VSS Power Other L29 VSS Power Other J28 VCC Power Other L30 VCC Power Other J29 VSS Power Other L31 VSS Power Other J30 VCC Power Other M1 VCC Power Other Datasheet 73 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 35 Pin Listing by Pin Number intel Table 35 Pin Listing by Pin Number Signal Signal Pin No Pin Name Buffer Type Direction Pin No Pin Name Buffer Type Direction M2 VSS Power Other P4 VCC Power Other M3 VCC Power Other P5 VSS Power Other M4 VSS Power Other P6 VCC Power Other M5 VCC Power Other P7 VSS Power Other M6 VSS Power Other P8 VCC Power Other M7 VCC Power Other P9 VSS Power Other M8 VSS Power Other P23 VSS Power Other M9 VCC Power Other P24 VCC Power Other M23 VCC Power Other P25 VSS Power Other M24 VSS Power Other P26
115. pable of cooling the processor even when the TCC is active continuously Refer to the Intel Xeon Processor Thermal Design Guidelines for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Thermal Diode The processor incorporates an on die thermal diode A thermal sensor located on the processor may be used to monitor the die temperature of the processor for thermal management long term die temperature change purposes This thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Thermal Diode The Low Voltage Intel Xeon processor incorporates an on die thermal diode A thermal sensor located on the baseboard may monitor the die temperature of the processor for thermal management long term die temperature change purposes Table 39 and Table 40 provide the diode parameter and interface specifications This thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor Table 39 Thermal Diode Parameters Symbol Parameter Min Typ Max Unit Notes PM icu 5 300 UA 1 n
116. pport signal used by debug tools TMS This signal does not have on die termination and must be terminated at the end agent See the appropriate platform design guidelines for additional information TRDY Target Ready is asserted by the target to indicate that it is ready to receive TRDY a write or implicit writeback data transfer TRDY must connect the appropriate pins of all system bus agents TRST Test Reset resets the Test Access Port TAP logic TRST must be driven TRST low during power on Reset See the appropriate Platform Design Guideline for additional information VCCA provides isolated power for the analog portion of the internal PLL s Use a discrete RLC filter to provide clean power Use the filter defined in Section 2 5 to Veca provide clean power to the PLL The tolerance and total ESR for the filter is important Refer to the appropriate platform design guidelines for complete implementation details provides isolated power for digital portion of the internal PLL s Follow the VccioPLL guidelines for Veca Section 25 and refer to the appropriate platform design guidelines for complete implementation details The Vccsense and Vsssense pins are the points for which processor minimum and maximum voltage requirements are specified Uniprocessor designs may utilize these pins for voltage sensing for the processor s voltage regulator However VsssENSE multiprocessor designs must not connect
117. pts presented in the following documents Document Intel Order Number AP 485 Inte Processor Identification and the CPUID Instruction 241618 1 32 Intel Architecture Software Developer s Manual Volume I Basic Architecture 245470 Volume Il Instruction Set Reference 245471 Volume System Programming Guide 245472 Low Voltage Inte Xeon Processor Thermal Design Guide 273764 604 Pin Socket Design Guidelines Inte Xeon Processor Specification Update 249678 Inte Xeon Processor with 512 KB L2 Cache and Inte E7500 Chipset 298649 Platform Design Guide Inte Xeon Processor with 512 KB L2 cache and Intel 9 E7500 E7501 273707 Chipset Platform Design Guide Addendum for Embedded Applications CKO00 Clock Synthesizer Driver Design Guidelines 249206 VRM 9 0 DC DC Converter Design Guidelines 249205 VRM 9 1 DC DC Converter Design Guidelines 298646 Dual Inte Xeon Processor Voltage Regulator Down VRD Design Hali 298644 Guidelines ITP700 Debug Port Design Guide 249679 Inte Xeon Processor with 512 KB L2 Cache System Compatibility 298645 Guidelines NOTES 1 Contact your Intel representative for the latest revision of documents without order numbers 2 The signal integrity models are in IBIS format 11 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz 12 intel Document Intel Order Number Low Voltage Inte Xeon Processor
118. put Output A7 A33 Source Sync Input Output A8 VCC Power Other A9 A26 Source Sync Input Output A10 A20 Source Sync Input Output A11 VSS Power Other A12 A14 Source Sync Input Output A13 A10 Source Sync Input Output A14 VCC Power Other A15 Reserved Reserved Reserved A16 Reserved Reserved Reserved A17 LOCK n Input Output A18 VCC Power Other A19 A7 Source Sync Input Output A20 A4 Source Sync Input Output A21 VSS Power Other A22 A3 Source Sync Input Output A23 HITM an Input Output A24 VCC Power Other A25 TMS TAP Input A26 Reserved Reserved Reserved A27 VSS Power Other A28 VCC Power Other A29 VSS Power Other A30 VCC Power Other A31 VSS Power Other B1 Reserved Reserved Reserved B2 VSS Power Other B3 VIDA Power Other Output 70 Pin No Pin Name Butler Typs Direction B4 VCC Power Other B5 OTDEN Power Other Input B6 VCC Power Other B7 A31 Source Sync Input Output B8 A27 Source Sync Input Output B9 VSS Power Other B10 A211 Source Sync Input Output B11 A22 Source Sync Input Output B12 VCC Power Other B13 A13 Source Sync Input Output B14 12 Source Sync Input Output B15 VSS Power Other B16 A113 Source Sync Input Output B17 VSS Power Other B18 Ab Source Sync Input Output B19 REQO uo Input Output B20 VCC Power Other B21 REQ1 M Input Output B22 REQ4 rn Input Output B23 VSS Power Other B24 LINTO Async GTL Input B25 PROCHOT Power Other Input Output
119. put current is based on maximum current handling capability of the buffer and is not specified into the test load 8 VoL max Of 0 450 V is ensured when driving into a test load as indicated in Figure 4 with enabled 9 Leakage to Vcc with Pin held at 300 mV 10 Leakage to Vss with pin held at 26 Datasheet intel 2 12 Table 12 2 13 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz AGTL System Bus Specifications Routing topologies are dependent on the number of processors supported and the chipset used in the design Please refer to the appropriate platform design guidelines In most cases termination resistors are not required as these are integrated into the processor See Table 5 for details on which AGTL signals do not include on die termination The termination resistors are enabled or disabled through the ODTEN pin To enable termination this pin should be pulled up to through a resistor and to disable termination this pin should be pulled down to V ss through a resistor For optimum noise margin all pull up and pull down resistor values used for the ODTEN pin should have a resistance value within 20 percent of the impedance of the baseboard transmission line traces For example when the trace impedance is 50 W then a value between 40 and 60 W should be used The processor s on die termination must be enabled for the end agent only Please refer to Table 12 for termi
120. r Clocking eese 14 ZAN BUS COCK m 15 25 EE 15 2 5 1 Mixing Processors EEA 17 2 6 Voltage Identification 17 2 6 1 Mixing Processors of Different 18 2 7 Reserved Or Unused Pins aee cinta eco rad Dan euet dg Ua dE eai pe eed 19 2 8 System Bus Signal nnnm nnn en nnn rennen 19 29 Asynchronous GQTLs tee dee 21 2 10 Maximum Ratings ceci eem t ecd a E RBS 21 2 11 Processor DC 22 2 12 AGTL System Bus Specifications eene nenne rne 27 2 13 System Bus AC Specifications nnnm nnn 27 2 14 Processor AC Timing 31 3 0 System Bus Signal Quality 39 3 1 System Bus Clock BCLK Signal Quality Specifications and Measurement Guidelines seeeeneeene 39 3 2 System Bus Signal Quality Specifications and Measurement Guidelines eese nennen nnne nre nnns 40 3 8 System Bus Signal Quality Sp
121. r Other VSS D28 Power Other VSS J9 Power Other VSS D30 Power Other VSS J23 Power Other Datasheet 67 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 34 Pin Listing by Pin Name intel Table 34 Pin Listing by Pin Name Pin Name Pin No Direction Pin Name Pin No Bae Direction VSS J25 Power Other VSS N30 Power Other VSS J27 Power Other VSS P1 Power Other VSS J29 Power Other VSS P3 Power Other VSS J31 Power Other VSS P5 Power Other VSS K2 Power Other VSS P7 Power Other VSS K4 Power Other VSS P9 Power Other VSS K6 Power Other VSS P23 Power Other VSS K8 Power Other VSS P25 Power Other VSS K24 Power Other VSS P27 Power Other VSS K26 Power Other VSS P29 Power Other VSS K28 Power Other VSS P31 Power Other VSS K30 Power Other VSS R2 Power Other VSS L1 Power Other VSS R4 Power Other VSS L3 Power Other VSS R6 Power Other VSS L5 Power Other VSS R8 Power Other VSS L7 Power Other VSS R24 Power Other VSS L9 Power Other VSS R26 Power Other VSS L23 Power Other VSS R28 Power Other VSS L25 Power Other VSS R30 Power Other VSS L27 Power Other VSS T1 Power Other VSS L29 Power Other VSS T3 Power Other VSS L31 Power Other VSS T5 Power Other VSS M2 Power Other VSS T7 Power Other VSS M4 Power Other VSS T9 Power Other VSS M6 Power Other VSS T23 Power Other VSS M8 Power Other VSS T2
122. re frequency ratio specifications for 2 4 GHz Added processor thermal design power specifications fo September 2003 004 CHE rp Added Overshoot undershoot specification for 2 4 GHz Added Table 1 and Figure 7 Updated Tables 2 3 7 8 13 14 15 17 and 37 and Figure 11 Added and lec voltage and current specifications for 2 0 GHz Added system bus to core frequency ratio specifications April 2003 003 for 2 0 GHz Added processor thermal design power specifications for 2 0 GHz Changed the PROCHOT signal type Redefi AE2 AE29 pins November 2002 002 Added VID Voc Voltage and current specifications September 2002 001 Initial release of this document Contents n Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz tel 8 Datasheet intel 1 0 Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Introduction Datasheet The Low Voltage Intel Xeon processor is based on the Intel NetBurst micro architecture which operates at significantly higher clock speeds and delivers performance levels that are significantly higher than previous generations of IA 32 processors While based on the Intel NetBurst micro architecture it maintains the tradition of compatibility with IA 32 software The Intel NetBurst micro architecture features begin with innovative techniques that enhance processor execution such as Hyper Pipelined Technology a Rapid Execution Engine Advanced
123. rshoot Undershoot Tolerance 49 533 MHz Asynchronous GTL PWRGOOD and TAP Signal Groups Overshoot Undershoot Tol erance49 Dimensions for the Low Voltage Intel Xeon Processor inthe 2 iiie te n e ee Uu e Ee a E LE AD LE uu te Aa 54 Package Dynamic and Static Load Specifications 56 MOI Tar 57 Processor Material Properties eee teret 57 Pini Listing by Pin censos aT ai 61 Pin Listing by Pin d M 70 79 Processor Thermal Design 90 Power On Configuration Option Pins 93 Thermal Diode Parameters 97 Thermal Diode Mna beau rt det vba tu 97 Datasheet intel Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Revision History Datasheet Contents Date Revision Description September 2003 005 Updated Figure 3 Low Voltage and Current Projections in a Dual Processor Configuration Added Vcc and lcc voltage and current specificaitons for 2 4 GHz Added system bus to co
124. s are referenced at GTLREF at the processor core pads 2 All source synchronous AC timings for AGTL signals are referenced to their associated strobe address or data at GTLREF Source synchronous data signals are referenced to the Datasheet 31 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz lal amp Figure 4 Figure 5 32 falling edge of their associated data strobe Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe All source synchronous AGTL signal timings are referenced at GTLREF at the processor core pads 3 All AC timings for AGTL strobe signals are referenced to BCLK 1 0 at Vcgoss All AGTL strobe signal timings are referenced at GTLREF at the processor core pads 4 All AC Timing for he TAP signals are referenced to the signal at 0 5 at the processor pins All TAP signal timings TMS TDI etc are referenced at the 0 5 at the processor core pads Electrical Test Circuit Vtt Vtt Zo 50 ohms d 420mils So 169ps in Rload 50 ohms E AC Timings gt specified at pad TCK Clock Waveform CLK T 56 T58 Rise Time T T57 T59 Fall Time T 155 Period p V1 V2 For rise and fall times is measured between 20 to 80 points on the waveform is referenced to 0 5 Vcc Datasheet Low Voltage Inte Xeon Proces
125. s the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor heatsink When this is the case the logic analyzer vendor may provide a cooling solution as part of the LAI Electrical Considerations The LAI may also affect the electrical performance of the system bus therefore it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool may work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide 99 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz This page intentionally left blank 100 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Appendix A 9 1 Datasheet Processor Core Frequency Determination To allow system debug and multiprocessor configuration flexibility the core frequency of the processor may be configured using an MSR Clock multiplying within the processor is provided by the internal Ph
126. same frequency Individual processors may only operate at their specified system bus clock frequency Baseboards designed for the Intel Xeon processor employ a 100 133 MHz system bus clock On these baseboards BSEL 1 0 are considered reserved at the processor socket System Bus Clock Frequency Select Truth Table for BSEL 1 0 BSEL1 BSELO Bus Clock Frequency L L 100 MHz L H 133 MHz H L Reserved H H Reserved PLL Filter Veca and are power sources required by the processor PLL clock generator This requirement is identical to that of the Intel Xeon processor Since these PLLs are analog in nature they require quiet power supplies for minimum jitter Jitter is detrimental to the system it degrades external I O timings as well as internal core timings i e maximum frequency To prevent this degradation these supplies must be low pass filtered from A typical filter topology is shown in Figure 1 The AC low pass requirements with input at and output measured across the capacitor C4 or Cio in Figure 1 is as follows 02 dB gain in pass band e 0 5 dB attenuation in pass band lt 1 Hz see DC drop in next set of requirements gt 34 dB attenuation from 1 MHz to 66 MHz 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 2 For recommendations on implementing the filter refer to the appropriate platform design
127. so known as the Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support 6 0 All TESTHI 6 0 pins should be individually connected to via a pull up resistor which matches the trace impedance within a range of 10 ohms TESTHI 3 0 and TESTHI 6 5 may all be tied together and pulled up to Vcc with a single resistor when desired However utilization of boundary scan test will not be functional when these pins are connected together TESTHI4 must always be pulled up independently from the other TESTHI pins For optimum noise margin all pull up resistor values used for TESTHI 6 0 pins should have a resistance value within 20 percent of the impedance of the baseboard transmission line traces For example when the trace impedance is 50 Q then a value between 40 Q and 60 Q should be used The TESTHI 6 0 termination recommendations provided in the Intel Xeon processor datasheet are still suitable for the Intel Xeon processor with 512 KB L2 cache However Intel recommends new designs or designs undergoing design updates follow the trace impedance matching termination guidelines given in this section THERMDA Thermal Diode Anode THERMDC Thermal Diod
128. sor at 1 60 GHz 2 0 GHz and 2 4 GHz Figure 6 Differential Clock Waveform Tph Overshoot Rising Edge s Mo tar ON SEREGET Ringback Crossing Crossing Ringback Threshold Voltage Voltage j Margin Region 2 m mM IESU Falling Edge SS ME Sy esis es aay Ringback BCLKO _ VL MEE D rw as BNW poe hs Undershoot Tp T1 BCLK 1 0 period T2 BCLK 1 0 Period stability not shown Tph T3 BCLK 1 0 pulse high time Tpl T4 BCLK 1 0 pulse low time T5 BCLK 1 0 rise time through the threshold region T6 BCLK 1 0 fall time through the threshold region Figure 7 Differential Clock Crosspoint Specification A 550 0 5 710 250 0 5 710 200 amp 2 o amp D 50 mo 4D 40 50 30 25 20 68D 670 680 EBD 70 710 720 730 740 750 W 770 780 W AD BIO 820 BD EED Vhavg mV Datasheet 33 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Figure 8 System Bus Common Clock Valid Delay Timing Waveform TO T1 BCLK1 BCLKO Common Clock Signal driver Common Clock Signal receiver T T10 Common Clock Output Valid Delay T11 Common Clock Input Setup Tp T12 Common Clock Input Hold Time T2 Figure 9 System Bus Source Synchronous 2X Address Timing Waveform
129. sors the Low Voltage Intel Xeon processor does not sample the pins IGNNE LINT O INTR LINT 1 NMI and A20M to establish the core to system bus ratio Rather the processor runs at its tested frequency at initial power on When the processor needs to run at a lower core frequency as must be done when a higher speed processor is added to a system that contains a lower frequency processor the system BIOS is able to effect the change in the core to system bus ratio Voltage Identification The VID specification for the processor is defined in this datasheet and is supported by power delivery solutions designed according to the Dual Intel Xeon Processor Voltage Regulator Down VRD Design Guidelines VRM 9 0 DC DC Converter Design Guidelines and VRM 9 1 DC DC Converter Design Guidelines The minimum voltage is provided in Table 7 and varies with processor frequency This allows processors running at a higher frequency to have a relaxed minimum voltage specification The specifications have been set such that one voltage regulator design may work with all supported processor frequencies Note that the VID pins may drive valid and correct logic levels when the Intel Xeon processor is provided with a valid voltage applied to the VID Vcc pins VID V cc must be correct and stable prior to enabling the output of the that supplies V Similarly the output of the must be disabled before VID becomes invalid Refer to Figur
130. ss 29 Datasheet 5 Contents n Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz tel 24 25 26 27 28 29 30 Miscellaneous Signals AC 30 System Bus AC Specifications Reset Conditions sse 31 TAP Signal Group AC Specifications nennen nnnm 31 BCLK Signal Quality enne 39 Ringback Specifications for AGTL and Asynchronous GTL Buffers 40 Ringback Specifications for TAP eene enne 41 Source Synchronous 400 MHz AGTL Signal Group Overshoot Undershoot Tolerance 46 Source Synchronous 400 MHz AGTL Signal Group Overshoot Undershoot Tolerance 46 Common Clock 400 MHz AGTL Signal Group Overshoot Undershoot Tolerance sse nnne 47 400 MHz Asynchronous GTL PWRGOOD and TAP Signal Groups Overshoot Undershoot Tolerance 47 Source Synchronous 533 MHz AGTL Signal Group Overshoot Undershoot Tolerance 48 Source Synchronous 533 MHz AGTL Signal Group Overshoot Undershoot Tolerance 48 Common Clock 533 MHz AGTL Signal Group Ove
131. ssary for designing a thermal solution for the Low Voltage Intel Xeon processor Thermal solutions should include heatsinks that apply pressure to the integrated low voltage heat spreader IHS The IHS provides a common interface intended to be compatible with many heatsink designs Thermal specifications are based on the temperature of the IHS top referred to as the case temperature or Tease Thermal solutions should be designed to maintain the processor within Tcasg specifications For information on performing Tcasz measurements refer to the Intel Xeon Processor Thermal Design Guidelines See Figure 34 for an exploded view of the processor package and thermal solution assembly Figure 34 Processor with Thermal and Mechanical Components Exploded View Note 6 1 Datasheet Heat sink clip Heat sink EMI ground frame Retention mechanism This is a graphical representation For specifications see each component s respective documentation listed in Section 1 3 Thermal Specifications To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed such that the processor remains between the minimum and maximum case temperature TC specifications when operating at or below the 89 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz In lal 37 6 2 6 2 1 90 Th
132. these pins to sense logic but rather utilize them for power delivery validation VccsENSE VID 4 0 Voltage ID pins may be used to support automatic selection of power supply voltages Vcc Unlike previous processor generations these pins are driven by processor logic Hence the voltage supply for these pins VID Voc must be VID 4 0 valid before the VRM supplying Vcc to the processor is enabled Conversely the VRM output must be disabled prior to the voltage supply for these pins becomes invalid The VID pins are needed to support processor voltage specification variations See Table 4 for definitions of these pins The power supply must supply the voltage that is requested by these pins or disable itself VID Vcc Voltage for VID and BSEL logic Vssa provides an isolated internal ground for internal PLL s Do not connect VssA directly to ground This pin is to be connected to Veca and Vcciop through a discrete filter circuit Note Low Voltage Intel Xeon processors only support BRO and BR1 However the Low Voltage Intel Xeon processors must terminate BR2 and BR3 to the processor Datasheet 87 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz This page intentionally left blank 88 Datasheet intel 6 0 Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Thermal Specifications This chapter provides the thermal specifications nece
133. to power or ground a resistor may also allow for system testability For unused AGTL input or I O signals use pull up resistors of the same value for the on die termination resistors Rrr See Table 12 TAP Asynchronous GTL inputs and Asynchronous GTL outputs do not include on die termination Inputs and all used outputs must be terminated on the baseboard Unused outputs may be terminated on the baseboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the 7P700 Debug Port Design Guide TESTHI 6 0 pins should be individually connected to through a pull up resistor which matches the trace impedance within 10 Q TESTHI 3 0 and TESTHI 6 5 may all be tied together and pulled up to with a single resistor when desired However utilization of the boundary scan test may not be functional when these pins are connected together TESTHI4 must always be pulled up independently from the other TESTHI pins For optimum noise margin all pull up resistor values used for TESTHI 6 0 pins should have a resistance value within 20 percent of the impedance of the baseboard transmission line traces For example when the trace impedance is 50 W then a pull up resistor value between 40 and 60 W should be used The TESTHI 6 0 termination recommendations provided in the
134. tput AE8 VCC Power Other AE9 D44 Source Sync Input Output AE10 D42 Source Sync Input Output AE11 VSS Power Other AE12 DBI2 Source Sync Input Output AE13 D35 Source Sync Input Output AE14 VCC Power Other AE15 Reserved Reserved Reserved AE16 Reserved Reserved Reserved AE17 DP3 Input Output AE18 VCC Power Other AE19 DP1 Input Output AE20 D28 Source Sync Input Output AE21 VSS Power Other AE22 D27 Source Sync Input Output AE23 D22 Source Sync Input Output AE24 VCC Power Other AE25 D19 Source Sync Input Output AE26 D16 Source Sync Input Output AE27 VSS Power Other AE28 VID Power Other AE29 VID Voc Power Other AE30 e 78 In systems utilizing the Low Voltage Xeon processor the system designer must pull up these signals to the processor Voc Baseboards treating AA3 and AB3 as Reserved may operate correctly with a bus clock of 100 MHz processor with CPUID of OF27h Itis an output only on 1 6 GHz Low Voltage Intel Xeon Datasheet Intel Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz 5 2 Signal Definitions Table 36 Signal Definitions Sheet 1 of 9 Name Type Description A 35 3 y o A 35 3 Address define a 236 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals m
135. ultiple low power states Advanced System Management Features Thermal Monitor Machine Check Architecture MCA The Low Voltage Intel Xeon processor at 1 6 Ghz and 2 0 Ghz with 400 Mhz system bus and 2 4 Ghz with 533 Mhz system bus are designed for high performance dual and single processor applications Based on the Intel NetBurst micro architecture and the new Hyper Threading Technology it is binary compatible with previous Intel Architecture 32 processors The Low Voltage Intel Xeon processor is scalable to two processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Windows XP Windows 2000 Linux and UNIX The Low Voltage Intel Xeon processor delivers compute power at unparalleled value and flexibility for embedded applications The Intel NetBurst micro architecture and Hyper Threading Technology deliver outstanding performance and headroom for embedded applications resulting in faster response times support for more users and improved scalability Order Number 273766 005 September 2003 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRO
136. used terms are explained here for clarification 604 pin socket The 604 pin socket contains an additional contact to accept the additional keying pin on the Low Voltage Intel Xeon processor in the FC uPGA2 packages at pin location AE30 The 604 pin socket may also accept processors with the INT mPGA package Since the additional contact for pin AE30 is electrically inert the 604 pin socket may not have a solder ball at this location Therefore the additional keying pin may not require a baseboard via nor a surface mount pad See the 604 Pin Socket Design Guidelines for details regarding this socket Integrated Heat Spreader IHS The surface used to attach a heatsink or other thermal solution to the processor Datasheet 1 2 1 3 Datasheet Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz OEM Original Equipment Manufacturer Processor core The processor s execution engine All AC timing and signal integrity specifications are to the pads of the processor core Retention mechanism The support components that are mounted through the baseboard to the chassis to provide mechanical retention for the processor and heatsink assembly State of Data The data contained in this document is subject to change It is the best information that Intel is able to provide at the publication date of this document References The reader of this specification should also be familiar with material and conce
137. ust connect the appropriate pins of all agents on the system bus A 35 3 are protected by parity signals AP 1 0 A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 35 3 pins to determine their power on configuration See Section 7 1 A20M When A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting 20 emulates the 8086 processor s address wrap around at the 1 MByte boundary Assertion of A2Z0M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding write bus transaction ADS yo ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must connect the appropriate pins on all system bus agents 1 0 yo Address strobes are used to latch 35 3 and REQ 4 0 on their rising and falling edge 1 0
138. wer Other VCC T28 Power Other VCC AB2 Power Other VCC T30 Power Other VCC AB8 Power Other VCC U1 Power Other VCC AB14 Power Other VCC U3 Power Other VCC AB18 Power Other VCC U5 Power Other VCC AB24 Power Other VCC U7 Power Other VCC AB30 Power Other VCC U9 Power Other VCC AC3 Power Other VCC U23 Power Other VCC AC4 Power Other VCC U25 Power Other VCC AC10 Power Other VCC U27 Power Other VCC AC16 Power Other VCC U29 Power Other VCC AC22 Power Other VCC U31 Power Other VCC 1 Power Other VCC V2 Power Other VCC AD2 Power Other VCC V4 Power Other VCC AD6 Power Other VCC V6 Power Other VCC AD12 Power Other VCC V8 Power Other VCC AD20 Power Other VCC V24 Power Other VCC AD26 Power Other VCC V26 Power Other VCC AD30 Power Other VCC V28 Power Other VCC AE3 Power Other VCC V30 Power Other VCC AE8 Power Other VCC W1 Power Other VCC AE14 Power Other VCC W25 Power Other VCC AE18 Power Other VCC W27 Power Other VCC AE24 Power Other 66 Datasheet In Low Voltage Inte Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz Table 34 Pin Listing by Pin Name Table 34 Pin Listing by Pin Name Signal Signal Pin Name Pin No Buffer Type Direction Pin Name Pin No
139. x Unit Figure Notes1 2 8 T55 TCK Period 60 0 ns 5 T56 TCK Rise Time 9 5 ns 5 3 T57 TCK Fall Time 9 5 ns 5 3 T58 TMS TDI Rise Time 8 5 ns 8 59 TMS TDI Fall Time 8 5 ns 5 3 T61 TDI TMS Setup Time 0 ns 13 4 6 T62 TDI TMS Hold Time 3 0 ns 13 4 6 T63 TDO Clock to Output Delay 0 5 3 5 ns 13 5 T64 TRST Assert Time 2 0 14 NOTES 1 Not 100 tested Specified by design characterization 2 All AC timings for the TAP signals are referenced to the signal at 0 5 Vcc at the processor pins All TAP signal timings TMS TDI etc are referenced at the 0 5 Voc processor pins Rise and fall times are measured from the 20 to 80 points of the signal swing Referenced to the rising edge of TCK Referenced to the falling edge of TCK Specification for a minimum swing defined between TAP 20 to 80 This assumes a minimum edge rate of 0 5 V ns TRST must be held asserted for two TCK periods to ensure recognition by the processor Itis recommended that TMS be asserted while TRST is being deasserted oN 2 14 Processor AC Timing Waveforms The following figures are used in conjunction with the AC timing tables Table 12 through Table 18 Note For Figure 5 through Figure 14 the following apply 1 All common clock AC timings for AGTL signals are referenced to the Crossing Voltage of the BCLK 1 0 at rising edge of BCLKO All common clock signal timing
140. y Models for I V characteristics 4 COMP resistors are pull downs to Vgg provided on the baseboard with 1 tolerance See the appropriate platform design guidelines for implementation details 5 The Vec referred to in these specifications refers to instantaneous Vcc 6 The COMP resistance value varies by platform Refer to the appropriate platform design guideline for the recommended COMP resistance value 7 The values for and COMP noted as New Designs apply to designs that are optimized for the Intel Xeon processor Refer to the appropriate platform design guideline for the recommended COMP resistance value System Bus AC Specifications The processor system bus timings specified in this section are defined at the processor core pads See Section 5 0 for the pin listing and signal definitions Table 12 through Table 18 list the AC specifications associated with the processor system bus 27 Low Voltage Intel Xeon Processor at 1 60 GHz 2 0 GHz and 2 4 GHz 28 Intel All AGTL timings are referenced to GTLREF for both 0 and 1 logic levels unless otherwise specified The timings specified in this section should be used in conjunction with the signal integrity models provided by Intel These signal integrity models which include package information are available for the Intel Xeon processor in IBIS format AGTL layout guidelines are also available in the appropriate platform design guidelines Note

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