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Supermicro Xeon 2.8GHz

1. 2 0 8 000 4 10 39 3 5 Package Insertion 4 4 02 4 000000 39 3 6 Processor Mass 2 222 1 39 3 7 Processor Materials 39 28 Processor Markirigs iiie ete tetro epee donee eens nO ox re 40 3 9 Processor Pinout 41 Signal DST MIO NS ae site eee chided rariss eam 43 4 4 Signal Definitions ied uev EYE uan 43 6 OA E E 53 5 1 Low Voltage Intel Xeon Processor with 800 MHz System Bus Pin Assignments 53 5 1 1 Pin Listing by eroe ree eee ex xL 54 5 1 2 Pin Listing by Pin Number 62 Thermal Specifications ues eus 71 6 1 Package Thermal Specifications nnne 71 6 1 1 Thermal Specifications 71 Datasheet 3 7 0 8 0 6 1 2 Thermal Metrology eene tet Beet eet tend 74 6 2 Processor Thermal Features ccccccccssssssccececessseeececeanseseceeeaeeasceeececeasasseeseeaeauseseeeeeanees 74 6 2 1 Thermal iier tete ove er beet e eb arb et ee avere vore
2. Q3H21VH 5509 90 1104337 LNINOdNOD 1971 Xe 680 1H913H LNINOdNOD 318YMOTlV XYN 1272 Xe 37 Datasheet 3 2 3 3 Table 17 38 Intel Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements thermal and mechanical solution design must not intrude into the required keepout zones Decoupling capacitors are typically mounted to either the topside or pin side of the package substrate See Figure 7 for keepout zones Package Loading Specifications Table 17 provides dynamic and static load specifications for the processor package These mechanical load limits should not be exceeded during heat sink assembly mechanical stress testing or standard drop and shipping conditions The heat sink attach solutions must not include continuous stress onto the processor with the exception of a uniform load to maintain the heat sink to processor thermal interface Also any mechanical system or component testing should not exceed these limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal or mechanical solutions Processor Loading Specifications Parameter Min Max Unit Notes Static 44 222 N 1 2 3 4 Compressive Load 10 50 Ibf 44 288 N 1 2 3 5 10 65 Ibf Dynamic NA 222 0 45 kg 100 G N 1 3 4 6 7 Compressive L
3. 86 Datasheet intel Figures 1 Phase Lock Loop PLL Filter Requirements 15 2 Low Voltage Intel Xeon Processor with 800 MHz System Bus Load Current vs 10 0 M 27 3 VCC Static and Transient nennen nennen nenne 29 4 VCC Overshoot Example eene nennen nnne nennen 30 5 Processor Package Assembly 5 35 6 Processor Package Drawing Sheet 1 of 2 36 7 Processor Package Drawing Sheet 2 37 8 Processor Top Side Markings enne 40 9 Processor Bottom Side Markings 40 10 Processor Pinout Coordinates Top eene nnne 41 11 Processor Pinout Coordinates Bottom View nennen 42 12 Low Voltage Intel Xeon Processor with 800 MHz System Bus Thermal Profile 73 13 Case Temperature TCASE Measurement Location sse 74 14 Stop Clock State nnne 81 Datasheet 5 Tables 1 Features of the Low Voltage Intel Xeon Processor with 800 MHz System Bus 9 2 Frequency to Front Side Bus Multiplier Configuration 14 3 BSEL 1 0 Frequency Table
4. processor with 800 MHz system bus implement independent power planes for each system bus agent As a result the processor core voltage Vcc and system bus termination voltage must connect to separate supplies The processor core voltage uses power delivery guidelines denoted by VRM 10 0 and the associated load line see Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines for further details The Low Voltage Intel Xeon processor with 800 MHz system bus uses a scalable system bus protocol referred to as the system bus in this document The system bus uses a split transaction deferred reply protocol The system bus uses Source Synchronous Transfer SST of address and data to improve performance The processor transfers data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or the 2X address bus In addition the Request Phase completes in one clock cycle Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 6 4 GBytes second 6400 MBytes second Finally the system bus is also used to deliver interrupts The Low Voltage Intel Xeon processor with 800 MHz system bus also includes the Execute Disable Bit capability previously available in Itanium processors This feature combined with a supported op
5. TDI TEST BUS TESTHI 6 0 THERMDA THERMDC THERMTRIP TMS TRDY TRST VID 5 0 VIDPWRGD VTTEN Open Drain Signals 5 0 BRO BSEL 1 0 FERR PBE IERR THERMTRIP VID 5 0 NOTES 1 Signals that do not have nor are actively driven to their high voltage level 2 The termination for these signals is not The OPTIMIZED COMPAT and BOOT SELECT pins have 500 5000 pull up to Signal Reference Voltages GTLREF 0 5 Vir A20M A 35 3 ADS ADSTB 1 0 1 0 BINIT BNR 5 0 BPRI BR 3 0 D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 8 0 DSTBP 3 0 FORCEPR HIT HITM IGNNE INIT LINTO INTR LINT1 NMI LOCK MCERR ODTEN RESET 4 0 RS 2 0 RSP SLEW_CTRL SLP SMI STPCLK TRDY BOOT_SELECT OPTIMIZED COMPAT PWURGOOD TCK TMS TRST VIDPWRGD NOTES 1 These signals also have hysteresis added to the reference voltage See Table 14 for more information 21 2 7 2 8 2 9 22 intel GTL Asynchronous and AGTL Asynchronous Signals The Low Voltage Intel Xeon processor with 800 MHz system bus does not use CMOS voltage levels on any signals that connect to the processor silicon As a result input signals such as A20M FORCEPR IGNNE INIT LINTO INTR LINT1 NMI SMI SLP and STPCLK use GIL input buffers Legac
6. 39 20 SiGMal BI Tio C 43 21 BE Sieben 54 22 Listing by Pin Nu mbor 62 23 Low Voltage Intel Xeon Processor with 800 MHz System Bus Thermal Specifications 72 24 Low Voltage Intel Xeon Processor with 800 MHz System Bus Thermal Profile 73 25 Thermal Diode 76 26 Thermal Diode 2 2 21 1 0 77 27 Power On Configuration Option 79 Datasheet intel Revision History Datasheet Date Revision Description October 2004 001 Initial release THIS PAGE INTENTIONALLY LEFT BLANK Datasheet 1 0 Introduction Table 1 Datasheet The Low Voltage Intel Xeon processor with 800 MHz system bus is a 32 bit processor based on improvements to the Intel NetBurst microarchitecture It maintains the tradition of compatibility with IA 32 software and includes features found in the Low Voltage Intel processor such as Hyper Pipelined Technology a Rapid Execution Engine and an Execution Trace Cache Hyper Pipelined Technology includes a multi stage pipeline allowing the processor to reach much higher core frequencies The 800 MHz system bus is a quad pumped bus running off a 200 MHz system clock making 6 4 GB per second data tran
7. This signal does not have on die termination and must be terminated at the end agent 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor front side bus agents RSP RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all processor front side bus agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity SKTOCC SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present There is no connection to the processor silicon for this signal SLEW_CTRL The front side bus slew rate control input SLEW_CTRL is used to establish distinct edge rates for middle and end agents SLP SLP Sleep when asserted in Stop Grant state causes processors to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Lock Loop PLL still operating Processors in this state wi
8. intel Table 21 Pin Listing by Pin Name Sheet 2 of 8 Pin Name amp Direction Pin Name E HT uh Direction D17 AC26 Source Sync I O D57 AD7 Source Sync I O D18 AD25 Source Sync I O D58 AE7 Source Sync I O D19 AE25 Source Sync I O D59 AC6 Source Sync I O D20 AC24 Source Sync I O D60 AC5 Source Sync I O D21 AD24 Source Sync I O 061 AA8 Source Sync I O 022 AE23 Source Sync I O D62 Y9 Source Sync I O 023 AC23 Source Sync I O 063 Source Sync I O 024 18 Source Sync I O DBSY F18 Common Clk I O D25 AC20 Source Sync I O DEFER C23 Common Clk Input D26 AC21 Source Sync I O DBIO 27 Source Sync I O D27 AE22 Source Sync I O DBI1 AD22 Source Sync I O D28 AE20 Source Sync I O DBI2 AE12 Source Sync I O D29 AD21 Source Sync I O DBI3 AB9 Source Sync I O D30 AD19 Source Sync I O DPO AC18 Common Clk I O 031 AB17 Source Sync I O DP1 AE19 Common Clk I O 032 AB16 Source Sync I O DP2 AC15 Common Clk I O D33 AA16 Source Sync I O DP3 AE17 Common Clk I O D34 AC17 Source Sync I O DRDY E18 Common Clk I O D35 AE13 Source Sync I O DSTBNO Y21 Source Sync I O 036 AD18 Source Sync I O DSTBN1 Y18 Source Sync I O D37 AB15 Source Sync
9. 13 2 2 3 Front Side Bus AGTL 24444 14 2 3 Front Side Bus Clock BCLK 1 0 and Processor Clocking 14 2 3 1 Front Side Bus Frequency Select Signals 0 14 2 3 2 Phase Lock Loop PLL and Filter essen 15 2 4 Voltage Identification VID et tetris vett in nec ee E dup Yan 16 2 5 Reserved or Unused Pins eei T 18 26 Front Side Bus Signal Groups icti tested sad RUE Rn ex ee 19 2 7 GTL Asynchronous and AGTL Asynchronous 5 22 2 8 Test Access Port TAP 4 nn ERAEN KERNER 22 29 Mixing PIOCOSSOIS nece eiecier ue 22 2 10 Absolute Maximum and Minimum 0 23 2 11 Processor DO SpecifICations a ined edite E 24 2 11 1 Overshoot Specification 30 2 11 2 Die Voltage Validation itte etre 31 Mechanical 35 3 1 Package Mechanical 35 3 2 Processor Component Keepout 2 22 0 38 3 3 Package Loading enne 38 3 4 Package Handling
10. Low Voltage Intel Xeon Processor with 800 MHz System Bus Datasheet Product Features m Available at 2 80 GHz m Enhanced branch prediction m 90 nm process technology m Includes 16 KB Level 1 data cache m Dual processing support m Intel Extended Memory 64 Technology m Binary compatible with applications m Advanced Transfer Cache On die running on previous members of Intel s full speed Level 2 L2 Cache with 8 way IA 32 microprocessor line associativity and Error Correcting Code m Intel NetBurst microarchitecture ECC m Hyper Threading Technology m Enables system support of up to 64 GB of m physical memory m Supports Execute Disable Bit capability m 144 Streaming SIMD Extensions 2 SSE2 m Hardware support for multithreaded instructions m 13 Streaming SIMD Extensions 3 SSE3 m Faster 800 MHz system bus m Rapid Execution Engine Arithmetic Logic m Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D performance m System Management mode m Thermal Monitor m Machine Check Architecture MCA Units ALUS run at twice the processor core frequency m Hyper Pipelined Technology m Advanced Dynamic Execution m Very deep out of order execution The Low Voltage Intel Xeon processor with 800 MHz system bus is designed for high performance dual processor applications Based on the Intel NetBurst microarchitecture and the Hyper Threading Technology
11. 5 ADSTB1 0 15 0 DBIO DSTBPO DSTBNO 0 31 16 DBI1 DSTBP1 DSTBN1 DSTBP2 DSTBN2 DSTBP3 DSTBN3 D 47 32 f 2 D 63 48 f DBIS AGTL Strobe Synchronous to BCLKT 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 amp AGTL Asynchronous Output Asynchronous FERR PBE IERR PROCHOT GTL Asynchronous Input Asynchronous A20M FORCEPR IGNNE INIT LINTO INTR LINT1 NMI SMIP SLP STPCLK GTL Asynchronous Output Asynchronous THERMTRIP Front Side Bus Clock Clock BCLK1 BCLKO TAP Input Synchronous to TCK TCK TDI TMS TRST TAP Output Synchronous to TCK TDO Power Other Power Other BOOT SELECT BSEL 1 0 COMP 1 0 GTLREF 3 0 ODTEN OPTIMIZED COMPAT PWRGOOD Reserved SLEW CTRL SMB_PRT TEST BUS TESTHI 6 0 THERMDA THERMDO Veca VccioPLL VccPLL VCCSENSE VID S 0 Vss VssA VSSSENSE VIDPWRGD VTTEN NOTES 1 Refer to Section 4 0 for signal descriptions 2 The Low Voltage Intel processor with 800 MHz system bus only uses BRO and BR1 BR2 and BR3 must be terminated to For additional details regarding the BR 3 0 signals see Section 4 0 and Section 7 1 3 The value of these pins during the active to inactive edge of RESET defines the processor configuration options See Section 7 1 for details 4 These signals may be driven simultaneously by multiple
12. Input J27 VSS Power Other 64 Datasheet intel Table 22 Pin Listing by Pin Number Sheet 4 of 8 Pin Name ate amp Direction Pin Name a M Direction J28 VCC Power Other M1 VCC Power Other J29 VSS Power Other M2 VSS Power Other J30 VCC Power Other M3 VCC Power Other J31 VSS Power Other M4 VSS Power Other K1 VCC Power Other M5 VCC Power Other K2 VSS Power Other M6 VSS Power Other K3 VCC Power Other M7 VCC Power Other K4 VSS Power Other M8 VSS Power Other K5 VCC Power Other M9 VCC Power Other K6 VSS Power Other M23 VCC Power Other K7 VCC Power Other M24 VSS Power Other K8 VSS Power Other M25 VCC Power Other K9 VCC Power Other M26 VSS Power Other K23 VCC Power Other M27 VCC Power Other K24 VSS Power Other M28 VSS Power Other K25 VCC Power Other M29 VCC Power Other K26 VSS Power Other M30 VSS Power Other K27 VCC Power Other M31 VCC Power Other K28 VSS Power Other N1 Power Other K29 Power Other N2 VSS Power Other K30 VSS Power Other N3 Power Other K31 Power Other 4 VSS Power Other L1 VSS Power Other N5 Power Other L2 VCC Power Other N6 VSS Power Other L3 VSS Power Other N7 Power Other L4 VCC Power Other N8 VSS Power Other L5 VSS Power Other N9 Power Other L6 VCC Power Other N23 VCC Power Other L7 VSS Power Other N24 VSS Power
13. On Demand mode may be used in conjunction with the Thermal Monitor If the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal Pin An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its factory configured trip point If Thermal Monitor is enabled note that Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel Architecture Software Developer s Manual s for specific register and programming details PROCHOT is designed to assert at or a few degrees higher than maximum Tagg as specified by Thermal Profile when dissipating TDP power and cannot be interpreted as an indication of processor case temperature This temperature delta accounts for processor package lifetime and manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below maximum when dissipating TDP power There is no defined or fixed correlation between the PROCHOT trip temperature the case temperature or the thermal diode temperature Thermal solutions must be designed to the processor specifications and cannot be adjusted based on
14. ennt tenente nens 15 4 Voltage Identification Definition nennen nnne nnn nennen nnns 17 5 Front Side Bus Signal nennen nennen nennen re nnne nennen 20 6 Signal Description Table cerae epar e XX Eua EE E da a ca se e ER EE Dae Ee XX ER edes 21 Signal Reference 21 8 Absolute Maximum and Minimum 23 9 Voltage and Current Specifications enne nennen 25 10 VCC Static and Transient 28 11 VCC Overshoot 30 12 BSEL 1 0 and VID 5 0 Signal Group DC 31 13 AGTL Signal Group DC Specifications 31 14 PWRGOOD Input and TAP Signal Group DC 32 15 GTL Asynchronous AGTL Asynchronous Signal Group DC Specifications 32 16 VIDPWRGD DC Specifications oet eot dee ck sane ean nk ane dai 33 17 Processor Loading Specifications eene nnne 38 18 Package Handling Guidelines 39 19 Processor Maltertlals orsus Reiche fade nrbe EE Pk He Ege un ar
15. providing internal clock signals to all processor core units except the front side bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input Datasheet 49 Table 20 Intel Signal Definitions Sheet 8 of 9 Name Type Description Notes Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TEST BUS Must be connected to all other processor TEST BUS signals in the system TESTHI 6 0 All TESTHI inputs should be individually connected to via a pull up resistor which matches the trace impedance TESTHI 3 0 and TESTHI 6 5 may all be tied together and pulled up to Vr with a single resistor if desired However usage of boundary scan test will not be functional if these pins are connected together TESTHI4 must always be pulled up independently from the other TESTHI pins For optimum nois
16. 1 0 frequency The processor bus ratio multiplier will be set during manufacturing The default setting will be the maximum speed for the processor It will be possible to override this setting using software This will permit operation at a speed lower than the processor s tested frequency BCLK 1 0 inputs directly control the operating speed of the front side bus interface The processor core frequency is configured during reset by using values stored internally during manufacturing The stored value sets the highest bus fraction at which the particular processor can operate Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK 1 0 input with exceptions for spread spectrum clocking The Low Voltage Intel Xeon processor with 800 MHz system bus uses differential clocks Details regarding BCLK 1 0 driver specifications are provided in the CK409 Clock Synthesizer Driver Design Guidelines or CK409B Clock Synthesizer Driver Design Guidelines Table 2 contains core frequency to front side bus multipliers and their corresponding core frequencies Core Frequency to Front Side Bus Multiplier Configuration Core Frequency to Core Frequency with Front Side Bus Multiplier 200 MHz Front Side Bus Clock 1 14 2 80 GHz Front Side Bus Frequency Select Signals BSEL 1 0 Upon power up the front side bus frequency is set to the maximum supported by t
17. 31 29 27 25 23 21 19 17 15 13 11 9 7 oleoooe Beeeeoceo oloeoeo eo ce ceeoeooec o elooeoo Oo 9 6 0 Dje e e o ooo elo oleoooe 0 Eeeeeceoo e Oojoeoeo eooe Feeeeocceo v eoceoco 0000 Gleeeseeeeso Heeeeeeeee eee Jeeeececocce eco eee Intel amp eco Meeeeeeeoe Processor eee Peeeeceoeccceo 800 MHz Reeeeeeeeee Bottom View eee Teeeeeeeece eee Veeeeoeccceo eco wleeeeeeeec 00 Yeeooooeoo ooe AANleeoooeooe eoo ABeeooeooeo oeo ACleoooooeoo ooe ADleeoooeooe eoo AE 00000080 oeo 30 28 26 24 22 20 18 16 14 12 10 8 6 DATA O Signal GTLREF Power Reserved No Connect Ground COMMON CLOCK 5 3 1 oceoo eooeco e o e o0 0 eeoooo lt 5 lt 292 gt SSA 99A eoee eoee AA e O e AB e e e O AC e e 9 O Ap 4 2 CLOCKS Datasheet In 4 0 Signal Definitions 4 1 Table 20 Signal Definitions Signal Definitions Sheet 1 of 9 Name Type Description Notes 35 3 y o 35 3 Address define a 239 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appro
18. Datasheet intel Table 21 Pin Listing by Pin Name Sheet 6 of 8 Pin Name on EUER IS amp Direction Pin Name E E Nul Direction VCCPLL AD1 Power Other Input VSS E31 Power Other VCCSENSE B27 Power Other Output VSS F2 Power Other VIDO F3 Power Other Output VSS F7 Power Other VID1 E3 Power Other Output VSS F13 Power Other VID2 D3 Power Other Output VSS F19 Power Other VID3 C3 Power Other Output VSS F25 Power Other VIDA B3 Power Other Output VSS F28 Power Other VID5 Al Power Other Output VSS F30 Power Other VIDPWRGD B1 Power Other Input VSS G1 Power Other VSS A5 Power Other VSS G3 Power Other VSS A11 Power Other VSS G5 Power Other VSS A21 Power Other VSS G9 Power Other VSS A27 Power Other VSS G25 Power Other VSS A29 Power Other VSS G27 Power Other VSS A31 Power Other VSS G29 Power Other VSS B2 Power Other VSS G31 Power Other VSS B9 Power Other VSS H2 Power Other VSS B15 Power Other VSS H4 Power Other VSS B17 Power Other VSS H6 Power Other VSS B23 Power Other VSS H8 Power Other VSS B28 Power Other VSS H24 Power Other VSS B30 Power Other VSS H26 Power Other VSS C7 Power Other VSS H28 Power Other VSS C13 Power Other VSS H30 Power Other VSS C19 Power Other VSS J1 Power Other VSS C25 Power Other VSS J3 Power Other VSS C29 Power Other VSS J5 Power Other VSS C31 Power Other VSS J7
19. NetBurst and Itanium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Intel Extended Memory 64 Technology Intel EM64T requires a computer system with a processor chipset BIOS OS device drivers and applications enabled for Intel EM64T Processor will not operate including 32 bit operation without an Intel EM64T enabled BIOS Performance will vary depending on your hardware and software configurations Intel EM64T enabled OS BIOS device drivers and applications may not be available Check with your vendor for more information 4 Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor_number for details Other names and brands may be claimed as the property of others Copyright 2004 Intel Corporation 2 Datasheet intel Contents 1 0 2 0 3 0 4 0 5 0 6 0 079 m 9 NEN Code 10 1 2 RENONCE EE 12 lt T 12 Electrical Specifications cee tec cee td tenes eee eee een ene 13 2 1 Power Ground 13 2 2 Decoupling Guidelines 13 2 2 4 Decoupling rette ERR ER Ed Raus 13 2 2 2 NIT Becouplitg
20. Other VSS AA15 Power Other VSS AE27 Power Other VSS AA17 Power Other VSSA 5 Power Other Input VSS AA23 Power Other VSSSENSE D26 Power Other Output VSS 0 Power Other VTT A4 Power Other VSS AB1 Power Other VTT B4 Power Other VSS AB5 Power Other VIT C5 Power Other VSS AB11 Power Other VTT B12 Power Other VSS AB21 Power Other VIT C10 Power Other VSS AB27 Power Other VTT E12 Power Other VSS AB31 Power Other VTT F10 Power Other VSS AC2 Power Other VTT Y10 Power Other VSS Power Other VTT 12 Power Other VSS AC13 Power Other VIT AC10 Power Other VSS AC19 Power Other VTT AD12 Power Other VSS AC25 Power Other VTTEN E1 Power Other Output NOTE systems using the Low Voltage Intel Xeon processor with 800 MHz system bus the system designer must pull up these signals to the processor V r Datasheet 61 5 1 2 Pin Listing Pin Number Table 22 Pin Listing by Pin Number Sheet 1 of 8 den Pin Name inet es Direction n Pin Name MR Direction A1 VID5 Power Other Output B8 27 Source Sync 2 VCC Power Other B9 VSS Power Other A3 SKTOCC Power Other Output B10 21 Source Sync I O 4 VTT Power Other B11 22 Source Sync 5 VSS Power Other B12 VTT Power Other A6 A32 Source Sync
21. Other L8 VCC Power Other N25 VCC Power Other L9 VSS Power Other N26 VSS Power Other L23 VSS Power Other N27 VCC Power Other L24 VCC Power Other N28 VSS Power Other L25 VSS Power Other N29 VCC Power Other L26 VCC Power Other N30 VSS Power Other L27 VSS Power Other N31 VCC Power Other L28 VCC Power Other P1 VSS Power Other L29 VSS Power Other P2 Power Other L30 VCC Power Other P3 VSS Power Other L31 VSS Power Other P4 Power Other Datasheet 65 Intel Table 22 Pin Listing by Pin Number Sheet 5 of 8 des Pin Name esc M Direction E Pin Name RR Direction P5 VSS Power Other T9 VSS Power Other P6 VCC Power Other T23 VSS Power Other P7 VSS Power Other T24 VCC Power Other P8 VCC Power Other T25 VSS Power Other P9 VSS Power Other T26 VCC Power Other P23 VSS Power Other T27 VSS Power Other P24 VCC Power Other T28 VCC Power Other P25 VSS Power Other T29 VSS Power Other P26 VCC Power Other T30 VCC Power Other P27 VSS Power Other T31 VSS Power Other P28 VCC Power Other U1 VCC Power Other P29 VSS Power Other U2 VSS Power Other P30 VCC Power Other U3 VCC Power Other P31 VSS Power Other U4 VSS Power Other R1 VCC Power Other 05 VCC Power Other R2 VSS Power Other 06 VSS Power Other R3 VCC Power Other U7 VCC Power Other R4 VSS Power Other U8 VSS Power Other R5 VCC Power Other 09 VCC Power
22. Other R6 VSS Power Other U23 VCC Power Other R7 VCC Power Other U24 VSS Power Other R8 VSS Power Other U25 VCC Power Other R9 VCC Power Other U26 VSS Power Other R23 VCC Power Other U27 VCC Power Other R24 VSS Power Other U28 VSS Power Other R25 VCC Power Other U29 VCC Power Other R26 VSS Power Other U30 VSS Power Other R27 VCC Power Other U31 VCC Power Other R28 VSS Power Other V1 VSS Power Other R29 VCC Power Other V2 VCC Power Other R30 VSS Power Other V3 VSS Power Other R31 VCC Power Other V4 VCC Power Other T1 VSS Power Other V5 VSS Power Other T2 VCC Power Other V6 VCC Power Other T3 VSS Power Other V7 VSS Power Other T4 VCC Power Other V8 VCC Power Other T5 VSS Power Other V9 VSS Power Other T6 VCC Power Other V23 VSS Power Other T7 VSS Power Other V24 VCC Power Other T8 VCC Power Other V25 VSS Power Other 66 Datasheet intel Table 22 Pin Listing by Pin Number Sheet 6 of 8 P Pin Name Direction E Pin Name T Nob Direction V26 VCC Power Other Y17 DSTBP1 Source Sync I O V27 VSS Power Other Y18 DSTBN1 Source Sync I O V28 Power Other Y19 VSS Power Other V29 VSS Power Other Y20 DSTBPO Source Sync I O V30 VCC Power Other Y21 DSTBNO Source Sync I O V31 VSS Power Other Y22 VCC Power Other VCC Power Other Y23 05 Source Sync I O W2 VSS Power Other Y24
23. Other VSS M28 Power Other VSS U6 Power Other VSS M30 Power Other VSS U8 Power Other VSS N2 Power Other VSS U24 Power Other VSS N4 Power Other VSS U26 Power Other VSS N6 Power Other VSS U28 Power Other VSS N8 Power Other VSS U30 Power Other VSS N24 Power Other VSS V1 Power Other VSS N26 Power Other VSS V3 Power Other VSS N28 Power Other VSS V5 Power Other VSS N30 Power Other VSS V7 Power Other VSS P1 Power Other VSS V9 Power Other VSS P3 Power Other VSS V23 Power Other VSS P5 Power Other VSS V25 Power Other VSS P7 Power Other VSS V27 Power Other VSS P9 Power Other VSS V29 Power Other VSS P23 Power Other VSS V31 Power Other VSS P25 Power Other VSS W2 Power Other VSS P27 Power Other VSS WA Power Other VSS P29 Power Other VSS W24 Power Other VSS P31 Power Other VSS W26 Power Other VSS R2 Power Other VSS W28 Power Other VSS R4 Power Other VSS W30 Power Other 60 Datasheet intel Table 21 Pin Listing by Pin Name Sheet 8 of 8 Pin Name amp Direction Pin Name d E Nu Direction VSS Y1 Power Other VSS AD3 Power Other VSS Y5 Power Other VSS AD9 Power Other VSS Y7 Power Other VSS AD15 Power Other VSS Y13 Power Other VSS AD17 Power Other VSS Y19 Power Other VSS AD23 Power Other VSS Y25 Power Other VSS ADS31 Power Other VSS Y31 Power Other VSS AE2 Power Other VSS AA2 Power Other VSS AE11 Power Other VSS AAQ Power Other VSS AE21 Power
24. Other VCC L26 Power Other VCC G6 Power Other VCC L28 Power Other VCC G8 Power Other VCC L30 Power Other VCC G24 Power Other 1 Power Other VCC G26 Power Other Power Other G28 Power Other M5 Power Other VCC G30 Power Other 7 Power Other VCC H1 Power Other VCC Mg Power Other VCC H3 Power Other VCC M23 Power Other VCC H5 Power Other VCC M25 Power Other VCC H7 Power Other VCC M27 Power Other VCC H9 Power Other VCC M29 Power Other VCC H23 Power Other VCC M31 Power Other VCC H25 Power Other VCC N1 Power Other VCC H27 Power Other VCC N3 Power Other VCC H29 Power Other VCC N5 Power Other VCC H31 Power Other VCC N7 Power Other VCC J2 Power Other VCC N9 Power Other VCC J4 Power Other VCC N23 Power Other VCC J6 Power Other VCC N25 Power Other VCC J8 Power Other VCC N27 Power Other VCC J24 Power Other VCC N29 Power Other VCC J26 Power Other VCC N31 Power Other VCC J28 Power Other VCC P2 Power Other VCC J30 Power Other VCC P4 Power Other Datasheet 57 Intel Table 21 Pin Listing by Pin Name Sheet 5 of 8 Pin Name LS Direction Pin Name E Direction VCC P6 Power Other VCC V28 Power Other VCC P8 Power Other VCC V30 Power Other VCC P24 Power Other VCC W1 Power Other VCC P26 Power Other VCC W25 Power Other VCC P28 Power Other VCC W27 Power Ot
25. Power Other Input C12 A23 Source Sync I O B6 VCC Power Other C13 VSS Power Other B7 1 Source Sync C14 A163 Source Sync I O 62 Datasheet intel Table 22 Pin Listing by Pin Number Sheet 2 of 8 n Pin Name amp Direction m Pin Name a No Direction C15 A15 Source Sync I O D24 VCC Power Other C16 VCC Power Other D25 Reserved Reserved Reserved C17 A8 Source Sync I O D26 VSSSENSE Power Other Output C18 A6 Source Sync D27 VSS Power Other C19 VSS Power Other D28 VSS Power Other C20 REQ3 Source Sync I O D29 VCC Power Other C21 2 Source Sync D30 VSS Power Other C22 VCC Power Other D31 VCC Power Other C23 DEFER Common Clk Input E1 VTTEN Power Other Output C24 TDI TAP Input E2 VCC Power Other C25 VSS Power Other E3 VID1 Power Other Output C26 IGNNE Async GTL Input E4 5 Common Clk I O C27 GTL Input E5 IERR Async GTL Output C28 VCC Power Other E6 VCC Power Other C29 VSS Power Other E7 BPM2 Common Clk I O C30 VCC Power Other E8 BPM4 Common Clk I O C31 VSS Power Other E9 VSS Power Other D1 VCC Power Other E10 APO Common Clk I O D2 VSS Power Other E11 BR2jt Common CIk Input D3 VID2 Power Other Output E12 VTT Power Other D4 STPCLK Async GTL Input E13 A28 Source Sync I O D5 VSS Power Other E
26. Power Other VSS D2 Power Other VSS J9 Power Other VSS D5 Power Other VSS J23 Power Other VSS D11 Power Other VSS J25 Power Other VSS 021 Power Other VSS J27 Power Other VSS D27 Power Other VSS J29 Power Other VSS D28 Power Other VSS J31 Power Other VSS D30 Power Other VSS K2 Power Other VSS E9 Power Other VSS K4 Power Other VSS E15 Power Other VSS K6 Power Other VSS E17 Power Other VSS K8 Power Other VSS E23 Power Other VSS K24 Power Other VSS E29 Power Other VSS K26 Power Other Datasheet 59 Intel Table 21 Pin Listing by Pin Name Sheet 7 of 8 Pin Name E LS Direction Pin Name Direction VSS K28 Power Other VSS R6 Power Other VSS K30 Power Other VSS R8 Power Other VSS L1 Power Other VSS R24 Power Other VSS L3 Power Other VSS R26 Power Other VSS L5 Power Other VSS R28 Power Other VSS L7 Power Other VSS R30 Power Other VSS L9 Power Other VSS T1 Power Other VSS L23 Power Other VSS T3 Power Other VSS L25 Power Other VSS T5 Power Other VSS L27 Power Other VSS T7 Power Other VSS L29 Power Other VSS T9 Power Other VSS L31 Power Other VSS T23 Power Other VSS M2 Power Other VSS T25 Power Other VSS M4 Power Other VSS T27 Power Other VSS M6 Power Other VSS T29 Power Other VSS M8 Power Other VSS T31 Power Other VSS M24 Power Other VSS U2 Power Other VSS M26 Power Other VSS U4 Power
27. Y13 VSS Power Other AA22 D10 Source Sync I O Y14 DSTBP2 Source Sync I O AA23 VSS Power Other Y15 DSTBN2 Source Sync I O 24 D6 Source Sync I O Y16 Power Other AA25 D3 Source Sync I O Datasheet 67 Intel Table 22 Pin Listing by Pin Number Sheet 7 of 8 LS Direction dn Pin Name Direction AA26 VCC Power Other 4 VCC Power Other AA27 Di Source Sync I O AC5 D60 Source Sync I O AA28 N C N C N C AC6 D59 Source Sync I O AA29 N C N C N C 55 Power Other 0 VSS Power Other AC8 D56 Source Sync I O AA31 VCC Power Other AC9 D47 Source Sync I O AB1 VSS Power Other 10 VTT Power Other AB2 VCC Power Other 11 D43 Source Sync BSEL1 Power Other Output 12 D41 Source Sync I O 4 VCCA Power Other Input AC13 VSS Power Other AB5 VSS Power Other 14 D50 Source Sync AB6 063 Source Sync AC15 2 Common Clk I O AB7 PWRGOOD Async GTL Input AC16 VCC Power Other AB8 VCC Power Other 17 D34 Source Sync AB9 DBI3 Source Sync I O 18 DPO Common Clk I O AB10 D55 Source Sync I O AC19 VSS Power Other AB11 VSS Power Other AC20 D25 Source Sync 12 D51 Source Sync I O AC21 D26 Source Sync I O
28. all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor front side bus agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST Datasheet 47 Table 20 Intel Signal Definitions Sheet 6 of 9 Name Type Description Notes LINT 1 0 LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all front side bus agents When the APIC functionality is disabled the LINTO INTR signal becomes INTR a maskable interrupt request signal and LINT 1 NMI becomes NMI a non maskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK y o LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor front side bus age
29. available Listed frequencies are not necessarily committed production frequencies 2 Each processor is programmed with a maximum valid voltage identification value VID which is set at the manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency might have different settings within the VID range Please note that this differs from the VID employed by the processor during power management event 3 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 4 for more information 4 The voltage specification requirements are measured across vias on the platform for the VOCSENSE and VSSSENSE pins close to the socket with 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 5 Refer to Table 10 and corresponding Figure 3 The processor should not be subjected to any static level that exceeds the Vcc Max associated with any particular current Failure to adhere to this specification can shorten processor lifetime 6 Minimum Vcc and maximum are specified at the maximum processor case temperature Tease shown in Table 24 Max is specified at the relative Voc max point
30. experimental measurements of Tcasp PROCHOT or T diode on random processor samples FORCEPR Signal Pin The FORCEPR force power reduction input can be used by the platform to cause the Low Voltage Intel Xeon processor with 800 MHz system bus to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal The TCC will remain active until the system deasserts FORCEPR FORCEPR is an asynchronous input FORCEPR can be used to thermally protect other system components To use the VR as an example when the FORCEPR pin is asserted the TCC circuit in the processor will activate reducing the current consumption of the processor and the corresponding temperature of the VR If should be noted that assertion of FORCEPR does not automatically assert PROCHOT As mentioned previously the PROCHOT signal is asserted when a high temperature situation is detected A minimum pulse width of 500 us is recommend when the FORCEPR is asserted by the system Sustained activation of the FORCEPR pin may cause noticeable platform performance degradation 75 6 2 5 6 2 6 6 2 7 Table 25 76 Intel THERMTRIP Signal Pin Regardless of whether or not Thermal Monitor is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 20 At thi
31. it is binary compatible with previous Intel Architecture 32 processors The Low Voltage Intel Xeon processor with 800 MHz system bus is scalable to two processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Windows XP Windows Server 2003 Linux and UNIX The Low Voltage Intel Xeon processor with 800 MHz system bus delivers compute power at unparalleled value and flexibility for powerful workstations internet infrastructure and departmental server applications The Intel NetBurst microarchitecture and Hyper Threading Technology deliver outstanding performance and headroom for peak internet server workloads resulting in faster response times support for more users and improved scalability Oe oe be or pe Document Number 304097 001US October 2004 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel pro
32. processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings This is reflected by the VID Range values provided in Table 9 Refer to the Intel Xeon Processor with 800 MHz System Bus Specification Update for further details on specific valid core frequency and VID values of the processor The Low Voltage Intel processor with 800 MHz system bus uses six voltage identification signals VID 5 0 to support automatic selection of power supply voltages Table 4 specifies the voltage level corresponding to the state of VID 5 0 417 in this table refers to a high voltage level and 0 refers to a low voltage level If the processor socket is empty VID 5 0 x11111 or the voltage regulation circuit cannot supply the voltage that is requested it must disable itself See the Voltage Regulator Module VRM Voltage Regulator Down EVRD 10 0 Design Guidelines or Voltage Regulator Module VRM for further details The Low Voltage Intel Xeon processor with 800 MHz system bus provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not perm
33. the equation Terror N 1 lew minl nk q Where Terror sensor temperature error sensor current ratio Boltzmann Constant q electronic charge Datasheet In Table 26 Datasheet Thermal Diode Interface Pin Name Pin Number Pin Description THERMDA Y27 diode anode THERMDC Y28 diode cathode 77 78 THIS PAGE INTENTIONALLY LEFT BLANK Datasheet 7 0 Features 7 1 Table 27 7 2 Datasheet Power On Configuration Options Several configuration options can be configured by hardware The Low Voltage Intel processor with 800 MHz system bus samples its hardware configuration at reset on the active to inactive transition of RESET For specifics on these options please refer to Table 14 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset and a power on reset Power On Configuration Option Pins Configuration Option Pin Notes Output tristate SMI 1 2 Execute BIST Built In Self Test INIT 1 2 In Order Queue de pipelining set IOQ depth to 1 7 1 2 Disable MCERR observation 9 1 2 Disable BINIT observation A103 1 2 Disable bus parking 15 1 2 Symmetric agent arbitration ID BR 3 0 1 2
34. 1 Common G30 Power Other F9 GTLREF Power Other Input G31 VSS Power Other F10 VTT Power Other H1 VCC Power Other F11 BINIT Common H2 VSS Power Other F12 BR1 Common Input H3 VCC Power Other F13 VSS Power Other H4 VSS Power Other F14 ADSTB1 Source Sync I O H5 VCC Power Other F15 A193 Source Sync I O H6 VSS Power Other F16 VCC Power Other H7 VCC Power Other F17 ADSTBO Source Sync I O H8 VSS Power Other F18 DBSY Clk H9 VCC Power Other F19 VSS Power Other H23 VCC Power Other F20 BNR H24 VSS Power Other F21 RS2 Common Input H25 VCC Power Other F22 VCC Power Other H26 VSS Power Other F23 GTLREF Power Other Input H27 VCC Power Other F24 TRST TAP Input H28 VSS Power Other F25 VSS Power Other H29 VCC Power Other F26 THERMTRIP Async GTL Output H30 VSS Power Other F27 A20M Async GTL Input H31 VCC Power Other F28 VSS Power Other J1 VSS Power Other F29 VCC Power Other J2 VCC Power Other F30 VSS Power Other J3 VSS Power Other F31 VCC Power Other J4 VCC Power Other G1 VSS Power Other J5 VSS Power Other G2 VCC Power Other J6 VCC Power Other G3 VSS Power Other J7 VSS Power Other G4 VCC Power Other J8 VCC Power Other G5 VSS Power Other J9 VSS Power Other G6 VCC Power Other J23 VSS Power Other G7 BOOT_SELECT Power Other Input J24 VCC Power Other G8 VCC Power Other J25 VSS Power Other G9 VSS Power Other J26 VCC Power Other G23 LINT1 NMI Async GTL
35. 1 2 3 VCC Max VCC Typ VCC Min 0 VID 0 000 VID 0 020 VID 0 040 5 VID 0 006 VID 0 026 VID 0 046 10 VID 0 013 VID 0 033 VID 0 052 15 VID 0 019 VID 0 039 VID 0 059 20 VID 0 025 VID 0 045 VID 0 065 25 VID 0 031 VID 0 051 VID 0 071 30 VID 0 038 VID 0 058 VID 0 077 35 VID 0 044 VID 0 064 VID 0 084 40 VID 0 050 VID 0 070 VID 0 090 45 VID 0 056 VID 0 076 VID 0 096 50 VID 0 063 VID 0 083 VID 0 103 55 VID 0 069 VID 0 089 VID 0 109 60 VID 0 075 VID 0 095 VID 0 115 NOTES 1 The and loadlines represent static and transient limits Please see Section 2 11 1 for overshoot specifications 2 This table is intended to aid in reading discrete points on Figure 3 3 The loadlines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins Voltage regulation feedback for voltage regulator circuits must be taken from processor Vcc and Vss pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines for socket loadline guidelines and VR implementation Datasheet In Figure 3 Vcc Static and Transient Tolerance A 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 VID 0 000 4 VID 0 020 4 VID 0 040 VID 0 0
36. 14 A24 Source Sync I O D6 INIT GTL Input E15 VSS Power Other D7 MCERR Common Clk I O E16 1 Power Other Input D8 VCC Power Other E17 VSS Power Other 09 AP1 Common Clk I O E18 DRDY Common Clk I O D10 BR3 Common Clk Input E19 TRDY Common Clk Input D11 VSS Power Other E20 VCC Power Other D12 29 Source Sync E21 RSO Common Clk Input D13 A25 Source Sync I O E22 HIT Common Clk I O D14 VCC Power Other E23 VSS Power Other D15 A18 Source Sync I O E24 TCK TAP Input D16 17 Source Sync 25 TDO TAP Output D17 A9 Source Sync I O E26 VCC Power Other D18 VCC Power Other E27 FERR PBE Async GTL Output D19 ADS Common Clk I O E28 Power Other D20 BRO Common Clk I O E29 VSS Power Other D21 VSS Power Other E30 VCC Power Other D22 RS1 Common Clk Input E31 VSS Power Other D23 BPRI Common Clk Input F1 VCC Power Other Datasheet 63 Intel Table 22 Pin Listing by Pin Number Sheet 3 of 8 LS Direction E Pin Name Rd Direction F2 VSS Power Other G24 VCC Power Other F3 VIDO Power Other Output G25 VSS Power Other F4 VCC Power Other G26 VCC Power Other F5 BPM3 I O G27 VSS Power Other F6 BPMO Common Clk I O G28 Power Other F7 VSS Power Other G29 VSS Power Other F8 BPM
37. 2B Instruction Set 253667 Reference N Z 1 32 Intef Architecture Software Developer s Manual Volume 3 System Programming 253668 Guide ITP700 Debug Port Design Guide 249679 Inte Xeon Processor with 800 MHz System Bus Specification Update 302402 Inte Xeon Processor with 800 MHz System Bus Core Boundary Scan Descriptive 302403 Language BSDL Model V1 0 and Cell Descriptor File V1 0 Inte Xeon Processor with 800 MHz System Bus Thermal Models zip file Xeon Processor with 800 MHz System Bus Mechanical Models IGES zip file Inte Xeon Processor with 800 MHz System Bus Mechanical Models ProE zip file Low Voltage Intef Xeon Processor with 800 MHz System Bus in Embedded 304061 Applications Thermal Mechanical Design Guide Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 302731 Design Guidelines NOTE Contact your Intel representative for the latest revision of documents without document numbers State of Data The data contained within this document is subject to change It is the most accurate information available by the publication date of this document Datasheet Electrical Specifications 2 1 2 2 2 2 1 2 2 2 Datasheet Power and Ground Pins For clean on chip power distribution the processor has 181 power and 185 ss ground inputs pins must be connected to the processor power plane while all Vss pins must be connected to th
38. 3 Disable Hyper Threading Technology 1 1 2 1 Asserting this signal during RESET will select the corresponding option 2 Address pins not identified in this table as configuration options should not be asserted during RESET 3 The Low Voltage Intel processor with 800 MHz system bus only uses the BRO and BR1 signals Platforms must not use BR2 and BR3 signals Clock Control and Low Power States The processor allows the use of HALT Stop Grant and Sleep states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 14 for a visual representation of the processor low power states The Stop Grant state requires chipset and BIOS support on multiprocessor systems In a multiprocessor system all the STPCLK signals are bussed together thus all processors are affected in unison The Hyper Threading Technology feature adds the conditions that all logical processors share the same STPCLK signal internally When the STPCLK signal is asserted the processor enters the Stop Grant state issuing a Stop Grant Special Bus Cycle SBC for each processor or logical processor The chipset needs to account for a variable number of processors asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states Refer to the applicable chipset specification for more in
39. 4 Pin side capacitors 5 Package pin 6 Die Side Capacitors Processor Package Assembly Sketch NOTE This drawing is not to scale and is for reference only The mPGA604 socket is not shown Package Mechanical Drawings The package mechanical drawings are shown in Figure 6 and Figure 7 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include Package reference and tolerance dimensions total height length width etc IHS parallelism and tilt Pin dimensions 2 3 4 Top side and back side component keepout dimensions 5 Reference datums 6 drawing dimensions are in mm in 35 Processor Package Drawing Sheet 1 of 2 Z 30 133 OKINVEO 31 25 LON 00 ne mm aimee e 11 ONIMVHC SLW3 200 100 1 920 gus as 03 0302 6118 25096 Y YO VINS Pyu 05900 7520704 dD 59 00 61185 X08 Od QA1G 3931102 NOISSIN 0022 0 4 0 310 18 03N91530 00 080 8070 lt 072 i 710 0107 998 0 54270 105071 E 21598 L 2 n es 105071 215
40. 5 mm 0 837 in Measure T case at this point 42 5 mm FC mPGA4 Package NOTE Figure is not to scale and is for reference only Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the Thermal Control Circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The Thermal Monitor feature must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Clocks will not be off for more than 3 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near it
41. 60 4 VID 0 080 gt VID 0 100 gt VID 0 120 1 Typical d VID 0 140 4 Voc Minimum VID 0 160 VID 0 180 VID 0 200 NOTES 1 The Vcc and Voc loadlines represent static and transient limits Please see Section 2 11 1 for Voc overshoot specifications 2 The Vcc and Vcc loadlines are plots of the discrete point found in Table 10 3 Refer to Table 9 for processor VID information 4 The loadlines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins Voltage regulation feedback for voltage regulator circuits must be taken from processor Vcc and Vss pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines for socket loadline guidelines and VR implementation Datasheet 29 2 11 1 Table 11 Figure 4 30 Vcc Overshoot Specification Intel The Low Voltage Intel processor with 800 MHz system bus can tolerate short transient overshoot events where exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCCSENSE and VSSSENSE pins Vcc Overshoot Specifications Symbol Parameter Min Max Units Fi
42. 7 Common Clk I O TCK E24 TAP Input N C Y29 N C N C TDI C24 TAP Input N C AA28 N C N C TDO E25 TAP Output N C AA29 N C N C TEST BUS A16 Power Other Input N C 28 N C N C TESTHIO W6 Power Other Input N C AB29 N C N C TESTHH W7 Power Other Input N C AC28 N C N C TESTHI2 W8 Power Other Input N C AC29 N C N C TESTHI3 Y6 Power Other Input N C AD28 N C TESTHI4 AA7 Power Other Input N C AD29 TESTHI5 AD5 Power Other Input N C AE30 N C N C TESTHI6 Power Other Input ODTEN B5 Power Other Input THERMDA Y27 Power Other Output OPTIMIZED COMPAT C1 Power Other Input THERMDC Y28 Power Other Output PROCHOT B25 Async GTL Output THERMTRIP F26 Async GTL Output PWRGOOD AB7 Async GTL Input TMS A25 TAP Input REQO B19 Source Sync I O TRDY E19 Common Clk Input 1 21 Source Sync I O TRST F24 TAP Input REQ2 C21 Source Sync I O VCC A2 Power Other REQ3 C20 Source Sync VCC A8 Power Other REQ4 B22 Source Sync I O VCC A14 Power Other Reserved A26 Reserved Reserved VCC A18 Power Other Reserved D25 Reserved Reserved VCC A24 Power Other Reserved W3 Reserved Reserved VCC A28 Power Other Reserved Y3 Reserved Reserved VCC A30 Power Other Reserved AC1 Reserved Reserved VCC B6 Power Other Reserved AE15 Reserved Reserved VCC B20 Power Other Reserved AE16 Reserved Reserved VCC B26 Power Other Reserved AE28 Reserved Reserved VCC B29 Power Other Reserved AE29 Reserved Rese
43. 75 1 0 0 0 1 0 1 0250 1 1 0 0 1 0 1 4000 0 0 0 0 1 0 1 0375 0 1 0 0 1 0 1 4125 1 0 0 0 0 1 1 0500 1 1 0 0 0 1 1 4250 0 0 0 0 0 1 1 0625 0 1 0 0 0 1 1 4375 1 0 0 0 0 0 1 0750 1 1 0 0 0 0 1 4500 0 0 0 0 0 0 1 0875 0 1 0 0 0 0 1 4625 1 1 1 1 1 1 OFF 1 0 1 1 1 1 1 4750 0 1 1 1 1 1 OFF 0 0 1 1 1 1 1 4875 1 1 1 1 1 0 1 1000 1 0 1 1 1 0 1 5000 0 1 1 1 1 0 1 1125 0 0 1 1 1 0 1 5125 1 1 1 1 0 1 1 1250 1 0 1 1 0 1 1 5250 0 1 1 1 0 1 1 1375 0 0 1 1 0 1 1 5375 1 1 1 1 0 0 1 1500 1 0 1 1 0 0 1 5500 0 1 1 1 0 0 1 1625 0 0 1 1 0 0 1 5625 1 1 1 0 1 1 1 1750 1 0 1 0 1 1 1 5750 0 1 1 0 1 1 1 1875 0 0 1 0 1 1 1 5875 1 1 1 0 1 0 1 2000 1 0 1 0 1 0 1 6000 NOTES 1 When this VID pattern is observed the voltage regulator output should be disabled Datasheet 17 2 5 18 intel Reserved or Unused Pins Reserved pins must remain unconnected Connection of these pins to Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 5 0 for a pin listing of the processor and the location of all Reserved pins For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level In a system level design on die termination has been included by the processor to allow end agents to be terminated within the processor silicon for most signals In this context end agent refers to the bus agent that resides on either end o
44. 8 1271 r 0 170 5 2101021 vez 0B PUTER zy 2601 2 161021 907 og 10917 5 21539 50761 H WH LE ig 002711 2 9 2 1800 1 0 0 7 JLYYLSENS 30 2 4 215 8 1796 9 1800 1 8070 1Nv1V3S SHI 15171 968 0811 SHI 5165071 1 nun a teeo 1 i amp m NIA 14033 V 1919717 1119711 2 672 8 99 1119711 8 ey Sp er 8 NIN SLN3ANO2 IS382N 1 708845 TIN M31 NOLLOG 3015 401 is Figure 6 Datasheet 36 Processor Package Drawing Sheet 2 of 2 Figure 7 30 Z 1338s 31455 104 OG 1 3195 5118 2096 vo VINYS du09 l 9r026V 3 6118S 109 0i yaana 3002 3ovo 3215 CA8 931102 OISSIN 40 1 1 30 5 N31 WOLLOS E 166071 4 1H913H IN3NOdAO2 J1GVMOTTY XVN S d es t MN MM et m m pare m MN m et SPOS eRe gt 100471 1721 tib ee tette eh ti tet ten pear aren ararar ana Beetboreceetsstekbeestbosevts 88958854888 rar arena ar er ares ee ee ee cete tn 301 NAIA 401
45. AB13 D52 Source Sync I O AC22 VCC Power Other AB14 VCC Power Other AC23 D23 Source Sync I O AB15 037 Source Sync AC24 020 Source Sync I O AB16 032 Source Sync I O AC25 VSS Power Other AB17 D31 Source Sync I O AC26 D17 Source Sync I O AB18 VCC Power Other AC27 DBIO Source Sync I O AB19 D14 Source Sync I O AC28 N C N C N C AB20 D12 Source Sync I O AC29 N C N C N C AB21 VSS Power Other 0 SLEW CTRL Power Other Input AB22 D13 Source Sync I O 1 VCC Power Other AB23 09 Source Sync AD1 VCCPLL Power Other Input AB24 VCC Power Other AD2 VCC Power Other 25 D8 Source Sync I O ADS VSS Power Other AB26 D7 Source Sync I O AD4 VCCIOPLL Power Other Input AB27 VSS Power Other AD5 TESTHI5 Power Other Input AB28 N C N C N C AD6 VCC Power Other AB29 N C N C N C AD7 D57 Source Sync I O AB30 VCC Power Other AD8 D46 Source Sync I O AB31 VSS Power Other AD9 VSS Power Other AC1 Reserved Reserved Reserved AD10 D45 Source Sync I O AC2 VSS Power Other AD11 D40 Source Sync I O AC3 VCC Power Other AD12 VTT Power Other 68 Datasheet intel Table 22 Pin Listing by Pin Number Sheet 8 of 8 5 amp Direction T Nob Direction AD13 D38 Source Sync I O AE7 D58 Source Sync I O AD14 D39 Source Sync
46. Commonly used terms are explained here for clarification Low Voltage Intel Xeon Processor with 800 MHz System Bus Intel 32 bit microprocessor intended for single dual processor applications The Low Voltage Intel Xeon processor with 800 MHz system bus is based on Intel s 90 nm process and will include core frequency improvements a large cache array microarchitectural improvements and additional instructions The Low Voltage Intel Xeon processor with 800 MHz system bus will use the mPGA604 socket For this document processor is used as the generic term for the Low Voltage Intel Xeon processor with 800 MHz system bus Central Agent The central agent is the host bridge to the processor and is typically known as the chipset Datasheet Data tel sheet Enterprise Voltage Regulator Down EVRD DC DC converter integrated onto the system board that provide the correct voltage and current for the processor based on the logic state of the VID bits Flip Chip Micro Pin Grid Array FC mPGA4 Package The processor package is a Flip Chip Micro Pin Grid Array FC mPGA4 consisting of a processor core mounted on a pinned substrate with an integrated heat spreader IHS This package technology employs a 1 27 mm 0 05 in pitch for the processor pins Front Side Bus FSB The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the syste
47. D integer and memory management operations In addition SSE3 instructions have been added to further extend the capabilities of Intel processor technology Other processor enhancements include core frequency improvements and microarchitectural improvements The Low Voltage Intel Xeon processor with 800 MHz system bus supports Intel Extended Memory 64 Technology Intel EM64T as an enhancement to Intel s IA 32 architecture This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Further details on Intel Extended Memory 64 Technology and its programming model can be found in the 64 bit Extension Technology Software Developer s Guide at http developer intel com technology 64bitextensions The Low Voltage Intel Xeon processor with 800 MHz system bus is intended for high performance systems with up to two processors on one system bus The processor will be packaged in a 604 pin Flip Chip Micro Pin Grid Array 4 package and will use a surface mount Zero Insertion Force ZIF socket mPGA 604 Features of the Low Voltage Intel Xeon Processor with 800 MHz System Bus No of Supported L2 Advanced Symmetric Transfer b nnd E Package Agents Cache Low Voltage Intel 604 pin processor with 800 MHz system 1 2 1 800 MHz FC mPGA4 bus 1 1 10 intel Platforms based on the Low Voltage Intel
48. D2 Source Sync I O W3 Reserved Reserved Reserved Y25 VSS Power Other WA VSS Power Other Y26 DO Source Sync I O W5 BCLK1 Sys Bus Clk Input Y27 THERMDA Power Other Output W6 TESTHIO Power Other Input Y28 THERMDC Power Other Output W7 TESTHI1 Power Other Input Y29 N C N C N C W8 TESTHI2 Power Other Input Y30 VCC Power Other W9 GTLREF Power Other Input 1 VSS Power Other W23 GTLREF Power Other Input 1 VCC Power Other W24 VSS Power Other AA2 VSS Power Other W25 VCC Power Other AA3 BSELO Power Other Output W26 VSS Power Other AA4 VCC Power Other W27 VCC Power Other 5 VSSA Power Other Input W28 VSS Power Other AA6 VCC Power Other weg Power Other TESTHI4 Power Other Input W30 VSS Power Other 061 Source Sync I O W31 VCC Power Other AA9 VSS Power Other Y1 VSS Power Other AA10 D54 Source Sync I O Y2 VCC Power Other 11 D53 Source Sync I O Reserved Reserved Reserved AA12 VTT Power Other Y4 BCLKO Sys Bus Input AA13 D48 Source Sync I O Y5 VSS Power Other AA14 D49 Source Sync I O Y6 TESTHIS Power Other Input AA15 VSS Power Other Y7 VSS Power Other AA16 D33 Source Sync I O Y8 RESET Common Clk Input 17 VSS Power Other Y9 D62 Source Sync I O AA18 D24 Source Sync I O Y10 VTT Power Other AA19 D15 Source Sync I O 11 DSTBP3 Source Sync I O AA20 VCC Power Other Y12 DSTBN3 Source Sync I O AA21 011 Source Sync I O
49. D23 Common Clk Input A16 C14 Source Sync I O BRO D20 Common Clk I O A17 D16 Source Sync I O 1 F12 Common Input A188 015 Source Sync 2 E11 Common Clk Input 19 F15 Source Sync BR3 D10 Common Clk Input A20 A10 Source Sync I O BSELO Power Other Output A211 B10 Source Sync BSEL1 ABS Power Other Output A22 B11 Source Sync I O COMPO AD16 Power Other Input A23 C12 Source Sync I O 1 E16 Power Other Input A24 E14 Source Sync I O DO Y26 Source Sync I O A25 D13 Source Sync I O 01 27 Source Sync I O A26 AQ Source Sync I O D2 Y24 Source Sync I O A27 B8 Source Sync I O D3 AA25 Source Sync I O A28 E13 Source Sync I O D4 AD27 Source Sync I O 29 012 Source Sync 05 Y23 Source Sync I O A30 C11 Source Sync I O D6 AA24 Source Sync I O A311 B7 Source Sync 07 AB26 Source Sync I O A32 A6 Source Sync I O D8 AB25 Source Sync I O A33 A7 Source Sync I O 09 AB23 Source Sync I O A34 C9 Source Sync 010 22 Source Sync I O A35 C8 Source Sync I O 011 21 Source Sync I O 20 F27 Async GTL Input 012 20 Source Sync I O ADS D19 Common Clk I O D13 AB22 Source Sync I O ADSTBO F17 Source Sync I O D14 AB19 Source Sync I O ADSTB1 F14 Source Sync I O D15 19 Source Sync I O APO E10 Common Clk I O D16 AE26 Source Sync I O 54 Datasheet
50. Datasheet intel Figure 12 Low Voltage Intel Xeon Processor with 800 MHz System Bus Thermal Profile 100 80 4 Thermal Profile 704 Y 0 56 x 55 60 4 504 Tcase 40 30 4 20 0 5 10 15 20 25 30 35 40 45 50 55 60 Power W TDP NOTES 1 Please refer to Table 24 for discrete points that constitute the thermal profile 2 Utilization of thermal solutions that do not meet the Thermal Profile do not meet the processor s thermal specifications and may result in permanent damage to the processor 3 Refer to the Low Voltage Nocona Processor 800 MHz in Embedded Applications Thermal Design Guidelines for system and environmental implementation details Table 24 Low Voltage Intel Xeon Processor with 800 MHz System Bus Thermal Profile Power W Tease Datasheet 73 6 1 2 Figure 13 6 2 6 2 1 74 intel The maximum case temperatures Asp are specified in Table 23 and Table 24 and measured at the geometric top center of the processor integrated heat spreader IHS Figure 13 illustrates the location where temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the appropriate thermal mechanical design guide Thermal Metrology Case Temperature Measurement Location 21 25 mm 0 837 in Measure from edge of processor 21 2
51. I O AE8 VCC Power Other AD15 VSS Power Other AE9 D44 Source Sync I O AD16 COMPO Power Other Input AE10 D42 Source Sync I O AD17 VSS Power Other AE11 VSS Power Other AD18 D36 Source Sync I O AE12 DBI2 Source Sync I O AD19 D30 Source Sync I O AE13 D35 Source Sync I O AD20 VCC Power Other AE14 VCC Power Other AD21 D29 Source Sync I O AE15 Reserved Reserved Reserved AD22 Source Sync I O AE16 Reserved Reserved Reserved AD23 VSS Power Other AE17 DP3 Common Clk I O AD24 D21 Source Sync I O AE18 VCC Power Other AD25 D18 Source Sync I O AE19 DP1 Common Clk I O AD26 VCC Power Other AE20 D28 Source Sync I O AD27 D4 Source Sync I O AE21 VSS Power Other AD28 N C N C N C AE22 D27 Source Sync I O AD29 N C N C AE23 D22 Source Sync I O AD30 VCC Power Other AE24 VCC Power Other AD31 VSS Power Other AE25 D19 Source Sync I O AE2 VSS Power Other AE26 D16 Source Sync I O AE3 VCC Power Other AE27 VSS Power Other AE4 SMB_PRT Power Other Output AE28 Reserved Reserved Reserved AE5 TESTHI6 Power Other Input AE29 Reserved Reserved Reserved AE6 SLP Async GTL Input AE30 N C N C N C NOTE systems using the Low Voltage Intel processor with 800 MHz system bus the system designer must pull up these signals to the processor V r Datasheet 69 70 THIS PAGE INTENTIONALLY LEF
52. I O B13 A13 Source Sync I O A7 A33 Source Sync I O B14 A12 Source Sync I O A8 VCC Power Other B15 VSS Power Other AQ A26 Source Sync I O B16 A114 Source Sync I O A10 A20 Source Sync I O B17 VSS Power Other A11 VSS Power Other B18 Abit Source Sync I O A12 A148 Source Sync B19 REQO Source Sync I O A13 A10 Source Sync I O B20 VCC Power Other A14 VCC Power Other B21 REQ1 Source Sync A15 FORCEPR Async GTL Input B22 REQ4 Source Sync I O A16 TEST_BUS Power Other Input B23 VSS Power Other A17 LOCK Common Clk I O B24 LINTO INTR Async GTL Input A18 VCC Power Other B25 PROCHOT Power Other Output A19 7 Source Sync B26 VCC Power Other A20 A4 Source Sync I O B27 VCCSENSE Power Other Output A21 VSS Power Other B28 VSS Power Other A22 Source Sync B29 VCC Power Other A23 HITM Common I O B30 VSS Power Other A24 VCC Power Other B31 VCC Power Other A25 TMS TAP Input C1 OPTIMIZED COMPAT Power Other Input A26 Reserved Reserved Reserved C2 VCC Power Other A27 VSS Power Other C3 VID3 Power Other Output A28 VCC Power Other C4 VCC Power Other A29 VSS Power Other C5 VTT Power Other A30 VCC Power Other C6 Common Input A31 VSS Power Other C7 VSS Power Other B1 VIDPWRGD Power Other Input C8 A35 Source Sync I O B2 VSS Power Other C9 A34 Source Sync I O B3 VIDA Power Other Output C10 VTT Power Other B4 VTT Power Other C11 A30 Source Sync I O B5 OTDEN
53. I O DSTBN2 Y15 Source Sync I O 038 AD13 Source Sync DSTBN3 Y12 Source Sync I O 039 AD14 Source Sync I O DSTBPO Y20 Source Sync I O D40 AD11 Source Sync I O DSTBP1 Y17 Source Sync I O D41 12 Source Sync I O DSTBP2 Y14 Source Sync I O D42 AE10 Source Sync I O DSTBP3 Y11 Source Sync I O D43 AC11 Source Sync I O FERR PBE E27 Async GTL Output D44 Source Sync FORCEPR A15 Async GTL Input D45 AD10 Source Sync I O GTLREF W23 Power Other Input D46 AD8 Source Sync I O GTLREF W9 Power Other Input D47 AC9 Source Sync I O GTLREF F23 Power Other Input D48 AA13 Source Sync I O GTLREF F9 Power Other Input D49 AA14 Source Sync I O HIT E22 Common Clk I O D50 AC14 Source Sync I O HITM A23 Common Clk I O D51 AB12 Source Sync I O IERR E5 Async GTL Output D52 AB13 Source Sync I O IGNNE C26 Async GTL Input D53 AA11 Source Sync I O INIT D6 Async GTL Input D54 AA10 Source Sync I O LINTO INTR B24 Async GTL Input D55 AB10 Source Sync I O LINT1 NMI G23 Async GTL Input D56 AC8 Source Sync I O LOCK A17 Common Clk I O Datasheet 55 Table 21 Pin Listing by Pin Name Sheet 3 of 8 Intel Pin Name Direction Pin Name Direction MCERR D
54. MAX 0 5 Vuvs MIN V 4 Threshold Voltage 7 Output High Voltage N A Vit V 4 lon Output Low Current 45 mA 5 Iu Input Leakage Current N A 200 lio Output Leakage Current N A 200 Buffer On Resistance 7 11 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 All outputs are open drain 3 represents the amount of hysteresis nominally centered about 0 5 for all PWRGOOD and inputs 4 The represented in these specifications refers to instantaneous VT 5 The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load Table 15 GTL Asynchronous and AGTL Asynchronous Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vi Input Low Voltage 0 0 GTLREF 0 10 V 2 3 Input High Voltage GTLREF 0 10 V 2 4 5 Vou Output High Voltage 0 90 Vi Vit V 2 5 lot Output Low Current N A mA 2 6 0 50 RTT Ron_min lu Input Leakage Current N A 200 7 8 Output Leakage Current N A 200 7 8 Ron Buffer On Resistance 7 11 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vr1 represented in these specifications refers to instantaneous Vr 3 Vi is defined as the voltage range at a receiving agent that will be interpreted as
55. MHz system bus operate with the same front side bus frequency core frequency and have the same internal cache sizes Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel Note Processors within a system must operate at the same frequency per bits 15 8 of the IA 32 FLEX BRVID SEL MSR however this does not apply to frequency transitions initiated due to thermal events or assertion of the FORCEPR signal See Section 6 0 Not all operating systems can support dual processors with mixed frequencies Intel does not support or validate operation of processors with different cache sizes Mixing processors of different steppings but the same model as per CPUID instruction is supported Please see the Intel Xeon Processor with 800 MHz System Bus Specification Update for the applicable mixed stepping table Details regarding the CPUID instruction are provided in the Intel Processor Identification and the CPUID Instruction application note Datasheet In 2 10 Table 8 Datasheet Absolute Maximum and Minimum Ratings Table 8 specifies absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to co
56. Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no pins can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any tray or packaging 23 2 11 24 intel Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless noted otherwise See Section 5 1 for the Low Voltage Intel Xeon processor with 800 MHz system bus pin listings and Section 4 1 for signal definitions Voltage and current specifications are detailed in Table 9 For platform power delivery planning refer to Table 10 which provides static and transient tolerances This same information is presented graphically in Figure 3 BSEL 1 0 and VID 5 0 signals are specified in Table 12 The DC specifications for the AGTL signals are listed in Table 13 The DC specifications for the PWRGOOD input and TAP signal group are listed in Table 14 and the Asynchronous signal group is listed in Table 15 Table 9 through Table 15 list the DC specifications for the processor and are valid only while meeting specifications for case temperature as specified in Section 6 0 clock frequency and input voltages Care sh
57. T BLANK Datasheet intel 6 0 Thermal Specifications 6 1 6 1 1 Datasheet Package Thermal Specifications The Low Voltage Intel processor with 800 MHz system bus requires a thermal solution to maintain temperatures within operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heat sinks attached to the processor Integrated Heat Spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting For more information on designing a component level thermal solution refer to the Low Voltage Intel Xeon Processor with 800 MHz System Bus in Embedded Applications Thermal Mechanical Design Guidelines Thermal Specifications To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature specifications as defined by the applicable thermal profile see Table 23 and Figure 12 T
58. a logical low value 4 is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 5 and Voy may experience excursions above 6 Refer to Table 2 5 to determine which signals include additional on die termination resistance 7 Leakage to Vss with pin held at Vr 8 Leakage to with pin held at 300 mV 32 Datasheet intel Table 16 Datasheet VIDPWRGD DC Specifications Symbol Parameter Min Max Unit Vit Input Low Voltage 0 0 0 30 V Input High Voltage 0 90 Vit V 33 34 THIS PAGE INTENTIONALLY LEFT BLANK Datasheet Mechanical Specifications Figure 5 3 1 Datasheet The Low Voltage Intel Xeon processor with 800 MHz system bus is packaged in Flip Chip Micro Pin Grid Array FC mPGA4 package that interfaces to the baseboard via an mPGA604 socket The package consists of a processor core mounted on a substrate pin carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heat sink Figure 5 shows a sketch of the processor package components and how they are assembled together Refer to the mPGA604 Socket Design Guidelines for complete details on the mPGA604 socket The package components shown in Figure 5 include the following 1 Integrated Heat Spreader IHS 2 Processor die 3 Substrate
59. agents wired OR Datasheet Table 6 Table 7 Datasheet Table 6 outlines the signals which include on die termination and lists signals which include additional on die resistance Open drain signals are also included Table 7 provides signal reference voltages Signal Description Table Signals with Rr Signals with No 35 3 ADS 1 0 0 BINIT BNR SELECT BPRI D 63 0 DBI 3 0 DBSY DEFER DP 3 0 t DRDY DSTBN 3 0 DSTBP 3 0 FORCEPR HIT HITM LOCK MCERR OPTIMIZED COMPAT 2 4 0 RS 2 0 RSP SLEW_CTRL TEST_BUS TRDY A20M BCLK 1 0 BPM 5 0 BR 3 0 BSEL 1 0 1 0 FERR PBE GTLREF 3 0 IERR IGNNE INIT LINTO INTR LINT1 NMI ODTEN PROCHOT PWRGOOD RESET SLP SMI STPCLK TDI TESTHI 6 0 THERMDA THERMDC THERMTRIP TMS TRST VID 5 0 VIDPWRGD VTTEN Signals with RL Signals with No R BINIT BNR HIT HITM MCERR A20M 35 3 ADS ADSTB 1 0 1 0 BCLK 1 0 BPM 5 0 BR 3 0 BSEL 1 0 BOOT_SELECT COMP 1 0 D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FERR PBE FORCEPR GTLREF 3 0 IERR IGNNE INIT LINTO INTR LINT1 NMI LOCK ODTEN OPTIMIZED COMPAT 2 PROCHOT PWRGOOD 4 0 RESET RS 2 0 f RSP SKTOCC SLEW_CTRL SLP SMI STPCLK
60. and falling edge Strobes are associated with signals as shown below Signals Associated Strobes ADSTBO ADSTB1 REQ 4 0 16 3 A 85 17 amp 1 0 y o AP 1 0 Address Parity are driven by the request initiator along with ADS A 35 3 and the transaction type on the REQ 4 0 pins A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all Low Voltage Intel Xeon processor with 800 MHz System bus agents The following table defines the coverage model of these signals Request Signals Sub Phase 1 Sub Phase 2 35 24 1 23 3 1 BCLK 1 0 The differential bus clock pair BCLK 1 0 determines the front side bus frequency All processor front side bus agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing VcnRoss Datasheet 43 Table 20 Signal Definitions Sheet 2 of 9 Name Type Description Notes BINIT y o BINIT Bus Initialization may be observed and driven by all processor front side bus agents and if used must connect the appropriate pins of a
61. ant state are out of specification and may results in illegal operation Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP or RESET are allowed on the front side bus while the processor is in Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant state If RESET is driven active while the processor is in the Sleep state the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the reset sequence When the processor is in Sleep state it will not respond to interrupts or snoop transactions 83 84 THIS PAGE INTENTIONALLY LEFT BLANK Datasheet Debug Tools Specifications 8 1 Note 8 2 8 2 1 8 3 Datasheet Please refer to the 7 700 Debug Port Design Guide for information regarding debug tool specifications Section 1 2 provides collateral details Debug Port System Requirements The Low Volta
62. are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all processor front side bus agents DRDY y o DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor front side bus agents DSTBN 3 0 y o Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBIO DSTBNO 0 31 16 DBI1 DSTBN1 0 47 32 DBI2 DSTBN2 D 63 48 DBIS DSTBN3 DSTBP 3 0 4 y o Data strobe used to latch in D 63 0 Signals Associated Strobes 0 15 0 DBIO DSTBPO 0 31 16 DBI1 DSTBP1 0 47 32 DBI2 DSTBP2 D 63 48 ft DBIS DSTBP3 46 Datasheet intel Table 20 Signal Definitions Sheet 5 of 9 Name Type Description Notes FERR PBE FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK t is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLKst is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with s
63. bus stall at the same time BNR is a wired OR signal which must connect the appropriate pins of all processor front side bus agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers is activated on specific clock edges and sampled on specific clock edges BOOT_ SELECT The BOOT_SELECT input informs the processor whether the platform supports the Low Voltage Intel Xeon processor with 800 MHz system bus The processor will not operate if this signal is low This input has a weak pull up to 5 0 y o 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance 5 0 should connect the appropriate pins of all front side bus agents provides PRDY Probe Ready functionality for the port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents These signals do not have on die termination and must be terminated at the end agent BPRI Bus Priority Request is used to arbitrate for ownership of the processor front side b
64. cessor with 800 MHz system bus the maximum number of symmetric agents is 51 52 THIS PAGE INTENTIONALLY LEFT BLANK Datasheet intel 5 0 Pin List 5 1 Datasheet Low Voltage Intel Xeon Processor with 800 MHz System Bus Pin Assignments This section provides sorted pin lists in Table 21 and Table 22 Table 21 is a listing of all processor pins ordered alphabetically by pin name Table 22 is a listing of all processor pins ordered by pin number 53 5 1 1 Pin Listing by Pin Name Table 21 Pin Listing by Pin Name Sheet 1 of 8 Pin Name d esc m Direction Pin Name S ek Direction 22 Source Sync I O AP1 D9 Common Clk I O A4 A20 Source Sync I O BCLKO 4 Sys Bus Input Abit B18 Source Sync I O BCLK1 W5 Sys Bus Input A6 C18 Source Sync I O BINIT F11 Common Clk I O A7 A19 Source Sync I O BNR F20 Common Clk I O A8 C17 Source Sync I O BOOT_SELECT G7 Power Other Input 9 017 Source Sync I O BPMO F6 Common I O A103 A13 Source Sync I O 1 F8 Common Clk I O 11 B16 Source Sync 2 E7 Common Clk I O A12 B14 Source Sync I O BPM3 F5 Common Clk I O A13 B13 Source Sync I O BPM4 E8 Common Clk I O 14 12 Source Sync 5 4 Common Clk I O A15 C15 Source Sync I O BPRI
65. cifications Symbol Parameter Min Max Unit Notes Vi Input Low Voltage 0 0 0 10 V 2 3 Input High Voltage GTLREF V 2 4 5 0 10 Vou Output High Voltage 0 90 V 2 5 lot Output Low Current N A mA 2 6 0 50 Row li Input Leakage Current N A 200 7 8 lio Output Leakage Current N A 200 7 8 Ron Buffer On Resistance 7 11 Ww NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The represented in these specifications refers to instantaneous Vr 3 is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 4 is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 5 and Voy may experience excursions above 6 Refer to Table 6 to determine which signals include additional on die termination resistance 7 Leakage to Vss with pin held at 8 Leakage to with pin held at 300 mV Datasheet 31 Table 14 PWRGOOD Input and TAP Signal Group DC Specifications Symbol Parameter Min Max Unit Noles Vuvs Input Hysteresis 200 350 mV Vie Input Low to High 0 5 Vrr t Vuys MIN 0 5 t Vuvs MAX V 4 Threshold Voltage m 7 V Input High to Low 0 5 Vuvs
66. ducts are not intended for use in medical life saving life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Low Voltage Intel Xeon processor with 800 MHz system bus may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Hyper Threading Technology requires a computer system with an Intel Pentium 4 processor supporting HT Technology and a HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use See Hyper Threading Technology http developer intel com products ht Hyperthreading more htm for more information Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Intel Pentium Intel Xeon Intel Inside Intel
67. e specifications This thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor Thermal Diode Parameters Symbol Symbol Min Typ Max Unit Notes lew Forward Bias Current 11 187 1 n Diode ideality factor 1 0083 1 011 1 0183 2 3 4 Series Resistance 3 242 3 33 3 594 Ww 2 3 5 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Characterized at 75 3 Not 10095 tested Specified by design characterization 4 The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation lpw lg e VD nkT 1 Where saturation current q electronic charge VD voltage across the diode Boltzmann Constant and T absolute temperature Kelvin 5 The series resistance is provided to allow for a more accurate measurement of the junction temperature as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and external remote diode thermal sensor can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term Another application that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by
68. e wired OR signals which must connect the appropriate pins of all processor front side bus agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers HIT and HITM are activated on specific clock edges and sampled on specific clock edges IERR IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor front side bus This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination and must be terminated at the end agent IGNNE IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute non control floating point instructions If IGNNE is deasserted the processor generates an exception on a non control floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction INIT INIT Initialization when asserted resets integer registers inside
69. e assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state HALT Snoop State or Snoop State The processor will respond to snoop or interrupt transactions on the front side bus while in Stop Grant state or in HALT Power Down state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or HALT Power Down state as appropriate Datasheet In 7 2 5 Datasheet Sleep State The Sleep state is a very low power state in which each processor maintains its context maintains the phase locked loop PLL and has stopped most of internal clocks The Sleep state can only be entered from Stop Grant state Once in the Stop Grant state the processor will enter the Sleep state upon the assertion of the SLP signal The SLP pin has a minimum assertion of one BCLK period The SLP pin should only be asserted when the processor is in the state For Low Voltage Intel Xeon processor with 800 MHz system bus the SLP pin may only be asserted when all logical processors are in the Stop Grant state SLP assertions while the processors are not in the Stop Gr
70. e margin all pull up resistor values used for TESTHI 6 0 should have a resistance value within 20 of the impedance of the baseboard transmission line traces For example if the trace impedance is 50 than a value between 40 60 should be used THERMDA Other Thermal Diode Anode See Section 6 2 7 THERMDC Other Thermal Diode Cathode See Section 6 2 7 THERMTRIP Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through an internal thermal sensor Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP Driving of the THERMTRIP signals is enabled within 10 ms of the assertion of PWRGOOD and is disabled on de assertion of PWRGOOD Once activated THERMTRIP remains latched until PWRGOOD is de asserted While the de assertion of the PWRGOOD signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP5 will again be asserted within 10 ms of the assertion of PWRGOOD TMS TMS Test Mode Select is a JTAG specification support signal used by debug tools This signal does not
71. e system ground plane The processor pins must be supplied with the voltage determined by the processor Voltage IDentification VID pins Eleven signals are denoted as which provide termination for the front side bus and power to the I O buffers The platform must implement a separate supply for these pins which meets the V rr specifications outlined in Table 9 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the Low Voltage Intel Xeon processor with 800 MHz system bus is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cau such as electrolytic or aluminum polymer capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 9 Failure to do so can result in timing violations or reduced lifetime of the component Vcc Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and the baseboard designer must assure a low interconnect resistance f
72. ect indus 74 6 2 2 On Demand 75 0 2 3 oro Eee Pete 75 62 4 FORGEPR Signal Pin iieri 75 6 2 5 THERMTRIPs Signal Pit E pir teri pe ont gere eti Pe iuda 76 6 2 6 TCONTROL and Fan Speed 76 6 2 7 Lhermal Di de z iac tef tt uere ee Er ea dee eda 76 anaes 79 7 1 Power On Configuration 79 7 2 Clock Control and Low Power States 79 7 2 1 Normal St dte uc oic di eee eh 80 T22 HAET Power Down State nei eet ice vetat 80 1 2 3 Otop Grant tale tdeo tente 82 7 2 4 HALT Snoop State or Snoop 82 Stale ie eee at ani 83 Debug Tools Specifications 85 8 1 Debug Port System Requirements eene enn 85 8 2 Target System nnne nennen 85 8 2 1 System Implementation nennen 85 8 3 Logic Analyzer Interface LAI 85 8 3 1 Mechanical eene 86 8 32 Electrical Consideratioris
73. erating system allows memory to be marked as executable or non executable When code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel Architecture Software Developer s Manual for more detailed information Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the asserted state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 refers to a hex A and D 3 0 also refers to a hex A H High logic level L Low logic level Front side bus or System bus refers to the interface between the processor system core logic also known as the chipset components and other bus agents The system bus is a multiprocessing interface to processors memory and I O For this document front side bus or system bus are used as generic terms for the Low Voltage Intel Xeon processor with 800 MHz system bus
74. f the daisy chained front side bus interface while a middle agent is any bus agent in between the two end agents For end agents most unused AGTL inputs should be left as no connects as termination is provided on the processor silicon However see Table 6 for details on AGTL signals that do not include on die termination For middle agents the on die termination must be disabled so the platform must ensure that unused AGTL input signals which do not connect to end agents are connected to via pull up resistor Unused active high inputs should be connected through a resistor to ground Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the baseboard trace for front side bus signals For unused input or I O signals use pull up resistors of the same value as the on die termination resistors Asynchronous inputs and Asynchronous outputs do not include on die termination Inputs and utilized outputs must be terminated on the baseboard Unused outputs may be terminated on the baseboard or left unconnected Note that leaving unused outputs unterminated may
75. face LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Low Voltage Intel processor with 800 MHz system bus systems Tektronix and Agilent should be contacted to obtain specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Low Voltage Intel processor with 800 MHz system bus based multiprocessor systems the LAI is critical in providing the ability to probe and capture front side bus signals There are two sets of considerations to keep in mind when designing a Low Voltage Intel Xeon processor with 800 MHz system bus based system that can make use of an LAT mechanical and electrical 85 8 3 1 8 3 2 86 intel The is installed between the processor socket and the processor The LAI pins plug into the socket while the processor pins plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout
76. formation 79 7 2 1 7 2 2 80 intel Due to the inability of processors to recognize bus transactions during the Sleep state multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the other processors in Normal or Stop Grant state Normal State This is the normal operating state for the processor HALT Power Down State HALT is a low power state entered when all logical processors have executed the HALT or MWAIT instruction When one of the logical processors executes the HALT or MWAIT instruction that logical processor is halted however the other processor continues normal operation The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or an interrupt delivered over the front side bus RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the 32 Intel Architecture Software Developer s Manual Volume III System Programming Guide for more information The system can generate a STPCLK while the processor is in the HALT Power Down state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state While in HALT Power Down state the processor will process front side bus snoops and interrupts Datasheet Intel Figure 14 Stop Clock Sta
77. frequency The filter requirements are illustrated in Figure 1 Phase Lock Loop PLL Filter Requirements TM c4 uos ae Zee uos LEE rr a es 2 gt Sus DC 1Hz fpeak 1 MHz 66 MHz fcore 1 67 GHz lt gt lt 50 kHz 500 MHz High Passband Frequency CS00141 NOTES 1 Diagram not to scale 2 No specifications for frequencies beyond core frequency foeak If existent should be less than 0 05 MHz 4 represents the maximum core frequency supported by the platform 15 2 4 16 intel Voltage Identification VID The Voltage Identification VID specification for the Low Voltage Intel processor with 800 MHz system bus is defined by the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines The voltage set by the VID signals is the maximum voltage allowed by the processor please see Section 2 11 1 for overshoot specifications VID signals are open drain outputs which must be pulled up to Please refer to Table 12 for the DC specifications for these signals A minimum voltage is provided in Table 9 and changes with frequency This allows processors running at a higher frequency to have a relaxed minimum voltage specification The specifications have been set such that one voltage regulator can operate with all supported frequencies Individual
78. ge Intel Xeon processor with 800 MHz system bus debug port is the command and control interface for the In Target Probe ITP debugger The ITP enables run time control of the processors for system debug The debug port which is connected to the front side bus is a combination of the system JTAG and execution signals There are several mechanical electrical and functional constraints on the debug port that must be followed The mechanical constraint requires the debug port connector to be installed in the system with adequate physical clearance Electrical constraints exist due to the mixed high and low speed signals of the debug port for the processor While the JTAG signals operate at a maximum of 75 MHZ the execution signals operate at the common clock front side bus frequency 200 MHz The functional constraint requires the debug port to use the JTAG system via a handshake and multiplexing scheme In general the information in this chapter may be used as a basis for including all run control tools in Low Voltage Intel Xeon processor with 800 MHz system bus based system designs including tools from vendors other than Intel The debug port and JTAG signal chain must be designed into the processor board in order to use the ITP for debug purposes Target System Implementation System Implementation Specific connectivity and layout guidelines for the Debug Port are provided in the TP700 Debug Port Design Guide Logic Analyzer Inter
79. gure Notes Vos MAX Magnitude of Voc 0 050 V 4 2 overshoot above VID Tos Time duration of 25 us 4 B overshoot above VID Vcc Overshoot Example Waveform VID 0 050 Vos gt o 8 o gt VID 0 000 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID NOTES 1 Vog is measured overshoot voltage 2 Tog is measured time duration above VID Datasheet intel 2 11 2 Die Voltage Validation Overshoot events from application testing on processor must meet the specifications in Table 11 when measured across the VCCSENSE and VSSSENSE pins Overshoot events that are 10 ns in duration may be ignored These measurement of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope Table 12 BSEL 1 0 and VID 5 0 Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes Ron BSEL 1 0 and VID 5 0 N A 60 2 Buffer On Resistance lo Maximum Pin Current N A 8 mA 2 lio Output Leakage Current N A 200 2 3 ReuLL UP Pull Up Resistor 500 VTOL Voltage Tolerance 0 95 1 05 Vi V NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 These parameters are based on design characterization and are not tested 3 Leakage to Vgg with pin held at Table 13 AGTL Signal Group DC Spe
80. have on die termination and must be terminated at the end agent TRDY TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all front side bus agents TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset Veca Provides isolated power for the analog portion of the internal processor core PLLs VccioPLL provides isolated power for digital portion of the internal processor PLLs VccPLL The on die PLL filter solution will not be implemented on this platform The Vccp input should left unconnected VCCSENSE VSSSENSE VCCSENSE and VSSSENSE provide an isolated low impedance connection to the processor core power and ground They can be used to sense or measure power near the silicon with little noise VID 5 0 VID 5 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc These are open drain signals that are driven by the processor and must be pulled up through a resistor Conversely the VR output must be disabled prior to the voltage supply for these pins becomes invalid The VID pins are needed to support processor voltage specification variations See Table 4 for definitions of these pins The VR must supply the voltage that is requested by these
81. he individual processor BSEL 1 0 are open drain outputs which must be pulled up to and are used to select the front side bus frequency Please refer to Table 12 for DC specifications Table 3 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processor s chipset and clock synthesizer front side bus agents must operate at the same core and front side bus frequencies Individual processors will only operate at their specified front side bus clock frequency Datasheet Table 3 2 3 2 Figure 1 Datasheet BSEL 1 0 Frequency Table BSEL1 BSELO Bus Clock Frequency 0 0 Reserved 0 1 Reserved 1 0 200 MHz 1 1 Reserved Phase Lock Loop PLL and Filter and are power sources required by the PLL clock generators on the Low Voltage Intel Xeon processor with 800 MHz system bus Since these PLLs are analog in nature they require quiet power supplies for minimum jitter Jitter is detrimental to the system it degrades external I O timings as well as internal core timings 1 maximum frequency To prevent this degradation these supplies must be low pass filtered from The AC low pass requirements are as follows 02 dB gain in pass band e lt 0 5 dB attenuation in pass band lt 1 Hz gt 34 dB attenuation from 1 MHz to 66 MHz 28 dB attenuation from 66 MHz to core
82. hen the DBI signal is active the corresponding data group is inverted and therefore sampled active high Datasheet 45 Table 20 In Signal Definitions Sheet 4 of 9 Name Type Description Notes DBI 3 0 amp y o DBI 3 0 are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electronically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DBIO D 15 0 DBI 0 31 16 DBI2 D 47 32 DBI3 0163 48 DBSY y o DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor front side bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor front side bus agents DEFER DEFERZ is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the appropriate pins of all processor front side bus agents 3 0 y o DP 3 0 Data Parity provide parity protection for the 0 63 0 signals They
83. her VCC P30 Power Other VCC W29 Power Other VCC R1 Power Other VCC W31 Power Other VCC R3 Power Other VCC Y2 Power Other VCC R5 Power Other VCC Y16 Power Other VCC R7 Power Other VCC Y22 Power Other VCC R9 Power Other VCC Y30 Power Other VCC R23 Power Other VCC AA1 Power Other VCC R25 Power Other VCC 4 Power Other VCC R27 Power Other VCC AA6 Power Other VCC R29 Power Other VCC AA20 Power Other VCC R31 Power Other VCC AA26 Power Other VCC T2 Power Other VCC AA31 Power Other VCC T4 Power Other VCC AB2 Power Other VCC T6 Power Other VCC AB8 Power Other VCC T8 Power Other VCC AB14 Power Other VCC T24 Power Other VCC AB18 Power Other VCC T26 Power Other VCC AB24 Power Other VCC T28 Power Other VCC AB30 Power Other VCC T30 Power Other VCC AC3 Power Other VCC U1 Power Other VCC AC4 Power Other VCC U3 Power Other VCC AC16 Power Other VCC U5 Power Other VCC AC22 Power Other VCC U7 Power Other VCC 1 Power Other VCC U9 Power Other VCC AD2 Power Other VCC U23 Power Other VCC AD6 Power Other VCC U25 Power Other VCC AD20 Power Other VCC U27 Power Other VCC AD26 Power Other VCC U29 Power Other VCC AD30 Power Other VCC U31 Power Other VCC AE3 Power Other VCC V2 Power Other VCC AE8 Power Other VCC V4 Power Other VCC AE14 Power Other VCC V6 Power Other VCC AE18 Power Other VCC V8 Power Other VCC AE24 Power Other VCC V24 Power Other VCCA AB4 Power Other Input VCC V26 Power Other VCCIOPLL AD4 Power Other Input 58
84. hermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the appropriate processor thermal mechanical design guideline The Low Voltage Intel Xeon processor with 800 MHz system bus introduces a new methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and assure processor reliability Selection of the appropriate fan speed will be based on the temperature reported by the processor s Thermal Diode If the diode temperature is greater than or equal to Tcontrol see Section 6 2 6 then the processor case temperature must remain at or below the temperature as specified by the thermal profile see Figure 12 If the diode temperature is less than Tcontrol then the case temperature is permitted to exceed the thermal profile but the diode temperature must remain at or below Tcontrol Systems that implement fan speed control must be designed to take these conditions into account Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications Intel has developed a thermal profile for the Low Voltage Intel Xeon processor with 800 MHz system bus which can be implemented with the Low Voltage Intel Xeon processor with 800 MHz system bus It ensures adherence to Intel reliability requi
85. ific clock edges and sampled on specific clock edges ODTEN ODTEN On die termination enable should be connected to to enable on die termination for end bus agents For middle bus agents pull this signal down via a resistor to ground to disable on die termination Whenever ODTEN is high on die termination will be active regardless of other states of the bus OPTIMIZED This is an input to the processor to determine if the processor is in an optimized platform or a compatible platform This signal does includes a weak on die pull up to PROCHOT PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor die temperature has reached its factory configured trip point This indicates that the processor Thermal Control Circuit TCC has been activated if enabled See Section 6 2 3 for more details PWRGOOD PWRGOOD Power Good is an input The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable bef
86. ined in the mPGA604 Socket Design Guidelines Processor Mass Specifications The typical mass of the Low Voltage Intel Xeon processor with 800 MHz system bus is 25 grams 0 88 oz This mass weight includes all components which make up the entire processor product Processor Materials The Low Voltage Intel Xeon processor with 800 MHz system bus is assembled from several components The basic material properties are described in Table 19 Processor Materials Component Material Integrated Heat Spreader IHS Nickel over copper Substrate Fiber reinforced resin Substrate Pins Gold over nickel 39 intel 3 8 Processor Markings Figure 8 shows the topside markings and Figure 9 shows the bottom side markings on the processor These diagrams are to aid in the identification of the Low Voltage Intel processor with 800 MHz system bus Figure 8 Processor Top Side Markings Example 2D Matrix Processor Name Includes ATPO and Serial note Number front end mark ATPO Serial Number Pin 1 Indicator NOTES 1 All characters will be in upper case 2 Drawing is not to scale Figure 9 Processor Bottom Side Markings Example Pin 1 Indicator Pin Field Speed Cache Bus Voltage Y 3600DP 1MB 800 1 325V SL6ENY COSTA RICA S Spec C0096109 0021 Country of Assy FPO Serial 13 characters NOTES 1 A
87. initely and should be used for the voltage regulator temperature assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please see the applicable design guidelines for further details The processor is capable of drawing Icc indefinitely Refer to Figure 2 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested 16 This specification refers to platforms implementing a power delivery system that complies with VR 10 0 guidelines Please see the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines for further details 26 Datasheet Intel Figure 2 Low Voltage Intel Xeon Processor with 800 MHz System Bus Load Current vs Time VRM 10 0 VRM 10LV Current 62 61 60 59 58 57 Sustained Current A 56 55 0 01 0 1 1 10 100 1000 Time Duration s NOTES 1 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than 7 2 Not 100 tested Specified by design characterization Datasheet 27 Table 10 28 Vcc Static and Transient Tolerance Voltage Deviation from VID Setting V
88. interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the 7P700 Debug Port Design Guide See Section 1 2 All TESTHI 6 0 pins should be individually connected to via a pull up resistor which matches the nominal trace impedance TESTHI 3 0 and TESTHI 6 5 may be tied together and pulled up to with a single resistor if desired However usage of boundary scan test will not be functional if these pins are connected together TESTHIA must always be pulled up independently from the other TESTHI pins For optimum noise margin all pull up resistor values used for TESTHI 6 0 pins should have a resistance value within 20 of the impedance of the board transmission line traces For example if the nominal trace impedance is 50 then a value between 40 and 60 should be used N C no connect pins of the processor are not used by the processor There is no connection from the pin to the die These pins may perform functions in future processors intended for platforms using the Low Voltage Intel processor with 800 MHz system bus Datasheet Datasheet Front Side Bus Signal Groups front side bus signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF as a reference level In this document the term Input refers to the AGTL inp
89. is defined as a 2 second duration peak load superimposed on the static load requirement representative of loads experienced by the package during heat sink installation NO com Datasheet intel 3 4 Table 18 3 5 3 6 3 7 Table 19 Datasheet Package Handling Guidelines Table 18 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heat sink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N 1 4 5 80 Ibf Tensile 156N 2 4 5 35 Ibf Torque 8 N m 3 4 5 70 Ibf in NOTES 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 3 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization and incidental applications one time only 5 Handling guidelines are for the package only and do not include the limits of the processor socket Package Insertion Specifications The Low Voltage Intel Xeon processor with 800 MHz system bus can be inserted and removed 15 times from an mPGA604 socket which meets the criteria outl
90. itted Table 9 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 10 and Figure 3 The VRM or VRD used must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 9 and Table 10 Please refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines for further details Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable Datasheet Intel Table 4 Voltage Identification Definition VID5 VID4 VID3 VID2 VID1 VIDO Vcc max VID5 VID4 VID3 VID2 VID1 VIDO max 0 0 1 0 1 0 0 8375 0 1 1 0 1 0 1 2125 1 0 1 0 0 1 0 8500 1 1 1 0 0 1 1 2250 0 0 1 0 0 1 0 8625 0 1 1 0 0 1 1 2375 1 0 1 0 0 0 0 8750 1 1 1 0 0 0 1 2500 0 0 1 0 0 0 0 8875 0 1 1 0 0 0 1 2625 1 0 0 1 1 1 0 9000 1 1 0 1 1 1 1 2750 0 0 0 1 1 1 0 9125 0 1 0 1 1 1 1 2875 1 0 0 1 1 0 0 9250 1 1 0 1 1 0 1 3000 0 0 0 1 1 0 0 9375 0 1 0 1 1 0 1 3125 1 0 0 1 0 1 0 9500 1 1 0 1 0 1 1 3250 0 0 0 1 0 1 0 9625 0 1 0 1 0 1 1 3375 1 0 0 1 0 0 0 9750 1 1 0 1 0 0 1 3500 0 0 0 1 0 0 0 9875 0 1 0 1 0 0 1 3625 1 0 0 0 1 1 1 0000 1 1 0 0 1 1 1 3750 0 0 0 0 1 1 1 0125 0 1 0 0 1 1 1 38
91. ll characters will be in upper case 2 Drawing is not to scale 40 Datasheet 3 9 Figure 10 Datasheet Processor Pinout Coordinates Figure 10 and Figure 11 show the top and bottom view of the processor pin coordinates respectively The coordinates are referred to throughout the document to identify processor pins Processor Pinout Coordinates Top View Vcc Vss COMMON CLOCK COMMON ADDRESS CLOCK 9 11 13 15 17 19 21 23 e000 elo O o e olo ooceoole O O 6 O e o e o e o o e o e 06 69200000 09 e o e o e e o e o 6e 0 09 0009096 vjeoeoeoe 00000000 gt CLOCKS Intel Xeon Processor 800 MHz Top View e0o00e 00 0006006000 6 009 amp 00 0000000100000 0 Ooeooeo Async JTAG 25 27 29 31 O O e e e e oeoeeeej B e o o e e e eic ooceeeee p O e o e e e e E eocceeeer G H J K L M N P R T U V eoooo e j 6 6 AB e 00000 e AC 9 AD Oooeoo AE 10 12 14 16 18 20 22 24 26 28 30 DATA Signal GTLREF Power Reserved No Connect Ground SSA 99A 41 Figure 11 42 Processor Pinout Coordinates Bottom View Intel Vcc Vss Async COMMON ADDRESS JTAG CLOCK
92. ll not recognize snoops or interrupts The processor will only recognize the assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units SMB_PRT The SMBus present SMB_PRT pin is defined to inform the platform if the installed processor includes SMBus components such as the integrated thermal sensor and the processor information ROM PIROM This pin is tied to VSS by the processor if these features are not present Platforms using this pin should use a pull up resistor to the appropriate voltage level for the logic tied to this pin Because this pin does not connect to the processor silicon any platform voltage and termination value is acceptable System Management Interrupt is asserted asynchronously by system logic accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If is asserted during the deassertion of RESET the processor will tristate its outputs STPCLK STPCLK Stop Clock when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops
93. ll such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future information If BINIT observation is enabled during power on configuration see Figure 7 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their Queue and transaction tracking state machines upon observation of BINIT assertion Once the BINIT assertion has been observed the bus agents will re arbitrate for the front side bus and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system Since multiple agents may drive this signal at the same time BINIT is a wired OR signal which must connect the appropriate pins of all processor front side bus agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers BINIT is activated on specific clock edges and sampled on specific clock edges BNR y o Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a
94. m bus All memory and I O transactions as well as interrupt messages pass between the processor and the chipset over the FSB Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied Integrated Heat Spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface mPGA 604 Socket The Low Voltage Intel Xeon processor with 800 MHz system bus mates with the baseboard through this surface mount 604 pin zero insertion force ZIF socket See the mPGA604 Socket Design Guidelines for details regarding this socket Processor Core The processor s execution engine Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor pins should not be connected to any supply voltages have any I Os biased or receive any clocks Symmetric Agent A symmetric agent is a processor which shares the same I O subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric agents are known as Symmetric Multiprocessor SMP systems The Low Voltage Intel Xeon processor with 800 MHz system b
95. nditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes Voc Core voltage with respect to Vss 0 30 1 55 V Vit System bus termination voltage with 0 30 1 55 V respect to Vss TcasE Processor case temperature See See C Section 6 0 Section 6 0 Storage temperature 40 85 C 3 4 NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3
96. nts For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor front side bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor front side bus throughout the bus locked operation and ensure the atomicity of lock MCERR yo MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor front side bus agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the A 32 Software Developer s Manual Volume 3 System Programming Guide Since multiple agents may drive this signal at the same time MCERR is a wired OR signal which must connect the appropriate pins of all processor front side bus agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers MCERR t is activated on spec
97. oad NA 50 Ibf static 1 Ibm 100 G Ibf NA 288 0 45 kg 100G 1 3 5 6 7 65 Ibf static 1 Ibm 100 G bf Transient NA 445 N 1 3 8 100 Ibf NOTES 1 These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface 2 This is the minimum and maximum static force that can be applied by the heat sink and retention solution to maintain the heat sink and processor interface These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket This specification applies for thermal retention solutions that allow baseboard deflection This specification applies either for thermal retention solutions that prevent baseboard deflection or for the Intel enabled reference solution CEK Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement Experimentally validated test condition used a heat sink mass of 1 Ibm 0 45 kg with 100 G acceleration measured at heat sink mass The dynamic portion of this specification in the product application can have flexibility in specific values but the ultimate product of mass times acceleration should not exceed this validated dynamic load 1 Ibm x 100 G 100 Ib Allowable strain in the dynamic compressive load specification is in addition to the strain allowed in static loading 8 Transient loading
98. on all other input pins on the front side bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal When re entering the Stop Grant state from the Sleep state STPCLK should only be deasserted one or more bus clocks after the deassertion of SLP A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus see Section 7 2 4 A transition to the Sleep state see Section 7 2 5 will occur with the assertion of the SLP signal While in the Stop Grant state SMI INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus The PBE signal can be driven when the processor is in Stop Grant state PBE will be asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still caus
99. on the Vcc load line The processor is capable of drawing for up to 10 ms Refer to Figure 2 for further details on the average processor current draw over various time durations 7 must be provided via a separate voltage source and must not be connected to This specification is measured at the pin 8 Baseboard bandwidth is limited to 20 MHz 9 This specification refers to a single processor with enabled Please note the end agent and middle agent may not require Irr max simultaneously This parameter is based on design characterization and not tested 10 This specification refers to a single processor with disabled Please note the end agent and middle agent may not require Irr max simultaneously Details will be provided in future revisions of this document Datasheet 25 intel 11 These specifications apply to the PLL power pins VCCA VCCIOPLL and VSSA See Section 2 3 2 for details These parameters are based on design characterization and are not tested 12 This specification represents a total current for all GTLREF pins 13 The current specified is also for HALT State 14 The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of the PROCHOT signal is the maximum for the processor 15 1 Thermal Design Current is the sustained DC equivalent current that the processor is capable of drawing indef
100. ore a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 15 and be followed by a 1 10 ms RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation 48 Datasheet intel Table 20 Signal Definitions Sheet 7 of 9 Name Type Description Notes 4 0 y o REQ 4 0 Request Command must connect the appropriate pins of all processor front side bus agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Refer to the 0 signal description for details on parity checking of these signals RESET Asserting the RESET signal resets all processors to known states and invalidates their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least 1 ms after Vcc and BCLK have reached their proper specifications On observing active RESET all front side bus agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 7 1
101. ould be taken to read all notes associated with each parameter Datasheet Intel Table 9 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes VID range VID range for Low Voltage Intel 1 1125 1 2000 V 2 9 Xeon processor with 800 MHz System bus Vcc for Low Voltage Intel Xeon See Table 10 and VID max 1 25 V 3 4 5 6 processor with 800 MHz system bus Figure 3 Front Side Bus termination voltage 1 176 1 20 1 224 V ri DC specification Front Side Bus termination voltage 1 140 1 20 1 260 V 7 8 AC amp DC specification loc for Low Voltage Intel Xeon 60 A 6 16 processor with 800 MHz system bus Front Side Bus end agent 4 8 A 9 current Front Side Bus mid agent 1 5 A 10 current for PLL power pins 120 mA 11 lcc vccioPLL loc for PLL power pins 100 mA 11 loc_GTLREF loc for GTLREF pins 200 12 leGNT Icc Stop Grant for Low Voltage Intel 40 A 13 lai p Xeon processor with 800 MHz System bus Hcc loc TCC Active loc A 14 lcc for Low Voltage Intel 56 A 15 16 processor with 800 MHz system bus Thermal Design Current NOTES 1 Unless otherwise noted all specifications in this table apply to all processors These specifications are based on silicon characterization however they may be updated as further data becomes
102. pins or disable itself 50 Datasheet intel Table 20 Signal Definitions Sheet 9 of 9 Name Type Description Notes VIDPWRGD The processor requires this input to determine that the supply voltage for BSEL 1 0 and VID 5 0 is stable and within specification Vssa Vgga provides an isolated internal ground for internal PLL s Do not connect directly to ground This pin is to be connected to Veca and Vccjop through a discrete filter circuit The front side bus termination voltage input pins Refer to Table 9 for further details VTTEN The VTTEN can be used as an output enable for the VTT regulator in the event an incompatible processor is inserted into the platform There is no connection to the processor silicon for this signal and it must be pulled up through a resistor NOTES 1 The Low Voltage Intel processor with 800 MHz system bus only supports BRO and BR1 However platforms must terminate BR2 and BR3 to VTI 2 For this pin on Low Voltage Intel one Maximum number of central agents is zero 3 For this pin on Low Voltage Intel Xeon processor with 800 MHz system bus the maximum number of symmetric agents is two Maximum number of central agents is zero 4 For this pin on Low Voltage Intel Xeon processor with 800 MHz system bus the maximum number of symmetric agents is two Maximum number of central agents is one Datasheet pro
103. priate pins of all agents on the front side bus A 35 3 are protected by parity signals 1 0 A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 35 3 pins to determine their power on configuration See Section 7 1 20 If 20 Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode 20 15 an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding 1 write bus transaction ADS y o ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must connect the appropriate pins on all Low Voltage Intel Xeon processor with 800 MHz system bus agents ADSTB 1 0 y o Address strobes are used to latch A 35 3 and REQ 4 0 on their rising
104. refer to Section 6 2 Thermal Monitor feature must be enabled for the processor to remain within specification Low Voltage Intel Xeon Processor with 800 MHz System Bus Thermal Specifications Core Maximum Thermal Minimum Maximum Frequency Power Design Power Notes GHz W W See Figure 12 2 80 GHz 62 1 55 5 Table 24 1 2 3 4 5 NOTES 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and combination wherein Vcc exceeds max at specified loc Please refer to the static and transient tolerance specifications in Section 2 0 2 Maximum Power is the maximum thermal power that can be dissipated by the processor through the integrated heat spreader IHS Maximum Power is measured at maximum Tcase 3 Thermal Design Power TDP should be used for processor chipset thermal solution design targets TDP is not the maximum power that the processor can dissipate is measured at maximum Tease 4 These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available 5 Power specifications are defined at all VIDs found in Table 9 The Low Voltage Inte processor with 800 MHz system bus may be shipped under multiple VIDs listed for each frequency
105. rements The Low Voltage Intel Xeon processor with 800 MHz system bus thermal specifications are defined in Table 23 In addition the thermal profile for the Low Voltage Intel Xeon processor with 800 MHz system bus is shown in Figure 12 and Table 24 71 Table 23 72 intel The upper point of the thermal profile consists of the Thermal Design Power TDP defined in Table 23 and the associated Tc Asp value It should be noted that the upper point associated with the Thermal Profile x TDP and y Tease TDP represents a thermal solution design point In actuality the processor case temperature will never reach this value due to TCC activation see Figure 12 Please note that although Table 24 does not indicate a value production units will be programmed with a value Please see Section 6 2 6 for more information on TCONTROL The case temperature is defined at the geometric top center of the processor IHS Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 23 instead of the maximum processor power consumption The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature
106. requency select signals BSEL 1 0 are used to select the processor input clock frequency Table 3 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processors chipset and clock synthesizer All front side bus agents must operate at the same frequency The Low Voltage Intel processor with 800 MHz system bus currently operates at a 800 MHz system bus frequency 200 MHz BCLK 1 0 frequency COMPT 0 COMPT1 0 must be terminated to Vas on the baseboard using precision resistors These inputs configure the GTL drivers of the processor D 63 0 y o D 63 0 Data are the data signals These signals provide 64 bit data path between 4 the processor front side bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN S3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to strobes and DBI DSTBNZ Data Group DSTBP DBI D 15 0 0 0 0 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DBI pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal W
107. rom the voltage regulator VRD or VRM pins to the mPGA604 socket The power delivery solution must insure the voltage and current specifications are met defined in Table 9 Decoupling Decoupling must be provided on the baseboard Decoupling solutions must be sized to meet the expected load To insure optimal performance various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors 13 2 2 3 2 3 Table 2 2 3 1 14 intel The Low Voltage Intel processor with 800 MHz system bus integrates signal termination on the die as well as part of the required high frequency decoupling capacitance on the processor package However additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the front side bus Bulk decoupling must also be provided by the baseboard for proper AGTL bus operation Front Side Bus AGTL Decoupling Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the front side bus interface speed as well as the core frequency of the processor As in previous processor generations the Low Voltage Intel processor with 800 MHz system bus core frequency is a multiple of the BCLK
108. rved VCC B31 Power Other RESET Y8 Common Clk Input VCC C2 Power Other RSO E21 Common Clk Input VCC C4 Power Other RS1 D22 Common Clk Input VCC C16 Power Other 2 F21 Common CIk Input VCC C22 Power Other C6 Common Input VCC C28 Power Other SKTOCC A3 Power Other Output VCC C30 Power Other SLP AE6 Async GTL Input D1 Power Other SLEW_CTRL AC30 Power Other Input VCC D8 Power Other SMB PRT AE4 Power Other Output VCC D14 Power Other SMI C27 Async GTL Input VCC D18 Power Other STPCLK D4 Async GTL Input VCC D24 Power Other 56 Datasheet intel Table 21 Pin Listing by Pin Name Sheet 4 of 8 Pin Name EUER IA Direction Pin Name dk E Nu Direction VCC D29 Power Other VCC K1 Power Other VCC D31 Power Other VCC K3 Power Other VCC E2 Power Other VCC K5 Power Other VCC E6 Power Other VCC K7 Power Other VCC E20 Power Other VCC K9 Power Other VCC E26 Power Other VCC K23 Power Other VCC E28 Power Other VCC K25 Power Other VCC E30 Power Other VCC K27 Power Other VCC F1 Power Other VCC K29 Power Other VCC F4 Power Other VCC K31 Power Other VCC F16 Power Other VCC L2 Power Other VCC F22 Power Other VCC L4 Power Other VCC F29 Power Other VCC L6 Power Other VCC F31 Power Other VCC L8 Power Other VCC G2 Power Other VCC L24 Power Other VCC G4 Power
109. s maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Datasheet Intel 6 2 2 6 2 3 6 2 4 Datasheet On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems using the Low Voltage Intel Xeon processor with 800 MHz system bus must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the IA 32 CLOCK MODULATION MSR is written to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the IA 32 CLOCK MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 596 12 5 off in 12 596 increments
110. s point the system bus signal THERMTRIP will go active and stay active as described in Table 20 THERMTRIP activation is independent of processor activity and does not generate any bus cycles and Fan Speed Reduction Tcowrgor 1 temperature specification based on a temperature reading from the thermal diode The value for Toonrroy will be calibrated in manufacturing and configured for each processor The Tcowrgor temperature for a given processor can be obtained by reading the IA 32 TEMPERATURE TARGET MSR in the processor The value that is read from the IA 32 TEMPERATURE TARGET MSR must be converted from Hexadecimal to Decimal and added to a base value The base value is 50 The value of Tcontro may vary from OxOOh to Ox1Eh Systems that support the Low Voltage Intel processor with 800 MHz system bus must implement BIOS changes to detect which processor is present and then select the appropriate Tcontrol base value When Thione is above then TcAsg must be at or below max as defined by the thermal profile The processor temperature can be maintained at Thermal Diode The processor incorporates an on die thermal diode A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management long term die temperature change purposes Table 25 and Table 26 provide the diode parameter and interfac
111. sfer rates possible The Execution Trace Cache is a level 1 cache that stores decoded micro operations which removes the decoder from the main execution path thereby increasing performance The Low Voltage Intel Xeon processor with 800 MHz system bus supports Hyper Threading Technology This feature allows a single physical processor to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architecture state with its own set of general purpose registers control registers to provide increased system responsiveness in multitasking environments and headroom for next generation multi threaded applications More information on Hyper Threading Technology can be found at http www intel com technology hyperthread Other features within the Intel NetBurst microarchitecture include Advanced Dynamic Execution Advanced Transfer Cache enhanced floating point and multi media unit Streaming SIMD Extensions 2 SSE2 and Streaming SIMD Extensions 3 SSE3 Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The Advanced Transfer Cache is a 1 MB on die level 2 L2 cache with increased bandwidth The floating point and multi media units include 128 bit wide registers and a separate register for data movement Streaming SIMD2 SSE2 instructions provide highly efficient double precision floating point SIM
112. te Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Normal State INIT BINIT INTR NMI Normal execution RESET FSB interrupts STPCLK x De asserted STPCLK Asserted Stop Grant State Snoop Event Occurs HALT State BCLK running Snoops and interrupts allowed Snoop Event Occurs Snoop Event Serviced HALT Snoop State BCLK running Service snoops to caches BCLK running Snoops and interrupts allowed Snoop Event Serviced SLP SLP Asserted De asserted Sleep State BCLK running No snoops or interrupts allowed Stop Grant Snoop State BCLK running Service snoops to caches Datasheet 7 2 3 7 2 4 82 intel When the STPCLK pin is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Acknowledge special bus cycle Once the STPCLK pin has been asserted it may only be deasserted once the processor is in the state For the Low Voltage Intel processor with 800 MHz system bus both logical processors must be in the state before the deassertion of STPCLK Stop Grant State Since the signal pins receive power from the front side bus these pins should not be driven allowing the level to return to Vrr for minimum power drawn by the termination resistors in this state In additi
113. us It must connect the appropriate pins of all processor front side bus agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI 44 Datasheet intel Table 20 Signal Definitions Sheet 3 of 9 Name Type Description Notes BRO y o BR 3 0 Bus Request drive the BREQ 3 0 signals in the system The BREQ 3 0 1 4 BR signals are interconnected in a rotating manner to individual processor pins The tables below provide the rotating interconnect between the processor and bus signals for 2 way systems BR 1 0 Signals Rotating Interconnect 2 way system Bus Signal Agent 0 Pins Agent 1 Pins BREQO BRO BR1 BREQ1 BR1 BRO BR2 BR3 must not be used 2 way platform designs However they must still be terminated During power on configuration the central agent must assert the BRO bus signal All symmetric agents sample their BR 3 0 pins on the active to inactive transition of The pin which the agent samples asserted determines it s agent ID These signals do not have on die termination and must be terminated at the end agent BSEL 1 0 The BCLK 1 0 f
114. us should only be used in SMP systems which have two or fewer agents Thermal Design Power Processor chipset thermal solution should be designed to this target It is the highest expected sustainable power while running known power intensive real applications TDP is not the maximum power that the processor chipset can dissipate Voltage Regulator Module VRM DC DC converter built onto a module that interfaces with an appropriate card edge socket that supplies the correct voltage and current to the processor The processor core power supply Voss The processor ground The system bus termination voltage 11 1 2 1 3 12 Intel References Material and concepts available in the following documents may be beneficial when reading this document Intel Document Document Number Inte Extended Memory 64 Technology Software Developer s Manual Volume 1 300834 Inte Extended Memory 64 Technology Software Developer s Manual Volume 2 300835 mPGA604 Socket Design Guidelines 254232 AP 485 Intel Processor Identification and CPUID Instruction 241618 1 32 Intef Architecture Optimization Reference Manual 248966 1 32 Intef Architecture Software Developer s Manual Volume 1 Basic Architecture 253665 1 32 Intef Architecture Software Developer s Manual Volume 2A Instruction Set 253666 Reference A M 1 32 Intef Architecture Software Developer s Manual Volume
115. ut group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL group when driving AGTL asynchronous outputs can become active anytime and include an active pMOS pull up transistor to assist during the first clock of a low to high voltage transition With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLKO ADS HIT etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as rising edge of BCLKO Asynchronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 5 identifies which signals are common clock source synchronous and asynchronous 19 Table 5 20 Front Side Bus Signal Groups Signal Group Type Signals AGTL Common Clock Input Synchronous to BCLKT 1 0 BPRI BR 3 1 4 DEFER RESET 2 0 RSP TRDY AGTL Common Clock I O Synchronous to BCLKT 1 0 ADS AP 1 0 BINITZ BNR BPM 5 0 BRo DBSY DP 3 0 DRDY HITM LOCK MCERR 4 AGTL Source Synchronous Synchronous to assoc strobe Signals Associated Strobe REQ 4 0 A 16 3 4 ADSTBO 35 17
116. volume reserved for the LAI may include different requirements from the space normally occupied by the heat sink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Mechanical Considerations Electrical Considerations The LAI will also affect the electrical performance of the front side bus therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide Datasheet
117. y output THERMTRIP uses output buffers All of these Asynchronous signals follow the same DC requirements as signals however the outputs are not driven high during the logical 0 to 1 transition by the processor FERR PBE IERR and IGNNE have now been defined as asynchrnous signals as they include an active p MOS device asynchronous and AGTL asynchronous signals do not have setup hold time specifications in relation to BCLK 1 0 However all of the asynchronous and AGTL asynchronous signals are required to be asserted deasserted for at least six BCLKs in order for the processor to recognize them See Table 15 for the DC specifications for the asynchronous signal groups Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor s be first in the TAP chain and followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Similar considerations must be made for TCK TMS and TRST Two copies of each signal may be required with each driving a different voltage level Mixing Processors Intel only supports and validates dual processor configurations in which both Low Voltage Intel Xeon processor with 800
118. ystems using MS DOS type floating point error reporting When is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to Volume 3 of the A 32 Software Developer s Manual and the Inte Processor Identification and the CPUID Instruction application note This signal does not have on die termination and must be terminated at the end agent FORCEPR The FORCEPR input can be used by the platform to force the Low Voltage Intel Xeon processor with 800 MHz system bus to activate the Thermal Control Circuit TCC The TCC will remain active until the system deasserts FORCEPR GTLREF GTLREF determines the signal reference level for GTL input pins GTLREF is used by the GTL receivers to determine if a signal is a logical 0 or a logical 1 HIT HITM y o y o HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any front side bus agent may assert both HIT and together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together Since multiple agents may deliver snoop results at the same time HIT and HITM ar

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