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Intel Celeron M 440 1.86GHz

1. Pin Name Wo in adi Direction Pin Name m m a Direction DSTBP 3 AE25 Source Synch Input Output RSVD E26 Reserved FERR D3 Open Drain Output RSVD G1 Reserved GTLREF AD26 Power Other Input RSVD AC1 Reserved HIT K3 Common Clock Input Output SLP A6 CMOS Input HITM K4 Common Clock Input Output SMI B4 CMOS Input IERR A4 Open Drain Output STPCLK C6 CMOS Input IGNNE A3 CMOS Input TCK A13 CMOS Input INIT B5 CMOS Input TDI C12 CMOS Input ITP CLK 0 A16 CMOS input TDO A12 Open Drain Output ITP CLK 1 A15 CMOS input TEST1 C5 Test LINTO D1 CMOS Input TEST2 F23 Test LINT1 D4 CMOS Input TEST3 C16 Test LOCK J2 Common Clock Input Output THERMDA B18 Power Other PRDY A10 Common Clock Output THERMDC A18 Power Other PREQ B10 Common Clock Input eU C47 Open Drain Output FD B17 Open Drain Output TMS C11 CMOS Input PSI E1 CMOS Output TRDY M3 Common Clock Input PWRGOOD E4 CMOS Input TRST B13 CMOS Input REQ O R2 Source Synch Input Output VCC D6 Power Other REO 1 F P3 Source Synch Input Output VCC D8 Power Other REQ 2 T2 Source Synch Input Output VCC D18 Power Other REQ 3 P1 Source Synch Input Output VCC D20 Power Other REQ 4 T1 Source Synch Input Output VCC D22 Power Other RESET B11 Common Clock Input
2. Fin Pin Name Signal Buffer Direction Pin Pin Name Signal Butter Direction Number Type Number Type F26 VCCA 0 Power Other J4 VSS Power Other G1 RSVD Reserved J5 VCC Power Other G2 VSS Power Other J6 VSS Power Other G3 VID 3 CMOS Output J21 VCC Power Other G4 VID 4 CMOS Output J22 VSS Power Other G5 VCC Power Other Input J23 D 23 Source Synch Output G6 VSS Power Other J24 VSS Power Other G21 VCC Power Other J25 D 25 l Source Synch Input G22 vss Power Other 25 uree SY Output 923 yee Power other J26 DINV 1 Source Synch Put utput G24 D 22 Source Synch Input y Output K1 RS 1F Common Clock Input Input K2 VSS Power Other G25 D 17 Source Synch Output Input G26 vss Power Other K3 HITA Common Clock Output H1 RS O Common Clock Input KA HITME Common Clock Input Output Input He DRDY Common Clock Output K5 vss Power Other H3 VSS Power Other K6 VCCP Power Other H4 VID 5 CMOS Output K21 VSS Power Other H5 VSS Power Other K22 VCC Power Other H6 VCC Power Other K23 VSS Power Other Hel YSS Rowen tet K24 DSTBN 1 f Source Synch neat H22 VCC Power Other K25 D 31 Source Synch Inpull H23 D 16 Source Synch MPU Output y Output K26 VSS Power Other H24 D 20 Source Synch Pul aaah P L1 BNR Common Clock Gf utput H25 VSS Power Other L2 RS 2 Common Clock Input Input H26 D 29 Source Synch Output L3 vss Power Other J1 VSS Power Other L4 DEFER Common Clo
3. Table 23 Pin Listing by Pin Name Table 23 Pin Listing by Pin Name Pin Name Pa m aa raad Direction Pin Name m i and Direction VSS P2 Power Other VSS AA1 Power Other VSS P5 Power Other VSS AA4 Power Other VSS P21 Power Other VSS AA6 Power Other VSS P24 Power Other VSS AA8 Power Other VSS R1 Power Other VSS AA10 Power Other VSS R4 Power Other VSS AA12 Power Other VSS R6 Power Other VSS AA14 Power Other VSS R22 Power Other VSS AA16 Power Other VSS R25 Power Other VSS AA18 Power Other VSS T3 Power Other VSS AA20 Power Other VSS T5 Power Other VSS AA22 Power Other VSS T21 Power Other VSS AA25 Power Other VSS T23 Power Other VSS AB3 Power Other VSS T26 Power Other VSS AB5 Power Other VSS U2 Power Other VSS AB7 Power Other VSS U6 Power Other VSS AB9 Power Other VSS U22 Power Other VSS AB11 Power Other VSS U24 Power Other VSS AB13 Power Other VSS V1 Power Other VSS AB15 Power Other VSS V4 Power Other VSS AB17 Power Other VSS V5 Power Other VSS AB19 Power Other VSS V21 Power Other Vss AB21 Power Other VSS V25 Power Other VSS AB23 Power Other VSS W3 Power Other VSS AB26 Power Other VSS W6 Power Other VSS AC2 Power Other VSS W22 Power Other VSS AC5 Power Other VSS W23 Power Other VSS AC8 Power Other VSS W26 Power Other VSS AC10 Power Other VSS Y2 Power Other VSS AC12 Power Other VSS Y5 Power Other VSS AC14 Power Other VSS Y21 Power Other VSS AC16 Power Other VSS Y24 Power Other VSS AC18 Power Other
4. Intel Celeron M Processor Datasheet 45 Package Mechanical Specifications and Pin Information Table 23 Pin Listing by Pin Name Intel Table 23 Pin Listing by Pin Name a Pin Signal Buffer Pin Signal Buffer P Pin Name Number Type Direction Pin Name lumber Type Direction VSS AC21 Power Other VSS AF21 Power Other VSS AC24 Power Other VSS AF24 Power Other VSS AD1 Power Other VSSSENSE AF6 Power Other Output VSS AD4 Power Other Tf Table 24 Pin Listing by Pin Number VSS AD7 Power Other vss AD9 P Oth Pin Pin Name Signal Buffer Direction OWEHRZUMT Number Type VSS AD11 Power Other A2 vss PowerlOther VSS AD13 Power Other 3 IGNNE CMOS Input e ANS PowerOther A4 IERR Open Drain Output VSS AD17 Power Other A5 vss Power Other VSS AD19 Power Other AG SLP CMOS Input VSS AD22 Power Other A7 DBR CMOS Output VSS AD25 Power Other A8 vss Power Other yee RES PowerOther A9 BPM 2 Common Clock Output idu AED FOWRUCHHSE A10 PRDY Common Clock Output VSS AE8 Power Other A11 vss Power Other vee SEM FOWBHUHDST A12 TDO Open Drain Output VSS AE12 Power Other M3 TCK CMOS Input VSS AE14 Power Other MA vss Power Other VSS AE16 Power Other M5 ITP_CLK 1 CMOS input VSS AE18 Power Oth
5. Document Order Number Intel 855PM Chipset Platform Design Guide http developer intel com Intel 855PM Chipset Design Guide Update http developer intel com Intel 855PM Chipset Datasheet http developer intel com lintel 855GM 855GME Chipset Platform Design Guide http developer intel com Intel 855GM 855GME Chipset Datasheet http developer intel com Intel 855GM Specification Update http developer intel com Intel 852GM Chipset Datasheet http developer intel com Intel Architecture Software Developer s Manual http developer intel com Volume 1 Basic Architecture 253665 Volume 2A Instruction Set Reference 253666 Volume 2B Instruction Set Reference 253667 Volume 3 System Programming Guide 253668 ITP700 Debug Port Design Guide http developer intel com NOTE Contact your Intel representative for the latest revision and order number of this document 1 3 State of Data The data contained within this document represents the most accurate information available by the publication date However all data in this document is preliminary and subject to change Intel Celeron M Processor Datasheet 9 Introduction ntel amp 10 Intel Celeron M Processor Datasheet 2 1 Figure 1 2 1 1 2 1 2 Intel Celeron Low Power Features Low Power Features Clock Control and Low Power States The Intel Celeron M processor supports the AutoHALT Stop Grant Sleep an
6. STATIC Static Min Ripple Max 22 Intel Celeron M Processor Datasheet Electrical Specifications Table 6 Voltage Tolerances for Intel Celeron M Processor with VID 1 356 V Active State VID 1 356 V Offset 0 mode STATIC Ripple Vcc A Vec V Min Max Min Max 0 1 356 1 336 1376 1 326 1 386 0 8 1 354 1 333 1 374 1 323 1 384 1 6 1 351 1 331 1 372 1 321 1 382 23 1 349 1 329 1 369 1 319 1 379 3 1 1 347 1 326 1 367 1316 1377 39 1 344 1 324 1 365 1314 1375 47 1 342 1 322 1 362 1 312 1 372 54 1 340 1 319 1 360 1 309 1 370 6 2 1 337 1 347 1 358 1 307 1 368 7 0 1 335 1 315 1 355 1 305 1 365 78 1 333 1312 1 353 1 302 1 363 8 6 1 330 1 310 1 351 1 300 1 361 9 3 1 328 1 308 1 348 1 208 1 358 E 10 1 1 326 1 305 1 346 1 205 1 356 9 10 9 1323 1 303 1 344 1 293 1 354 11 7 1 321 1 301 1 341 1 291 1 351 12 4 1 319 1 298 1 339 1 288 1 349 13 2 1316 1 296 1 337 1 286 1 347 14 0 1 344 1 294 1 334 1 284 1 344 14 8 1 312 1 291 1 332 1 281 1 342 15 6 1 309 1 289 1 330 1279 1 340 16 3 1 307 1 287 1327 1277 1 337 17 4 1 305 1 284 1 325 1 274 1 335 17 9 1 302 1 282 1323 1272 1333 18 7 1 300 1 280 1 320 1270 1 330 19 4 1 298 1 277 1318 1 267 1 328 20 2 1 295 1 275 1316 1 265 1 326 21 0 1 293 1 273 1 313 1 263 1 323 Intel Celeron9 M Processor Datasheet 23 Electrical Specif
7. Electrical Specifications Symbol Parameter Min Typ Max Unit Notes Intel Celeron M processor 1 20 GHz Core Voc 1 356 1 30 GHz Core Voc 1 356 1 40 GHz Core Vcc 1 356 1 50 GHz Core Voc 1 356 y pa cc Ultra low voltage Intel Celeron M Processor 800 MHz Core Vcc 1 004 900 MHz Core Vcc 1 004 Default Vcc Voltage for initial Vcc Boor power up 1 14 1 20 1 26 V 2 7 Vccp AGTL Termination Voltage 0 997 1 05 1 102 V 2 VccA PLL supply voltage 1 71 1 8 1 89 V 2 Icc for Intel Celeron lccpEs MProcessors 25 Recommended Design Target A 5 lcc for Mobile Intel Celeron M processor by Frequency Voltage 1 20 GHz amp 1 356 V 21 1 30 GHz amp 1 356 V 21 1 40 GHz amp 1 356 V 21 1 50 GHz 8 1 356 V 21 cc A 3 ICC for ultra low voltage Intel Celeron M processor by Frequency Voltage 800 MHz amp 1 004V 7 4 900 MHz amp 1 004V 8 0 Icc Auto Halt amp Stop Grant at 1 356 V 1 20 Ghz 13 5 laH 1 356 V 1 30 GHz 12 9 1 356 V 1 40 GHz 12 3 A 4 Isewr 1 356 V 1 50 GHz 11 8 1 004 V 800 MHz ULV 3 4 1 004 V 900 MHz ULV 3 3 Icc Sleep at 1 356 V 1 20 Ghz 13 3 1 356 V 1 30 GHz 127 lsLP 1 356 V 1 40 GHz 12 1 A 4 1 356 V 1 50 GHz 11 6 1 004 V 800 MHz ULV 34 1 004 V 900 MHz ULV 32 Intel Celeron M Processor Datasheet 21 Electrical Specifications Table 5 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes
8. DSTBN 3 0 iF Input Output Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV O DSTBN O D 31 16 DINV 1 DSTBN 1 D 47 32 if DINV 2 DSTBN 2 D 63 48 DINV 3 DSTBN 3 DSTBP 3 0 Input Output Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV O DSTBP O D 31 16 DINV 1 DSTBP 1 D 47 32 DINV 2 DSTBP 2 f D 63 48 DINV 3 DSTBP 3 f FERR PBE Output FERR Floating point Error PBE Pending Break Event is a multiplexed signal and its meaning is qualified with STPCLK When STPCLK is not asserted FERR PBE indicates a floating point when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state When FERR PBE is asserted indicating a break event it will remain asserted until STPCLK is deasserted Assertion of PREQ when STPCLK is active will also cause an FERR break event For additional information on the pending break event functionality
9. Y26 D 32 Source Synch Output Intel Celeron M Processor Datasheet 55 4 2 56 Alphabetical Signals Reference Table 25 Signal Description Sheet 1 of 7 Name Type Description A 31 3 Input Output A 31 3 Address define a 23 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of both agents on the Intel Celeron M processor FSB A 31 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 Address signals are used as straps which are sampled before RESET is deasserted A20M Input If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 31
10. including identification of support of the feature and enable disable information refer to Volume 3 of the Intel Architecture Software Developer s Manual and the Intel Processor Identification and CPUID Instruction application note For termination reguirements please refer to the platform design guides GTLREF Input GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 2 3 Vccp GTLREF is used by the AGTL receivers to determine if a signal is a logical 0 or logical 1 Please refer to the platform design guides for details on GTLREF implementation 58 Intel Celeron M Processor Datasheet Table 25 Signal Description Sheet 4 of 7 Name Type Description HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Either FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR Output IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET BINIT or INIT For termination requirements ple
11. 0 988 1 018 0 978 1 028 0 5 1 002 0 987 1 017 0 977 1 027 0 8 1 002 0 986 1 017 0 976 1 027 14 1 001 0 986 1 016 0 976 1 026 14 1 000 0 985 1 015 0 975 1 025 1 6 0 999 0 984 1 014 0 974 1 024 19 0 998 0 983 1 013 0 973 1 023 22 0 997 0 982 1 012 0 972 1 022 25 0 997 0 982 1 012 0 972 1 022 27 0 996 0 981 1 011 0 971 1 021 3 0 0 995 0 980 1 010 0 970 1 020 33 0 994 0 979 1 009 0 969 1 019 u 3 6 0 993 0 978 1 008 0 968 1 018 o 3 8 0 992 0 977 1 008 0 967 1 018 41 0 992 0 977 1 007 0 967 1 017 44 0 991 0 976 1 006 0 966 1 016 47 0 990 0 975 1 005 0 965 1 015 4 9 0 989 0 974 1 004 0 964 1 014 52 0 988 0 973 1 003 0 963 1 013 55 0 988 0 972 1 003 0 962 1 013 5 8 0 987 0 972 1 002 0 962 1 012 6 0 0 986 0 971 1 001 0 961 1 011 6 3 0 985 0 970 1 000 0 960 1 010 6 6 0 984 0 969 0 999 0 959 1 009 6 9 0 983 0 968 0 999 0 958 1 009 74 0 983 0 968 0 998 0 958 1 008 74 0 982 0 967 0 997 0 957 1 007 Intel Celeron9 M Processor Datasheet 25 Electrical Specifications 26 intel Table 9 Voltage Tolerances for ULV Intel Celeron M Processor with VID 1 004 V Deep Sleep State VID 71 004 V Offset 1 2 moue STATIC Ripple lcc A Vec V Min Max Min Max 0 0 0 992 0 977 1 007 0 967 1 017 0 2 0 991 0 976 1 006 0 966 1 016 0 4 0 991 0 976 1 006 0 966 1 016 0 6 0 990 0 975 1 005 0 965
12. 1 015 0 9 0 989 0 974 1 004 0 964 1 014 1 1 0 989 0 974 1 004 0 964 1 014 1 3 0 988 0 973 1 003 0 963 1 013 o 2 1 5 0 987 0 972 1 003 0 962 1 013 o 1 7 0 987 0 972 1 002 0 962 1 012 a 1 9 0 986 0 971 1 001 0 961 1 011 2 1 0 986 0 970 1 001 0 960 1 011 2 3 0 985 0 970 1 000 0 960 1 010 2 6 0 984 0 969 0 999 0 959 1 009 2 8 0 984 0 969 0 999 0 959 1 009 3 0 0 983 0 968 0 998 0 958 1 008 3 2 0 982 0 967 0 997 0 957 1 007 Table 10 FSB Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Notes VL Input Low Voltage 0 V Vu Input High Voltage 0 660 0 710 0 850 V VcRoss Crossing Voltage 0 25 0 35 0 55 V 2 AVcRoss Range of Crossing Points N A N A 0 140 V 6 Vru Threshold Region Vcnoss 0 100 VcRoss 0 100 V 3 ILi Input Leakage Current 100 MA 4 Cpad Pad Capacitance 1 8 2 3 2 75 pF 5 NOTES 1 2 ons Unless otherwise noted all specifications in this table apply to all processor frequencies Crossing Voltage is defined as absolute voltage where rising edge of BCLKO is equal to the falling edge of BCLK1 switches It includes input threshold hysteresis For Vin between 0 V and Vy Cpad includes die capacitance only No package parasitics are included AVcnoss is defined as the total variation of all crossing voltages as defined in note 2 Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver Intel Celeron M Processor Datasheet Table 11 AGTL
13. 5 1 2 for thermal diode usage recommendation when the PROCHOT signal is not asserted Table 27 and Table 28 provide the diode interface and specifications The reading of the external thermal sensor on the motherboard connected to the processor thermal diode signals will not necessarily reflect the temperature of the hottest location on the die This is due to inaccuracies in the external thermal sensor on die temperature gradients between the location of the thermal diode and the hottest location on the die and time based variations in the die temperature measurement Time based variations can occur when the sampling rate of the thermal diode by the thermal sensor is slower than the rate at which the T temperature can change The offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor s automatic mode activation of thermal control circuit This temperature offset must be taken into account when using the processor thermal diode to implement power management events Thermal Diode Interface Signal Name Pin Ball Number Signal Description THERMDA B18 Thermal diode anode THERMDC A18 Thermal diode cathode Thermal Diode Specifications Symbol Parameter Min Typ Max Unit Notes lew Forward Bias Current 5 300 uA 1 n Diode Ideality Factor 1 00151 1 00220 1 00289 2 3 4 Rr Series Resist
14. Dimensions Symbol Parameter Min Max Unit A Overall height as delivered Refer to Note 1 2 60 2 85 mm A2 Die height 0 82 mm b Ball diameter 0 78 mm D Package substrate length 34 9 35 1 mm E Package substrate width D1 Die length E1 Die width F To Package Substrate Center G Die Offset from Package Center e Ball pitch K Package edge keep out K1 Package corner keep out K2 Die side capacitor height S Package edge to first ball center N Ball count Solder ball coplanarity Pdie Allowable pressure on the die for thermal solution 689 kPa W Package weight 4 5 g NOTE Overall height as delivered Values are based on design specifications and tolerances This dimension is subject to change based on OEM motherboard design or OEM SMT process 36 Intel Celeron M Processor Datasheet a ntel Package Mechanical Specifications and Pin Information 4 1 Processor Pin Out and Pin List Figure 11 on the next page shows the top view pinout of the Intel Celeron M processor The pin list is arranged in two different formats shown in Table 23 and Table 24 Intel Celeron9 M Processor Datasheet 37 Package Mechanical Specifications and Pin Information intel Figure 11 The Coordinates of the Processor Pins as Viewed From the Top of the Package eooeocoo VSS IGNNE IERR O O eos VCCA 1 RSVD VSS SMi e O O e vss A20M RSVD vss O 6 O o
15. Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Since the AGTL signal pins receive power from the FSB these pins should not be driven allowing the level to return to Vccp for minimum power drawn by the termination resistors in this state In addition all other input pins on the FSB should be driven to the inactive state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the deassertion of the STPCLK signal When re entering the Stop Grant state from the Sleep state STPCLK should be deasserted ten or more bus clocks after the deassertion of SLP A transition to the HALT Grant Snoop state will occur when the processor detects a snoop on the FSB see Section 2 1 4 A transition to the Sleep state see Section 2 1 5 will occur with the assertion of the SLP signal While in the Stop Grant State SMI INIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal State Only one occurrence of each event will be recognized upon return to the Normal state Please refer to the FERR pin description in Section 4 2 for details on FERR break event behavior in the Stop Grant state While in Stop Grant state the processor will process snoops on the FSB and it will latch interrupts deliv
16. High Voltage VCCP V 3 VoL Output Low Voltage 0 0 20 V loL Output Low Current 16 50 mA 2 lio Leakage Current 200 UA 4 Cpad Pad Capacitance 1 7 2 3 3 0 pF 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at 0 2 V 3 Von is determined by value of the external pull up resistor to VCCP Please refer to platform RDDP for details 4 For Vin between 0 V and Voy 5 Cpad includes die capacitance only No package parasitics are included 28 Intel Celeron M Processor Datasheet Package Mechanical Specifications and Pin Information Package Mechanical Specifications and Pin Information The processor is available in 478 pin Micro FCPGA and 479 ball Micro FCBGA packages Different views of the Micro FCPGA package are shown in Figure 4 through Figure 6 Package dimensions are shown in Table 14 Different views of the Micro FCBGA package are shown in Figure 8 through Figure 10 Package dimensions are shown in Table 15 The Intel Celeron M processor die offset is illustrated in Figure 7 The Micro FCBGA may have capacitors placed in the area surrounding the die Because the die side capacitors are electrically conductive and only slightly shorter than the die height care should be taken to avoid contacting the capacitors with electrically conductive materials Doing so may short the capacitors and possibly damage the device or render it inactive The use of an insulat
17. LINTO VSS FERR LINT1 O Oe Q PSI VIDIO vss GooD O O VID VID 2 vss e o o VSS VID 3 VID 4 O e o DRDY VSS VID 5 O O e LOCK BPRI e o HITM VSS HIT O O e RS 2 vss DEFERF O O e DBSY TRDY O ec ADS VSS e o0 REQ vss ine O e Q me AP ee lk e Q O ADSTB vss pe AF O O e AW AS VSS O e o A t0j VSS VCCQ e o o vss A I5 A 11 8 O O e AG A 14 vss d 9 O m A 24 8 e o o vss Appt A 18 Ooe A 3yt A 2t VSS O e o A 30 t A 7 t VSS A 22 8 O AI VSS A 29 ADIT vss O O e o e o e o e O e O e O e o e o o o e e vss O vss vss SEN SLP DBR e o VSS DPSLP ao Ue Qe CLK amp o e o vcc e BPM Oy e vcc e o e o e o e O e O e O e O e o e o vcc 9 eoo O o e VSS BPM 2 10 11 12 13 14 15 16 17 18 vss mek ITP_CLK TCK VSS it o O O O e TRST BCLK1 BCLKO VSS 6 o e THERM RSVD VSS TEST3 TRIPE O O e O VCCP VSS VCCP VSS PRDY VSS TDO O O PREQ RESET VSS e o Oo VSS TMS TDI O 6 O VCCP VSS VCCP e oe vss VCCP VSS O e o VCCP VSS VCCP ROC HOT e o e o vss VCCP VSS VCC O oe VCCP VSS VCCP VSS TOP VIEW O o e o e o e vss vcc o e vcc vss O O A 25 t A 19 O e vss o e vss o e o A26 Al28 VSS o vcc SENSE O RSVD 1 2 3 4 5 6 7 8 o e O VSS VCC Other vc
18. Output D 32 Y26 Source Synch Input Output DBR AT CMOS Output D 33 AA24 Source Synch Input Output DBSY M2 Common Clock Input Output D 34 T25 Source Synch Input Output DEFER L4 Common Clock Input D 35 U23 Source Synch Input Output DINV O D25 Source Synch Input Output D 36 V23 Source Synch Input Output DINV 1 J26 Source Synch Input Output D 37 R24 Source Synch Input Output DINV 2 T24 Source Synch Input Output D 38 R26 Source Synch Input Output DINV 3 AD20 Source Synch Input Output D 39 R23 Source Synch Input Output DPSLP B7 CMOS Input D 40 AA23 Source Synch Input Output DPWR C19 Common Clock Input D 41 U26 Source Synch Input Output DRDY H2 Common Clock Input Output D 42 V24 Source Synch Input Output DSTBN O Z C23 Source Synch Input Output D 43 U25 Source Synch Input Output DSTBN 1 K24 Source Synch Input Output D 44 V26 Source Synch Input Output DSTBN 2 W25 Source Synch Input Output D 45 Y23 Source Synch Input Output DSTBN 3 AE24 Source Synch Input Output D 46 AA26 Source Synch Input Output DSTBP 0 C22 Source Synch Input Output D 47 Y25 Source Synch Input Output DSTBP 1 L24 Source Synch Input Output D 48 AB25 Source Synch Input Output DSTBP 2 W24 Source Synch Input Output 40 Intel Celeron M Processor Datasheet In Package Mechanical Specifications and Pin Information Table 23 Pin Listing by Pin Name Table 23 Pin Listing by Pin Name
19. Pin Information Table 23 Pin Listing by Pin Name In Table 23 Pin Listing by Pin Name Pin Name Wo m ia adi Direction Pin Name Tm ig Direction D 17 G25 Source Synch Input Output D 49 AC23 Source Synch Input Output D 18 L23 Source Synch Input Output D 50 Z AB24 Source Synch Input Output D 19 M26 Source Synch Input Output D 51 AC20 Source Synch Input Output D 20 H24 Source Synch Input Output D 52 AC22 Source Synch Input Output D 21 F25 Source Synch Input Output D 53 AC25 Source Synch Input Output D 22 G24 Source Synch Input Output D 54 AD23 Source Synch Input Output D 23 J23 Source Synch Input Output D 55 AE22 Source Synch Input Output D 24 M23 Source Synch Input Output D 56 AF23 Source Synch Input Output D 25 J25 Source Synch Input Output D 57 AD24 Source Synch Input Output D 26 L26 Source Synch Input Output D 58 AF20 Source Synch Input Output D 27 N24 Source Synch Input Output D 59 AE21 Source Synch Input Output D 28 f M25 Source Synch Input Output D 60 AD21 Source Synch Input Output D 29 H26 Source Synch Input Output D 61 FF AF25 Source Synch Input Output D 30 N25 Source Synch Input Output D 62 AF22 Source Synch Input Output D 31 K25 Source Synch Input Output D 63 AF26 Source Synch Input
20. Power Other E25 VSS Power Other D22 VCC Power Other E26 RSVD Reserved D23 VSS Power Other F1 VSS Power Other D24 D 10 Source Synch pea De VIDI CMOS Output F3 VID 2 CMOS Output D25 DINV 0 Source Synch a F4 vss Power Other D26 VSS Power Other F5 VSS Power Other E1 PSI CMOS Output F6 VCC Power Other E2 VIDIO CMOS Output F7 VSS Power Other E3 VSS Power Other F8 VCC Power Other E4 PWRGOOD CMOS Input F9 VSS Power Other E5 VCC Power Other F10 VCCP Power Other E6 VSS Power Other F11 VSS Power Other E7 VCC Power Other F12 VCCP Power Other E8 VSS Power Other F13 VSS Power Other E9 VCC Power Other F14 VCCP Power Other E10 VSS Power Other F15 VSS Power Other E11 VCCP Power Other F16 VCCP Power Other E12 VSS Power Other F17 VSS Power Other E13 VCCP Power Other F18 VCC Power Other E14 VSS Power Other F19 VSS Power Other E15 VCCP Power Other F20 VCC Power Other E16 VSS Power Other F21 VSS Power Other E17 VCC Power Other F22 VCC Power Other E18 VSS Power Other F23 TEST2 Test E19 VCC Power Other F24 VSS Power Other E20 VSS Power Other F25 D 21 8 Source Synch MM utput E21 VCC Power Other Intel Celeron M Processor Datasheet 51 Package Mechanical Specifications and Pin Information Table 24 Pin Listing by Pin Number Intel Table 24 Pin Listing by Pin Number
21. Refer to Chapter 4 for signal descriptions and termination requirements 2 BPM 2 0 ff and PRDY are AGTL output only signals 3 In processor systems where there is no debug port implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects CMOS Signals CMOS input signals are shown in Table 3 Legacy output FERR IERR and other non AGTL signals THERMTRIP and PROCHOT utilize Open Drain output buffers These signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the CMOS signals are required to be asserted for at least three BCLKs in order for the chipset to recognize them See Section 3 10 for the DC specifications for the CMOS signal groups Intel Celeron M Processor Datasheet 19 Electrical Specifications n 3 9 Table 4 3 10 20 Maximum Ratings Table 4 lists the processor s maximum environmental stress ratings The processor should not receive a clock while subjected to these conditions Functional operating parameters are listed in the AC and DC tables Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circuitry to resist damage from electro static discharge ESD system designers should always take precautions to avoid high static voltages or electric fields Proces
22. Signal Group DC Specifications Electrical Specifications Symbol Parameter Min Typ Max Unit Notes VCCP I O Voltage 0 997 1 05 1 102 V GTLREF Reference Voltage 2 VCCP 23 vecP b VOGP iv Je VIH Input High Voltage GTLREF 0 1 VCCP 0 1 V 3 4 6 VIL Input Low Voltage 0 1 GTLREF O 1 V 2 VOH Output High Voltage VCCP 4 6 Rir Termination Resistance 47 55 63 W 7 RON Buffer On Resistance 17 7 24 7 32 9 Ww 5 ILi Input Leakage Current 100 UA 8 Cpad Pad Capacitance 1 8 2 3 2 75 pF 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 ViLis defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 ViH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 VIH and VoH may experience excursions above VCCP However input signal drivers must comply with the signal quality specifications in Chapter 4 5 This is the pull down driver resistance Refer to processor I O Buffer Models for I V characteristics Measured at 0 31 x VCCP Roy min 0 38 X Rrr Ron typ 0 45 x Rrr Ron max 0 52 x Ry 6 GTLREF should be generated from VCCP with a 196 tolerance resistor divider The VCCP referred to in these specifications is the instantaneous VCCP 7 Rrr is the on die termination resistance measured at Vo of the AGTL ou
23. agents DINV 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DINV 3 0 signals are activated when the data on the data bus is inverted The bus agent will invert the data bus signals if more than half the bits within the covered group would change level in the next cycle DINV 3 0 Assignment To Data Bus Input a DINV 3 0 Output Bus Signal Data Bus Signals DINV 3 D 63 48 DINV 2 D 47 32 DINV 1 D 31 16 DINV O FF D 15 0 FF Intel Celeron M Processor Datasheet 57 Intel Table 25 Signal Description Sheet 3 of 7 Name Type Description DPSLP Input DPSLP when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state In order to return to the Sleep State DPSLP must be deasserted DPSLP is driven by the ICH4 M component and also connects to the MCH M component of the Intel 855PM Intel 855GM or 852GM chipset DPWR Input DPWR is a control signal from the Intel 855PM and Intel 855GM chipsets used to reduce power on the Intel Celeron M processor data bus input buffers DRDY Input Output DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of both FSB agents
24. decoupling on the Vccg lines if necessary Vccseuse Output Vccsense IS an isolated low impedance connection to processor core power Vcc It can be used to sense or measure power near the silicon with little noise Please refer to the platform design guides for termination recommendations and more details VID 5 0 Output VID 5 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc Unlike some previous generations of processors these are CMOS signals that are driven by the Intel Celeron M processor The voltage supply for these pins must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID pins becomes valid The VID pins are needed to support the processor voltage specification variations See Table 2 for the encoding of these pins The VR must supply the voltage that is reguested by the pins or disable itself VsssENsE Output Vsssense iS an isolated low impedance connection to processor core Vss It can be used to sense or measure ground near the silicon with little noise Please refer to the platform design guides for termination recommendations and more details Intel Celeron M Processor Datasheet ntel Intel Celeron Thermal Specifications and Design Considerations Thermal Specifications and Design Considerations The Intel Celeron M processor reguires a thermal
25. for the processor Test Bus also known as the Test Access Port Please refer to the TP700 Debug Port Design Guide and the platform design guides for termination requirements and implementation details TDI Input TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support Please refer to the TP700 Debug Port Design Guide and the platform design guides for termination requirements and implementation details TDO Output TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support Please refer to the TP700 Debug Port Design Guide and the platform design guides for termination requirements and implementation details TEST1 TEST2 TEST3 Input TEST1 TEST2 and TEST3 must be left unconnected but should have a stuffing option connection to Vss separately using 1 k pull down resistors Please refer to the platform design guides for more details THERMDA Other Thermal Diode Anode THERMDC Other Thermal Diode Cathode THERMTRIP Output The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 125 C This i
26. lcc Deep Sleep at 1 356 V 1 20 GHz 12 9 1 356 V 1 30 GHz 12 3 1 356 V 1 40 GHz 11 7 IDSLP 1 356 V 1 50 GHz 11 1 A 1 004 V 800 MHz ULV 3 2 1 004 V 900 MHz ULV 3 Vi ower supply current slew dlccipr a p PPly 0 5 A ns 8 loca loc for Veca supply 120 mA locp lec for Vccp supply 2 5 A NOTES 1 The typical values shown are the VID encoded voltages Static and Ripple tolerances for minimum and maximum voltages are defined in the load line tables Table 6 Table 7 Table 8 and Table 9 2 The voltage specifications are assumed to be measured at a via on the motherboard s opposite side of the processor s socket or BGA ball with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 Mohm minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe oR Ow this specification 6 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested 7 Measured at the bulk capacitors on the motherboard Specified at Vcc static nominal under maximum signal loading conditions Specified at the VID voltage The lccpgs max specification comprehends future processor frequencies Platforms should be designed to Figure 2 Illustration of Active State Vcc Static and Ripple Tolerances VID 1 356V Active State
27. mode takes precedence The Intel Thermal Monitor Automatic Mode must be enabled via BIOS for the processor to be operating within specifications This mode is selected by writing values to the Model Specific Registers MSRs of the processor After the automatic mode is enabled the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation When Intel Thermal Monitor is enabled and a high temperature situation exists the clocks will be modulated by alternately turning the clocks off and on at a 50 duty cycle Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase After the temperature has returned to a non critical level modulation ceases and the TCC goes inactive A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near the trip point The duty cycle is factory configured and cannot be modified Also the automatic mode does not require any additional hardware software drivers or interrupt handling routines Processor performance will be decreased by the same amount as the duty cycle when the TCC is active however with a properly designed and characterized thermal solution the TCC most likely will never be activated or will be activated only briefly during the most power intensive applications The TCC may also be activated using On Demand mode If bit 4 of the AC
28. plane 1 88 2 02 Overall height top of die to PCB surface including socket Refer to Note 1 4 74 5 16 A1 Pin length 1 95 2 11 Die height Pin side capacitor height B Pin diameter 0 28 D Package substrate length 34 9 E Package substrate width 34 9 D1 Die length 10 56 E1 Die width 7 84 To Package Substrate Center 17 5 G Die Offset from Package Center 1 133 e Pin pitch 1 27 K Package edge keep out 5 K1 Package corner keep out 7 Pin side capacitor boundary Pin tip radial true position Pin count Pdie Allowable pressure on the die for thermal solution 689 Ww Package weight 4 5 Package Surface Flatness 0 286 NOTE Overall height with socket is based on design dimensions of the Micro FCPGA package with no thermal solution attached Values are based on design specifications and tolerances This dimension is subject to change based on socket design OEM motherboard design or OEM SMT process Intel Celeron M Processor Datasheet a ntel Package Mechanical Specifications and Pin Information Figure 8 Micro FCBGA Package Top and Bottom Isometric Views 4 PACKAGE KEEPOUT p d CAPACITOR AREA TOP VIEW BOTTOM VIEW Intel Celeron9 M Processor Datasheet 33 Package Mechanical Specifications and Pin Information n 34 Figure 9 Micro FCBGA Package Top and Side Views 7 K1 SUBSTRATE KEEPOUT
29. solution to maintain temperatures within operating limits A complete thermal solution includes both component and system level thermal management features Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die The solution should make firm contact with the die while maintaining processor mechanical specifications such as pressure A typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally coupled to the processor using a heat pipe or direct die attachment A secondary fan or air from the processor fan may also be used to cool other platform components or lower the internal ambient temperature within the system The processor must remain within the minimum and maximum junction temperature Tj specifications at the corresponding thermal design power TDP value listed in Table 26 The maximum junction temperature is defined by an activation of the Intel Thermal Monitor in the processor Refer to Section 5 1 2 for more details Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the TDP indicated in Table 26 The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a
30. sustained period of time For more details on the usage of this feature refer to Section 5 1 2 In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification M Processor Datasheet 63 Thermal Specifications and Design Considerations Table 26 Power Specifications for the Intel Celeron M Processor Core Frequency i i Symbol amp Voltage Thermal Design Power Unit Notes 1 20 GHz amp 1 356 V 24 5 1 30 GHz amp 1 356 V 24 5 1 40 GHz amp 1 356 V 24 5 1 50 GHz amp 1 356 V 24 5 S TDP Z w 100 C Notes 1 ULV Intel Celeron Mprocessor 800 MHz and 1 004 V 7 900 MHz and 1 004 V 7 Symbol Parameter Min Typ Max Unit Notes Auto Halt Stop Grant Power at 1 356 V 1 20 GHz 9 9 a 1 356 V 1 30 GHz Br AH 1 356 V 1 40 GHz a7 w At50 C Note 2 PsGNT 1 356 V 1 50 GHz s 1 004 V 800 MHz ULV 20 1 004 V 900 MHz ULV 2 0 Sleep Power at 1 356 V 1 20 GHz 9 7 1 356 V 1 30 GHz 9 3 1 356 V 1 40 GHz 8 9 o Psp 1 356 V 1 50 GHz 8 5 w At 50 C Note 2 1 004 V 800 MHz ULV 1 9 1 004 V 900 MHz ULV 1 9 Deep Sleep Power at 1 356 V 1 20 GHz 7 7 1 356 V 1 30 GHz 7 3 1 356 V 1 40 GHz 6 9 5 Poste 1 356 V 1 50 GHz 6 6 W At 35 C Note 2 1 004 V 800 MHz ULV 1 5 1 004 V 900 MHz ULV 1 4 Ty Junction Temperature 0 100 C Notes 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solut
31. 0 o 1 1 o 1 1 126 1 1 1 0 1 1 076 o 1 1 1fofo 120 1 1 1 1 0 0 0 748 o 1 1 11 G 1 124 tae a a ea ez Oa a a ae U 1228 a a a et ee rie 0 1 1 1 1 1 SEs 3 9 Catastrophic Thermal Protection The processor supports the THERMTRIP signal for catastrophic thermal protection An external thermal sensor should also be used to protect the processor and the system against excessive temperatures Even with the activation of THERMTRIP which halts all processor internal clocks and activity leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor If the external thermal sensor detects a catastrophic processor temperature of 125 C maximum or if the THERMTRIP signal is asserted the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor Intel Celeron9 M Processor Datasheet 17 Electrical Specifications ntel 3 6 3 7 Signal Terminations and Unused Pins All RSVD RESERVED pins must remain unconnected Connection of these pins to Vcc Vss or to any other signal including each other can result in component malfunction or incompatibility with future Intel Celeron M processors See Section 4 1 for a pin listing of the processor and the location of all RSVD pins For reliable operation always connect unused inputs or bidirectional signals to an
32. 3 and REQ 4 0 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 Input Output Address strobes are used to latch A 31 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTB O AI31 17 ADSTB 1 BCLK 1 0 Input The differential pair BCLK Bus Clock determines the FSB frequency All FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss BNR Input Output BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions BPM 2 0 BPM 3 Output Input Output BPM 3 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 3 0 should connect the appropriate pins of all Intel Celeron M processor FSB agents This includes debug or performance monitoring tools Please refer to the platform de
33. 3 Power Other VCC AAT Power Other VCC AE15 Power Other VCC AA9 Power Other VCC AE17 Power Other VCC AA11 Power Other VCC AE19 Power Other VCC AA13 Power Other VCC AF8 Power Other VCC AA15 Power Other VCC AF10 Power Other VCC AA17 Power Other VCC AF12 Power Other VCC AA19 Power Other VCC AF14 Power Other VCC AA21 Power Other VCC AF16 Power Other VCC AB6 Power Other VCC AF18 Power Other VCC AB8 Power Other VCCA 0 F26 Power Other VCC AB10 Power Other VCCA 1 B1 Power Other VCC AB12 Power Other VCCA 2 N1 Power Other VCC AB14 Power Other VCCA 3 AC26 Power Other VCC AB16 Power Other VCCP D10 Power Other 42 Intel Celeron M Processor Datasheet l n Package Mechanical Specifications and Pin Information Table 23 Pin Listing by Pin Name Table 23 Pin Listing by Pin Name Pin Name Pa m aa adi Direction Pin Name mu m d ai Direction VCCP D12 Power Other VID 4 G4 CMOS Output VCCP D14 Power Other VID 5 H4 CMOS Output VCCP D16 Power Other Vss A2 Power Other VCCP E11 Power Other Vss A5 Power Other VCCP E13 Power Other VSS A8 Power Other VCCP E15 Power Other VSS A11 Power Other VCCP F10 Power Other VSS A14 Power Other VCCP F12 Power Other VSS A17 Power Other VCCP F14 Power Other VSS A20 Power Other V
34. 5 Power Other VSS G23 Power Other VSS D17 Power Other VSS G26 Power Other VSS D19 Power Other VSS H3 Power Other VSS D21 Power Other VSS H5 Power Other VSS D23 Power Other VSS H21 Power Other VSS D26 Power Other VSS H25 Power Other VSS E3 Power Other VSS J1 Power Other VSS E6 Power Other VSS J4 Power Other VSS E8 Power Other VSS J6 Power Other VSS E10 Power Other VSS J22 Power Other VSS E12 Power Other VSS J24 Power Other VSS E14 Power Other VSS K2 Power Other VSS E16 Power Other VSS K5 Power Other VSS E18 Power Other VSS K21 Power Other VSS E20 Power Other VSS K23 Power Other VSS E22 Power Other VSS K26 Power Other VSS E25 Power Other VSS L3 Power Other VSS F1 Power Other VSS L6 Power Other VSS F4 Power Other VSS L22 Power Other VSS F5 Power Other VSS L25 Power Other VSS F7 Power Other VSS M1 Power Other VSS F9 Power Other VSS M4 Power Other VSS F11 Power Other VSS M5 Power Other VSS F13 Power Other VSS M21 Power Other VSS F15 Power Other VSS M24 Power Other VSS F17 Power Other VSS N3 Power Other VSS F19 Power Other VSS N6 Power Other VSS F21 Power Other VSS N22 Power Other VSS F24 Power Other VSS N23 Power Other VSS G2 Power Other VSS N26 Power Other 44 Intel Celeron M Processor Datasheet l n Package Mechanical Specifications and Pin Information
35. 8 Micro FCBGA Package Top and Bottom Isometric Views asana aaan anan anana anana nana 33 9 Micro FCBGA Package Top and Side Views sanan eran aaa aaa aana aana na aaa emm eene 34 10 Micro FCBGA Package Bottom Vilew e eeeee eaaa anaa ana aaa aana naa aana aa aana CLLH nnne 35 11 The Coordinates of the Processor Pins as Viewed From the Top of the acil J O 38 4 Intel Celeron M Processor Datasheet intel Tables 1 BOIS EMIL LLLI a alaa jan aaa a A Ta aga aa aa A aa d ad aa a A aaa aka gaden a aaa 2 Voltage Identification Definition ses eeeenee eaaa eaaa eaaa aana enn nennen 3 FSB Pin GroliDS iu eaaa awa ga a a aa aa GA eee eee ees 4 Processor DC Absolute Maximum Ratings aana anae HYLL EL LL HYLL ELLYR HR aana anana anna 5 Voltage and Current Specifications sssssssessse nenne eee nennen nnns 6 Voltage Tolerances for Intel Celeron M Processor with VID 1 356 V Active State M E 7 Voltage Tolerances for Intel Celeron M Processor with VID 1 356 V Deep Sleep Slat e L 8 Voltage Tolerances for ULV Intel Celeron M Processor with VID 1 004 V toll ice UL UU FEE FE HF E S E 9 Voltage Tolerances for ULV Intel Celeron M Processor with VID 1 004 V BI eEs niic M 10 FSB Differential BCLK Specification
36. AF3 Source Synch Input Output A 30 AE1 Source Synch Input Output A 31 AF1 Source Synch Input Output A20M C2 CMOS Input ADS N2 Common Clock Input Output Pin Name T m 9 Direction ADSTB 0 FF U3 Source Synch Input Output ADSTB 1 AE5 Source Synch Input Output BCLK 0 B15 Bus Clock Input BCLK 1 B14 Bus Clock Input BNR L1 Common Clock Input Output BPM 0 C8 Common Clock Output BPM 1 B8 Common Clock Output BPM 2 AQ Common Clock Output BPM 3 C9 Common Clock Input Output BPRI J3 Common Clock Input BRO N4 Common Clock Input Output COMP 0 P25 Power Other Input Output COMP 1 P26 Power Other Input Output COMP 2 AB2 Power Other Input Output COMP 3 AB1 Power Other Input Output D 0 A19 Source Synch Input Output D 1 A25 Source Synch Input Output D 2 A22 Source Synch Input Output D 3 B21 Source Synch Input Output D 4 A24 Source Synch Input Output D 5 B26 Source Synch Input Output D 6 A21 Source Synch Input Output D 7 B20 Source Synch Input Output D 8 C20 Source Synch Input Output D 9 B24 Source Synch Input Output D 10 D24 Source Synch Input Output D 11 E24 Source Synch Input Output D 12 C26 Source Synch Input Output D 13TFF B23 Source Synch Input Output D 14 E23 Source Synch Input Output D 15 f C25 Source Synch Input Output D 16 H23 Source Synch Input Output Intel Celeron M Processor Datasheet 39 Package Mechanical Specifications and
37. CCP F16 Power Other VSS A23 Power Other VCCP K6 Power Other VSS A26 Power Other VCCP L5 Power Other VSS B3 Power Other VCCP L21 Power Other VSS B6 Power Other VCCP M6 Power Other VSS B9 Power Other VCCP M22 Power Other VSS B12 Power Other VCCP N5 Power Other VSS B16 Power Other VCCP N21 Power Other VSS B19 Power Other VCCP P6 Power Other VSS B22 Power Other VCCP P22 Power Other VSS B25 Power Other VCCP R5 Power Other VSS C1 Power Other VCCP R21 Power Other VSS C4 Power Other VCCP T6 Power Other VSS C7 Power Other VCCP T22 Power Other VSS C10 Power Other VCCP U21 Power Other VSS C13 Power Other VCCQ 0 P23 Power Other VSS C15 Power Other VCCQ 1 WA Power Other VSS C18 Power Other od AE7 Power Other Output VSS C21 Power Other VSS C24 Power Other VID 0 E2 CMOS Output VSS D2 Power Other VID 1 F2 CMOS Output VSS D5 Power Other VID 2 F3 CMOS Output VSS D7 Power Other VID 3 G3 CMOS Output VSS D9 Power Other Intel Celeron M Processor Datasheet 43 Package Mechanical Specifications and Pin Information Table 23 Pin Listing by Pin Name In Table 23 Pin Listing by Pin Name Pin Name Wo m ia adi Direction Pin Name Ta Direction VSS D11 Power Other VSS G6 Power Other VSS D13 Power Other VSS G22 Power Other VSS D1
38. Celeron M processor and the ultra low voltage ULV Intel Celeron M processor are high performance low power mobile processors with several microarchitectural enhancements over existing mobile Intel Celeron processors The Intel Celeron M processor is available at the following core frequencies in the Micro FCBGA and Micro FCPGA packaging technologies 1 20 GHz 1 356 V 1 30 GHz 1 356 V 1 40 GHz 1 356 V 1 50 GHz 1 356 V The ultra low voltage Intel Celeron M processor is available at the following frequency in the Micro FCBGA packaging technology 800 MHz 1 004 V 900 MHz 1 004 V The Micro FCPGA package plugs into a 479 hole surface mount zero insertion force ZIF socket which is referred to as the mPGA479M socket The following list provides some of the key features of this processor Supports Intel architecture with dynamic execution Manufactured on Intel s advanced 0 13 micron process technology with copper interconnect High performance low power core featuring architectural innovations like micro ops fusion and advanced stack management that reduce the number of micro ops handled by the processor On die primary 32 kB instruction cache and 32 kB write back data cache On die 512 kB second level cache with Advanced Transfer Cache architecture Advanced branch prediction and data prefetch logic Streaming SIMD extensions 2 SSE2 that enables breakthrough levels of performance in mul
39. ID 5 0 A 1 in this refers to a high voltage level and a 0 refers to low voltage level Intel Celeron M Processor Datasheet n Electrical Specifications Table 2 Voltage Identification Definition VID Vec VID Vec 5 4 3 2 1 0 y 5 4 3 2 1 0 T o ojojojoj o 178 1 0 0o 0 0 0 1 196 o ojojojoj 1 1692 1 0 0o 0 0 1 1 180 o ojojoj 1 o 1676 1 0 o o0o 1 0 1 164 o0jolololj1ilj1ilj 1660 1 9 89 8 4 1 1148 o ojoj1 oj o 1644 1 0 0o 1 0 0 1 132 ojo o 1 j o 2 2 a 1 0 41 1 116 o o o 1 1 0o 1612 1 o o 1 1 a 1100 ojoljol 1 9 1 JJ o0jolj1il 1 1 1 084 ojlo 1 olo oj 1580 J1 0o0l 1 j0o0ljoljolj 1 068 olo 1 olo ilsld41o oS 1 1 052 ofo 1 of 1 o 158 1 0 1 0 1 0 1 36 ge o 1 BEER ETERE 1 020 ofo 1 1 ofo 156 1 0 1 1 0 0 1 004 ofo 1 1 of1 150 1 0 1 1 0 1 0988 o o0 1 t 1 To 3 p4 o 0 972 g epa 3 3 mE 4 3 3159 0956 o 1 ojojojo 142 1 1 0o 0 0 0 0940 o 1 ojojoj 1 143 1 1 0 0 0 1 0924 o 1 ojoj 1 o 1420 1 1 0 0 1 0 0 908 o 1 ojoj 1 1 144 1 1 0 0 1 1 0892 o 1 oj 1 oj o 138 1 1 0 1 0 0 087 o 1 oj 1 0 1 132 1 1 0 1 0 1 0860 0 419 1356 T4185 34 8 0 844 ud g T 1340 1 TY D T1 1 0 828 o1 1 5o 0 1324 111 6 0 O 0 812 o 1 1 oj o 1 138 1 1 1 0 0 1 0796 o 1 1 o 1 o 12 1 1 1 0 1 0 0 78
40. Input B23 D 13 Source Synch Output C25 D 15 Source Synch Output Input Input B24 D 9 Source Synch Output C26 D 12 Source Synch Output B25 VSS Power Other D1 LINTO CMOS Input Input D2 VSS Power Other B26 D 5 Source Synch Output D3 FERR Open Drain Output C1 VSS Power Other D4 LINT1 CMOS Input C2 A20M CMOS Input D5 VSS Power Other C3 RSVD Reserved D6 VCC Power Other C4 VSS Power Other D7 VSS Power Other C5 TEST1 Test D8 VCC Power Other C6 STPCLK CMOS Input D9 VSS Power Other C7 VSS Power Other D10 VCCP Power Other C8 BPM 0 Common Clock Output D11 VSS Power Other C9 BPM 3 Common Clock Put Output D12 VCCP Power Other C10 VSS Power Other D13 VSS Power Other C11 TMS CMOS Input D14 VCCP Power Other C12 TDI CMOS Input D15 VSS Power Other C13 VSS Power Other D16 VCCP Power Other 50 Intel Celeron M Processor Datasheet l n Package Mechanical Specifications and Pin Information Table 24 Pin Listing by Pin Number Table 24 Pin Listing by Pin Number Me Pin Name Mii co dad Direction ia Pin Name idi Direction D17 VSS Power Other E22 VSS Power Other D19 vee PO E23 D 14 8 Source Synch a D19 VSS Power Other D20 vcc Power Other Ee DETUR Source Synch Output pu D21 VSS
41. M Processor Datasheet 3 2 3 3 Intel Celeron Electrical Specifications Electrical Specifications FSB and GTLREF The Intel Celeron M processor FSB uses Advanced Gunning Transceiver Logic AGTL signalling technology a variant of GTL signalling technology with low power enhancements This signalling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates The termination voltage level for the Intel Celeron M processor AGTL signals is VCCP 1 05 V nominal Due to speed improvements to data and address bus signal integrity and platform design methods have become more critical than with previous processor families Design guidelines for the Intel Celeron M processor FSB will be detailed in the platform design guides The AGTL inputs require a reference voltage GTLREF that is used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF must be generated on the system board Termination resistors are provided on the processor silicon and are terminated to its I O voltage VCCP Intel s 855PM 855GM and 852GM chipsets will also provide on die termination thus eliminating the need to terminate the bus on the system board for most AGTL signals Refer to the platform design guides for board level termination resistor requirements The AGTL bus depends on incident wave switching Therefore timing calculations for AGTL signals are based on flig
42. O O D A7 D 32 e o vss D 46 O e D 4BjR VSS O O D 53 VCCA 3 e o VSS GTLREF 38 Intef Celeron9 M Processor Datasheet In Package Mechanical Specifications and Pin Information Table 23 Pin Listing by Pin Name Table 23 Pin Listing by Pin Name Pin Name a a Direction A 3 P4 Source Synch Input Output A 4 U4 Source Synch Input Output A 5 V3 Source Synch Input Output A 6 R3 Source Synch Input Output A 7 V2 Source Synch Input Output A 8 W1 Source Synch Input Output A 9 T4 Source Synch Input Output A10 W2 Source Synch Input Output A 11 Y4 Source Synch Input Output A 12 Y1 Source Synch Input Output A 13 U1 Source Synch Input Output A 14 AA3 Source Synch Input Output A 15 Y3 Source Synch Input Output A 16 AA2 Source Synch Input Output A 17 AF4 Source Synch Input Output A 18 AC4 Source Synch Input Output A 19 AC7 Source Synch Input Output A 20 AC3 Source Synch Input Output A 21 AD3 Source Synch Input Output A 22 AE4 Source Synch Input Output A 23 AD2 Source Synch Input Output A 24 AB4 Source Synch Input Output A 25 AC6 Source Synch Input Output A 26 AD5 Source Synch Input Output A 27 AE2 Source Synch Input Output A 28 AD6 Source Synch Input Output A 29
43. PI Intel Thermal Monitor Control register is written to a 1 the TCC will be activated immediately independent of the processor temperature When using On Demand mode to activate the TCC the duty cycle of the clock modulation is programmable via bits 3 1 of the same ACPI Intel Thermal Monitor Control Register In automatic mode the duty cycle is fixed at 50 on 50 off in On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in Intel Celeron M Processor Datasheet tel Note Thermal Specifications and Design Considerations 12 5 increments On Demand mode can be used at the same time automatic mode is enabled however if the system tries to enable the TCC via On Demand mode at the same time automatic mode is enabled and a high temperature condition exists automatic mode will take precedence An external signal PROCHOT processor hot is asserted when the processor detects that its temperature is above the thermal trip point Bus snooping and interrupt latching are also active while the TCC is active PROCHOT will not be asserted when the processor is in the Stop Grant Sleep and Deep Sleep low power states internal clocks stopped hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within the 100 C maximum specification If the platform thermal solution is not able to maintain the processor junction temperature within the max
44. SS Power Other AD6 A 28 Source Synch ae utput AC6 A 25 amp Source Synch Iul y Output AD7 vss Power Other ACT AT19 8 Source Synch e AD8 VCC Power Other utput AD9 VSS Power Other AC8 VSS Power Other AD10 VCC Power Other AC9 VCC Power Other AD11 VSS Power Other AC10 VSS Power Other AD12 VCC Power Other AC11 VCC Power Other AD13 VSS Power Other AC12 VSS Power Other AD14 VCC Power Other AC13 VCC Power Other AD15 VSS Power Other AC14 VSS Power Other AD16 VCC Power Other AC15 VCC Power Other AD17 VSS Power Other AC16 VSS Power Other AD18 VCC Power Other AC17 VCC Power Other AD19 VSS Power Other AC18 VSS Power Other Input AC19 VCC Power Other ADZO DINV S Source Synch Output Input Input AC20 D 51 Source Synch Output AD21 D 60 Source Synch Output AC21 VSS Power Other AD22 VSS Power Other Input Input AC22 D 52 Source Synch Output AD23 D 54 Source Synch Output Input Input AC23 D 49 Source Synch Output AD24 D 57 Source Synch Output AC24 VSS Power Other AD25 VSS Power Other AC25 DIS3 Source Synch a AD26 GTLREF Power Other utput AE1 A 30 4 Source Synch Input AC26 VCCA 3 Power Other Output AD1 VSS Power Other Input AE2 A 27 Source Synch Output AD2 A231 Source Synch nput y Output AE3 vss Power Other Input Input AD3 A 21 Source Synch Output AE4 A 22 Source Synch Output ADA vem dissi d AES ADSTB 1 Source Synch a 48 Intel Celeron M Processor Datasheet In Package Me
45. Specifications and Design Considerations eessssse 63 5 1 Thermal Specifications sasen uu LA GALLAI anana ILL LL LL FL LL FN 65 5143 Thermal Diode eee yn GC aaa a ea eaten 65 5 1 2 Intel Thermal Monitor YAA LL LL LI 66 6 Debug Tools Specifications seisssiscnndscccecensateassanssccantonnsiesesvaneanngncnniconrccensanesnennnnscnstenns 69 6 1 Logic Analyzer Interface LAI c cccceecceeceeeeeeeeeeeeeeaaeeaeeeeeeeeeeeeeseseenneneaees 69 6 1 1 Mechanical Considerations eeuu ueu LLALL LL LL FL LL uu 69 6 1 2 Electrical Considerations aas LI LILI LL LL nnn 69 Inte Celeron M Processor Datasheet 3 Figures 1 Clock Control States eere Rer a ad aaa a Ag da aa dina naja Aa aaa aa ai ngga a 11 2 Illustration of Active State VCC Static and Ripple Tolerances asas aaan anane a aana e anan anana 22 3 Illustration of Deep Sleep VCC Static and Ripple Tolerances sse 24 4 Micro FCPGA Package Top and Bottom Isometric Views asane aana naa anaa aan anana nana 29 5 Micro FCPGA Package Top and Side Views sunu aa aana aana aaa nana aaa ana mnes 30 6 Micro FCPGA Package Bottom View naas ae aane eaaa aaa anaa aana naen aaa aa mmm 31 7 Intel Celeron M Processor Die Offset a aaaaaaa aana naen anan anana LL LL LLY NNI RHY Y EL LLY LL nnne 31
46. VCC E5 Power Other RS 0 H1 Common Clock Input VCC E7 Power Other RS 1 K1 Common Clock Input VCC E9 Power Other RS 2 L2 Common Clock Input VCC E17 Power Other RSVD AF7 Reserved VCC E19 Power Other RSVD B2 Reserved VCC E21 Power Other RSVD C14 Reserved VCC F6 Power Other RSVD C3 Reserved VCC F8 Power Other Intel Celeron M Processor Datasheet 41 Package Mechanical Specifications and Pin Information Table 23 Pin Listing by Pin Name In Table 23 Pin Listing by Pin Name Pin Name Wo m a Direction Pin Name Tm i Direction VCC F18 Power Other VCC AB18 Power Other VCC F20 Power Other VCC AB20 Power Other VCC F22 Power Other VCC AB22 Power Other VCC G5 Power Other VCC AC9 Power Other VCC G21 Power Other VCC AC11 Power Other VCC H6 Power Other VCC AC13 Power Other VCC H22 Power Other VCC AC15 Power Other VCC J5 Power Other VCC AC17 Power Other VCC J21 Power Other VCC AC19 Power Other VCC K22 Power Other VCC AD8 Power Other VCC U5 Power Other VCC AD10 Power Other VCC V6 Power Other VCC AD12 Power Other VCC V22 Power Other VCC AD14 Power Other VCC W5 Power Other VCC AD16 Power Other VCC W21 Power Other VCC AD18 Power Other VCC Y6 Power Other VCC AE9 Power Other VCC Y22 Power Other VCC AE11 Power Other VCC AA5 Power Other VCC AE1
47. ZONE DO NOT CONTACT PACKAGE 8 places 0 20 i INSIDE THIS LINE 5 K 4 places A nja kab Pe 35 E PIN A1 CORNER p 0 78 b i p ra 479 places P NOTE All dimensions in millimeters Values shown for reference only Refer to Table 15 for details Intef Celeron9 M Processor Datasheet Figure 10 Micro FCBGA Package Bottom View Package Mechanical Specifications and Pin Information AF AE AD AC AB UU ooooooooooooooooooooooooo f a 25X 1 27 e ooooooo ooooooo ooooooo 00009090 ooooooo ooooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo Ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooooo ooooooo ooooooo 0000000 00009090 ooooooo 3 5 T7 2 4 6 8 L 25X 127 e OOOOOO oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo 1 625 S 4 places ooooooooooooo oooo0000000000 oooo0000000000 oooo0000000000 0000000000000 1 625 S ooooooooooooo 4 places oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo ooo0000000000 ooooooooooooo ooooooooooooo ooo00000000000 oooooo00000000 ooooooooooooo 14 16 18 2 2 24 26 NOTE All dimensions in millimeters Values shown for reference only Refer to Table 15 for details Intel Celeron M Processor Datasheet 35 Package Mechanical Specifications and Pin Information n Table 15 Micro FCBGA Package
48. ance 3 06 ohms 2 3 5 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range Characterized at 100 C Not 100 tested Specified by design characterization The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation AUN M Processor Datasheet 65 Thermal Specifications and Design Considerations n 5 1 2 66 lew ls X e aVD nKT 1 Where ls saturation current g electronic charge Vp voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin 5 The series resistance Ry is provided to allow for a more accurate measurement of the diode junction temperature Rr as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor Rr can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation Terror Rr X N 1 X IFwminl no q x In N Intel Thermal Monitor The Intel Thermal Monitor helps control t
49. ansceiver Logic AGTL signal technology a variant of GTL signalling technology with low power enhancements The term AGTL has been used for Assisted Gunning Transceiver Logic technology on other Intel products Terminology Term Definition A f symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level FSB Front Side Bus refers to the interface between the processor and system core logic also known as the chipset components Intel Celeron M Processor Datasheet n amp Introduction 1 2 References The following documents may be beneficial when reading this document Please note that platform design guides when used throughout this document refer to the following documents Jntel 852GM Chipset Platform Design Guide Intel 855GM 855GME Chipset Platform Design Guide Intel 855PM Chipset Platform Design Guide Table 1 References
50. appropriate signal level Unused active low AGTL inputs may be left as no connects if AGTL termination is provided on the processor silicon Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected For details on signal terminations please refer to the platform design guides TAP signal termination requirements are also discussed in TP700 Debug Port Design Guide The TESTI TEST2 and TEST3 pins must be left unconnected but should have a stuffing option connection to Vgs separately via 1 kQ pull down resistors FSB Signal Groups In order to simplify the following discussion the FSB signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF as a reference level In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals which are dependant upon the crossing of the rising edge of BCLKO and the falling edge of BCLK1 The second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLK0 Asychronous signals are still pre
51. ase refer to the platform design guides IGNNE Input IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT Input INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal However to ensure recognition of this signal following an Input Output Write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT must connect the appropriate pins of both FSB agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST For termin
52. ation requirements please refer to the platform design guides ITP_CLK 1 0 Input ITP_CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board ITP_CLK 1 0 are used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemented in the system ITP_CLK 1 0 are no connects These are not processor signals LINT 1 0 Input LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt reguest signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK Input Output LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of both FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the FSB it will wai
53. aueeeeunaes 13 2 3 Processor Power Status Indicator PSl Signal sess 14 3 Electrical Specifications an aeaaaee DADL LE Dan RSS D AREE HER RR RAE YR RE 15 3 1 FSB and GTLREF usseeuu uu LILI aaa a LL a baa aa LL LLI FL LL 15 3 2 Power and Grourd PIBS 2 1 iode Ru wd ida co DA SA SD E dna I ad aa gan A 15 3 3 Decoupling Guidelines iate tta a n d e E orae 15 9 3 1 VCC Decoupling sine iE en tta betae avait 16 3 3 3 FSB AGTL Decoupl g essri aana kaga na agan E emen 16 3 3 8 FSB Clock BCLK 1 0 and Processor Clocking 16 3 4 Voltage Identification aa ia to e ete to add geen ais 16 3 5 Catastrophic Thermal Protection cccccccceeeeeeeeeeeeeeeeaaecaeeeeeeeeeeeeeteeeseenaees 17 3 6 Signal Terminations and Unused Pins essseee eaaa 18 3 7 FSB Signal GFOUDS irae FRY terre dese rior eret IF Er rn bn E taeda uh 18 3 8 CMOS Signals cette rrt RR COE ORAU ADEGAU FD SAU ada aaa GLENN AWR RR ERR SER EROR d aa 19 3 9 Maximum RATINGS i ride ab a Eire deo tar tein ten ede e dee eode toned ynd A daa 20 3 10 Processor DC Specifications ssssssssssssssssseeseeeeene eene 20 4 Package Mechanical Specifications and Pin Information 29 4 1 Processor Pin Out and Pin List aee LL LLALL I nenne 37 4 2 Alphabetical Signals Reference sss 56 5 Thermal
54. c Pin B2 is depopulated on the Micro FCPGA package vss vcc vss vcc vss vcc VSS vcc VSS 19 20 O e D 0 VSS e o vss D 7 O o DPWR D 8 e o Vss vcc o e e o e e O DISIK DINV 3 vss O D 58 i 20 vss 21 22 O O D 6M D 2 O e DB VSS e DST P Oy e o vcc o e e o o e e o o e e o O e e o O e e o vccP O e o O e e O 6 e o vss vcc vec vss e o vcc o o e e o VSS D 52 O e D 60 amp VSS O O D s9 D 55 e o VSS D 62 21 22 23 24 e o vss D 4 f O O D 13 8f DIDIK DSTBN oy vss e o vss D to O O DIAH D 11 O e TEST2 VSS e o VSS D 22 O O D 16 D 20 O we D 23 8 vss e o vss DSTBN Ug DSTBP pues DEO D 24j VSS e o vss Dp O e VccQ 0 vss O o D 39 D 37 e o vss DINV 2 D 35 VSS O o D 36 D 42 9 vss 2 O e D 45 VSS O O D 40 D 33 e o vss D S0 O e D 49 VSS O O D 54 D 57 e mes DS vss BH O e D 56 VSS 23 24 25 26 O e D vss e o vss DISIK O 0 D 15 8 D 12 8 DINV 0 vss e o vss RSVD O O D 21 VCCA 0 O e D I7Z VSS e o vss D 29p DISIK VSS e o vss D 26 O O D 28 j amp D 19 8 O D 30 VSS Ren She VSS D 38 O w D 34 f VSS O O D 43 D 41 e o VSS D 44 RON e 2j VSS
55. chanical Specifications and Pin Information Table 24 Pin Listing by Pin Number Table 24 Pin Listing by Pin Number Fin Pin Name Signal Buffer Direction Pin Pin Name Signal Butter Direction Number Type Number Type AE6 VSS Power Other AF8 VCC Power Other AET VCCSENSE Power Other Output AF9 VSS Power Other AE8 VSS Power Other AF10 VCC Power Other AE9 VCC Power Other AF11 VSS Power Other AE10 VSS Power Other AF12 VCC Power Other AE11 VCC Power Other AF13 VSS Power Other AE12 VSS Power Other AF14 VCC Power Other AE13 VCC Power Other AF15 VSS Power Other AE14 VSS Power Other AF16 VCC Power Other AE15 VCC Power Other AF17 VSS Power Other AE16 VSS Power Other AF18 VCC Power Other AE17 VCC Power Other AF19 VSS Power Other AE YSS Powenother AF20 D 58 Source Synch a i AE19 VCC Power Other AF21 VSS Power Other AE20 VSS Power Other Input m m EN Input AF22 D 62 Source Synch Output Output Input io Ee MY Input AF23 D 56 Source Synch Output y Output AF24 VSS Power Other AE23 VSS Power Other Input Input AF25 D 61 Source Synch Output AE24 DSTBN 3 F Source Synch o utput AF26 D 63 Source Synch MPU Input Output AE25 DSTBP 3 Source Synch o utput B1 VCCA 1 Power Other AE26 VSS Power Other B2 RSVD Reserved AF1 A31 Source Sy
56. ck Input J2 LOCK Common Clock Input L5 VCCP Power Other Output L6 VSS Power Other J3 BPRI Common Clock Input L21 VCCP Power Other 52 Intel Celeron M Processor Datasheet In Package Mechanical Specifications and Pin Information Table 24 Pin Listing by Pin Number Table 24 Pin Listing by Pin Number Fin Pin Name Signal Buffer Direction Pin Pin Name Signal Butter Direction Number Type Number Type L22 VSS Power Other N25 D 30 Source Synch M hd utput Input L23 DUIS Source Synch Output N26 vss Power Other Input Input L24 DSTBP 1 Source Synch Output P1 REQ 3 Source Synch Output L25 VSS Power Other P2 VSS Power Other Input Input L26 D 26 Source Synch Output P3 REQ 1 Source Synch Output M1 VSS Power Other Input P4 A 3 Source Synch Output M2 DBSY Common Clock PUY Output P5 VSS Power Other M3 TRDY Common Clock Input P6 VCCP Power Other M4 VSS Power Other P21 VSS Power Other M5 VSS Power Other P22 VCCP Power Other M6 VCCP Power Other P23 VCCQ 0 Power Other M21 VSS Power Other P24 VSS Power Other M22 VCCP Power Other P25 COMP O Power Other Mod utput Input M23 D 24 Source Synch Output Input P26 COMP 1 Power Other 0 utput M24 VSS Power Other R1 VSS Power Other M25 D 28 Source Synch MMPUY Output R2 REQ O S
57. d Deep Sleep states for optimal power management See Figure 1 for a visual representation of the processor low power states Clock Control States STPCLK asserted SLP asserted SLP de asserted DPSLP snoop de asserted occurs DPSLP serviced asserted STPCLK de asserted serviced 0001 04 Halt break A2Z0M INIT INTR NMI PREQ RESET SMI or APIC interrupt Normal State This is the normal operating state for the processor AutoHALT Power Down State AutoHALT is a low power state entered when the processor executes the HALT instruction The processor will transition to the Normal state upon the occurrence of SMI INIT LINT 1 0 NMI INTR or FSB interrupt message RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal mode or the AutoHALT Power Down state See the Intel Architecture Software Developer s Manual Volume III System Programmer s Guide for more information M Processor Datasheet 11 Low Power Features ntel amp 2 1 5 The system can generate a STPCLK while the processor is in the AutoHALT Power Down state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state While in AutoHALT Power Down state the processor will process bus snoops Stop Grant State When the STPCLK pin is asserted the Stop
58. ecognize only assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units If DPSLP is asserted while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state SMIZ Input SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMIFF is asserted during the deassertion of RESET the processor will tristate its outputs STPCLK Input STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Input TCK Test Clock provides the clock input
59. efore placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s Web Site Intel Intel logo Celeron and MMX are registered trademarks or trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2004 Intel Corporation 2 Intel Celeron M Processor Datasheet intel Contents 1 THO GUC TION FFF e NENN EY sounds EA EF HAF REA NR RR RAE 7 1 1 Terminology FF Ero iio uie EF TF YY iu Eh c E EO o dade P eh 8 1 2 Reference m IEEE TT NT 9 1 3 State of BITE aaa a EE 9 2 Low Power Features tei ides recentia cede usata yc ce ek E adeo EDD ERA YDY Cn 11 2 1 Clock Control and Low Power States ssssesssesee enema 11 2 1 Normal State oie eene cisco RY sone eee nope cux 11 2 1 2 AutoHALT Power Down State ee e eeui ueu LILI I I LI enne nnns 11 2 1 3 Stop Grant State aaa aa aan aa sa RYN RAF SE ddan Rao NAU ERR e HEP IA ang ian 12 2 1 4 HALT Grant Snoop State sasa sasana A a ga ad NG Aga a 12 2 1 5 Sleep State scene coe eti e a pa gga TA a GA eaaa RE SEM A ga akah 12 2 1 6 Deep Sleep State aa sia aba aa nai da aab A ag GA dag e a na an daja kaa ae 13 2 2 FSB Low Power Enhancements 0 0ccccccccccceeceeeceecesuueecessuuseeeeuseueuaeeee
60. er M6 ITP CLK 0 CMOS input VSS AE20 Power Other M7 vss Power Other ue BER Power Olher A18 THERMDC Power Other VSS AE26 Power Other iut A19 DIO Source Synch Cn i VSS AF2 Power Other upu vss AF5 Power Other AM ys Fowenother Input VSS AF9 Power Other A21 D 6 Source Synch Output VSS AF11 Power Other A22 DI2 Source Synch on VSS AF13 Power Other upu vss AF15 Power Other dai Yum Kowen OMET Input VSS AF17 Power Other A24 D 4 Source Synch Output VSS AF19 Power Other 46 Intel Celeron M Processor Datasheet In Package Mechanical Specifications and Pin Information Table 24 Pin Listing by Pin Number Table 24 Pin Listing by Pin Number Pin Pin Name Signal Buffer Direction Pin Pin Name Signal Butter Direction Number Type Number Type Input Input A25 D 1 Source Synch Output AB1 COMP 3 Power Other Output pen Nas EEO AB2 COMP 2 Power Other a AA1 VSS Power Other AB3 VSS Power Other AA2 AT16H Source Synch pull y Output Input AB4 A 24 Source Synch o utput AA3 A14 Source Synch pull Output AB5 VSS Power Other AA4 VSS Power Other AB6 VCC Power Other AA5 VCC Power Other AB7 VSS Power Other AA6 VSS Power Other AB8 VCC Power Other AA7 VCC Power Other AB9 VSS Power Other AA8 VSS Po
61. ered on the FSB The PBE signal can be driven when the processor is in Stop Grant state PBE will be asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state HALT Grant Snoop State The processor will respond to snoop or interrupt transactions on the FSB while in Stop Grant state or in AutoHALT Power Down state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or AutoHALT Power Down state as appropriate Sleep State The Sleep state is a low power state in which the processor maintains its context maintains the phase locked loop PLL and has stopped all internal clocks The Sleep state can only be entered from Stop Grant state Once in the Stop Grant state the processor will enter the Sleep state upon Intel Celeron M Processor Datasheet 2 1 6 2 2 Intel Celeron Low Power Features the assertion of the SLP signal The SLP pin should only be asserted when the processor is in the Stop Grant
62. he processor temperature by activating the TCC when the processor silicon reaches its maximum operating temperature The temperature at which the Intel Thermal Monitor activates the thermal control circuit TCC is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would not be detectable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long term reliability of the processor In addition a thermal solution that is significantly underdesigned may not be capable of cooling the processor even when the TCC is active continuously The Intel Thermal Monitor controls the processor temperature by modulating starting and stopping the processor core clocks when the processor silicon reaches its maximum operating temperature The Intel Thermal Monitor uses two modes to activate the TCC Automatic mode and On Demand mode If both modes are activated automatic
63. ht time as opposed to capacitive deratings Analog signal simulation of the FSB including trace lengths is highly recommended when designing a system Power and Ground Pins For clean on chip power distribution the Intel Celeron M processor will have a large number of Voc power and Vss ground inputs All power pins must be connected to Vcc power planes while all Vsg pins must be connected to system ground planes Use of multiple power and ground planes is recommended to reduce I x R drop Please refer to the platform design guides for more details The processor Vcc pins must be supplied the voltage determined by the VID Voltage ID pins Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5 Failure to do so can result in timing violations or reduced lifetime of the component For further information and design guidelines refer to the platform design guides M Processor Datasheet 15 Electrical Specifications ntel T 3 3 1 3 3 2 3 3 3 3 4 Vcc Decoupling Regulator solutions need to provide bulk capacitance with a low effective se
64. ications ntel Table 7 Voltage Tolerances for Intel Celeron M Processor with VID 1 356 V Deep Sleep State VID 71 356 V Offset 1 2 moug STATIC Ripple loc A Vec V Min Max Min Max 0 0 1 340 1 319 1 360 1 309 1 370 0 8 1 337 1317 1 358 1 307 1 368 16 1 335 1314 1 355 1 304 1 365 25 1 332 1312 1 353 1 302 1 363 3 3 1 330 1 340 1 350 1 300 1 360 4 1 1 327 1 307 1 348 1 297 1 358 a 4 9 1 325 1 305 1 345 1 295 1 355 o 57 1323 1 302 1 343 1 292 1 353 2 6 6 1 320 1 300 1 340 1 290 1 350 a 74 1 318 1 297 1 338 1 287 1 348 82 1 345 1 295 1 335 1 285 1 345 9 0 1313 1 292 1 333 1 282 1 343 9 8 1 310 1 290 1 331 1 280 1 341 10 7 1 308 1 287 1 328 1 277 1 338 11 5 1 305 1 285 1 326 1 275 1 336 12 3 1 303 1 282 1 323 1 272 1 333 Figure 3 Illustration of Deep Sleep Vcc Static and Ripple Tolerances VID 1 356V Deep Sleep 00 20 40 6 0 80 10 0 120 Icc A SIATC Static Mn Static Max Ripple Mn Ripple Max 24 Intel Celeron M Processor Datasheet Intel Table 8 Voltage Tolerances for ULV Intel Celeron M Processor with VID 1 004 V Active Electrical Specifications State VID 1 004 V Offset 0 mane STATIC Ripple Vcc A Vec V Min Max Min Max 0 1 004 0 989 1 019 0 979 1 029 0 3 1 003
65. ile maintaining context Deep Sleep state is entered by asserting the DPSLP pin while in the Sleep state BCLK may be stopped during the Deep Sleep state for additional platform level power savings BCLK stop restart timings on Intel 855PM ICH4 M Intel 855GM ICH4 M and Intel 852GM ICH4 M chipset based platforms with the CK 408 clock chip are as follows Deep Sleep entry DPSLP and CPU_STP are asserted simultaneously CK 408 will stop tristate BCLK within 2 BCLKs a few nanoseconds Deep Sleep exit DPSLP and CPU_STP are deasserted simultaneously CK 408 will drive BCLK to differential DC levels within 2 3 ns and starts toggling BCLK 2 6 BCLK periods later To re enter the Sleep state the DPSLP pin must be deasserted BCLK can be restarted after DPSLP deassertion as described above A period of 30 microseconds to allow for PLL stabilization must occur before the processor can be considered to be in the Sleep State Once in the Sleep state the SLP pin must be deasserted to re enter the Stop Grant state While in Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior When the processor is in Deep Sleep state it will not respond to interrupts or snoop tran
66. imum specification the system must initiate an orderly shutdown to prevent damage If the processor enters one of the above low power states with PROCHOT already asserted PROCHOT will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point If automatic mode is disabled the processor will be operating out of specification Whether the automatic or On Demand modes are enabled or not in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature of approximately 125 C At this point the FSB signal THERMTRIP will go active THERMTRIP activation is independent of processor activity and does not generate any bus cycles When THERMTRIP is asserted the processor core voltage must be shut down within the time specified in Chapter 3 Intel Celeron M Processor Datasheet 67 Thermal Specifications and Design Considerations 68 Intel Celeron M Processor Datasheet 6 1 6 1 1 6 1 2 Debug Tools Specifications Debug Tools Specifications Please refer to the 7P700 Debug Port Design Guide and the platform design guides for information regarding debug tools specifications Logic Analyzer Interface LAI Intel is working with logic analyzer vendors to provide LAIs for use in debugging Intel Celeron M processor systems The following information is general in nature Specific informati
67. ing material between the capacitors and any thermal solution should be considered to prevent capacitor shorting Figure 4 Micro FCPGA Package Top and Bottom Isometric Views 42 TARA REFUOUT CAPACITOR AREA LABEL RN ED TOP VIEW BOTTOM VIEW NOTE All dimensions in millimeters Values shown for reference only Refer to Table 14 for details Intel Celeron9 M Processor Datasheet 29 Package Mechanical Specifications and Pin Information n Figure 5 Micro FCPGA Package Top and Side Views 7 K1 SUBSTRATE KEEPOUT ZONE 8 places DO NOT CONTACT PACKAGE INSIDE THIS LINE 5 K 4 places i lt E 1 25 MAX o o A i 3 35 D 0 32 B 478 places ya 2 032 0 08 35 E PIN A1 CORNER A1 NOTE All dimensions in millimeters Values shown for reference only Refer to Table 14 for details 30 Intel Celeron M Processor Datasheet n Package Mechanical Specifications and Pin Information 25X 127 NOTE All dimensions in millimeters Values shown for reference only Refer to Table 14 for details Figure 7 Intel Celeron M Processor Die Offset Intel Celeron9 M Processor Datasheet 31 Package Mechanical Specifications and Pin Information 32 Table 14 Micro FCPGA Package Dimensions Symbol Parameter Min Max A Overall height top of die to package seating
68. intel Intel Celeron M Processor Datasheet June 2004 Order Number 300302 003 IINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Celeron M Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and b
69. iod D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DINV Guad Pumped Signal Groups DSTBNW D 63 0 a Data Group DSTBP DINV D 15 0 FF 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DINV pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DINV signal When the DINV signal is active the corresponding data group is inverted and therefore sampled active high DBR Data Bus Reset is used only in processor systems where no debug port DBR Output is implemented on the system board DBR is used by a debug port interposer p so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect DBR is not a processor signal DBSY Data Bus Busy is asserted by the agent responsible for driving data on DBSY Input the FSB to indicate that the data bus is in use The data bus is released after Output DBSY is deasserted This signal must connect the appropriate pins on both FSB agents DEFER is asserted by an agent to indicate that a transaction cannot be DEFER Input guaranteed in order completion Assertion of DEFER is normally the p responsibility of the addressed memory or Input Output agent This signal must connect the appropriate pins of both FSB
70. ion The TDP is not the maximum theoretical power the processor can dissipate 2 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum T has been reached Refer to Section 5 1 for more details 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 64 Intel Celeron M Processor Datasheet 5 1 5 1 1 Note Table 27 Table 28 Intel Celeron Thermal Specifications and Design Considerations Thermal Specifications Thermal Diode The Intel Celeron M processor incorporates two methods of monitoring die temperature the Intel Thermal Monitor and the thermal diode The Intel Thermal Monitor detailed in Section 5 1 must be used to determine when the maximum specified processor junction temperature has been reached The second method the thermal diode can be read by an off die analog digital converter a thermal sensor located on the motherboard or a standalone measurement kit The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but cannot be used to indicate that the maximum Ty of the processor has been reached Please see Section
71. nch InpuU Output B3 VSS Power Other AF2 VSS Power Other B4 SMI CMOS Input Input B5 INIT CMOS Input AF3 A 29 Source Synch Output B6 VSS Power Other AF4 AT 7HE Source Synch InpuU Output B7 DPSLP CMOS Input AF5 VSS Power Other B8 BPM 1TFF Common Clock Output AF6 VSSSENSE Power Other Output B9 VSS Power Other AF7 RSVD Reserved B10 PREQ Common Clock Input Intel Celeron M Processor Datasheet 49 Package Mechanical Specifications and Pin Information Table 24 Pin Listing by Pin Number In Table 24 Pin Listing by Pin Number Fin Pin Name Signal Buffer Direction Pin Pin Name Signal Butter Direction Number Type Number Type B11 RESET Common Clock Input C14 RSVD Reserved B12 VSS Power Other C15 VSS Power Other B13 TRST CMOS Input C16 TEST3 Test B14 BCLK 1 Bus Clock Input C17 LE Open Drain Output B15 BCLK 0 Bus Clock Input C18 VSS Power Other B16 VSS Power Other C19 DPWR Common Clock Input B17 PROCHOT Open Drain Output Input B18 THERMDA Power Other C20 DIS Source Synch Output B19 VSS Power Other C21 VSS Power Other Input Input B20 D 7 Source Synch Output C22 DSTBP 0 Source Synch Output Input Input B21 D 3 Source Synch Output C23 DSTBN O Z Source Synch Output B22 VSS Power Other C24 VSS Power Other Input
72. npull T22 VCCP Power Other Output T23 VSS Power Other V25 VSS Power Other Input Input T24 DINV 2 CMOS Output V26 D 44 Source Synch Output Input Input T25 D 34 Source Synch Output W1 A 8 Source Synch Output T26 VSS Power Other Input W2 A 10 Source Synch Output Input U1 ASK Source Synch Output wa vss Power Other U2 VSS Power Other WA VCCQ 1 Power Other U3 ADSTB OM Source Synch a id TE Powerother W6 VSS Power Other U4 A4 Source Synch IMPUN y Output W21 vcc Power Other U5 VCC Power Other W22 VSS Power Other U6 VSS Power Other W23 VSS Power Other ia MEME Powerother W24 DSTBP 2M Source Synch ul U22 VSS Power Other Input Input W25 DSTBN 2 Source Synch Output U23 D 35 Source Synch o utput W26 VSS Power Other U24 VSS Power Other Y1 A112 Source Synch lnput U25 DJ43 Source Synch IMPUN Output y Output Y2 VSS Power Other U26 D 41 Source Synch Input Output Y3 A 159 Source Synch InPut y Output V1 VSS Power Other Y4 ALI Source Synch lnput v2 A 7 Source Synch MPU Output y Output 54 Intel Celeron M Processor Datasheet l n Package Mechanical Specifications and Pin Information Table 24 Pin Listing by Pin Number Fin Pin Name Signal Buffer Direction Number Type Y5 VSS Power Other Y6 VCC Power Other Y21 VSS Power Other Y22 VCC Power Other Y23 D 45 Source Synch MPU Output Y24 VSS Power Other Y25 D 47 Source Synch IPUK y Output Input
73. on must be obtained from the logic analyzer vendor Due to the complexity of Intel Celeron M processor based systems the LAI is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing a Intel Celeron M processor based system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the Intel Celeron M processor The LAI pins plug into the socket while the Intel Celeron M processor pins plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the Intel Celeron M processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide Intel Celeron M Processor Datasheet 69
74. ource Synch Input Output Input M26 D 19 Source Synch Output a MOTO Input y Output N1 VCCA 2 Power Other R4 VSS Power Other N2 ADS Common Clock PUY Output R5 VCCP Power Other N3 VSS Power Other R6 VSS Power Other N4 BRO Common Clock Input R21 VCCP Power Other Output R22 VSS Power Other N5 VCCP Power Other R23 D 39 Source Synch MPU N6 VSS Power Other Output N21 VCCP Power Other R24 D 37 8 Source Synch eae N22 VSS Power Other R25 VSS Power Other N23 VSS Power Other R26 D 38 Source Synch MPU N24 D 27 Source Synch Input Output y Output Intel Celeron M Processor Datasheet 53 Package Mechanical Specifications and Pin Information Table 24 Pin Listing by Pin Number Intel Table 24 Pin Listing by Pin Number Fin Pin Name Signal Buffer Direction Pin Pin Name Signal Butter Direction Number Type Number Type T1 REQU4 Source Synch nput V3 AIS Source Synch lnput Output Output Input V4 VSS Power Other T2 REQ 2 Source Synch Output V5 VSS Power Other T3 VSS Power Other V6 VCC Power Other T4 AI Source Synch Put y Output V21 vss Power Other T5 Vss Power Other V22 VCC Power Other T6 VCCP Power Other V23 D 36 Source Synch Hn utput T21 VSS Power Other V24 D 42 l Source Synch I
75. ries resistance ESR and keep a low interconnect resistance from the regulator to the socket Bulk decoupling for the large current swings when the part is powering on or entering exiting low power states must be provided by the voltage regulator solution For more details on decoupling recommendations please refer to the platform design guides Intel strongly recommends that the layout and decoupling recommendations in the platform design guides be followed FSB AGTL Decoupling Intel Celeron M processors integrate signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package Decoupling must also be provided by the system motherboard for proper AGTL bus operation For more information refer to the platform design guides FSB Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the Intel Celeron M processor core frequency is a multiple of the BCLK 1 0 frequency In regards to processor clocking the Intel Celeron M processor uses a differential clocking implementation Voltage Identification The processor uses six voltage identification pins VID 5 0 to support automatic selection of power supply voltages The VID pins for the processor are CMOS outputs driven by the processor VID circuitry Table 2 specifies the voltage level corresponding to the state of V
76. s ssssssssssssssssseeeenee eene 11 AGTL Signal Group DC Specifications cccccccccccecceeeeeeeeeeecenaecaeeeeeeeeeeeseeeeesecsaaaeeaeeeeeees 12 CMOS Signal Group DC Specifications ssssssssssssssssesseneeee enne 13 Open Drain Signal Group DC Specifications ssssssssssssssssseen 14 Micro FCPGA Package Dimensions sssssseeeeenen eene 15 Micro FCBGA Package Dimensions sessseeeeeenen eene 23 Pin Listing by Pin Name sssseeeennenenne nennen nne nen nnne nennen CCLD nennen enn 24 Pin Listing by Pin Number ceret ede iced reden ere Le aa ag apana aini 25 Signal Description sss nennen eene nemen enn KAGAN RYFEL aana aaaea 26 Power Specifications for the Intel Celeron M Processor sssssssseeeneeeee 27 Thermal Diode Interface saene aaa eaaa aana eaaa aaa aana Kae er Iren LLY LL n nennen nennen tenens 28 Thermal Diode Specifications nennen menter nennen Inte Celeron M Processor Datasheet Revision History m Order ran Revision Number Description Date 001 300302 Initial release January 2004 Added ULV 900 MHz and 1 40 GHz specs 002 300302 Ce NO April 2004 Updated DINV 3 0 and BPM3 pin direction 003 300302 Added 1 50 GHz specifications June 2004 6 Intel Celeron M Processor Datasheet Introduction Introduction The Intel
77. s signalled to the system by the THERMTRIP Thermal Trip pin For termination requirements please refer to the platform design guides TMS Input TMS Test Mode Select is a JTAG specification support signal used by debug tools Please refer to the TP700 Debug Port Design Guide and the platform design guides for termination requirements and implementation details Intel Celeron M Processor Datasheet 61 62 Intel Table 25 Signal Description Sheet 7 of 7 Name Type Description TRDY Input TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of both FSB agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset Please refer to the TP700 Debug Port Design Guide and the platform design guides for termination requirements and implementation details Voc Input Processor core power supply Vecal3 0 Input Vcca Provides isolated power for the internal processor core PLLs Refer to the platform design guides for complete implementation details Voce Input Processor I O power supply Vccol1 0 Input Ouiet power supply for on die COMP circuitry These pins should be connected to Vccp on the motherboard However these connections should enable addition of
78. sactions FSB Low Power Enhancements The Intel Celeron M processor incorporates the following FSB low power enhancements Dynamic FSB power down M Processor Datasheet 13 Low Power Features ntel amp 2 3 BPRI control for address and control input buffers Dynamic on die termination disabling e Low VCCP I O termination voltage The Intel Celeron M processor incorporates the DPWR signal that controls the data bus input buffers on the processor The DPWR signal disables the buffers when not used and activates them only when data bus activity occurs resulting in significant power savings with no performance impact BPRI control also allows the processor address and control input buffers to be turned off when the BPRI signal is inactive The On Die termination on the processor FSB buffers is disabled when the signals are driven low resulting in additional power savings The low I O termination voltage is on a dedicated voltage plane independent of the core voltage enabling low I O switching power at all times Processor Power Status Indicator PSI Signal The Intel Celeron M processor incorporates the PSI signal that is asserted when the processor is in a low power Deep Sleep state This signal is asserted upon Deep Sleep entry and deasserted upon exit PSI can be used to improve the light load efficiency of the voltage regulator resulting in platform power savings and extended battery life Intef Celeron9
79. sent A20M IGNNE etc and can become active at any time during the clock cycle Table 3 identifies which signals are common clock source synchronous and asynchronous Intef Celeron9 M Processor Datasheet In Table 3 3 8 FSB Pin Groups Electrical Specifications Signal Group Type Signals Synchronous BPRI DEFER DPWR PREQ RESET RS 2 0 AGTL Common Clock Input to BCLK 1 0 TRDY Synchronous ADS BNR BPM 3 0 2 BRO DBSY DRDY HIT d Comman Clock IO to BCLK 1 0 HITM LOCK PRDY Signals Associated Strobe REQI4 0 4 A 16 3 ADSTB 0 Synchronous A 31 17 ADSTB 1 AGTE Source SyNEhrONOUS IO S D 15 0 DINVO DSTBPO DSTBNO D 31 16 DINV1 DSTBP1 DSTBN1 D 47 32 DINV2 DSTBP2 DSTBN2 D 63 48 DINV3 DSTBP3 DSTBN3 Synchronous R P AGTL Strobes amp BCLK ro ADSTBI1 0 DSTBPIS 0 DSTBN 3 0F CMOS Input Asynchronous A20M DPSLP IGNNE INIT LINTO INTR LINT1 p y NMI PWRGOOD SMI SLPZ STPCLK Open Drain Output Asynchronous FERR IERR PROCHOT THERMTRIP CMOS Output Asynchronous PSI VID 5 0 Synchronous CMOS Input to TCK TCK TDI TMS TRST Open Drain Output Synchronous TDO to TCK FSB Clock Clock BCLK 1 0 ITP CLK 1 0 COMP 3 0 DBR 3 GTLREF RSVD TEST3 TEST2 Power Other TEST1 THERMDA THERMDG Veo Vcca 3 0 VocP Vccol1 0 Vec_sense Vss Vss_SENSE NOTES 1
80. sign guides and TP700 Debug Port Design Guide for more detailed information BPRI Input BPRI Bus Priority Request is used to arbitrate for ownership of the FSB It must connect the appropriate pins of both FSB agents Observing BPRI active as asserted by the priority agent causes the other agent to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BRO Input Output BRO is used by the processor to request the bus The arbitration is done between the Intel Celeron M processor Symmetric Agent and MCH M High Priority Agent of the Intel 852GM Intel 855PM and Intel 855GM chipsets Intel Celeron M Processor Datasheet Table 25 Signal Description Sheet 2 of 7 Name Type Description COMP 3 0 must be terminated on the system board using precision 1 COMP 3 0 Analog tolerance resistors Refer to the platform design guides for more details on implementation D 63 0 Data are the data signals These signals provide a 64 bit data path between the FSB agents and must connect the appropriate pins on both agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are guad pumped signals and will thus be driven four times in a common clock per
81. sor DC Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes TSTORAGE Processor storage temperature 40 85 C 2 Vec KN supply voltage with 03 1 75 V 1 M ie Ua input voltage with 0 1 1 75 V 1 2 A AO OO Eu LM input voltage with 0 1 1 75 V 1 2 NOTES 1 This rating applies to any processor pin 2 Contact Intel for storage requirements in excess of one year Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless noted otherwise See Table 11 for the pin signal definitions and signal pin assignments Most of the signals on the FSB are in the AGTL signal group The DC specifications for these signals are listed in Table 11 DC specifications for the CMOS group are listed in Table 12 Table 5 through Table 13 list the DC specifications for the Intel Celeron M processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages Active Mode load line specifications apply in all states except in the Deep Sleep state Vcc goor is the default voltage driven by the voltage regulator at power up in order to set the VID values Unless specified otherwise all specifications for the Intel Celeron M processor are at Tjunction 100 C Care should be taken to read all notes associated with each parameter Intef Celeron9 M Processor Datasheet Table 5 Voltage and Current Specifications
82. state SLP assertions while the processor is not in the Stop Grant state is out of specification and may result in unapproved operation Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP DPSLP or RESET are allowed on the FSB while the processor is in Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant State If RESETH is driven active while the processor is in the Sleep State the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the Reset sequence While in the Sleep state the processor is capable of entering an even lower power state the Deep Sleep state by asserting the DPSLP pin see Section 2 1 6 While the processor is in the Sleep state the SLP pin must be deasserted if another asynchronous FSB event needs to occur Deep Sleep State Deep Sleep state is a very low power state the processor can enter wh
83. t stay active for at least two milliseconds after Vcc and BCLK have reached their proper specifications On observing active RESET both FSB agents will deassert their outputs within two clocks All processor straps must be valid within the specified setup time before RESET is deasserted Please refer to the TP700 Debug Port Design Guide and the platform design guides for termination requirements and implementation details There is a 55 ohm nominal on die pull up resistor on this signal RS 2 0 Input RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of both FSB agents RSVD Reserved No Connect These pins are RESERVED and must be left unconnected on the board However it is recommended that routing channels to these pins on the board be kept open for possible future use Please refer to the platform design guides for more details Intel Celeron M Processor Datasheet Table 25 Signal Description Sheet 6 of 7 Name Type Description SLP Input SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will r
84. t until it observes LOCK deasserted This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock Intel Celeron M Processor Datasheet 59 60 Intel Table 25 Signal Description Sheet 5 of 7 Name Type Description PRDY Output Probe Ready signal used by debug tools to determine processor debug readiness Please refer to the TP700 Debug Port Design Guide and the platform design guides for more implementation details PREQ Input Probe Request signal used by debug tools to request debug operation of the processor Please refer to the TP700 Debug Port Design Guide and the platform design guides for more implementation details PROCHOT Output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled See Chapter 5 for more details For termination requirements please refer to the platform design guides This signal may require voltage translation on the motherboard Please refer to the platform design guides for more details PSI Output Processor Power Status Indicator signal This signal is asserted when the processor is in a lower state Deep Sleep See Section 2 1 4 for more details Please refer to
85. the IMVP IV Mobile Processor and Mobile Chipset Voltage Regulation with Power Status Indicator PSI Specification for more details on the PSI signal PWRGOOD Input PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation For termination requirements please refer to the platform design guides REQJ4 0 4 Input Output REQ 4 0 Request Command must connect the appropriate pins of both FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB O Z RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET mus
86. timedia applications including 3D graphics video decoding encoding and speech recognition e 400 MHz source synchronous front side bus FSB Advanced power management features e Maintained support for MMX technology Compatible with IA 32 software The processor also features a very advanced branch prediction architecture that significantly reduces the number of mispredicted branches The processor s Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache request occurs resulting in reduced bus cycle penalties and improved performance Intel Celeron M Processor Datasheet 7 Introduction 1 1 Note Intel The new packed double precision floating point instructions enhance performance for applications that reguire greater range and precision including scientific and engineering applications and advanced 3D geometry technigues such as ray tracing The processor s 400 MHz FSB utilizes a split transaction deferred reply protocol The 400 MHz FSB uses source synchronous transfer SST of address and data to improve performance by transferring data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or 2X address bus Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3 2 GB second The FSB uses Advanced Gunning Tr
87. tput driver Measured at 0 31 x VCCP Rrr is connected to VCCP on die Refer to processor I O buffer models for IV characteristics 8 Specified with on die Rrr and Roy are turned off 9 Cpad includes die capacitance only No package parasitics are included Table 12 CMOS Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes VCCP I O Voltage 0 997 1 05 1 102 V Vit input Low Voltage 0 1 03xVCCP v 23 CMOS VIH Input High Voltage 0 7 X VCCP VCCP 0 1 V 2 VoL Output Low Voltage 0 1 0 0 1 x VCCP V 2 VoH Output High Voltage 0 9xVCCP VCCP VCCP 0 1 V 2 loL Output Low Current 1 49 4 08 mA 4 loH Output High Current 1 49 4 08 mA 5 li Leakage Current 100 pA 6 Cpad Pad Capacitance 1 0 2 3 3 0 pF 7 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The VCCP referred to in these specifications refers to instantaneous VCCP 3 Refer to the processor I O Buffer Models for IM characteristics 4 Measured at 0 1 x VCCP Intel Celeron M Processor Datasheet 27 Electrical Specifications 5 Measured at 0 9 x VCCP 6 For Vin between OV and VCCP Measured when the driver is tristated 7 Cpad includes die capacitance only No package parasitics are included Table 13 Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes VoH Output
88. wer Other AB10 VCC Power Other AA9 VCC Power Other AB11 VSS Power Other AA10 VSS Power Other AB12 VCC Power Other AA11 VCC Power Other AB13 VSS Power Other AA12 VSS Power Other AB14 VCC Power Other AA13 VCC Power Other AB15 VSS Power Other AA14 VSS Power Other AB16 VCC Power Other AA15 VCC Power Other AB17 VSS Power Other AA16 VSS Power Other AB18 VCC Power Other AA17 VCC Power Other AB19 VSS Power Other AA18 VSS Power Other AB20 VCC Power Other AA19 VCC Power Other AB21 VSS Power Other AA20 VSS Power Other AB22 VCC Power Other AA21 VCC Power Other AB23 VSS Power Other AA22 VSS Power Other AB24 D 50 Source Synch ee utput Input AA23 D 40 Source Synch Output Input AB25 D 48 Source Synch 0 utput AA24 D 33 if Source Synch nput Output AB26 VSS Power Other AA25 VSS Power Other ACI RSVD Reserved Input AC2 VSS Power Other AA26 D 46 Source Synch Output Input AC3 A 20 Source Synch Output Intel Celeron M Processor Datasheet 47 Package Mechanical Specifications and Pin Information Table 24 Pin Listing by Pin Number In Table 24 Pin Listing by Pin Number Fin Pin Name Signal Buffer Direction Pin Pin Name Signal Butter Direction Number Type Number Type Input Input AC4 A 18 Source Synch Output AD5 A 26 Source Synch Output AC5 V

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