Transcend 1024MB With 64Mx4 CL3 168PIN PC133 Registered DIMM
Contents
1. Dimensions Side Millimeters Inches 133 35 0 400 5 250 0 016 65 67 2 585 C 23 49 0 925 D 8 89 0 350 E 3 00 0 12 F 30 48 0 200 1 20 0 008 G 19 80 0 779 H 15 80 0 622 l 1 27 0 100 0 050 0 004 Symbol Function SA0 SA12 Address Input SBAO 5 1 Select Bank Address SD0 SD63 Data Input Output 5 0 5 Check bit data in data out SCLKO Clock Input SCKEO Clock Enable Input Transcend Information Inc SCS0 SCS3 Chip Select Input SRAS Row Address Strobe ISCAS Column Address Strobe 5 Write Enable SDQM0 SDQM7 Data DQ Mask REGE Register Enable 0 2 Address EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection TS128MLR72V6L 168PIN PC133 Registered DIMM 1024MB With 64Mx4 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 Vss 43 Vss 85 Vss 127 Vss 02 SDO 44 NC 86 SD32 128 SCKEO 03 SD1 45 5 52 87 SD33 129 SCS3 04 SD2 46 SDQM2 88 SD34 130 SDQMG 05 SD3 47 SDQM3 89 SD35 131 SDQM7 06 Vcc 48 NC 90 Vcc 132 SA13 07 SD4 49 Vcc 91 SD36 133 Vcc 08 SD5 50 NC 92 SD37 134 09 SD6 51 NC 93 SD38 135 NC 10 SD7 52 SCB2 94 SD39 136 5 6 11 SD8 53 SCB3 95 SD40 137 SCB7 12 Vss 54 Vss 96 Vss 138 Vss 13 SD9 55 SD16 97 SD41 139 5048 14 SD10 56 SD17 98 SD42 140 5049 15 SD11 57 SD18 99 SD2. 4 5 PCK7 PCK8 PCK9 EEPROM SCL AO 1 SDA A2 0 EA1 EA2 10 ohm Every DQ pin to SDRAM This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 168 PC133 Registered DIMM TS128MLR72V6L 1024MB With 64Mx4 CL3 STANDARD TIMING DIAGRAM WITH PLL amp REGISTER 1 Register Input ii OLEI LK Roache Remi Frechen Row ACME Precharge Command command Command command Gh Deby Ta 2236 Notar 1 Ir care of mode th lig command geks delayed TC LEN ipittiningatthe addess aid ofthe bile lgi reg eter 16255 Tie rere or Me ction shot id be ICL Eearlkraz compared ip DIM 2 Dm E tobe chock rw tg commaid here nal tmligbeca ze Ds E Ezted p modit Transcend Information Inc 5 TS128MLR72V6L ABSOLUTE MAXIMUM RATINGS 168PIN PC133 Registered DIMM 1024MB With 64Mx4 CL3 Parameter Sy
3. Parameter Symbol Min Max Unit Input capacitance 5 5 12 SBAo SBA1 CIN1 15 pF Input capacitance SRAS SCAS SWE CIN2 15 pF Input capacitance SCKEO CIN3 15 pF Input capacitance SCLKO CIN4 20 pF Input capacitance SCS0 SCS3 CIN5 15 pF Input capacitance SDQMO SDQM7 CIN6 15 pF Data input output capacitance SD0 SD63 Cour 22 pF Data input output capacitance SCBO SCB7 Cour1 22 pF Transcend Information Inc 168PIN PC133 Registered DIMM TS128MLR72V6L 1024MB With 64Mx4 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition CAS Latency Value Unit Note Operating Current Burst Length 1 2 660 mA 1 One Bank Active tRC2tRC min loL 0mA Precharge Standby Icc2P CKExsViL max tcc 10ns 422 mA 3 Current Icc2PS CKE amp CLK lt ViL max tcc lt 74 power down mode Precharge Standby Icc2N gt CS ViH min tcc 10ns 1070 mA Current Input signals are changed one time during 20ns 3 non power down mode 2 6 gt CLKxViL max 362 Input signals are stable Active Standby Current Icc3P CKEsViL max tcc 10ns 566 mA 3 in power down mode IccaPS amp CLKxViL max tcc 218 Active Standby Current cc3N CKE SViH min CS ViH min tcc 10ns 1 430 mA in
4. 0 12 0 1 JRAS DOUBLE ICAS 64 4 WE CKE 0 12 0 1 DQ0 DQ7 DOUBLE 64Mx4 090 007 A0 A12 BA0 BA1 E RAS 5 DOUBLE 64Mx4 5 090 007 A0 A12 BA0 BA1 DOUBLE 64Mx4 SDRAM DQ0 DQ7 0 12 0 1 IRAS DOUBLE ICAS 64Mx4 000 007 0 12 0 1 RAS DOUB LE ICAS 64Mx SDRAM g 000 007 0 12 0 1 RAS DOUBLE DQ0 DQ7 A0 A12 BA0 BA1 IRAS DOUBI ICAS 64Mx4 SDRAI 090 007 A0 A12 BA0 BA1 DOUBLE 1 a ICS0 u ICS0 ICS2 ICS2 ICSO a PCKO PCK2 PCK6 PCK8 PCK1 SCBO SCB7 T DQ0 DQ7 E DQ0 DQ7 DQ0 DQ7 E DQ0 DQ7 E DQ0 DQ7 DQ0 DQ7 T A0 A12 BA0 BA1 0 12 0 1 E 0 12 0 1 0 12 0 1 E 0 12 0 1 E 0 12 0 1 IRAS DOUBLE RAS DOUBLE RAS DOUBLE 5 DOUBLE RAS DOUBLE RAS DOUBLE 64Mx4 64Mx4 64Mx4 64Mx4 64Mx4 64Mx4 SDRAM ICES SDRAM ICAS SDRAM ICAS SDRAM IGAS SDRAM ICAS SDRAM gt gt 9 9 9 0 8 g 3 8 8 9 ce 8 28 2 EN m EI Em DQM1 CS2 CS2 CS1 ICS1 CS3 CSO 5 PCK7 PCKO PCK2 PCK6 PCK4 SCBO0 SCB7 DQ0 DQ7 0 12 0 1 RAS DOUBLE 64Mx4 ICAS SDRAM SCLKO PLL PCKO PCK1 PCK2
5. non power down mode Input signals are changed one time during 20ns One Bank Active IccaNS gt CLKxViL max tcc 902 3 Input signals are stable Operating Current 4 loL 0 mA mA 1 Bust Mode Page Burst 3 020 tccp 2CLKs Refresh Current 5 tRC2tRC min 4 640 mA 2 Self Refresh Current 6 lt 0 2 458 3 Note 1 Measured with outputs open 2 Refresh period is 64ms 3 Measured with 1 PLL amp 3 Drive ICs 4 Unless otherwise noticed input swing level is CMOS VIHAVIL VDDQ VssqQ Transcend Information Inc 7 TS128MLR72V6L 168PIN PC133 Registered DIMM 1024MB With 64Mx4 CL3 AC OPERATING TEST CONDITIONS voo 3 3V 0 3V 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 O 1200 Ohm gt Von DC 2 4V 2 Vo DC 0 4V lo 2mA 5OpF 870 Ohm M Fig 1 DC Output Load Circuit 50 Ohm B5OpF Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note RAS to CAS delay tRCD min 15 ns 1 Row precharge time tRP min 20 ns 1 Row active time ns tRAS max 100 us Row cy
6. 168 PC133 Registered DIMM TS1 28 LR72V6L 1024MB With 64Mx4 CL3 Description Placement TS128MLR72V6L is a 128M x 72 bits Synchronous Dynamic RAM high density memory registered DIMM module TS128MLR72V6EL consists of 36pcs of CMOS 64Mx4bits Synchronous DRAMs TSOP II 400mil packages 3pcs of drive ICs 1pc of PLL and one 2048 bits serial EEPROM on 168 pin printed circuit board The TS128MLR72V6L is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 133 e Burst Mode Operation e Auto and Self Refresh e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply Roe e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock Transcend Information Inc 1 TS128MLR72V6L 168PIN PC133 Registered DIMM 1024MB With 64Mx4 CL3 Pin Identification
7. 43 141 SD50 16 SD12 58 SD19 100 58044 142 SD51 17 SD13 59 Vcc 101 SD45 143 Vcc 18 Vcc 60 SD20 102 Vcc 144 5052 19 014 61 103 046 145 NC 20 015 62 104 SD47 146 NC 21 5 0 63 SCKE1 105 SCB4 147 REGE 22 SCB1 64 Vss 106 5 5 148 Vss 23 Vss 65 021 107 Vss 149 5053 24 66 022 108 150 5054 25 67 023 109 151 055 26 Vcc 68 Vss 110 Vcc 152 Vss 27 ISWE 69 SD24 111 SCAS 153 056 28 SDQM0 70 SD25 112 SDQM4 154 5 57 29 SDOM1 71 SD26 113 SDQM5 155 SD58 30 SCSO 72 SD27 114 SCS1 156 SD59 31 NC 73 Vcc 115 SRAS 157 Vcc 32 Vss 74 SD28 116 Vss 158 SD60 33 SAO 75 029 117 SA1 159 58061 34 SA2 76 SD30 118 SA3 160 5062 35 SA4 77 SD31 119 SA5 161 5063 36 SA6 78 Vss 120 SA7 162 Vss 37 SA8 79 NC 121 SA9 163 NC 38 SA10 80 NC 122 SBAO 164 NC 39 SBA1 81 NC 123 SA11 165 0 40 Vcc 82 SDA 124 Vcc 166 1 41 Vcc 83 SCL 125 NC 167 EA2 42 SCLKO 84 Vcc 126 SA12 168 Vcc Please refer Block Diagram Transcend Information Inc TS128MLR72V6L 168PIN PC133 Registered DIMM 1024MB With 64Mx4 CL3 Block Diagram 500 5063 SA0 SA12 SBA0 SBA1 12 0 2 ISCAS IRCAS 64 4 Hive go SCKEO RCKEO 9 x SDQM0 SDQM7 SCS0 SCS3 REGE RDQMO 7 o 50 3 Ya 151 PCK9 DQ0 DQ7 E 0 12 0 1 JRAS DOUBLE 64Mx4 IAS SDRAM CKE g 090 007
8. Time 2 highest CL 10ns AO 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL Ons 00 26 SDRAM Access from Clock 31 highest CL Ons 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 512MB 80 32 Command Address Setup Time 1 5ns 15 Transcend Information Inc 11 TS128MLR72V6L 168PIN PC133 Registered DIMM 1024MB With 64Mx4 CL3 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC 2 02 63 Checksum for Bytes 0 62 22 64 71 Manufacturers ID code per JEP 108E Transcend 72 Manufacturing Location T 54 54 53 31 32 38 40 73 90 Manufacturers Part Number TS128MLR72V6L 4 52 37 32 56 36 4 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 3 Clock 0 84 128 Unused Storage Locations Open FF Transcend Information Inc 12
9. X L H Note Transcend Information Inc 1 V Valid X Don t Care H Logic High L Logic Low OP Code Operand Code SAo SA12 SBAo SBAt1 Program keys MRS MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state SBAo SBAt Bank select address If both SBAo and SBA are Low at read write row active and precharge bank is selected If both SBAo is Low and SBAt is High at read write row active and precharge bank B is selected If both SBAo is High and SBA1 is Low at read write row active and precharge bank C is selected If both SBAo and SBAt are High at read write row active and precharge bank D is selected If SA10 AP is High at row precharge SBAo and SBAt is ignored and both banks are selected During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length SDQM sampled at positive going edged of a CLK masks the data in at the very CLK Write SDQM latency is 0 but makes Hi
10. Z state the data out of 2 CLK cycles after Read SDQM latency is 2 10 TS128MLR72V6L Serial Presence Detect Specification 168PIN PC133 Registered DIMM 1024MB With 64Mx4 CL3 Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 13 00 4 of Column Addresses on this Assembly 11 0B 9 of Module Banks on this Assembly 2 bank 02 6 Data Width of this Assembly 7255 48 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC ECC 02 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X4 04 14 Error Checking SDRAM Width X4 04 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 3 04 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Registered DQM address control inputs 16 and on card PLL 22 SDRAM Device Attributes General Prec All Auto Prec R W OE Burst 23 SDRAM Cycle
11. cle time 65 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to Active delay tDAL 2CLK 20ns Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccb min 1 CLK 3 Names ot valid CAS latency 3 2 ea 4 output data Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend Information Inc 168 PC133 Registered DIMM TS128MLR72V6L 1024MB With 64Mx4 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Unit Note Min Max CLK cycle time CAS latency 3 Ten 75 1909 ns CLK to valid CAS latency 3 tSAC 5 4 ns 1 2 output delay Output data tOH ns 1 2 hold time CAS latency 3 3 CLK high pulse width tCH 2 5 ns 3 CLK low pulse width tCL 2 5 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output CAS latency 3 tSHZ 5 4 ns 1 in Hi Z Note 1 Parameters depend on programmed CAS latency 2 If clock rising ti
12. mbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation 18 Short circuit current los 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V 2 Output low voltage VOL 0 4 V IOL 2mA Input leakage current 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs CAPACITANCE Voo 3 3V 23 C f 1MHz
13. me is longer than ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend Information Inc 9 TS128MLR72V6L SIMPLIFIED TRUTH TABLE 168PIN PC133 Registered DIMM 1024MB With 64Mx4 CL3 COMMAND SCKEn 1 SCKEn SCS SRAS SCAS SWE SDQM 5 1 SA10 AP SA12 SA11 SA0 SAg Note Register Mode Register Set H x L L L L X OP CODE 12 Auto Refresh H H L L L H 3 L 3 Refresh Self L H H H 3 Refresh i Exit L H H X X X X X 3 Bank Active amp Row Addr H X L L H H X V Row Address Auto Precharge Disable L Column 4 Read amp 9 H x L H L H Xx v Address Column Address Auto Precharge Enable H SAo SAs SA11 4 5 i Auto Precharge Disable L Column 4 Write amp 9 H X L H L L X V Address Column Address Auto Precharge Enable H SAo SAs SA11 4 5 Burst Stop x L H H L X X 6 Bank Selection V L Precharge All Banks X L L H L X X H X H X X X Clock Suspend or Entry H x X Active Power Down L V V V Exit L H X X X X X H X X X Entry H L Precharge Power L H X Down Mode Exit H X X X L H X L V V V SDQM H X V X 7 H x No Operation Command H X X
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