Kingston Technology ValueRAM 1GB 533MHz DDR2 ECC Fully Buffered CL4 DIMM Dual Rank, x8
Contents
1. O 7 SAO A I RAS all SDRAMs TELA L CAS all SDRAMs SCK SCK I CK CK all SDRAMs AMB All address command control clock J VTT SPD AMB Notes 1 DQ to I O wiring may be changed within a byte 2 There are two physical copies of each address command control clock VALUERAM0480 001 A00 Serial PD WP AO A1 A2 SDA DO D17 AMB DO D17 DO D17 SPD AMB Page 4 E kingston Architecture Advanced Memory Buffer Pin Description FB DIMMChannelSignals o g9 DDR2 Interface Signals passu pesswbespste me B Sase Date Saves regains B baspireyoMes pau seches 4 DRAM onb postive lines These signals are driven low 19 x8 DRAM on wes o __ Barre pae Svobes a oram ony negates gt gt fP ew mam fe Ceao sazo Banca cresses Sid Op KETO Clock Enable ne prank O SSit o1 C810 CLK 1 0 used on 9 and 18 device DIMMs CLK 3 0 used on 36 device DIMMs CLK 3 2 should be out CLK 5 0 put disabled when not in use CLK 3 0 DDRC_C14 DDRC_B18 DDRC_C18 VALUERAM0480 001 A00 Page 5 E Kingston Advanced Memory Buffer Pin Description SPD Bus Interface Signals SCL Serial Presence Detect SPD Clock Input SDA SPD Data Input Output SA 2 0 SPD Address Inputs also used to select the DIMM number in the AMB Miscellaneous Signals PLLTSTO VCCAPLL Analog VCC for the PLL Tied with low pass filter to VCC 1 VSSAPLL Analog VSS for2. System Clock Signals SCK and SCK switch at one half the DRAM CK CK frequency 2 Eight pins reserved for forwarded clocks eight pins reserved for future architecture flexibility VALUERAM0480 001 A00 Page 3 Functional Block Diagram E Kingston S1 SO DQSO DQS4 DQSO DQS4 DQS9 DQS13 Rbas NUL CS DAS DAS Ras spas CS DAS Das RDas NUL CS DAS DAS Rbas Reys CS DAS DAS DQ0 1 0 0 I O 0 DQ32 O 0 H lOO Don O1 DO VO1 D9 DQ33 VO1 D4 O1 p13 DQ2 I O 2 I O 2 DQ34 I O 2 H 02 DQ3 1 03 I O 3 DQ35 10 3 H 03 DQ4 10 4 I O 4 DQ36 0 4 I O 4 DQS I O 5 I O 5 DQ37 0 5 H 1 05 DQ6 1 0 6 I O 6 DQ38 10 6 I O 6 DQ VO7 VO7 DQ39 07 O7 DQS1 DQS5 DQS10 DQS14 RO S NUL cs DAS DAS RBas Abas CS DAS DAS Roos NUL CS DAS DAS RBas Spas CS DAS DAS DQ8 I O 0 I O 0 DQ40 1 00 I O 0 DOS 1 01 D1 I O 1 D10 DQ41 I O 1 D5 I O 1 D14 DQ10 I O 2 I O 2 DQ42 IIO 2 O 2 DQ11 I O 3 I O 3 DO43 1 1 03 0 3 DQ12 I O 4 I O 4 DO44 1 0 4 IIO 4 DQ13 05 05 DQ45 JO 5 JO 5 DQ
3. gt N N N IN 3 e _ e C1 FU 225 RFU ii s N N Oo e J N N N si O Cc e O o SS2 O N N N 29 e N Se Y N N oO N e O C2 eo A C NIN amp a A N O These pin positions are reserved for future architecture flexibility 1 The following signals are CRC bits and thus appear out of the normal sequence PN12 PN12 SN12 SN12 PN13 PN13 SN13 SN13 PS9 PS9 SS9 SS9 VALUERAM0480 001 A00 Page 2 K Kingston DIMM Connector Pin Description PinName PinDescription System Clock Input positive line entiso Secondary Nontisouna Data postvetnes M C trsa Secondary Norhbound Data negatve nes h spo Secondary Southbound Dara postive es SSS so sss 0 cus gt f Ue Voltage ID These pins must be unconnected for DDR2 based Fully Buffered DIMMs VID 0 is Vpp value OPEN 1 8 V GND 1 5 V VID 1 is V cc value OPEN 1 5 V GND 12V RESET The DNU M Test pin provides an external connection on R Cs A D for testing the margin of Vref which is produced by a voltage divider on the module It is not intended to be used in normal system operation and must not be VID 1 0 DNU M Test connected DNU in a system This test pin may have other features on future card designs and if it does will be included in this specification at that time N N d 1
4. 1 po 1 06 49 i p n lt 0 042 1 06 0 054 1 37 Detail A 0 046 1 17 VALUERAM0480 001 A00 Page 7
5. Pns per m IM or s TE 8 Ves 128 vss f Pns js 2 Ves jie vec fel vss 0 Ves 180 Vec f4 Pms eo 11 Ve 9 ys e Pns 2 Vec 132 Yee a2 Ves fpe 9 Yee t99 Veo se e ve E Ves 194 Ves e nr pe mr s Ym ms Ym es m es m aj w SST e vor 186 voo fsf Vss 166 vss 75 we 17 RESET 137 onum estf 47 Vss 167 ves ve Ps2 196 ODES OK pia 168 sm Jar Pe 197 19 meu 189 Reue e PN 160 sn e Vss 196 2 reu 140 meo so Vss 170 Vss ro res no ve rr ve si Pwe i sno eo Ps 20 sss 22 pno 142 sno sj Pm 172 SNe DN RN n 2 mel wo S9 Ves 178 vss fef Pse zo 24 Ves 144 Vos spew rd M s Ps s e m x we C ae ss mr jus svo e we jm ve we 26 PNt e 5 DETON CRA E DE 3 27 Vss wr Vss CIK ALONE NN 86 mr me mer we e w Ge mere s Pre vs rm far cr ea ser n os PNZ ue 582 fe ves mo vs Ye ves 208 Vss Qol soa 230 so 20 Ves wo ves eo pro wo sw Nee ves 26 ves wo scr Taro se Li dL i ELI di ivwi re fre s f d RFU Reserved Future Use These pin positions are reserved for forwarded clocks to be used in future module implementations UU z z i Z SN5 Vss 8 Vss lt N O e e PS7 220 SS7 c eo BES e gt I oo ud NIN N uum O C1 O 9 O N X e wo PS8 223 SS8 oO A O O O
6. the PLL Tied to ground on the AMB die Do not tie to ground on the DIMM 1 TEST pin Leave floating on the DIMM TESTLO pin Tie to ground on the DIMM BFUNC Tie to ground to set functionality as buffer on DIMM RESET AMB reset signal No connect Many NC are connected to VDD on the DIMM to lower the impedance of the VDD power islands R Reserved for Future Use Power Ground Signals D O 3 163 1 5 1 1 1 NC FU 7 1 System Clock Signals SCK and SCK switch at one half the DRAM CK CK frequency 2 TESTLO_AB20 and TESTLO AC20 should be configured for debug purposes on prototype DIMMs each pin should have a zero ohm resistor pulldown to ground and an unpopulated resistor pullup to VCC These resistors can be replaced on production DIMMs with a direct connection to ground N S N Jal g oO VALUERAM0480 001 A00 Page 6 ie kingston Package Dimensions mun N Units 7 millimeters 133 35 R 0 75 VA 8 PLACES us oo C O O C LC lt t lt t N O 4 Es co co 1 19 DIA o i a 0 10 a lt nat A 129 97 23 15 Neg a mc MIN q 4 PLACES oa gt 30 235 4 l 778 0 120 0 a 2 PLACES ce DETAIL A Z lt 30 1 50 DIA R 0 75 OO QN rd ei 10 oun 2 PLACES R 2 PLACES ooo CJ CJ co 0 346 8 8 MAX with heat sink O Units inches millimeters 45 x 0 0071 0 18 N 0 047
7. 14 I O 6 DQ46 1 0 6 I O 6 DQ15 VO 7 DQ47 I O 7 I O 7 DQS2 DQS6 DQS2 DQS6 DQS11 DQS15 m NUI cs Das DOS Ras NL CS DOS Das Rias NUL cs Das Das Ros NUL cs DOS DOS DQ16 I O 0 H VO 0 DQ48 1 00 l O 0 DQ17 I O 1 D2 I O 1 D11 DQ49 1 01 D6 I O 1 D15 DQ18 I O 2 Mm VO 2 DQ50 I O 2 I O 2 DQ19 I O 3 I O 3 DQ51 1 0 3 I O 3 DQ20 I O 4 H VO 4 DQ52 I O 4 I O 4 DQ21 1 I O 5 m Vos DQ53 l O 5 O5 DQ22 I O 6 I O 6 DQ54 1 0 6 I O 6 DQ23 I O 7 VO 7 DQ55 O 7 I O 7 DQS3 m DQS7 DQS3 DQS7 ids 33815 1 1 NU Ts DOS DOS Ros NL CS DAS DAS Rugs NUL cs Das Das Ras mas CS DAS DAS DQ24 l O 0 DQ56 1 0 0 H 1 00 DQ25 I O 1 D12 DQ57 I O 1 D7 I O 1 D16 DQ26 I O 2 DQ58 1 02 I O 2 DQ27 0 3 DQ59 1 03 H 1 03 DQ28 I O 4 DQ60 1 04 I O 4 DQ29 I O 5 DQ61 1 05 H 1 05 DQ30 I O 6 DQ62 1 06 I O 6 DQ31 07 DQ63 1 07 I O 7 DQS8 DQS8 DQS17 PNO PN13 SNO SN13 PNO PN13 SNO SN13 Rivas NUL cs Das DAS RBas aps CS DAS DAS PSO PS9 SS0 SS9 CB0 _ 10O 0 I O 0 PS0 PS9 260399 CB1 I O 1 D8 O1 D17 DQ0 DQ63 A S0 CS D0 D8 CB2 I O 2 I O 2 CBO CB7 _ CKEO gt CKE D0 D8 CB3 I O 3 I O 3 Doso Dast M 81 gt CS D9 D17 CB4 I O 4 I O 4 DQso Dass B CKE1 gt CKE D9 D17 CB5 I O 5 I O 5 SCL 4 r ODT gt gt ODT all SDRAMs CB6 LO 6 LO 6 SDA w gt L BAO0 BA2 all SDRAMs CB7 SA1 SA2 A0 A15 all SDRAMs O 7
8. Ki Ingsto OT Memory Module Specifications Value ee CEEEEEEEEDEECEELELELELELETECECEELLI D KVR533D2D8F4 1G 1GB 128M x 72 Bit PC2 4200 CL4 ECC 240 Pin FBDIMM Description This document describes ValueRAM s 1GB 128M x 72 bit PC2 4200 CL4 SDRAM Synchronous DRAM fully buffered ECC dual rank memory module This module is based on eighteen 64M x 8 bit 533MHz DDR2 FBGA components The module also includes an AMB device Advanced Memory Buffer The electrical and mechanical specifications are as follows Feature e FBDIMM Module 240 pin e JEDEC Standard R C B e Memory Organization 2 rank of x8 devices e DDR2 DRAM Interface SSTL 18 o DDR2 Speed Grade 533 Mbps e CAS Latency 4 4 4 Module Bandwidth 4 2 GB s e FBDIMM Channel Peak Throughput 6 4 GB s e DRAM VDD VDDQ 1 8V e AMB VCC VCCFBD 1 5V e EEPROM VDDSPD 3 3V typical e Heat Spreader AMB only heat sink PCB Height 30 35mm double side e RoHS Compliant VALUERAM0480 001 A00 03 01 06 Page 1 R Kingst Ston DDR2 240 pin FBDIMM Pinout GEHE GEGEN GERE ee Side Side Side Side Side Side Side Side Am ives Tep en C em CINA BLU HEURE 32 PNS 152 SNS fef Vss 182 Ves dam a 3 Y 123 Y 35 Vss 158 vs fef ento 183 sw ffos rss 213 sso Ves jji vs se rw 154 sma fej Pwo 184 smo os Pss 214 S55 5 Y t5 Y f Pa 155 Sw e we 188 Vos s ve lae s 6 Vm 126 Yoo e en e Je pun e swa pse ere ss T Y 127 Yoo
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