Transcend 512MB DDR DDR400 ECC Registered Memory
Contents
1. Serial Presence Detect Byte No Function Described Standard Vendor Part Specification 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type DDR SDRAM 07 3 of Row Addresses on this Assembly 13 00 4 of Column Addresses on this Assembly 10 5 of Module Rows on this Assembly 2 bank 02 6 Data Width of this Assembly 7255 48 7 Data Width of this Assembly 0 00 8 VDDQ and Interface Standard of this Assembly SSTL 2 5V 04 9 DDR SDRAM Cycle Time at CAS Latency 2 5 6 0ns 50 10 DDR SDRAM Access Time from Clock at CL 2 5 t0 7ns 65 11 DIMM configuration type non parity Parity ECC ECC 02 12 jRefresh Rate Type 7 8us Self Refresh 82 13 jPrimary DDR SDRAM Width X8 08 14 Error Checking DDR SDRAM Width X8 08 15 Min Clock Delay for Back to B Back Random Column Address 9 16 Burst Lengths Supported 2 4 8 OE 17 ___ of banks on each DDR SDRAM device 4 bank 04 18 5 Latency supported 2 2 5 3 1C 19 CS Latency 0 CLK 01 20 Latency 1 CLK 02 Registered address 21 DDR SDRAM Module Attributes amp control inputs and 26 on card DLL 22 DDR SDRAM Device Attributes General Bien COGIR CO tolerance 23 DDR SDRAM Cycle Time CL 2 0 6ns 60 24 DDR SDRAM Access from Clock CL 2 0 0 7ns 70 25 DDR SDRAM Cycle Time CL 1 5 7 5ns 75 26 DDR SDRAM Access from Clock CL 1 5 0 75ns 75 27 Minimum Row Precharge Time tRP 15ns 3C 28 Minimum Row Acti2. ICS KE DM4 DM5 DM6 DM7 DQS4 DQS5 DQS6 5087 PCK10 PCK10 PCK1 PCK1 Pots PO o PCK4 PCK4 CKO CKO PLL PCK5 PCK5 PCK6 PCK6 A1 50 s si PCK9 PCK9 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 184 PIN DDR400 Registered DIMM TS64MDR72V4F3 512MB With 32Mx8 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 0 5 3 6 Voltage on VDD supply to Vss VDD VDDQ 1 0 3 6 V Storage temperature TSTG 55 150 Power dissipation PD 27 W Short circuit current IOS 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA
3. 184 PIN DDR400 Registered DIMM TS64MDR72V4F3 512MB With 32Mx8 CL3 SIMPLIFIED TRUTH TABLE V Valid Care H Logic High L Logic Low COMMAND CKEn 1 CKEn RAS CAS BAo 1 A10 AP Ao Ag A11 A12 Note Extended Register x H X L L L L OP CODE 1 2 Mode Register Set Register Mode Register Set H X L L L L OP CODE 1 2 Auto Refresh H 3 mo Reres H L L LH x Entry L 3 Refresh Self L H H H 3 Refresh Exit L H X X X 3 Bank Active amp Row Addr H X L L H H V Row Address Read amp Auto Precharge Disable L Column 4 H X L H L H V Address Column Address Auto Precharge Enable H 4 Write amp Auto Precharge Disable L Column 4 H X L H L L V Address Column Address Auto Precharge Enable H uus 4 6 07 A9 Burst Stop H X L H H L X 7 Bank Selection V L Precharge H X HL Banks X H 5 H X X X Entry H L Active Power Down L V V V X Exit L H X X X X H X X X Ent ntry H L Precharge Power L H H H Down Mode Eit H X X X L H L V V V DM H X X 8 No O tion C d H X X X 9 Operation Comman H X X L H H H 9 Note OP Code Operand Code A0 A12 amp Program keys EMRS MRS EMRS MRS can be issued only at all banks precharge state new command can be issued 2 clock cycles after EMRS or MRS Auto re
4. DM8 03 VSS 49 CB2 95 DQ5 141 A10 04 DQ1 50 VSS 96 VDDQ 142 CB6 05 DQSO 51 CB3 97 DMO 143 VDDQ 06 DQ2 52 BA1 98 DQ6 144 CB7 07 VDD 53 DQ32 99 DQ7 145 VSS 08 DQ3 54 VDDQ 100 VSS 146 DQ36 09 NC 55 DQ33 101 NC 147 DQ37 10 RESET 56 DQS4 102 NC 148 VDD 11 VSS 57 DQ34 103 149 DM4 12 008 58 VSS 104 VDDQ 150 0038 13 DQ9 59 BAO 105 0012 151 0039 14 DQS1 60 DQ35 106 0013 152 VSS 15 VDDQ 61 0040 107 DM1 153 0044 16 CK1 62 VDDQ 108 VDD 154 RAS 17 ICK1 63 ANE 109 0014 155 0045 18 VSS 64 DQ41 110 0015 156 VDDQ 19 0010 65 ICAS 111 CKE1 157 80 20 DQ11 66 VSS 112 VDDQ 158 CS1 21 CKEO 67 DQS5 113 NC 159 DM5 22 VDDQ 68 0042 114 0020 160 VSS 23 0016 69 0043 115 A12 161 0046 24 0017 70 VDD 116 VSS 162 DQ47 25 DQS2 71 NC 117 0021 163 NC 26 VSS 72 0048 118 A11 164 VDDQ 27 A9 73 0049 119 DM2 165 0052 28 0018 74 VSS 120 VDD 166 0053 29 AT 75 121 DQ22 167 NC 30 VDDQ 76 CK2 122 A8 168 VDD 31 DQ19 77 VDDQ 123 0023 169 DM6 32 A5 78 DQS6 124 VSS 170 0054 33 00924 79 0050 125 171 0055 34 VSS 80 DQ51 126 0028 172 VDDQ 35 0025 81 VSS 127 0029 173 NC 36 DQS3 82 NC 128 VDDQ 1 4 DQ60 37 A4 83 DQ56 129 DM3 175 0061 38 VDD 84 DQ57 130 A3 176 VSS 39 DQ26 85 VDD 131 DQ30 177 DM7 40 DQ27 86 DQS7 132 VSS 178 DQ62 41 A2 87 DQ58 133 0031 179 DQ63 42 VSS 88 DQ59 134 CB4 180 VDDQ 43 A1 89 VSS 135 CB5 181 SAO 44 CBO 90 NC 136 VDDQ 182 SA1 45 CB1 91 SDA 137 183 SA2 46 VDD 92 SCL 138 CKO 184 VDDSPD Please r
5. 0 to 70 C Parameter Symbol Min Max Unit Note Supply voltage VDD 2 5 2 7 V Supply voltage VDDQ 2 5 2 7 V Reference voltage VREF VDDQ 2 50mV VDDQ 2 50mV V 1 Termination voltage VTT VREF 0 04 VREF 0 04 V 2 Input logic high voltage VIH DC VREF 0 15 VDDQ 0 3 V 4 Input logic low voltage VIL DC 0 3 VREF 0 15 V 4 Input Voltage Level CK and CK inputs VIN DC 0 3 VDDQ 0 3 V Input Differential Voltage CK and CK inputs VID DC 0 3 VDDQ 0 6 V 3 Input crossing point voltage CK and CK inputs VIX DC 1 15 1 35 V 5 Input leakage current 2 2 uA Output leakage current loz 5 5 uA Output High Current Normal strength driver VOUT VTT 0 84V id n ih Output Low Current Normal strength driver VOUT 0 84V we d m Output High Current Half strength driver VOUT VTT 0 45V ii mA Output High Current Half strength driver 9 ye VOUT VTT 0 45V Note 1 Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and mus
6. Output O ZO 50ohm gt 31 VREF LL 205 VDDQ CLoap 30pF Output Load circuit Input Output CAPACITANCE vpn 2 5V 2 5V TA 25 C f 1MHz Input capacitance A0 A12 BAO BA1 RAS WE Input capacitance CKEO CKE1 Input capacitance 50 CS1 Input capacitance CLKO CLKO Input capacitance DMO DM8 Data and DQS input output capacitance 000 0063 Data input output capacitance CBO CB7 Transcend Information Inc 7 TS64MDR72V4F3 AC Timing Parameters amp Specifications These AC characteristics were tested on the Component 184 PIN DDR400 Registered DIMM 512MB With 32Mx8 CL3 Parameter Symbol Min Max Unit Note Row cycle time tRC 55 ns Refresh row cycle time tRFC 70 ns Row active time tRAS 40 70K ns RAS to CAS delay tRCD 15 ns Row active to Row active delay tRP 15 ns Row active to Row active delay tRRD 10 ns Write recovery time tWR 15 ns Last data in to Read command tWTR 2 tCK Col Address to Col Address delay tCCD 1 tCK Clock cycle time tCK 5 10 ns Clock high level width tCH 0 45 0 55 tCK Clock low level width tCL 0 45 0 55 tCK DQS out access time from CK CK tDQSCK 0 55 0 55 ns Output data access time from CK CK tAC 0 65 0 65 ns Data strobe edge to output data edge tDQSQ 0 40 ns Read Preamble tRPRE 0 9 1 1 tCK Read P
7. TS64MDR72V4F3 184 PIN DDR400 Registered DIMM 512MB With 32Mx8 CL3 Description The TS64MDR72V4F3 is a 64Mx72bits Double Data Rate SDRAM DDR400 The TS64MDR72V4F3 consists of 18pcs CMOS 32MXx8 bits Double Data Rate SDRAMs in 66 TSOP II 400mil packages 2pcs drive ICs for input control signal 1pcs PLL and a 2048 bits serial EEPROM on a 184 pin printed circuit board The TS64MDR72V4F3 is a Dual In Line Memory Module and is intended for mounting into high density for 184 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features Power supply VDD 2 6V 0 1V VDDQ 2 6V 0 1V e clock Freq 400MHZ e Double data rate architecture two data transfers per clock cycle e Differential clock inputs CK and CK e Burst Mode Operation Auto and Self Refresh Data I O transactions on both edge of data strobe e Edge aligned data output center aligned data Input e Serial Presence Detect SPD with serial EEPROM SSTL_2 compatible inputs and outputs e MRS cycle with address key programs CAS Latency Access from column address 3 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Transcend Informatio
8. e obtained with the output open Transcend Information Inc 6 184 PIN DDR400 Registered DIMM TS64MDR72V4F3 512MB With 32Mx8 CL3 AC OPERATING CONDITIONS Parameter Symbol Min Max Unit Note Input High Logic 1 Voltage DQ DQS and DM signals VIH AC VREF 0 31 3 Input Low Logic 0 Voltage DQ DQS and DM signals VIL AC VREF 0 31 V 3 Input Differential Voltage CK and CK inputs VID AC 0 7 VDDQ 0 6 V 1 Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 0 2 0 5 VDDQ 0 2 V 2 Note 1 VID is the magnitude of the difference between the input level CK and the input on CK 2 The value of VIX is expected to equal 0 5 V of the transmitting device and must track variations in the DC level of the same 3 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation the AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz AC OPERATING TEST CONDITIONS VDD 2 5 VDDQ 2 5 0 to 70 C Parameter Value Unit Note Input reference voltage for Clock 0 5 VDDQ V Input signal maximum peak swing 1 5 V Input Levels VIH VIL VREF 0 31 VREF 0 31 V Input timing measurement reference level VREF V Output timing measurement reference level VTT V Output load condition See Load Circuit VTT 0 5 VDDQ L
9. e power down standby current one bank active power down mode CKE VIL min IDD3P 720 mA VIN VREF for DQ DQS and DM Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax tCK tCK min DQ DQS and DM inputs changing twice per clock cycle address and other control inputs changing once per clock cycle IDD1 1566 mA IDD2F 1080 mA IDD3N 1260 mA Operating current burst read Burst length 2 reads continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at IDD4R 1836 mA min 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at min DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst IDD4W 1701 mA Auto refresh current tRC tRFC min IDD5 4680 mA Self refresh current CKE lt 0 2V IDD6 72 mA Operating current Four bank operation Four bank interleaving with BL 4 IDD7 4266 mA Refer to the following page for detailed test condition Note 1 These parameters depend on the cycle rate and these values are measured a cycle rate with the minimum values of tCK and Trc 2 These parameters depend on the output loading Specified values ar
10. efer Block Diagram Transcend Information Inc TS64MDR72V4F3 184 PIN DDR400 Registered DIMM 512MB With 32Mx8 CL3 Block Diagram DQ0 DQ63 A0 A12 BA0 BA1 IRAS ICAS INE CSO CKEO CS1 CKE1 PCK10 PCK10 HdlSlodH DQ0 DQ7 DQ0 DQ7 0 12 32 8 DDR PCK1 PCK1 PCK2 PCK2 PCK6 PCK6 PCK7 PCK7 DQ0 DQ7 0 12 BAO BA1 IRAS ICAS DQ0 DQ7 _ A0 A12 32Mx8 DDR 32Mx8 DDR SDRAM DQ0 DQ7 PCK8 PCK8 DQ0 DQ7 A0 A12 BAO BA1 IRAS ICAS IWE ICS CKE DQ0 DQ7 A0 A12 BAO BA1 IRAS ICAS IWE CS CKE 32Mx8 DDR 32Mx8 z a DQS3 4 4 PCK5 PCK5 PCK9 PCK9 DQ0 DQ7 0 12 BAO BA1 IRAS ICAS 32Mx8 DDR SDRAM 32Mx8 DDR SDRAM DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 A0 A12 A0 A12 A0 A12 BAO BA1 BAO BA1 0 1 32Mx8 IRAS 32Mx8 IRAS 32 8 IRAS 32Mx8 DDR ICAS DDR leas DDR EPA DDR SDRAM SDRAM SDRAM SDRAM ICS EI a CKE 2 CKE 2 CKE DMO DM1 DM3 DQSO DQS1 DQS2 DQS3 CBO CB7 PCK1JPCK1 PCK2JPCK2 PCK3 PCK3 PCK4 PCK4 pum 5 5 PCK6 PCK6 PCK7JPCK PCK8 PCK8 PCK9 PCK9 A0 A12 A0 A12 A0 A12 A0 A12 BAO BA1 BAO BA1 BAO BA1 BAO BA1 DQ0 DQ7 DQ0 DQ7 4 DQ0 DQ7 4 DQ0 DQ7 IRAS 32Mx8 IRAS 32Mx8 RAS 32Mx8 RAS 32Mx8 DDR _ por _ DDR _ DDR ICAS ICAS ICAS SDRAM SDRAM
11. fresh functions are same as the CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 1 Bank select addresses If both BAO and 1 Low at read write row active and precharge bank A is selected If both is High and is Low at read write row active and precharge bank B is selected If both is Low and is High at read write row active and precharge bank C is selected If both BAO and 1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAO and BA1 are ignored and all banks are selected 2uring burst write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is 0 This combination is not defined for any function which means No Operation NOP in DDR SDRAM Transcend Information Inc 9 TS64MDR72V4F3 184 PIN DDR400 Registered DIMM 512MB With 32Mx8 CL3 Serial Presence Detect Specification
12. n Inc Placement zum u B nu PCB 09 1590 TS64MDR72V4F3 184 PIN DDR400 Registered DIMM 512MB With 32Mx8 CL3 Pin Identification Symbol Function A0 A12 BAO Address input Dimensions Side Millimeters Inches A 133 35 0 20 5 250 0 008 B 72 39 2 850 6 35 0 250 D 2 20 0 087 E 30 48 0 20 1 20 0 008 F 19 80 0 779 G 4 00 0 157 H 12 00 0 472 1 27 0 10 0 050 0 004 Refer Placement Transcend Information Inc DQ0 DQ63 Data Input Output CBO CB7 Check bit Data in data out DQS0 DQS8 Data strobe input output CKO CKO Clock Input CKEO CKE1 Clock Enable Input CSO CS1 Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe Write Enable DMO0 DM8 Data in Mask VDD 2 6 Voltage power supply VDDQ 2 6 Voltage Power Supply for DQS VREF Power Supply for Reference VDDSPD 2 5 Voltage Serial EEPROM Power Supply SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground RESET Reset enable NC No Connection TS64MDR72V4F3 184 PIN DDR400 Registered DIMM 512MB With 32Mx8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 VREF 47 DQS8 93 VSS 139 VSS 02 DQO 48 94 004 140
13. nused Storage Locations Undefined 00 Transcend Information Inc T
14. ostamble tRPST 0 4 0 6 tCK CK to valid DQS in tDQSS 0 72 1 28 tCK Write preamble setup time tWPRES 0 ps 2 DQS in hold time tWPREH 0 25 tCK DQS falling edge to CK rising setup time tDSS 0 2 tCK DQS falling edge from CK rising hold time tDSH 0 2 tCK DQS in high level width tDQSH 0 35 tCK DQS in low level width tDQSL 0 35 tCK Address and Control input setup time tIS 0 6 ns Address and Control input hold time tlH 0 6 ns Data out high impedance time from CK CK tHZ tAC max ns Data out low impedance time from CK CK tLZ tACmin tAC max ns Mode register set cycle time tMRD 2 2tCK DQ amp DM setup time to DQS tDS 0 4 ns DQ amp DM hold time to DQS tDH 0 4 ns DQ amp DM input pulse width tDIPW 1 75 ns Exit self refresh to read command tXSRD 200 tCK Refresh interval time tREFI 7 8 us 1 tCLmin or Clock half period tHP tCHmin ns DQS write postamble time tWPST 0 4 0 6 tCK 3 Note 1 Maximum burst refresh of 8 2 The specific requirement is that DQS be valid High or Low on or before this CK edge The case shown DQS going from High Z to logic Low applies when no writes were previously in progress on the bus If a previous write was in progress DQS could be High at this time depending on tDQSS 3 The Maximum limit for this parameter is not a device limit The device will operate with a great value for this parameter but system performance bus turnaround will degrade accordingly Transcend Information Inc
15. t track variations in the DC level of VREF 3 VID is the magnitude of the difference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ 5 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same Transcend Information Inc 5 184 PIN DDR400 Registered DIMM TS64MDR72V4F3 512MB With 32Mx8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V 10 C Parameter Symbol Max Unit Note Operating current One bank Active Precharge tRC tRCmin tCK min DM and DQS inputs changing twice per clock cycle Address and control inputs changing once per clock cycle IDDO 1251 mA Operating current One bank Active Read Precharge Burst 2 tRC tRC min 2 5 tCK tCK min VIN VREF fro DQ DQS and DM Precharge power down standby current All banks idle power down mode CKE lt VIL max tCK min IDD2P 72 mA VIN VREF for DQ DQS and DM Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min tCK 133Mhz for DDR266 Address and other control inputs changing once per clock cycle VIN VREF for DQ DQS and DM Activ
16. ve to Row Activate delay tRRD 10ns 28 29 Minimum RAS to CAS Delay tRCD 15ns 3C 30 Minimum active to Precharge time tRAS 40ns 28 31 Module ROW density 256MB 40 32 Command Address Input Setup Time 0 6ns 60 33 Command Address Input Hold Time 0 6ns 60 34 Data Signal Input Setup Time 0 4 5 40 35 Data Signal Input Hold Time 0 4ns 40 36 40 Superset Information 00 Transcend Information Inc 10 TS64MDR72V4F3 184 PIN DDR400 Registered DIMM 512MB With 32Mx8 CL3 41 DDR SDRAM Minimum Active to Active Auto Refresh 55ns 37 Time tRC 42 DDR SDRAM Minimum Auto Refresh to Active Auto 70ns 46 Refresh Command Period tRFC 43 DDR SDRAM Maximum Device Cycle Time tCK max 10ns 28 44 DDR SDRAM DQS DQ Skew for DQS and associated 0 4ns 28 DQ signals tDQSQ max 45 DDR SDRAM Read Data Hold Skew Factor tQHS 0 5ns 50 46 PLL Relock Time 100us 64 47 61 Superset Information 00 62 SPD Data Revision Code Revision 1 0 10 63 Checksum for Bytes 0 62 E8 64 71 Manufacturers JEDEC ID Transcend TF 4 72 Manufacturing Location T 54 54 53 36 34 4D 44 73 90 Manufacturers Part Number TS64MDR72V4F3 52 37 32 56 34 46 33 20 20 20 20 20 91 92 Revision Code 00 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 127 Manufacturer Specific Data 00 128 255 U
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