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Transcend DDR2 256 MB DDR2-533

1. Pinouts Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 VREF 41 VSS 81 DQ33 121 VSS 161 CB4 201 VSS 02 VSS 42 CBO 82 VSS 122 DQ4 162 CB5 202 DM4 03 DQO 43 CB1 83 DQS4 123 DQ5 163 VSS 203 NC 04 DQ1 44 VSS 84 DQS4 124 VSS 164 DM8 204 VSS 05 VSS 45 DQS8 85 VSS 125 DMO 165 NC 205 DQ38 06 DQSO 46 DQS8 86 DQ34 126 NC 166 VSS 206 DQ39 07 DQSO 47 VSS 87 DQ35 127 VSS 167 CB6 207 VSS 08 VSS 48 CB2 88 VSS 128 DQ6 168 CB7 208 DQ44 09 DQ2 49 CB3 89 DQ40 129 DQ7 169 VSS 209 DQ45 10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS 11 VSS 51 VDDQ 91 VSS 131 DQ12 171 CKE1 211 DM5 12 DQ8 52 CKEO 92 DQS5 132 DQ13 172 VDD 212 NC 13 DQ9 53 VDD 93 DQS5 133 VSS 173 NC 213 VSS 14 VSS 54 NC 94 VSS 134 DM1 174 NC 214 DQ46 15 DQS1 55 NC 95 DQ42 135 NC 175 VDDQ 215 DQ47 16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 216 VSS 17 VSS 57 A11 97 VSS 137 CK1 177 AQ 217 DQ52 18 NC 58 A7 98 DQ48 138 CK1 178 VDD 218 DQ53 19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS 20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 CK2 21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 221 CK2 22 DQ11 62 VDDQ 102 NC 142 VSS 182 A3 222 VSS 23 VSS 63 A2 103 VSS 143 DQ20 183 A1 223 DM6 24 DQ16 64 VDD 104 DQS6 144 DQ21 184 VDD 224 NC 25 DQ17 65 VSS 105 DQS6 145 VSS 185 CKO 225 VSS 26 VSS 66 VSS 106 VSS 146 DM2 186 CKO 226 DQ54 27 DQS2 67 VDD 107 DQ50 147 NC 187 VDD 227 DQ55 28 DQS2 68 NC 108 DQ51 148 VSS 188 AO 2
2. 37 Internal write to read command delay tWTR 7 5ns 1E 38 Internal read to precharge command delay tRTP 7 5ns 1E 39 Memory analysis probe characteristics 00 40 Reserved 00 41 DDR SDRAM Minimum Active to Active Auto Refresh 55ns 37 Time tRC 42 DDR SDRAM Minimum Auto Refresh to 75ns 4B Active Auto Refresh Command Period tRFC 43 DDR SDRAM Maximum Device Cycle Time tCK max 8ns 80 AA DDR SDRAM DQS DQ Skew for DQS and associated 0 3ns 1E DQ signals tDQSQ max i 45 DDR SDRAM Read Data Hold Skew Factor tQHS 0 4ns 28 46 PLL Relock Time 7 00 47 61 Superset Information 00 62 SPD Data Revision Code REV 1 0 10 63 Checksum for Bytes 0 62 D9 64 71 Manufacturers JEDEC ID Transcend 7F 4F 72 Manufacturing Location T 54 54 53 33 32 4D 4C 73 90 Manufacturers Part Number TS32MLQ72V5F 51 37 32 56 35 46 20 20 20 20 20 20 91 92 Revision Code 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 127 Manufacturer Specific Data 128 255 Open for customer use Undefined Transcend Information Inc 11
3. tCK IDD tRC tRC IDD tRAS tRASmin IDD CKE is HIGH CS is HIGH between valid commands IDDO 900 mA Address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating One bank Active read Precharge current IOUT OmA BL 4 CL CL IDD AL 0 tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD tRCD tRCD IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W IDD1 990 mA Precharge power down current All banks idle tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are FLOATING IDD2P 72 mA Precharge quiet standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are STABLE Data bus inputs are pp2Q 225 mA FLOATING Precharge standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are SWITCHING Data bus inputs are IDD2N 270 mA SWITCHING Active power down current All banks open tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are _ FLOATING Slow PDN Exit MRS 12 1mA IDD3P S 135 Fast PDN Exit MRS 12 OmA IDD3P F 270 mA Active standby current All banks open tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Other control IDD3N 630 mA and address bus inputs are S
4. CK1 and CK1 Input capacitance CKEO and CS Input capacitance AO A12 BAO BA1 RAS CAS WE Input capacitance DQ DM DQS DQS DM is internally loaded to match DQ and DQS identically Input capacitance CK2 and CK2 Transcend Information Inc 7 240PIN DDR2 533 Unbuffered DIMM TS32MLQ72V5F 256MB With 32Mx8 CL4 Timing Parameters amp Specifications These AC characteristics were tested on the Component Parameter Symbol Min Max Unit Note DQ output access time from CK amp CK tAC 500 500 ps DQS output access time from CK amp CK tDQSCK 450 450 ps CK high level width tCH 0 45 0 55 tCK CK low level width tCL 0 45 0 55 tCK CK half period tHP min tCL tCH X ps Clock cycle time CL x tCK 3750 8000 ps DQ and DM input hold time tDH 225 x ps DQ and DM input setup time tDS 100 X ps Control amp Address input pulse width for each input tIPW 0 6 x tCK DQ and DM input pulse width for each input tDIPW 0 35 X tCK Data out high impedance time from CK CK tHZ X tAC max ps DQS low impedance time from CK CK tLZ DQS tAC min tAC max ps DQ low impedance time from CK CK tLZ DQ 2 tACmin TACmax ps DQS DQ skew for DQS and associated DQ signals tDQSQ X 300 ps DQ hold skew factor tQHS X 400 ps DQ DQS output hold time from DQS tQH tHP tQHS X ps Write command to first DQS latching transition tDQSS WL 0 25 WL 0 25 tCK
5. Lower power CKE minimum pulse width high and low pulse width tCKE tCK ODT turn on delay tAOND 2 tCK ODT turn on tAON tAC min tAC max 1 ns ODT turn on Power Down mode tAONPD tAC min 2 ORE ns ODT turn off delay tAOFD 2 5 2 5 tCK ODT turn off tAOF tAC min tAC max 0 6 ns ODT turn off Power Down mode tAOFPD tAC min 2 eine ns ODT to power down entry latency tANPD 3 tCK ODT power down exit latency tAXPD 8 tCK OCD drive mode output delay tOlT 0 12 ns Minimum time clocks remains ON after CKE Delay tIS tCK tlH ne Transcend Information Inc TS32MLQ72V5F 240PIN DDR2 533 Unbuffered DIMM 256MB With 32Mx8 CL4 SERIAL PRESENCE DETECT SPECIFICATION Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Serial PD Bytes written during module production 128bytes 80 1 Total of Bytes of S P D Memory Device 256bytes 08 2 Fundamental Memory Type DDR2 SDRAM 08 3 of Row Addresses on this Assembly 12 oD 4 of Column Addresses on this Assembly 10 OA 5 of Module Rows on this Assembly eRe Nena 60 30 0mm 6 Data Width of this Assembly 72bits 48 7 Reserved 00 8 VDDQ and Interface Standard of this Assembly SSTL 1 8V 05 DDR2 SDRAM cycle time at Max Supported CA 9 rex y A dicne 3 75ns 3D 10 DDR2 SDRAM Access time from clock at CL X 0 5ns 50 11 DIMM configuration
6. 20 102 D 3s WA 103 DQ 27 103 U4 DQ59 wr 103 U8 DQ 28 1 04 DQ 60 W 1 04 DQ 29 105 DQ 61 W 1 05 DQ 30 106 DQ 62 WH 1 06 DQ 31 107 DQ 63 WY 107 DQS8 WJ DQS8 w DM8 DA H DM CS DQS DQS A0 A13 wr gt U1 U9 Cap wf 100 BAO BA1 w gt Ul U9 CK0 CKO gt U4 U6 CB2 AWA He 4 CKEO U1 U9 CK1 CK1 gt U1 U3 CBS Ww 103 U9 CBS SW 1104 RAS w UIU CK2 CK2 U7 U9 CB6 awy 1 0 6 CAS w U1 U9 CE MOT WWE w gt U1 U9 ODTO gt UI1 U8 EEPROM SCL SDA VDDSPD 4 EEPROM SAO SA1 SA2 Note VDD VDDQ r gt U1 U9 1 DQ DM DQS amp DQS resistors 22 Ohms 5 VREF 7 _ gt U1 U9 2 Bx Ax RAS CAS amp WE resistors 5 1 Ohms 5 VSS T gt U1 U9 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 240PIN DDR2 533 Unbuffered DIMM TS32 M LQ72V5F 256MB With 32Mx8 CL4 Absolute Maximum DC Ratings Parameter Symbol Value Unit Notes Voltage on VDD relative to Vss VDD 1 0 2 3 V 1 Voltage on VDDQ pin relative to Vss VDDQ 0 5 2 3 V 1 Voltage on VDDL pin relative to Vss VD
7. 28 VSS 29 VSS 69 VDD 109 VSS 149 DQ22 189 VDD 229 DQ60 30 DQ18 70 A10 AP 110 DQ56 150 DQ23 190 BA1 230 DQ61 31 DQ19 71 BAO 111 DQ57 151 VSS 191 VDDQ 231 VSS 32 VSS 72 VDDQ 112 VSS 152 DQ28 192 RAS 232 DM7 33 DQ24 73 WE 113 DQS7 153 DQ29 193 CS0 233 NC 34 DQ25 74 CAS 114 DQS7 154 VSS 194 VDDQ 234 VSS 35 VSS 75 VDDQ 115 VSS 155 DM3 195 ODTO 235 DQ62 36 DQS3 76 CS1 116 DQ58 156 NC 196 A13 236 DQ63 37 DQS3 77 ODT1 117 DQ59 157 VSS 197 VDD 237 VSS 38 VSS 78 VDDQ 118 VSS 158 DQ30 198 VSS 238 VDDSPD 39 DQ26 79 VSS 119 SDA 159 DQ31 199 DQ36 239 SAO 40 DQ27 80 DQ32 120 SCL 160 VSS 200 DQ37 240 SA1 For ECC type Please refer Block Diagram Transcend Information Inc 3 240PIN DDR2 533 Unbuffered DIMM TS32MLQ72V5F 256MB With 32Mx8 CL4 Block Diagram DQS4 DQS4 DM4 WwW DM CS_ DQS DQS D35 w 103 U5 DO 38 WH DQ 39 WY DQSS v DQS5S w DMS AM DM CS_ DQS DQS DM CS_ DQS DQS 10 0 DQ 40 WM O1 DQ 41 Ws U2 DQ 42 WN BEBO OOSE O a O ARBNHS I I I I I I I I Bug DQ 47 W DQS6 DQS6 w DM6 w DM CS DQS DQS DM CS DQS DQS DQ 48 W 1 00 DO 49 w 1 0 1 DO 50 AAW 1 02 DOsi w mos U7 DQ 52 W 1 04 DA 53 WA 1 05 DQ 54 H 1 06 DQ 55 WY 1 07 DQS7 DQS7 w DM7 ema DM CS_ DQS DQS DM CS_DQS DQS DQ 24 10 0 DQ 56 w 1 00 BO
8. DD was calculated on the basis of component IDD and can be differently measured according to DQ loading capacitor Transcend Information Inc 6 240PIN DDR2 533 Unbuffered DIMM TS32MLQ72V5F 256MB With 32Mx8 CL4 Input AC Logic Level Parameter Symbol Min Max Unit Note Input High Logic 1 Voltage DQ DQS and DM signals VIH AC VREF 0 250 V Input Low Logic 0 Voltage DQ DQS and DM signals VIL AC VREF 0 250 V AC Input Test Condition Condition Symbol Vae Unt Note VSWING MAX Input signal minimum slew rate 2 3 1 Input waveform timing is referenced to the input signal crossing through the VIH IL AC level applied to the device under test 2 The input signal minimum slew rate is to be maintained over the range from VREF to VIH AC min for rising edges and the range from VREF to VIL AC max for falling edges as shown in the below figure 3 AC timings are referenced with input waveforms switching from VIL AC to VIH AC on the positive transitions and VIH AC to VIL AC on the negative transitions a 552 VDD TMB ee ane ee ge ee VIH AC min SS er ele VIH DC min VR delta TF gt delta TR V rer V L A C max Rising Slew Vin AC min VREF delta TF delta TR Falling Slew AC Input Test Signal Waveform Input Output Capacitance Voo 1 8V Vopa 1 8V TA 25 C Input capacitance CKO and CKO Input capacitance
9. DL 0 5 2 3 V 1 Voltage on any pin relative to Vss VIN VOUT 0 5 2 3 V 1 Storage temperature TSTG 55 100 C 1 2 Mean time between failure MTBF Reserved year Temperature Humidity Burning THB Reserved C Temperature Cycling Test TC Reserved C Note 1 Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard AC amp DC Operating Conditions Recommended DC operating conditions SSTL 1 8 Rating Parameter Symbol Unit Notes Min Typ Max Supply voltage VDD 1 7 1 8 1 9 V Supply voltage for DLL VDDL 1 7 1 8 1 9 V 4 Supply voltage for Output VDDQ 1 7 1 8 1 9 V 4 I O Reference voltage VREF 0 49 VDbDa 0 50 VDDQ VpDa 2 50mV V 1 2 I O Termination voltage VTT VREF 0 04 VREF VREF 0 04 V 3 DC Input logic high VIH DC VREF 0 125 VDDQ 0 3 V DC Input logic low VIL DC 0 3 VREF 0 125 V Note There is no specific device VDD supply voltage requirement for SSTL 1 8 compliance However under all condi
10. DQS input high pulse width tDQSH 0 35 X tCK DQS input low pulse width tDQSL 0 35 X tCK DQS falling edge to CK setup time tDSS 0 2 xX tCK DQS falling edge hold time from CK tDSH 0 2 X tCK Mode register set command cycle time tMRD 2 X tCK Write postamble tWPST 0 4 0 6 tCK Write preamble tWPRE 0 35 X tCK Address and control input hold time tIH 375 X ps Address and control input setup time tIS 250 X ps Read preamble tRPRE 0 9 1 1 tCK Read postamble tRPST 0 4 0 6 tCK Se active command period for 1KB page size IRRD 75 xX ae Se active command period for 2KB page size IRRD 10 xX ie Four Activate Window for 1KB page size products tFAW 37 5 ns Transcend Information Inc 8 TS32MLQ72V5F 240PIN DDR2 533 Unbuffered DIMM 256MB With 32Mx8 CL4 asynchronously drops LOW Four Activate Window for 2KB page size products tFAW 50 ns ICAS to CAS command delay tCCD 2 tCK Write recovery time tWR 15 x ns Auto precharge write recovery precharge time tDAL tWR tRP x tCK Internal write to read command delay tWTR 7 5 X ns Internal read to precharge command delay tRTP 7 5 ns Exit self refresh to a non read command tXSNR tRFC 10 ns Exit self refresh to a read command tXSRD 200 tCK Exit precharge power down to any non read command tXP 2 x tCK Exit active power down to read command tXARD 2 X tCK Exit active power down to read command Slow exit tXARDS 6 AL tCK
11. TS32MLQ72V5F 240PIN DDR2 533 Unbuffered DIMM 256MB With 32Mx8 CL4 Description The TS32MLQ72V5F is a 32M x 64bits DDR2 533 Unbuffered DIMM The TS32MLQ72V5F consists of 9 pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages and a 2048 bits serial EEPROM on a 240 pin printed circuit board The TS32MLQ72V5F is a Dual In Line Memory Module and is intended for mounting into 240 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e JEDEC standard 1 8V 0 1V Power supply e VDDQ 1 8V 0 1V e Max clock Freq 267MHZ 533Mb S Pin e Posted CAS e Programmable CAS Latency 3 4 5 e Programmable Additive Latency 0 1 2 3 and 4 e Write Latency WL Read Latency RL 1 e Burst Length 4 8 Interleave nibble sequential e Programmable sequential Interleave Burst Mode e Bi directional Differential Data Strobe Single ended data strobe is an optional feature e Off Chip Driver OCD Impedance Adjustment e MRS cycle with address key programs e On Die Termination e Refresh and Self Refresh Average Refresh Period 7 8us at lower then TCASE 85 C 3 9us at 85 C lt TCASE lt 95 C e Serial presence detect with EEPROM Transcend Info
12. WITCHING Data bus inputs are SWITCHING Operating burst read current All banks open Continuous burst reads IOUT OmA BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W IDD4R 1 440 mA Operating burst write current All banks open Continuous burst writes BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING DD4W 1 575 mA Data bus inputs are SWITCHING IDD4R Burst Auto refresh current tCK tCK IDD Refresh command at every tRFC IDD interval CKE is HIGH CS is HIGH between valid commands Other control and IDD5B 1 485 mA address bus inputs are SWITCHING Data bus inputs are SWITCHING Self refresh current CK and CK at OV CKE 0 2V Other control and address bus inputs are FLOATING Data bus inputs are FLOATING PPG i mi Operating bank interleave read current All bank interleaving reads IOUT 0mA BL 4 CL CL IDD AL tRCD IDD 1 tCK IDD tCK tCK IDD tRC tRC IDD tRRD tRRD IDD tRCD 1 tCK IDD CKE is HIGH CS is HIGH between valid IDD7 2 295 mA commands Address bus inputs are STABLE during Deselects Data pattern is same as IDD4R Refer to the following page for detailed timing conditions Note 1 Module I
13. rmation Inc Placement Goro Bp SE cay yy Coe E Hij L M O t a I gt e t t i M gt gt tJ k gt PCB 09 2130 TS32MLQ72V5F 240PIN DDR2 533 Unbuffered DIMM 256MB With 32Mx8 CL4 Pin Identification Symbol Function A0 A13 BAO BA1 Address input DQ0 DQ63 Data Input Output CBO CB7 DIMM ECC Check Bits DQS0 DQS8 Data strobe DQS0 DQS8 Differential Data strobe Dimensions Side Millimeters Inches 133 35 0 15 5 250 0 006 B 55 2 165 C 63 2 480 D 5 0 197 E 2 5 0 098 F 1 5 0 10 0 059 0 039 G 5 175 0 204 H 2 2 0 867 4 0 157 J 10 0 394 K 17 8 0 701 L 30 0 15 1 181 0 006 M 1 27 0 10 0 050 0 004 Refer Placement Transcend Information Inc CKO CKO CK1 CK1 Clock Input CK2 CK2 CKEO CKE1 Clock Enable Input ODTO On die termination control line CSO Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe IWE Write Enable DMO DM8 Data in Mask VDD 1 8 Voltage power supply 1 8 Voltage Power Supply for VDDQ DQS VREF Power Supply for Reference Serial EEPROM Positive Power VDDSPD Supply SA0 SA2 Address select for EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground NC No Connection 240PIN DDR2 533 Unbuffered DIMM TS32MLQ72V5F 256MB With 32Mx8 CL4
14. tions VDDQ must be less than or equal to VDD 1 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 2 Peak to peak AC noise on VREF may not exceed 2 VREF DC 3 VTT of transmitting device must track VREF of receiving device 4 AC parameters are measured with VDD VDDQ and VDDDL tied together Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature TOPER 0 to 95 C 1 2 3 Note 1 Operating Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 2 At 0 85 C operation temperature range are the temperature which all DRAM specification will be supported 3 At 85 95 C operation temperature range doubling refresh commands in frequency to a 32ms period tREFI 3 9 us is required and to enter to self refresh mode at this temperature range an EMRS command is required to change internal refresh rate Transcend Information Inc 5 240PIN DDR2 533 Unbuffered DIMM TS32MLQ72V5F 256MB With 32Mx8 CL4 IDD Specification parameters Definition IDD values are for full operating range of voltage and Temperature Parameter Symbol Max Unit Note Operating One bank Active Precharge current tCK
15. type non parity Parity ECC ECC 02 12 Refresh Rate 7 8us 02 13 Primary DDR2 SDRAM Width X8 08 14 Error Checking DDR2 SDRAM Width X8 08 15 Reserved 00 DDR2 SDRAM device attributes Burst lengths ie supported 4 8 oc 47 DDR2 SDRAM device attributes of banks on each 4 banks 04 DDR2 SDRAM device 18 DDR2 SDRAM device attributes CAS Latency 543 38 supported 19 Reserved 00 20 DIMM type information Regular UDIMM 02 Analysis probe not 21 DDR2 SDRAM Module Attributes installed FET switch 00 external not enable 22 DDR2 SDRAM Device Attributes General Supports weak driver 01 23 DDR2 SDRAM Cycle Time CL X 1 3 75ns 3D 24 DDR SDRAM Access from Clock CL X 1 0 5ns 50 25 DDR SDRAM Cycle Time CL X 2 5 0ns 50 26 DDR SDRAM Access from Clock CL X 2 0 6ns 60 27 Minimum Row Precharge Time tRP 15ns 3C 28 Minimum Row Active to Row Activate delay tRRD 7 5ns 1E 29 Minimum RAS to CAS Delay tRCD 15ns 3C 30 Minimum active to Precharge time tRAS 40ns 28 31 Module ROW density 256MB 40 32 Command and address setup time before clock tlS 0 25ns 25 33 Command and address hold time after clock tlH 0 37ns 37 34 Data input setup time before strobe tDS 0 10ns 10 35 Data input hold time after strobe tDH 0 22ns 22 36 Write recovery time tWR 15ns 3C Transcend Information Inc 10 TS32MLQ72V5F 240PIN DDR2 533 Unbuffered DIMM 256MB With 32Mx8 CL4

Transcend DDR2 256 MB DDR2-533

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