Transcend 64MB SDRAM PC100 Unbuffer Non-ECC Memory
Contents
1. Parameter Symbol Min Max Unit Note CAS latency 3 10 CLK cycle time y tcc 1000 ns 1 CAS latency 2 10 CLK to valid CAS latency 3 6 output delay ihe ie CAS latency 2 6 Output data CAS latency 3 3 hold time aH ns 2 CAS latency 2 3 CLK high pulse width tCH 3 ns 3 CLK low pulse width tCL 3 ns 3 Input setup time tss 2 ns 3 Input hold time tSH 1 1 3 CLK to output in Low Z tSLZ 1 1 2 CLK to output CAS latency 3 tSHZ 6 g in Hi Z CAS latency 2 6 Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 168PIN PC100 Unbuffered DIMM TS8 M LS 64V8C 64MB With 8Mx16 CL3 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low Refresh Auto Refresh ae Self Entry ian Refresh Ewe Toa Bank Active amp Row Addr HHH KARA Meee Read amp Auto Precharge Disable Auto Precharge Enable E Auto Precharge Disable Auto Precharge Enable Burst Stop Precharge Bank Selection Both Banks Column Address Column Address Clock Suspend or Entry Active Power Down es Precharge Power Down Mode No RN oe Command SS Heme f2. Fig 2 5 ow 1200 Ohm 50 Ohm Vou DC 2 4V loH 2MA Output Z0 50 Ohm Vou DC 0 4V lo 2mA 50pF 50F 870 Ohm ZIT Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 20 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time ippS ini nS 1 tRAS max 100 us Row cycle time tRC min 70 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccD min 1 CLK 3 Number of valid CASAC CS 2 ea 4 output data CAS latency 2 1 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 7 168PIN PC100 Unbuffered DIMM TS8 M LS 64V8C 64MB With 8Mx16 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module
3. ree R i m One Bank Active IRE ROUT loL OmA Precharge Standby Current ICC2P___ CKE lt VIL max tcc 10ns 8 mA in power down mode Icc2PS_ CKE amp CLK lt VIL max tcc 8 CKE2VIH min CS2VIH min tcc 10ns Icc2N Input signals are changed one time during 20ns 80 Precharge Standby Current mA in non power down mode i mh IccoNS CKE2VIH min CLK lt VIL max tcc 40 Input signals are stable Active Standby Current Icc3P CKE lt VIL max tcc 10ns 20 mA in power down mode Icc3PS_ CKE amp CLK lt VIL max tcc 20 Active Standby Current Icc3N CKE2VIH min CS VIH min tcc 10ns 420 Input signals are changed one time during 20ns in non power down mode HA Bank Acti One Bank Active Icc3NS CKE gt VIH min CLK lt ViL max tcc 0 Input signals are stable IOL 0 mA Operating Current EF Page Burst 3 520 mA 1 Bust Mode tecp 2CLKs 2 520 Refresh Current ICc5 tRc tRC min 760 mA 2 Self Refresh Current ICC6 CKE lt 0 2V 8 mA Note 1 Measured with outputs open 2 Refresh period is 64ms Transcend information Inc 6 168PIN PC100 Unbuffered DIMM TS8 M LS 64V8C 64MB With 8Mx16 CL3 AC OPERATING TEST CONDITIONS VDD 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See
4. 0 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 20ns 14 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 50ns 32 31 Density of Each Bank on Module 1 row of 64MB 10 32 Command Address Setup Time 2ns 20 33 Command Address Hold Time 1ns 10 34 Data Signal Setup Time 2ns 20 35 Data Signal Hold Time 1ns 10 36 61 Superset Information 00 Transcend information Inc 10 TS8MLS64V8C 168PIN PC100 Unbuffered DIMM 64MB With 8Mx16 CL3 62 SPD Data Revision Code JEDEC2 12 63 Checksum for Bytes 0 62 3D 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 54 53 38 4D 4C 53 73 90 Manufacturers Part Number TS8MLS64V8C 36 34 56 138143120 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufactory Variable 95 98 Assembly Serial Number By Manufactory Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 100MHz 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 3 F4 128 Unused Storage Locations Open FF Transcend information Inc
5. 16 CL3 Dimensions Pin Identification Side Millimeters Inches Symbol Function A 133 35 0 40 5 250 0 016 A0 A11 BAO BA1 Address input B 65 67 2 585 DQO DQ63 Data Input Output C 23 49 0 925 D 8 89 0 350 CLKO CLK2 Clock Input E 3 00 0 118 CKEO Clock Enable Input eu peso we CSO CS2 Chip Select Input G 19 80 0 788 H 15 80 0 622 RAS Row Address Strobe 1 27 0 10 0 050 0 004 CAS Column Address Strobe Refer Placement WE Write Enable DQMO DQM7 Data DQ Mask SAO SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection Transcend information Inc 168PIN PC100 Unbuffered DIMM TS8 M LS 64V8C 64MB With 8Mx16 CL3 Pinouts Pin Name No Name No Name No Name Vss 43 85 Vss 127 Vss DQO 44 86 DQ32 128 CKEO DQ1 DQ33 129 CS3 DQ2 DQ34 130 DQM6 DQ3 DQ35 131 DQM7 Vcc Vcc 132 A13 DQ4 DQ36 133 DQ5 DQ37 134 DQ6 DQ38 135 DQ7 DQ39 136 DQ8 DQ40 137 Vss Vss 138 DQ9 DQ41 139 DQ10 DQ42 140 DQ11 DQ43 141 DQ12 DQ44 142 DQ13 DQ45 143 Vcc 144 DQ46 145 DQ47 146 CB4 147 CB5 148 149 150 151 152 153 154 A6 A10 AP 80 BA1 Vcc Vcc CLKO Please refer Block Diagram Transcend information Inc 3 168PIN PC100 Unbuffered DIMM TS8 M LS 64V8C 64MB With 8Mx16 CL3 Block Diagram X A0 A11 A0 A11 A0 A11 AO A11 AOL BAU
6. 168PIN PC100 Unbuffered DIMM TS8 M LS 64V8C 64MB With 8Mx16 CL3 Description Placement The TS8MLS64V8C is a 8M bit x 64 Synchronous Dynamic RAM high density for PC 100 The TS8MLS64V8C consists of 4pcs CMOS 8Mx16 bits Synchronous DRAMs in TSOP II 400mil packages anda 2048 bits serial EEPROM on a 168 pin printed circuit board The TS8MLS64V8C is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 100 e Conformed to JEDEC Standard Spec e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs PCB 09 7130 Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock Transcend information Inc 1 TS8MLS64V8C 168PIN PC100 Unbuffered DIMM 64MB With 8Mx
7. DA BAO BA1 BAO BA1 BAO BA1 BAO BA1 DQ0 DQ63 DQ0 DQ15 DQ0 DQ15 DQ0 DQ15 DQ0 DQ15 RAS IRAS 8Mx16 ICAS SDRAM INE ICS0 CLKO CKEO ICS2 CLK2 Serial EEPROM SCL SCL SDA SDA AO A1 A2 SA0 SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 4 168PIN PC100 Unbuffered DIMM 64MB With 8Mx16 CL3 TS8MLS64V8C ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 4 W Short circuit current los 50 mA Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Typ Max Uni
8. MLS64V8C 168PIN PC100 Unbuffered DIMM 64MB With 8Mx16 CL3 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described s Sene ard Vendor Part pecification 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 12 0C 4 of Column Addresses on this Assembly 9 09 5 of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 10ns AO 10 SDRAM Access from Clock highest CL 6ns 60 11 DIMM configuration type non parity ECC Non parity 00 12 Refresh Rate Type eee elt 80 13 Primary SDRAM Width X16 10 14 Error Checking SDRAM Width None 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 amp 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffered 00 22 SDRAM Device Attributes General PASC ll Auto RIEG 0E R W Burst 23 SDRAM Cycle Time 2 highest CL 12ns CO 24 SDRAM Access from Clock 2 highest CL 7ns 70 25 SDRAM Cycle Time 3 highest CL 0
9. g SRO Note 1 OP Code Operand Code Ao A11 BAo BA11 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatical precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA is ignored and both banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 O Transcend information Inc 9 TS8
10. t Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current Inputs liL 10 10 uA 3 Input leakage current I O pins liL 1 5 1 5 uA Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs 4 Dout is disabled OV lt VOUT lt VDDQ CAPACITANCE VDD 3 3V TA 20 C f 1MHz VREF 1 4V 200 mV Parameter Symbol Min Max Unit Input capacitance Ao A11 BAo BA CIN1 15 25 pF Input capacitance RAS CAS WE CIN2 15 25 pF Input capacitance CKEO CIN3 15 25 pF Input capacitance CLKO CLK2 CIN4 10 13 pF Input capacitance CSO CS2 CIN5 10 15 pF Input capacitance DQMO DQM7 CIN6 8 10 pF Data input output capacitance DQO DQ63 CouT1 9 12 pF Transcend information Inc 168PIN PC100 Unbuffered DIMM TS8 M LS 64V8C 64MB With 8Mx16 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition CAS Latency Value Typ Unit Note Operating Current a Burst Length 1
Download Pdf Manuals
Related Search