Transcend 256MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory
Contents
1. SEK CLK S S DQM2 DQM7 SDA This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 4 TS32MSS64V6F ABSOLUTE MAXIMUM RATINGS 144PIN PC133 Unbuffered SO DIMM 256MB With 32M X 8 CL3 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply relative to Vss VDD VDDQ 1 0 4 6 V Storage temperature TsTG 55 150 C Power dissipation PD 8 Short circuit current los 50 mA Operating Temperature TA 0 70 C Note Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 32. 0 0 8 V 2 Output high voltage VOH 24 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current ILI 10 10 uA 3 Note 1 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt Vin lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri state output CAPACITANCE Vo 3 3V 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Input capacitance A0 A12 BAO BA1 25 45 Input capacitance RAS CAS WE CIN2 25 45 pF Input capacitance CIN3 25 45 pF Input capacitance CLKO CLK1 CIN4 15 21 pF Input capacitance 0 CIN5 25 45 pF Input capacitance DQMO DQM7 CIN6 10 12 pF Data input output capacitance DQ0 DQ63 Cour 10 12 pF Transcend information Inc 5 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6F 256MB With 32M X 8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Unit Note Operating Current Icc1 Burst Length 1 960 mA 1 One Bank Active tRC2tRC min loL OmA Precharge Standby Current jIcc2P lt tcc 10ns 16 mA in power down mode IcczPS CKE amp CLK lt ViL max tcc 16 Precharge Standby Current ICc2N CKE ViH min CS2ViH min tcc 10ns 128 mA in non power
3. 13 Vcc 18 DQ38 66 CAS 114 Vcc 19 DQ7 67 115 DQM2 20 0039 68 CKE1 116 DQM6 21 Vss 69 CSO 117 DQM3 22 Vss 70 A12 118 DQM7 23 DQMO 71 CS1 119 Vss 24 DQM4 72 A13 120 Vss 25 DQM1 73 NC 121 DQ24 26 DQM5 74 CLK1 122 DQ56 27 Vcc 75 Vss 123 DQ25 28 Vcc 76 Vss 124 DQ57 29 77 2 125 00926 30 78 126 0058 31 A1 79 127 0027 32 4 80 CB7 128 0059 33 A2 81 Vcc 129 Vcc 34 A5 82 Vcc 130 Vcc 35 Vss 83 DQ16 131 DQ28 36 Vss 84 0048 132 09060 37 008 85 0017 133 00929 38 0040 86 0049 134 09061 39 009 87 0018 135 0030 40 0041 88 0050 136 09062 41 0010 89 0019 137 0031 42 0042 90 2051 138 09063 43 0011 91 Vss 139 Vss 44 DQ43 92 Vss 140 Vss 45 Vcc 93 0020 141 SDA 46 Vcc 94 DQ52 142 SCL 47 0012 95 0021 143 Vcc 48 0044 96 0053 144 Vcc Please refer Block Diagram Transcend information Inc 3 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6F 256MB With 32M X 8 CL3 Block Diagram A0 A12 1 A0 12 BA0 1 HA0 12 BA0 1 AO 12 BA0 1 DQ0 DQ63 50 8 DQ0 8 RAS E pera IRAS ICAS 32Mx8 ICAS 32Mx8 dicas 32Mx8 H CAS 32Mx8 i WE SDRAM Jwe SDRAM H we SDRAM SDRAM ICS ICS ICS cuo 8 Hek DOMT A0 12 BA0 1 MA0 12 BA0 1 12 1 be A0 12 BA0 1 DQ0 8 8 8 IRAS IRAS IRAS IRAS ICAS 32Mx8 32Mx8 Hicas 32Mx8 H cas 32 8 Wwe SDRAM we we SDRAM we SDRAM ICS ICS ICS ICS CKE cke gt Ucke
4. EO Clock Enable Input CSO Chip Select Input RAS Row address strobe ICAS Column address strobe ANE Write Enable DQMO 7 DQM Vcc Power Supply Vss Ground SDA Serial Address Data I O SCL Serial Clock NC No Connection TS32MSS64V6F 144PIN PC133 Unbuffered SO DIMM 256MB With 32M X 8 CL3 Dimensions o UT an an ca E UT Vienn ann RE REEL I V HR UU UE aimed alma gt N o 1 gt J PCB 09 6857 Side Millimeters Inches A 67 60 0 200 2 661 0 008 B 32 80 1 291 23 20 0 913 D 4 60 0 181 E 3 30 0 130 F 2 50 0 098 G 4 00 0 157 H 6 00 0 236 20 00 0 787 J 29 21 0 200 1 150 0 008 1 00 0 100 0 039 0 004 Transcend information Inc 2 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6F 256MB With 32M X 8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 Vss 49 DQ13 97 0022 02 Vss 50 DQ45 98 DQ54 03 DQO 51 DQ14 99 DQ23 04 DQ32 52 DQ46 100 0055 05 001 53 0015 101 Vcc 06 DQ33 54 DQ47 102 Vcc 07 DQ2 55 Vss 103 08 0034 56 Vss 104 A7 09 003 57 CBO 105 A8 10 DQ35 58 CB4 106 BAO 11 Vcc 59 CB1 107 Vss 12 Vcc 60 CB5 108 Vss 13 004 61 CLKO 109 9 14 DQ36 62 CKEO 110 BA1 15 DQ5 63 Vcc 111 10 16 DQ37 64 Vcc 112 A11 17 DQ6 65 RAS 1
5. Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 NC tRAS min 45 ns 1 Row active time tRAS max 100 um Row cycle time Operation tRC min 65 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccp min 1 CLK 3 Number of valid 2 4 output data Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 7 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6F 256MB With 32M X 8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Unit Note Min Max CLK cycle time tcc 7 5 1000 ns 1 tsac 5 4 ns 1 2 output delay Output data hold time tOH 3 0 ns 2 CLK high pulse width tCH 2 5 ns 3 CLK l
6. TS32MSS64V6F Description The TS32MSS64V6F is a 32M bit x 64 Synchronous Dynamic high density memory module The TS32MSS64V6F consists of 8 piece of CMOS 32Mx8bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 144 pin printed circuit board The TS32MSS64V6F is a Dual In Line Memory Module and is intended for mounting into 144 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e ROHS compliant products e Performance Range PC133 e Burst Mode Operation e Auto and Self Refresh e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock Transcend information Inc 144PIN PC133 Unbuffered SO DIMM Pin Identification 256MB With 32M X 8 CL3 Symbol Function A0 A12 Address inputs BAO BA1 Select Bank DQ0 DQ63 Data inputs outputs CLKO CLK1 Clock Input CK
7. down mode Input signals are changed one time during 20ns Icc2NS_ CKE ViH min CLK lt ViL max tcc lt 112 Input signals are stable Active Standby Current IccaP lt tcc 10ns 48 mA in power down mode IccaPS CKE amp CLK lt ViL max tcc 48 Active Standby Current Icc3N gt CS2ViH min tcc 10ns 240 mA in non power down mode Input signals are changed one time during 20ns One Bank Active IccaNS CKE ViH min CLKxViL max tcc lt 200 Input signals are stable Operating Current Icc4 loL 0 mA mA 1 Burst Mode Page Burst 1120 tccp 2CLKs mA 2 Refresh current Icc5 tRC gt tRC min 1680 Self Refresh Current cce lt 0 2 40 Note Module IDD was calculated the basis of component IDD and can be differently measured according to DQ loading cap Transcend information Inc 6 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6F 256MB With 32M X 8 CL3 AC OPERATING TEST CONDITIONS 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 1200 Ohm 50 Ohm Output gt DC 2 4V 2 Output Z0 50 Ohm Vo DC 0 4V lo 2mA 5 870 Ohm Fig 1 DC
8. lock Signal Support CL2 amp Clock 0 1 128 Unused Storage Locations Open FF Transcend information Inc 11
9. of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc 9 TS32MSS64V6F Serial Presence Detect Specification 144PIN PC133 Unbuffered SO DIMM 256MB With 32M X 8 CL3 Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly A0 A12 00 4 of Column Addresses on this Assembly A0 A9 5 of Module Banks this Assembly 1 banks 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC DIMM 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width 0 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency CL2 am
10. ow pulse width tCL 2 5 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output in Hi Z tSHZ 5 4 ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6F 256MB With 32M X 8 CL3 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CS RAS CAS wE pam Baon awap ASAT Note Register Mode Register Set H x L L L L x OP CODE 1 2 Auto Betrest H L L L H Refresh Self 1 7 5 Refresh i efres Exit L H H X X X X X 3 Bank Active amp Row Addr H X L L H H X V Row Address Read amp Auto Precharge Disable L Column 4 H X L H L H X V Address Column Address Auto Precharge Enable H Ao As i Auto Precharge Disable L Column 4 Write amp H X L H L L X V Address Column Address Auto Precharge Enable H AoAo 4 5 Burst Stop H X L H H L X X 6 Bank Selection V L L X X Precharge Both Banks H X L L H X H H X X X Clock Suspend or Ent
11. p CL3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec R W Burst OE 23 SDRAM Cycle Time 2 highest CL 10ns AO 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 256MB 40 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 Transcend information Inc 10 TS32MSS64V6F 144PIN PC133 Unbuffered SO DIMM 256MB With 32M X 8 CL3 62 SPD Data Revision Code VER1 2 12 63 Checksum for Bytes 0 62 D2 D2 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend 4 72 Manufacturing Location T 54 54 53 33 32 4D 53 73 90 Manufacturers Part Number TS32MSS64V6F 53 36 34 56 36 46 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency C
12. ry H L A x Active Power Down L Exit L H X X X X X H X X X Entry H L Precharge Power L H H H x Down Mode Exit H X X X L H X L V V V DQM H X V X 7 H X X X No Operation Command H X X X L H H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A12 Program keys MRS 2 MRS can be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatical precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAo BA1 Bank select address If both BAo and BAt1 are Low at read write row active and precharge bank is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BAt1 is Low at read write row active and precharge bank C is selected If both BAo and are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA is ignored and all banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end
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